1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "radeon_drm.h"
32 #include "nid.h"
33 #include "atom.h"
34 #include "ni_reg.h"
35 #include "cayman_blit_shaders.h"
36
37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
40 extern void evergreen_mc_program(struct radeon_device *rdev);
41 extern void evergreen_irq_suspend(struct radeon_device *rdev);
42 extern int evergreen_mc_init(struct radeon_device *rdev);
43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
45 extern void si_rlc_fini(struct radeon_device *rdev);
46 extern int si_rlc_init(struct radeon_device *rdev);
47
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define BTC_MC_UCODE_SIZE 6024
52
53 #define CAYMAN_PFP_UCODE_SIZE 2176
54 #define CAYMAN_PM4_UCODE_SIZE 2176
55 #define CAYMAN_RLC_UCODE_SIZE 1024
56 #define CAYMAN_MC_UCODE_SIZE 6037
57
58 #define ARUBA_RLC_UCODE_SIZE 1536
59
60 /* Firmware Names */
61 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
62 MODULE_FIRMWARE("radeon/BARTS_me.bin");
63 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
64 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
65 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
66 MODULE_FIRMWARE("radeon/TURKS_me.bin");
67 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
68 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
69 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
70 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
71 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
72 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
73 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
74 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
75 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
76 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
77 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
78
79 #define BTC_IO_MC_REGS_SIZE 29
80
81 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
82 {0x00000077, 0xff010100},
83 {0x00000078, 0x00000000},
84 {0x00000079, 0x00001434},
85 {0x0000007a, 0xcc08ec08},
86 {0x0000007b, 0x00040000},
87 {0x0000007c, 0x000080c0},
88 {0x0000007d, 0x09000000},
89 {0x0000007e, 0x00210404},
90 {0x00000081, 0x08a8e800},
91 {0x00000082, 0x00030444},
92 {0x00000083, 0x00000000},
93 {0x00000085, 0x00000001},
94 {0x00000086, 0x00000002},
95 {0x00000087, 0x48490000},
96 {0x00000088, 0x20244647},
97 {0x00000089, 0x00000005},
98 {0x0000008b, 0x66030000},
99 {0x0000008c, 0x00006603},
100 {0x0000008d, 0x00000100},
101 {0x0000008f, 0x00001c0a},
102 {0x00000090, 0xff000001},
103 {0x00000094, 0x00101101},
104 {0x00000095, 0x00000fff},
105 {0x00000096, 0x00116fff},
106 {0x00000097, 0x60010000},
107 {0x00000098, 0x10010000},
108 {0x00000099, 0x00006000},
109 {0x0000009a, 0x00001000},
110 {0x0000009f, 0x00946a00}
111 };
112
113 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
114 {0x00000077, 0xff010100},
115 {0x00000078, 0x00000000},
116 {0x00000079, 0x00001434},
117 {0x0000007a, 0xcc08ec08},
118 {0x0000007b, 0x00040000},
119 {0x0000007c, 0x000080c0},
120 {0x0000007d, 0x09000000},
121 {0x0000007e, 0x00210404},
122 {0x00000081, 0x08a8e800},
123 {0x00000082, 0x00030444},
124 {0x00000083, 0x00000000},
125 {0x00000085, 0x00000001},
126 {0x00000086, 0x00000002},
127 {0x00000087, 0x48490000},
128 {0x00000088, 0x20244647},
129 {0x00000089, 0x00000005},
130 {0x0000008b, 0x66030000},
131 {0x0000008c, 0x00006603},
132 {0x0000008d, 0x00000100},
133 {0x0000008f, 0x00001c0a},
134 {0x00000090, 0xff000001},
135 {0x00000094, 0x00101101},
136 {0x00000095, 0x00000fff},
137 {0x00000096, 0x00116fff},
138 {0x00000097, 0x60010000},
139 {0x00000098, 0x10010000},
140 {0x00000099, 0x00006000},
141 {0x0000009a, 0x00001000},
142 {0x0000009f, 0x00936a00}
143 };
144
145 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
146 {0x00000077, 0xff010100},
147 {0x00000078, 0x00000000},
148 {0x00000079, 0x00001434},
149 {0x0000007a, 0xcc08ec08},
150 {0x0000007b, 0x00040000},
151 {0x0000007c, 0x000080c0},
152 {0x0000007d, 0x09000000},
153 {0x0000007e, 0x00210404},
154 {0x00000081, 0x08a8e800},
155 {0x00000082, 0x00030444},
156 {0x00000083, 0x00000000},
157 {0x00000085, 0x00000001},
158 {0x00000086, 0x00000002},
159 {0x00000087, 0x48490000},
160 {0x00000088, 0x20244647},
161 {0x00000089, 0x00000005},
162 {0x0000008b, 0x66030000},
163 {0x0000008c, 0x00006603},
164 {0x0000008d, 0x00000100},
165 {0x0000008f, 0x00001c0a},
166 {0x00000090, 0xff000001},
167 {0x00000094, 0x00101101},
168 {0x00000095, 0x00000fff},
169 {0x00000096, 0x00116fff},
170 {0x00000097, 0x60010000},
171 {0x00000098, 0x10010000},
172 {0x00000099, 0x00006000},
173 {0x0000009a, 0x00001000},
174 {0x0000009f, 0x00916a00}
175 };
176
177 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
178 {0x00000077, 0xff010100},
179 {0x00000078, 0x00000000},
180 {0x00000079, 0x00001434},
181 {0x0000007a, 0xcc08ec08},
182 {0x0000007b, 0x00040000},
183 {0x0000007c, 0x000080c0},
184 {0x0000007d, 0x09000000},
185 {0x0000007e, 0x00210404},
186 {0x00000081, 0x08a8e800},
187 {0x00000082, 0x00030444},
188 {0x00000083, 0x00000000},
189 {0x00000085, 0x00000001},
190 {0x00000086, 0x00000002},
191 {0x00000087, 0x48490000},
192 {0x00000088, 0x20244647},
193 {0x00000089, 0x00000005},
194 {0x0000008b, 0x66030000},
195 {0x0000008c, 0x00006603},
196 {0x0000008d, 0x00000100},
197 {0x0000008f, 0x00001c0a},
198 {0x00000090, 0xff000001},
199 {0x00000094, 0x00101101},
200 {0x00000095, 0x00000fff},
201 {0x00000096, 0x00116fff},
202 {0x00000097, 0x60010000},
203 {0x00000098, 0x10010000},
204 {0x00000099, 0x00006000},
205 {0x0000009a, 0x00001000},
206 {0x0000009f, 0x00976b00}
207 };
208
ni_mc_load_microcode(struct radeon_device * rdev)209 int ni_mc_load_microcode(struct radeon_device *rdev)
210 {
211 const __be32 *fw_data;
212 u32 mem_type, running, blackout = 0;
213 u32 *io_mc_regs;
214 int i, ucode_size, regs_size;
215
216 if (!rdev->mc_fw)
217 return -EINVAL;
218
219 switch (rdev->family) {
220 case CHIP_BARTS:
221 io_mc_regs = (u32 *)&barts_io_mc_regs;
222 ucode_size = BTC_MC_UCODE_SIZE;
223 regs_size = BTC_IO_MC_REGS_SIZE;
224 break;
225 case CHIP_TURKS:
226 io_mc_regs = (u32 *)&turks_io_mc_regs;
227 ucode_size = BTC_MC_UCODE_SIZE;
228 regs_size = BTC_IO_MC_REGS_SIZE;
229 break;
230 case CHIP_CAICOS:
231 default:
232 io_mc_regs = (u32 *)&caicos_io_mc_regs;
233 ucode_size = BTC_MC_UCODE_SIZE;
234 regs_size = BTC_IO_MC_REGS_SIZE;
235 break;
236 case CHIP_CAYMAN:
237 io_mc_regs = (u32 *)&cayman_io_mc_regs;
238 ucode_size = CAYMAN_MC_UCODE_SIZE;
239 regs_size = BTC_IO_MC_REGS_SIZE;
240 break;
241 }
242
243 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
244 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
245
246 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
247 if (running) {
248 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
249 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
250 }
251
252 /* reset the engine and set to writable */
253 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
254 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
255
256 /* load mc io regs */
257 for (i = 0; i < regs_size; i++) {
258 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
259 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
260 }
261 /* load the MC ucode */
262 fw_data = (const __be32 *)rdev->mc_fw->data;
263 for (i = 0; i < ucode_size; i++)
264 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
265
266 /* put the engine back into the active state */
267 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
268 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
270
271 /* wait for training to complete */
272 for (i = 0; i < rdev->usec_timeout; i++) {
273 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
274 break;
275 udelay(1);
276 }
277
278 if (running)
279 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
280 }
281
282 return 0;
283 }
284
ni_init_microcode(struct radeon_device * rdev)285 int ni_init_microcode(struct radeon_device *rdev)
286 {
287 struct platform_device *pdev;
288 const char *chip_name;
289 const char *rlc_chip_name;
290 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
291 char fw_name[30];
292 int err;
293
294 DRM_DEBUG("\n");
295
296 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
297 err = IS_ERR(pdev);
298 if (err) {
299 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
300 return -EINVAL;
301 }
302
303 switch (rdev->family) {
304 case CHIP_BARTS:
305 chip_name = "BARTS";
306 rlc_chip_name = "BTC";
307 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
308 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
309 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
310 mc_req_size = BTC_MC_UCODE_SIZE * 4;
311 break;
312 case CHIP_TURKS:
313 chip_name = "TURKS";
314 rlc_chip_name = "BTC";
315 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
316 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
317 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
318 mc_req_size = BTC_MC_UCODE_SIZE * 4;
319 break;
320 case CHIP_CAICOS:
321 chip_name = "CAICOS";
322 rlc_chip_name = "BTC";
323 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
324 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
325 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
326 mc_req_size = BTC_MC_UCODE_SIZE * 4;
327 break;
328 case CHIP_CAYMAN:
329 chip_name = "CAYMAN";
330 rlc_chip_name = "CAYMAN";
331 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
332 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
333 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
334 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
335 break;
336 case CHIP_ARUBA:
337 chip_name = "ARUBA";
338 rlc_chip_name = "ARUBA";
339 /* pfp/me same size as CAYMAN */
340 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
341 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
342 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
343 mc_req_size = 0;
344 break;
345 default: BUG();
346 }
347
348 DRM_INFO("Loading %s Microcode\n", chip_name);
349
350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
352 if (err)
353 goto out;
354 if (rdev->pfp_fw->size != pfp_req_size) {
355 printk(KERN_ERR
356 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
357 rdev->pfp_fw->size, fw_name);
358 err = -EINVAL;
359 goto out;
360 }
361
362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
364 if (err)
365 goto out;
366 if (rdev->me_fw->size != me_req_size) {
367 printk(KERN_ERR
368 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
369 rdev->me_fw->size, fw_name);
370 err = -EINVAL;
371 }
372
373 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
374 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
375 if (err)
376 goto out;
377 if (rdev->rlc_fw->size != rlc_req_size) {
378 printk(KERN_ERR
379 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
380 rdev->rlc_fw->size, fw_name);
381 err = -EINVAL;
382 }
383
384 /* no MC ucode on TN */
385 if (!(rdev->flags & RADEON_IS_IGP)) {
386 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
387 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
388 if (err)
389 goto out;
390 if (rdev->mc_fw->size != mc_req_size) {
391 printk(KERN_ERR
392 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
393 rdev->mc_fw->size, fw_name);
394 err = -EINVAL;
395 }
396 }
397 out:
398 platform_device_unregister(pdev);
399
400 if (err) {
401 if (err != -EINVAL)
402 printk(KERN_ERR
403 "ni_cp: Failed to load firmware \"%s\"\n",
404 fw_name);
405 release_firmware(rdev->pfp_fw);
406 rdev->pfp_fw = NULL;
407 release_firmware(rdev->me_fw);
408 rdev->me_fw = NULL;
409 release_firmware(rdev->rlc_fw);
410 rdev->rlc_fw = NULL;
411 release_firmware(rdev->mc_fw);
412 rdev->mc_fw = NULL;
413 }
414 return err;
415 }
416
417 /*
418 * Core functions
419 */
cayman_get_tile_pipe_to_backend_map(struct radeon_device * rdev,u32 num_tile_pipes,u32 num_backends_per_asic,u32 * backend_disable_mask_per_asic,u32 num_shader_engines)420 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
421 u32 num_tile_pipes,
422 u32 num_backends_per_asic,
423 u32 *backend_disable_mask_per_asic,
424 u32 num_shader_engines)
425 {
426 u32 backend_map = 0;
427 u32 enabled_backends_mask = 0;
428 u32 enabled_backends_count = 0;
429 u32 num_backends_per_se;
430 u32 cur_pipe;
431 u32 swizzle_pipe[CAYMAN_MAX_PIPES];
432 u32 cur_backend = 0;
433 u32 i;
434 bool force_no_swizzle;
435
436 /* force legal values */
437 if (num_tile_pipes < 1)
438 num_tile_pipes = 1;
439 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
440 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
441 if (num_shader_engines < 1)
442 num_shader_engines = 1;
443 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
444 num_shader_engines = rdev->config.cayman.max_shader_engines;
445 if (num_backends_per_asic < num_shader_engines)
446 num_backends_per_asic = num_shader_engines;
447 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
448 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
449
450 /* make sure we have the same number of backends per se */
451 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
452 /* set up the number of backends per se */
453 num_backends_per_se = num_backends_per_asic / num_shader_engines;
454 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
455 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
456 num_backends_per_asic = num_backends_per_se * num_shader_engines;
457 }
458
459 /* create enable mask and count for enabled backends */
460 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
461 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
462 enabled_backends_mask |= (1 << i);
463 ++enabled_backends_count;
464 }
465 if (enabled_backends_count == num_backends_per_asic)
466 break;
467 }
468
469 /* force the backends mask to match the current number of backends */
470 if (enabled_backends_count != num_backends_per_asic) {
471 u32 this_backend_enabled;
472 u32 shader_engine;
473 u32 backend_per_se;
474
475 enabled_backends_mask = 0;
476 enabled_backends_count = 0;
477 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
478 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
479 /* calc the current se */
480 shader_engine = i / rdev->config.cayman.max_backends_per_se;
481 /* calc the backend per se */
482 backend_per_se = i % rdev->config.cayman.max_backends_per_se;
483 /* default to not enabled */
484 this_backend_enabled = 0;
485 if ((shader_engine < num_shader_engines) &&
486 (backend_per_se < num_backends_per_se))
487 this_backend_enabled = 1;
488 if (this_backend_enabled) {
489 enabled_backends_mask |= (1 << i);
490 *backend_disable_mask_per_asic &= ~(1 << i);
491 ++enabled_backends_count;
492 }
493 }
494 }
495
496
497 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
498 switch (rdev->family) {
499 case CHIP_CAYMAN:
500 case CHIP_ARUBA:
501 force_no_swizzle = true;
502 break;
503 default:
504 force_no_swizzle = false;
505 break;
506 }
507 if (force_no_swizzle) {
508 bool last_backend_enabled = false;
509
510 force_no_swizzle = false;
511 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
512 if (((enabled_backends_mask >> i) & 1) == 1) {
513 if (last_backend_enabled)
514 force_no_swizzle = true;
515 last_backend_enabled = true;
516 } else
517 last_backend_enabled = false;
518 }
519 }
520
521 switch (num_tile_pipes) {
522 case 1:
523 case 3:
524 case 5:
525 case 7:
526 DRM_ERROR("odd number of pipes!\n");
527 break;
528 case 2:
529 swizzle_pipe[0] = 0;
530 swizzle_pipe[1] = 1;
531 break;
532 case 4:
533 if (force_no_swizzle) {
534 swizzle_pipe[0] = 0;
535 swizzle_pipe[1] = 1;
536 swizzle_pipe[2] = 2;
537 swizzle_pipe[3] = 3;
538 } else {
539 swizzle_pipe[0] = 0;
540 swizzle_pipe[1] = 2;
541 swizzle_pipe[2] = 1;
542 swizzle_pipe[3] = 3;
543 }
544 break;
545 case 6:
546 if (force_no_swizzle) {
547 swizzle_pipe[0] = 0;
548 swizzle_pipe[1] = 1;
549 swizzle_pipe[2] = 2;
550 swizzle_pipe[3] = 3;
551 swizzle_pipe[4] = 4;
552 swizzle_pipe[5] = 5;
553 } else {
554 swizzle_pipe[0] = 0;
555 swizzle_pipe[1] = 2;
556 swizzle_pipe[2] = 4;
557 swizzle_pipe[3] = 1;
558 swizzle_pipe[4] = 3;
559 swizzle_pipe[5] = 5;
560 }
561 break;
562 case 8:
563 if (force_no_swizzle) {
564 swizzle_pipe[0] = 0;
565 swizzle_pipe[1] = 1;
566 swizzle_pipe[2] = 2;
567 swizzle_pipe[3] = 3;
568 swizzle_pipe[4] = 4;
569 swizzle_pipe[5] = 5;
570 swizzle_pipe[6] = 6;
571 swizzle_pipe[7] = 7;
572 } else {
573 swizzle_pipe[0] = 0;
574 swizzle_pipe[1] = 2;
575 swizzle_pipe[2] = 4;
576 swizzle_pipe[3] = 6;
577 swizzle_pipe[4] = 1;
578 swizzle_pipe[5] = 3;
579 swizzle_pipe[6] = 5;
580 swizzle_pipe[7] = 7;
581 }
582 break;
583 }
584
585 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
586 while (((1 << cur_backend) & enabled_backends_mask) == 0)
587 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
588
589 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
590
591 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
592 }
593
594 return backend_map;
595 }
596
cayman_get_disable_mask_per_asic(struct radeon_device * rdev,u32 disable_mask_per_se,u32 max_disable_mask_per_se,u32 num_shader_engines)597 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
598 u32 disable_mask_per_se,
599 u32 max_disable_mask_per_se,
600 u32 num_shader_engines)
601 {
602 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
603 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
604
605 if (num_shader_engines == 1)
606 return disable_mask_per_asic;
607 else if (num_shader_engines == 2)
608 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
609 else
610 return 0xffffffff;
611 }
612
cayman_gpu_init(struct radeon_device * rdev)613 static void cayman_gpu_init(struct radeon_device *rdev)
614 {
615 u32 cc_rb_backend_disable = 0;
616 u32 cc_gc_shader_pipe_config;
617 u32 gb_addr_config = 0;
618 u32 mc_shared_chmap, mc_arb_ramcfg;
619 u32 gb_backend_map;
620 u32 cgts_tcc_disable;
621 u32 sx_debug_1;
622 u32 smx_dc_ctl0;
623 u32 gc_user_shader_pipe_config;
624 u32 gc_user_rb_backend_disable;
625 u32 cgts_user_tcc_disable;
626 u32 cgts_sm_ctrl_reg;
627 u32 hdp_host_path_cntl;
628 u32 tmp;
629 int i, j;
630
631 switch (rdev->family) {
632 case CHIP_CAYMAN:
633 rdev->config.cayman.max_shader_engines = 2;
634 rdev->config.cayman.max_pipes_per_simd = 4;
635 rdev->config.cayman.max_tile_pipes = 8;
636 rdev->config.cayman.max_simds_per_se = 12;
637 rdev->config.cayman.max_backends_per_se = 4;
638 rdev->config.cayman.max_texture_channel_caches = 8;
639 rdev->config.cayman.max_gprs = 256;
640 rdev->config.cayman.max_threads = 256;
641 rdev->config.cayman.max_gs_threads = 32;
642 rdev->config.cayman.max_stack_entries = 512;
643 rdev->config.cayman.sx_num_of_sets = 8;
644 rdev->config.cayman.sx_max_export_size = 256;
645 rdev->config.cayman.sx_max_export_pos_size = 64;
646 rdev->config.cayman.sx_max_export_smx_size = 192;
647 rdev->config.cayman.max_hw_contexts = 8;
648 rdev->config.cayman.sq_num_cf_insts = 2;
649
650 rdev->config.cayman.sc_prim_fifo_size = 0x100;
651 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
652 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
653 break;
654 case CHIP_ARUBA:
655 default:
656 rdev->config.cayman.max_shader_engines = 1;
657 rdev->config.cayman.max_pipes_per_simd = 4;
658 rdev->config.cayman.max_tile_pipes = 2;
659 if ((rdev->pdev->device == 0x9900) ||
660 (rdev->pdev->device == 0x9901) ||
661 (rdev->pdev->device == 0x9905) ||
662 (rdev->pdev->device == 0x9906) ||
663 (rdev->pdev->device == 0x9907) ||
664 (rdev->pdev->device == 0x9908) ||
665 (rdev->pdev->device == 0x9909) ||
666 (rdev->pdev->device == 0x990B) ||
667 (rdev->pdev->device == 0x990C) ||
668 (rdev->pdev->device == 0x990F) ||
669 (rdev->pdev->device == 0x9910) ||
670 (rdev->pdev->device == 0x9917) ||
671 (rdev->pdev->device == 0x9999) ||
672 (rdev->pdev->device == 0x999C)) {
673 rdev->config.cayman.max_simds_per_se = 6;
674 rdev->config.cayman.max_backends_per_se = 2;
675 rdev->config.cayman.max_hw_contexts = 8;
676 rdev->config.cayman.sx_max_export_size = 256;
677 rdev->config.cayman.sx_max_export_pos_size = 64;
678 rdev->config.cayman.sx_max_export_smx_size = 192;
679 } else if ((rdev->pdev->device == 0x9903) ||
680 (rdev->pdev->device == 0x9904) ||
681 (rdev->pdev->device == 0x990A) ||
682 (rdev->pdev->device == 0x990D) ||
683 (rdev->pdev->device == 0x990E) ||
684 (rdev->pdev->device == 0x9913) ||
685 (rdev->pdev->device == 0x9918) ||
686 (rdev->pdev->device == 0x999D)) {
687 rdev->config.cayman.max_simds_per_se = 4;
688 rdev->config.cayman.max_backends_per_se = 2;
689 rdev->config.cayman.max_hw_contexts = 8;
690 rdev->config.cayman.sx_max_export_size = 256;
691 rdev->config.cayman.sx_max_export_pos_size = 64;
692 rdev->config.cayman.sx_max_export_smx_size = 192;
693 } else if ((rdev->pdev->device == 0x9919) ||
694 (rdev->pdev->device == 0x9990) ||
695 (rdev->pdev->device == 0x9991) ||
696 (rdev->pdev->device == 0x9994) ||
697 (rdev->pdev->device == 0x9995) ||
698 (rdev->pdev->device == 0x9996) ||
699 (rdev->pdev->device == 0x999A) ||
700 (rdev->pdev->device == 0x99A0)) {
701 rdev->config.cayman.max_simds_per_se = 3;
702 rdev->config.cayman.max_backends_per_se = 1;
703 rdev->config.cayman.max_hw_contexts = 4;
704 rdev->config.cayman.sx_max_export_size = 128;
705 rdev->config.cayman.sx_max_export_pos_size = 32;
706 rdev->config.cayman.sx_max_export_smx_size = 96;
707 } else {
708 rdev->config.cayman.max_simds_per_se = 2;
709 rdev->config.cayman.max_backends_per_se = 1;
710 rdev->config.cayman.max_hw_contexts = 4;
711 rdev->config.cayman.sx_max_export_size = 128;
712 rdev->config.cayman.sx_max_export_pos_size = 32;
713 rdev->config.cayman.sx_max_export_smx_size = 96;
714 }
715 rdev->config.cayman.max_texture_channel_caches = 2;
716 rdev->config.cayman.max_gprs = 256;
717 rdev->config.cayman.max_threads = 256;
718 rdev->config.cayman.max_gs_threads = 32;
719 rdev->config.cayman.max_stack_entries = 512;
720 rdev->config.cayman.sx_num_of_sets = 8;
721 rdev->config.cayman.sq_num_cf_insts = 2;
722
723 rdev->config.cayman.sc_prim_fifo_size = 0x40;
724 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
725 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
726 break;
727 }
728
729 /* Initialize HDP */
730 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
731 WREG32((0x2c14 + j), 0x00000000);
732 WREG32((0x2c18 + j), 0x00000000);
733 WREG32((0x2c1c + j), 0x00000000);
734 WREG32((0x2c20 + j), 0x00000000);
735 WREG32((0x2c24 + j), 0x00000000);
736 }
737
738 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
739
740 evergreen_fix_pci_max_read_req_size(rdev);
741
742 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
743 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
744
745 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
746 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
747 cgts_tcc_disable = 0xffff0000;
748 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
749 cgts_tcc_disable &= ~(1 << (16 + i));
750 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
751 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
752 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
753
754 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
755 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
756 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
757 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
758 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
759 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
760 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
761 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
762 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
763 rdev->config.cayman.backend_disable_mask_per_asic =
764 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
765 rdev->config.cayman.num_shader_engines);
766 rdev->config.cayman.backend_map =
767 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
768 rdev->config.cayman.num_backends_per_se *
769 rdev->config.cayman.num_shader_engines,
770 &rdev->config.cayman.backend_disable_mask_per_asic,
771 rdev->config.cayman.num_shader_engines);
772 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
773 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
774 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
775 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
776 if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
777 rdev->config.cayman.mem_max_burst_length_bytes = 512;
778 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
779 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
780 if (rdev->config.cayman.mem_row_size_in_kb > 4)
781 rdev->config.cayman.mem_row_size_in_kb = 4;
782 /* XXX use MC settings? */
783 rdev->config.cayman.shader_engine_tile_size = 32;
784 rdev->config.cayman.num_gpus = 1;
785 rdev->config.cayman.multi_gpu_tile_size = 64;
786
787 //gb_addr_config = 0x02011003
788 #if 0
789 gb_addr_config = RREG32(GB_ADDR_CONFIG);
790 #else
791 gb_addr_config = 0;
792 switch (rdev->config.cayman.num_tile_pipes) {
793 case 1:
794 default:
795 gb_addr_config |= NUM_PIPES(0);
796 break;
797 case 2:
798 gb_addr_config |= NUM_PIPES(1);
799 break;
800 case 4:
801 gb_addr_config |= NUM_PIPES(2);
802 break;
803 case 8:
804 gb_addr_config |= NUM_PIPES(3);
805 break;
806 }
807
808 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
809 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
810 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
811 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
812 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
813 switch (rdev->config.cayman.num_gpus) {
814 case 1:
815 default:
816 gb_addr_config |= NUM_GPUS(0);
817 break;
818 case 2:
819 gb_addr_config |= NUM_GPUS(1);
820 break;
821 case 4:
822 gb_addr_config |= NUM_GPUS(2);
823 break;
824 }
825 switch (rdev->config.cayman.multi_gpu_tile_size) {
826 case 16:
827 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
828 break;
829 case 32:
830 default:
831 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
832 break;
833 case 64:
834 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
835 break;
836 case 128:
837 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
838 break;
839 }
840 switch (rdev->config.cayman.mem_row_size_in_kb) {
841 case 1:
842 default:
843 gb_addr_config |= ROW_SIZE(0);
844 break;
845 case 2:
846 gb_addr_config |= ROW_SIZE(1);
847 break;
848 case 4:
849 gb_addr_config |= ROW_SIZE(2);
850 break;
851 }
852 #endif
853
854 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
855 rdev->config.cayman.num_tile_pipes = (1 << tmp);
856 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
857 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
858 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
859 rdev->config.cayman.num_shader_engines = tmp + 1;
860 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
861 rdev->config.cayman.num_gpus = tmp + 1;
862 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
863 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
864 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
865 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
866
867 //gb_backend_map = 0x76541032;
868 #if 0
869 gb_backend_map = RREG32(GB_BACKEND_MAP);
870 #else
871 gb_backend_map =
872 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
873 rdev->config.cayman.num_backends_per_se *
874 rdev->config.cayman.num_shader_engines,
875 &rdev->config.cayman.backend_disable_mask_per_asic,
876 rdev->config.cayman.num_shader_engines);
877 #endif
878 /* setup tiling info dword. gb_addr_config is not adequate since it does
879 * not have bank info, so create a custom tiling dword.
880 * bits 3:0 num_pipes
881 * bits 7:4 num_banks
882 * bits 11:8 group_size
883 * bits 15:12 row_size
884 */
885 rdev->config.cayman.tile_config = 0;
886 switch (rdev->config.cayman.num_tile_pipes) {
887 case 1:
888 default:
889 rdev->config.cayman.tile_config |= (0 << 0);
890 break;
891 case 2:
892 rdev->config.cayman.tile_config |= (1 << 0);
893 break;
894 case 4:
895 rdev->config.cayman.tile_config |= (2 << 0);
896 break;
897 case 8:
898 rdev->config.cayman.tile_config |= (3 << 0);
899 break;
900 }
901
902 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
903 if (rdev->flags & RADEON_IS_IGP)
904 rdev->config.cayman.tile_config |= 1 << 4;
905 else {
906 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
907 case 0: /* four banks */
908 rdev->config.cayman.tile_config |= 0 << 4;
909 break;
910 case 1: /* eight banks */
911 rdev->config.cayman.tile_config |= 1 << 4;
912 break;
913 case 2: /* sixteen banks */
914 default:
915 rdev->config.cayman.tile_config |= 2 << 4;
916 break;
917 }
918 }
919 rdev->config.cayman.tile_config |=
920 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
921 rdev->config.cayman.tile_config |=
922 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
923
924 rdev->config.cayman.backend_map = gb_backend_map;
925 WREG32(GB_BACKEND_MAP, gb_backend_map);
926 WREG32(GB_ADDR_CONFIG, gb_addr_config);
927 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
928 if (ASIC_IS_DCE6(rdev))
929 WREG32(DMIF_ADDR_CALC, gb_addr_config);
930 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
931
932 /* primary versions */
933 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
934 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
935 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
936
937 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
938 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
939
940 /* user versions */
941 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
942 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
943 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
944
945 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
946 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
947
948 /* reprogram the shader complex */
949 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
950 for (i = 0; i < 16; i++)
951 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
952 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
953
954 /* set HW defaults for 3D engine */
955 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
956
957 sx_debug_1 = RREG32(SX_DEBUG_1);
958 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
959 WREG32(SX_DEBUG_1, sx_debug_1);
960
961 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
962 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
963 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
964 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
965
966 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
967
968 /* need to be explicitly zero-ed */
969 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
970 WREG32(SQ_LSTMP_RING_BASE, 0);
971 WREG32(SQ_HSTMP_RING_BASE, 0);
972 WREG32(SQ_ESTMP_RING_BASE, 0);
973 WREG32(SQ_GSTMP_RING_BASE, 0);
974 WREG32(SQ_VSTMP_RING_BASE, 0);
975 WREG32(SQ_PSTMP_RING_BASE, 0);
976
977 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
978
979 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
980 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
981 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
982
983 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
984 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
985 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
986
987
988 WREG32(VGT_NUM_INSTANCES, 1);
989
990 WREG32(CP_PERFMON_CNTL, 0);
991
992 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
993 FETCH_FIFO_HIWATER(0x4) |
994 DONE_FIFO_HIWATER(0xe0) |
995 ALU_UPDATE_FIFO_HIWATER(0x8)));
996
997 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
998 WREG32(SQ_CONFIG, (VC_ENABLE |
999 EXPORT_SRC_C |
1000 GFX_PRIO(0) |
1001 CS1_PRIO(0) |
1002 CS2_PRIO(1)));
1003 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1004
1005 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1006 FORCE_EOV_MAX_REZ_CNT(255)));
1007
1008 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1009 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1010
1011 WREG32(VGT_GS_VERTEX_REUSE, 16);
1012 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1013
1014 WREG32(CB_PERF_CTR0_SEL_0, 0);
1015 WREG32(CB_PERF_CTR0_SEL_1, 0);
1016 WREG32(CB_PERF_CTR1_SEL_0, 0);
1017 WREG32(CB_PERF_CTR1_SEL_1, 0);
1018 WREG32(CB_PERF_CTR2_SEL_0, 0);
1019 WREG32(CB_PERF_CTR2_SEL_1, 0);
1020 WREG32(CB_PERF_CTR3_SEL_0, 0);
1021 WREG32(CB_PERF_CTR3_SEL_1, 0);
1022
1023 tmp = RREG32(HDP_MISC_CNTL);
1024 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1025 WREG32(HDP_MISC_CNTL, tmp);
1026
1027 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1028 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1029
1030 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1031
1032 udelay(50);
1033 }
1034
1035 /*
1036 * GART
1037 */
cayman_pcie_gart_tlb_flush(struct radeon_device * rdev)1038 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1039 {
1040 /* flush hdp cache */
1041 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1042
1043 /* bits 0-7 are the VM contexts0-7 */
1044 WREG32(VM_INVALIDATE_REQUEST, 1);
1045 }
1046
cayman_pcie_gart_enable(struct radeon_device * rdev)1047 int cayman_pcie_gart_enable(struct radeon_device *rdev)
1048 {
1049 int i, r;
1050
1051 if (rdev->gart.robj == NULL) {
1052 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1053 return -EINVAL;
1054 }
1055 r = radeon_gart_table_vram_pin(rdev);
1056 if (r)
1057 return r;
1058 radeon_gart_restore(rdev);
1059 /* Setup TLB control */
1060 WREG32(MC_VM_MX_L1_TLB_CNTL,
1061 (0xA << 7) |
1062 ENABLE_L1_TLB |
1063 ENABLE_L1_FRAGMENT_PROCESSING |
1064 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1065 ENABLE_ADVANCED_DRIVER_MODEL |
1066 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1067 /* Setup L2 cache */
1068 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1069 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1070 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1071 EFFECTIVE_L2_QUEUE_SIZE(7) |
1072 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1073 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1074 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1075 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1076 /* setup context0 */
1077 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1078 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1079 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1080 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1081 (u32)(rdev->dummy_page.addr >> 12));
1082 WREG32(VM_CONTEXT0_CNTL2, 0);
1083 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1084 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1085
1086 WREG32(0x15D4, 0);
1087 WREG32(0x15D8, 0);
1088 WREG32(0x15DC, 0);
1089
1090 /* empty context1-7 */
1091 for (i = 1; i < 8; i++) {
1092 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1093 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
1094 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1095 rdev->gart.table_addr >> 12);
1096 }
1097
1098 /* enable context1-7 */
1099 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1100 (u32)(rdev->dummy_page.addr >> 12));
1101 WREG32(VM_CONTEXT1_CNTL2, 0);
1102 WREG32(VM_CONTEXT1_CNTL, 0);
1103 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1104 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1105
1106 cayman_pcie_gart_tlb_flush(rdev);
1107 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1108 (unsigned)(rdev->mc.gtt_size >> 20),
1109 (unsigned long long)rdev->gart.table_addr);
1110 rdev->gart.ready = true;
1111 return 0;
1112 }
1113
cayman_pcie_gart_disable(struct radeon_device * rdev)1114 void cayman_pcie_gart_disable(struct radeon_device *rdev)
1115 {
1116 /* Disable all tables */
1117 WREG32(VM_CONTEXT0_CNTL, 0);
1118 WREG32(VM_CONTEXT1_CNTL, 0);
1119 /* Setup TLB control */
1120 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1121 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1122 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1123 /* Setup L2 cache */
1124 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1125 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1126 EFFECTIVE_L2_QUEUE_SIZE(7) |
1127 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1128 WREG32(VM_L2_CNTL2, 0);
1129 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1130 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1131 radeon_gart_table_vram_unpin(rdev);
1132 }
1133
cayman_pcie_gart_fini(struct radeon_device * rdev)1134 void cayman_pcie_gart_fini(struct radeon_device *rdev)
1135 {
1136 cayman_pcie_gart_disable(rdev);
1137 radeon_gart_table_vram_free(rdev);
1138 radeon_gart_fini(rdev);
1139 }
1140
cayman_cp_int_cntl_setup(struct radeon_device * rdev,int ring,u32 cp_int_cntl)1141 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1142 int ring, u32 cp_int_cntl)
1143 {
1144 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1145
1146 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1147 WREG32(CP_INT_CNTL, cp_int_cntl);
1148 }
1149
1150 /*
1151 * CP.
1152 */
cayman_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)1153 void cayman_fence_ring_emit(struct radeon_device *rdev,
1154 struct radeon_fence *fence)
1155 {
1156 struct radeon_ring *ring = &rdev->ring[fence->ring];
1157 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1158
1159 /* flush read cache over gart for this vmid */
1160 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1161 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1162 radeon_ring_write(ring, 0);
1163 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1164 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1165 radeon_ring_write(ring, 0xFFFFFFFF);
1166 radeon_ring_write(ring, 0);
1167 radeon_ring_write(ring, 10); /* poll interval */
1168 /* EVENT_WRITE_EOP - flush caches, send int */
1169 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1170 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1171 radeon_ring_write(ring, addr & 0xffffffff);
1172 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1173 radeon_ring_write(ring, fence->seq);
1174 radeon_ring_write(ring, 0);
1175 }
1176
cayman_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)1177 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1178 {
1179 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1180
1181 /* set to DX10/11 mode */
1182 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1183 radeon_ring_write(ring, 1);
1184 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1185 radeon_ring_write(ring,
1186 #ifdef __BIG_ENDIAN
1187 (2 << 0) |
1188 #endif
1189 (ib->gpu_addr & 0xFFFFFFFC));
1190 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1191 radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1192
1193 /* flush read cache over gart for this vmid */
1194 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1195 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1196 radeon_ring_write(ring, ib->vm_id);
1197 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1198 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1199 radeon_ring_write(ring, 0xFFFFFFFF);
1200 radeon_ring_write(ring, 0);
1201 radeon_ring_write(ring, 10); /* poll interval */
1202 }
1203
cayman_cp_enable(struct radeon_device * rdev,bool enable)1204 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1205 {
1206 if (enable)
1207 WREG32(CP_ME_CNTL, 0);
1208 else {
1209 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1210 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1211 WREG32(SCRATCH_UMSK, 0);
1212 }
1213 }
1214
cayman_cp_load_microcode(struct radeon_device * rdev)1215 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1216 {
1217 const __be32 *fw_data;
1218 int i;
1219
1220 if (!rdev->me_fw || !rdev->pfp_fw)
1221 return -EINVAL;
1222
1223 cayman_cp_enable(rdev, false);
1224
1225 fw_data = (const __be32 *)rdev->pfp_fw->data;
1226 WREG32(CP_PFP_UCODE_ADDR, 0);
1227 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1228 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1229 WREG32(CP_PFP_UCODE_ADDR, 0);
1230
1231 fw_data = (const __be32 *)rdev->me_fw->data;
1232 WREG32(CP_ME_RAM_WADDR, 0);
1233 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1234 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1235
1236 WREG32(CP_PFP_UCODE_ADDR, 0);
1237 WREG32(CP_ME_RAM_WADDR, 0);
1238 WREG32(CP_ME_RAM_RADDR, 0);
1239 return 0;
1240 }
1241
cayman_cp_start(struct radeon_device * rdev)1242 static int cayman_cp_start(struct radeon_device *rdev)
1243 {
1244 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1245 int r, i;
1246
1247 r = radeon_ring_lock(rdev, ring, 7);
1248 if (r) {
1249 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1250 return r;
1251 }
1252 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1253 radeon_ring_write(ring, 0x1);
1254 radeon_ring_write(ring, 0x0);
1255 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1256 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1257 radeon_ring_write(ring, 0);
1258 radeon_ring_write(ring, 0);
1259 radeon_ring_unlock_commit(rdev, ring);
1260
1261 cayman_cp_enable(rdev, true);
1262
1263 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1264 if (r) {
1265 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1266 return r;
1267 }
1268
1269 /* setup clear context state */
1270 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1271 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1272
1273 for (i = 0; i < cayman_default_size; i++)
1274 radeon_ring_write(ring, cayman_default_state[i]);
1275
1276 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1277 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1278
1279 /* set clear context state */
1280 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1281 radeon_ring_write(ring, 0);
1282
1283 /* SQ_VTX_BASE_VTX_LOC */
1284 radeon_ring_write(ring, 0xc0026f00);
1285 radeon_ring_write(ring, 0x00000000);
1286 radeon_ring_write(ring, 0x00000000);
1287 radeon_ring_write(ring, 0x00000000);
1288
1289 /* Clear consts */
1290 radeon_ring_write(ring, 0xc0036f00);
1291 radeon_ring_write(ring, 0x00000bc4);
1292 radeon_ring_write(ring, 0xffffffff);
1293 radeon_ring_write(ring, 0xffffffff);
1294 radeon_ring_write(ring, 0xffffffff);
1295
1296 radeon_ring_write(ring, 0xc0026900);
1297 radeon_ring_write(ring, 0x00000316);
1298 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1299 radeon_ring_write(ring, 0x00000010); /* */
1300
1301 radeon_ring_unlock_commit(rdev, ring);
1302
1303 /* XXX init other rings */
1304
1305 return 0;
1306 }
1307
cayman_cp_fini(struct radeon_device * rdev)1308 static void cayman_cp_fini(struct radeon_device *rdev)
1309 {
1310 cayman_cp_enable(rdev, false);
1311 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1312 }
1313
cayman_cp_resume(struct radeon_device * rdev)1314 int cayman_cp_resume(struct radeon_device *rdev)
1315 {
1316 struct radeon_ring *ring;
1317 u32 tmp;
1318 u32 rb_bufsz;
1319 int r;
1320
1321 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1322 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1323 SOFT_RESET_PA |
1324 SOFT_RESET_SH |
1325 SOFT_RESET_VGT |
1326 SOFT_RESET_SPI |
1327 SOFT_RESET_SX));
1328 RREG32(GRBM_SOFT_RESET);
1329 mdelay(15);
1330 WREG32(GRBM_SOFT_RESET, 0);
1331 RREG32(GRBM_SOFT_RESET);
1332
1333 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1334 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1335
1336 /* Set the write pointer delay */
1337 WREG32(CP_RB_WPTR_DELAY, 0);
1338
1339 WREG32(CP_DEBUG, (1 << 27));
1340
1341 /* ring 0 - compute and gfx */
1342 /* Set ring buffer size */
1343 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1344 rb_bufsz = drm_order(ring->ring_size / 8);
1345 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1346 #ifdef __BIG_ENDIAN
1347 tmp |= BUF_SWAP_32BIT;
1348 #endif
1349 WREG32(CP_RB0_CNTL, tmp);
1350
1351 /* Initialize the ring buffer's read and write pointers */
1352 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1353 ring->wptr = 0;
1354 WREG32(CP_RB0_WPTR, ring->wptr);
1355
1356 /* set the wb address wether it's enabled or not */
1357 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1358 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1359 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1360
1361 if (rdev->wb.enabled)
1362 WREG32(SCRATCH_UMSK, 0xff);
1363 else {
1364 tmp |= RB_NO_UPDATE;
1365 WREG32(SCRATCH_UMSK, 0);
1366 }
1367
1368 mdelay(1);
1369 WREG32(CP_RB0_CNTL, tmp);
1370
1371 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1372
1373 ring->rptr = RREG32(CP_RB0_RPTR);
1374
1375 /* ring1 - compute only */
1376 /* Set ring buffer size */
1377 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1378 rb_bufsz = drm_order(ring->ring_size / 8);
1379 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1380 #ifdef __BIG_ENDIAN
1381 tmp |= BUF_SWAP_32BIT;
1382 #endif
1383 WREG32(CP_RB1_CNTL, tmp);
1384
1385 /* Initialize the ring buffer's read and write pointers */
1386 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1387 ring->wptr = 0;
1388 WREG32(CP_RB1_WPTR, ring->wptr);
1389
1390 /* set the wb address wether it's enabled or not */
1391 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1392 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1393
1394 mdelay(1);
1395 WREG32(CP_RB1_CNTL, tmp);
1396
1397 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1398
1399 ring->rptr = RREG32(CP_RB1_RPTR);
1400
1401 /* ring2 - compute only */
1402 /* Set ring buffer size */
1403 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1404 rb_bufsz = drm_order(ring->ring_size / 8);
1405 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1406 #ifdef __BIG_ENDIAN
1407 tmp |= BUF_SWAP_32BIT;
1408 #endif
1409 WREG32(CP_RB2_CNTL, tmp);
1410
1411 /* Initialize the ring buffer's read and write pointers */
1412 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1413 ring->wptr = 0;
1414 WREG32(CP_RB2_WPTR, ring->wptr);
1415
1416 /* set the wb address wether it's enabled or not */
1417 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1418 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1419
1420 mdelay(1);
1421 WREG32(CP_RB2_CNTL, tmp);
1422
1423 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1424
1425 ring->rptr = RREG32(CP_RB2_RPTR);
1426
1427 /* start the rings */
1428 cayman_cp_start(rdev);
1429 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1430 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1431 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1432 /* this only test cp0 */
1433 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1434 if (r) {
1435 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1436 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1437 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1438 return r;
1439 }
1440
1441 return 0;
1442 }
1443
cayman_gpu_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)1444 bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1445 {
1446 u32 srbm_status;
1447 u32 grbm_status;
1448 u32 grbm_status_se0, grbm_status_se1;
1449 struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1450 int r;
1451
1452 srbm_status = RREG32(SRBM_STATUS);
1453 grbm_status = RREG32(GRBM_STATUS);
1454 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1455 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1456 if (!(grbm_status & GUI_ACTIVE)) {
1457 r100_gpu_lockup_update(lockup, ring);
1458 return false;
1459 }
1460 /* force CP activities */
1461 r = radeon_ring_lock(rdev, ring, 2);
1462 if (!r) {
1463 /* PACKET2 NOP */
1464 radeon_ring_write(ring, 0x80000000);
1465 radeon_ring_write(ring, 0x80000000);
1466 radeon_ring_unlock_commit(rdev, ring);
1467 }
1468 /* XXX deal with CP0,1,2 */
1469 ring->rptr = RREG32(ring->rptr_reg);
1470 return r100_gpu_cp_is_lockup(rdev, lockup, ring);
1471 }
1472
cayman_gpu_soft_reset(struct radeon_device * rdev)1473 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1474 {
1475 struct evergreen_mc_save save;
1476 u32 grbm_reset = 0;
1477
1478 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1479 return 0;
1480
1481 dev_info(rdev->dev, "GPU softreset \n");
1482 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1483 RREG32(GRBM_STATUS));
1484 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1485 RREG32(GRBM_STATUS_SE0));
1486 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1487 RREG32(GRBM_STATUS_SE1));
1488 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1489 RREG32(SRBM_STATUS));
1490 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1491 RREG32(0x14F8));
1492 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1493 RREG32(0x14D8));
1494 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1495 RREG32(0x14FC));
1496 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1497 RREG32(0x14DC));
1498
1499 evergreen_mc_stop(rdev, &save);
1500 if (evergreen_mc_wait_for_idle(rdev)) {
1501 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1502 }
1503 /* Disable CP parsing/prefetching */
1504 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1505
1506 /* reset all the gfx blocks */
1507 grbm_reset = (SOFT_RESET_CP |
1508 SOFT_RESET_CB |
1509 SOFT_RESET_DB |
1510 SOFT_RESET_GDS |
1511 SOFT_RESET_PA |
1512 SOFT_RESET_SC |
1513 SOFT_RESET_SPI |
1514 SOFT_RESET_SH |
1515 SOFT_RESET_SX |
1516 SOFT_RESET_TC |
1517 SOFT_RESET_TA |
1518 SOFT_RESET_VGT |
1519 SOFT_RESET_IA);
1520
1521 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1522 WREG32(GRBM_SOFT_RESET, grbm_reset);
1523 (void)RREG32(GRBM_SOFT_RESET);
1524 udelay(50);
1525 WREG32(GRBM_SOFT_RESET, 0);
1526 (void)RREG32(GRBM_SOFT_RESET);
1527 /* Wait a little for things to settle down */
1528 udelay(50);
1529
1530 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1531 RREG32(GRBM_STATUS));
1532 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1533 RREG32(GRBM_STATUS_SE0));
1534 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1535 RREG32(GRBM_STATUS_SE1));
1536 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1537 RREG32(SRBM_STATUS));
1538 evergreen_mc_resume(rdev, &save);
1539 return 0;
1540 }
1541
cayman_asic_reset(struct radeon_device * rdev)1542 int cayman_asic_reset(struct radeon_device *rdev)
1543 {
1544 return cayman_gpu_soft_reset(rdev);
1545 }
1546
cayman_startup(struct radeon_device * rdev)1547 static int cayman_startup(struct radeon_device *rdev)
1548 {
1549 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1550 int r;
1551
1552 /* enable pcie gen2 link */
1553 evergreen_pcie_gen2_enable(rdev);
1554
1555 evergreen_mc_program(rdev);
1556
1557 if (rdev->flags & RADEON_IS_IGP) {
1558 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1559 r = ni_init_microcode(rdev);
1560 if (r) {
1561 DRM_ERROR("Failed to load firmware!\n");
1562 return r;
1563 }
1564 }
1565 } else {
1566 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1567 r = ni_init_microcode(rdev);
1568 if (r) {
1569 DRM_ERROR("Failed to load firmware!\n");
1570 return r;
1571 }
1572 }
1573
1574 r = ni_mc_load_microcode(rdev);
1575 if (r) {
1576 DRM_ERROR("Failed to load MC firmware!\n");
1577 return r;
1578 }
1579 }
1580
1581 r = r600_vram_scratch_init(rdev);
1582 if (r)
1583 return r;
1584
1585 r = cayman_pcie_gart_enable(rdev);
1586 if (r)
1587 return r;
1588 cayman_gpu_init(rdev);
1589
1590 r = evergreen_blit_init(rdev);
1591 if (r) {
1592 r600_blit_fini(rdev);
1593 rdev->asic->copy.copy = NULL;
1594 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1595 }
1596
1597 /* allocate rlc buffers */
1598 if (rdev->flags & RADEON_IS_IGP) {
1599 r = si_rlc_init(rdev);
1600 if (r) {
1601 DRM_ERROR("Failed to init rlc BOs!\n");
1602 return r;
1603 }
1604 }
1605
1606 /* allocate wb buffer */
1607 r = radeon_wb_init(rdev);
1608 if (r)
1609 return r;
1610
1611 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1612 if (r) {
1613 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1614 return r;
1615 }
1616
1617 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1618 if (r) {
1619 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1620 return r;
1621 }
1622
1623 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1624 if (r) {
1625 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1626 return r;
1627 }
1628
1629 /* Enable IRQ */
1630 if (!rdev->irq.installed) {
1631 r = radeon_irq_kms_init(rdev);
1632 if (r)
1633 return r;
1634 }
1635
1636 r = r600_irq_init(rdev);
1637 if (r) {
1638 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1639 radeon_irq_kms_fini(rdev);
1640 return r;
1641 }
1642 evergreen_irq_set(rdev);
1643
1644 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1645 CP_RB0_RPTR, CP_RB0_WPTR,
1646 0, 0xfffff, RADEON_CP_PACKET2);
1647 if (r)
1648 return r;
1649 r = cayman_cp_load_microcode(rdev);
1650 if (r)
1651 return r;
1652 r = cayman_cp_resume(rdev);
1653 if (r)
1654 return r;
1655
1656 r = radeon_ib_pool_start(rdev);
1657 if (r)
1658 return r;
1659
1660 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1661 if (r) {
1662 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1663 rdev->accel_working = false;
1664 return r;
1665 }
1666
1667 r = radeon_vm_manager_start(rdev);
1668 if (r)
1669 return r;
1670
1671 return 0;
1672 }
1673
cayman_resume(struct radeon_device * rdev)1674 int cayman_resume(struct radeon_device *rdev)
1675 {
1676 int r;
1677
1678 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1679 * posting will perform necessary task to bring back GPU into good
1680 * shape.
1681 */
1682 /* post card */
1683 atom_asic_init(rdev->mode_info.atom_context);
1684
1685 rdev->accel_working = true;
1686 r = cayman_startup(rdev);
1687 if (r) {
1688 DRM_ERROR("cayman startup failed on resume\n");
1689 rdev->accel_working = false;
1690 return r;
1691 }
1692 return r;
1693 }
1694
cayman_suspend(struct radeon_device * rdev)1695 int cayman_suspend(struct radeon_device *rdev)
1696 {
1697 /* FIXME: we should wait for ring to be empty */
1698 radeon_ib_pool_suspend(rdev);
1699 radeon_vm_manager_suspend(rdev);
1700 r600_blit_suspend(rdev);
1701 cayman_cp_enable(rdev, false);
1702 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1703 evergreen_irq_suspend(rdev);
1704 radeon_wb_disable(rdev);
1705 cayman_pcie_gart_disable(rdev);
1706 return 0;
1707 }
1708
1709 /* Plan is to move initialization in that function and use
1710 * helper function so that radeon_device_init pretty much
1711 * do nothing more than calling asic specific function. This
1712 * should also allow to remove a bunch of callback function
1713 * like vram_info.
1714 */
cayman_init(struct radeon_device * rdev)1715 int cayman_init(struct radeon_device *rdev)
1716 {
1717 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1718 int r;
1719
1720 /* This don't do much */
1721 r = radeon_gem_init(rdev);
1722 if (r)
1723 return r;
1724 /* Read BIOS */
1725 if (!radeon_get_bios(rdev)) {
1726 if (ASIC_IS_AVIVO(rdev))
1727 return -EINVAL;
1728 }
1729 /* Must be an ATOMBIOS */
1730 if (!rdev->is_atom_bios) {
1731 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1732 return -EINVAL;
1733 }
1734 r = radeon_atombios_init(rdev);
1735 if (r)
1736 return r;
1737
1738 /* Post card if necessary */
1739 if (!radeon_card_posted(rdev)) {
1740 if (!rdev->bios) {
1741 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1742 return -EINVAL;
1743 }
1744 DRM_INFO("GPU not posted. posting now...\n");
1745 atom_asic_init(rdev->mode_info.atom_context);
1746 }
1747 /* Initialize scratch registers */
1748 r600_scratch_init(rdev);
1749 /* Initialize surface registers */
1750 radeon_surface_init(rdev);
1751 /* Initialize clocks */
1752 radeon_get_clock_info(rdev->ddev);
1753 /* Fence driver */
1754 r = radeon_fence_driver_init(rdev);
1755 if (r)
1756 return r;
1757 /* initialize memory controller */
1758 r = evergreen_mc_init(rdev);
1759 if (r)
1760 return r;
1761 /* Memory manager */
1762 r = radeon_bo_init(rdev);
1763 if (r)
1764 return r;
1765
1766 ring->ring_obj = NULL;
1767 r600_ring_init(rdev, ring, 1024 * 1024);
1768
1769 rdev->ih.ring_obj = NULL;
1770 r600_ih_ring_init(rdev, 64 * 1024);
1771
1772 r = r600_pcie_gart_init(rdev);
1773 if (r)
1774 return r;
1775
1776 r = radeon_ib_pool_init(rdev);
1777 rdev->accel_working = true;
1778 if (r) {
1779 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1780 rdev->accel_working = false;
1781 }
1782 r = radeon_vm_manager_init(rdev);
1783 if (r) {
1784 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1785 }
1786
1787 r = cayman_startup(rdev);
1788 if (r) {
1789 dev_err(rdev->dev, "disabling GPU acceleration\n");
1790 cayman_cp_fini(rdev);
1791 r600_irq_fini(rdev);
1792 if (rdev->flags & RADEON_IS_IGP)
1793 si_rlc_fini(rdev);
1794 radeon_wb_fini(rdev);
1795 r100_ib_fini(rdev);
1796 radeon_vm_manager_fini(rdev);
1797 radeon_irq_kms_fini(rdev);
1798 cayman_pcie_gart_fini(rdev);
1799 rdev->accel_working = false;
1800 }
1801
1802 /* Don't start up if the MC ucode is missing.
1803 * The default clocks and voltages before the MC ucode
1804 * is loaded are not suffient for advanced operations.
1805 *
1806 * We can skip this check for TN, because there is no MC
1807 * ucode.
1808 */
1809 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1810 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1811 return -EINVAL;
1812 }
1813
1814 return 0;
1815 }
1816
cayman_fini(struct radeon_device * rdev)1817 void cayman_fini(struct radeon_device *rdev)
1818 {
1819 r600_blit_fini(rdev);
1820 cayman_cp_fini(rdev);
1821 r600_irq_fini(rdev);
1822 if (rdev->flags & RADEON_IS_IGP)
1823 si_rlc_fini(rdev);
1824 radeon_wb_fini(rdev);
1825 radeon_vm_manager_fini(rdev);
1826 r100_ib_fini(rdev);
1827 radeon_irq_kms_fini(rdev);
1828 cayman_pcie_gart_fini(rdev);
1829 r600_vram_scratch_fini(rdev);
1830 radeon_gem_fini(rdev);
1831 radeon_semaphore_driver_fini(rdev);
1832 radeon_fence_driver_fini(rdev);
1833 radeon_bo_fini(rdev);
1834 radeon_atombios_fini(rdev);
1835 kfree(rdev->bios);
1836 rdev->bios = NULL;
1837 }
1838
1839 /*
1840 * vm
1841 */
cayman_vm_init(struct radeon_device * rdev)1842 int cayman_vm_init(struct radeon_device *rdev)
1843 {
1844 /* number of VMs */
1845 rdev->vm_manager.nvm = 8;
1846 /* base offset of vram pages */
1847 if (rdev->flags & RADEON_IS_IGP) {
1848 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1849 tmp <<= 22;
1850 rdev->vm_manager.vram_base_offset = tmp;
1851 } else
1852 rdev->vm_manager.vram_base_offset = 0;
1853 return 0;
1854 }
1855
cayman_vm_fini(struct radeon_device * rdev)1856 void cayman_vm_fini(struct radeon_device *rdev)
1857 {
1858 }
1859
cayman_vm_bind(struct radeon_device * rdev,struct radeon_vm * vm,int id)1860 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1861 {
1862 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1863 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1864 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1865 /* flush hdp cache */
1866 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1867 /* bits 0-7 are the VM contexts0-7 */
1868 WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1869 return 0;
1870 }
1871
cayman_vm_unbind(struct radeon_device * rdev,struct radeon_vm * vm)1872 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1873 {
1874 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
1875 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
1876 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1877 /* flush hdp cache */
1878 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1879 /* bits 0-7 are the VM contexts0-7 */
1880 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1881 }
1882
cayman_vm_tlb_flush(struct radeon_device * rdev,struct radeon_vm * vm)1883 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1884 {
1885 if (vm->id == -1)
1886 return;
1887
1888 /* flush hdp cache */
1889 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1890 /* bits 0-7 are the VM contexts0-7 */
1891 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1892 }
1893
1894 #define R600_PTE_VALID (1 << 0)
1895 #define R600_PTE_SYSTEM (1 << 1)
1896 #define R600_PTE_SNOOPED (1 << 2)
1897 #define R600_PTE_READABLE (1 << 5)
1898 #define R600_PTE_WRITEABLE (1 << 6)
1899
cayman_vm_page_flags(struct radeon_device * rdev,struct radeon_vm * vm,uint32_t flags)1900 uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
1901 struct radeon_vm *vm,
1902 uint32_t flags)
1903 {
1904 uint32_t r600_flags = 0;
1905
1906 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
1907 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1908 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1909 if (flags & RADEON_VM_PAGE_SYSTEM) {
1910 r600_flags |= R600_PTE_SYSTEM;
1911 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1912 }
1913 return r600_flags;
1914 }
1915
cayman_vm_set_page(struct radeon_device * rdev,struct radeon_vm * vm,unsigned pfn,uint64_t addr,uint32_t flags)1916 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1917 unsigned pfn, uint64_t addr, uint32_t flags)
1918 {
1919 void __iomem *ptr = (void *)vm->pt;
1920
1921 addr = addr & 0xFFFFFFFFFFFFF000ULL;
1922 addr |= flags;
1923 writeq(addr, ptr + (pfn * 8));
1924 }
1925