1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
3 #ifndef IRDMA_MAIN_H
4 #define IRDMA_MAIN_H
5 
6 #include <linux/ip.h>
7 #include <linux/tcp.h>
8 #include <linux/if_vlan.h>
9 #include <net/addrconf.h>
10 #include <net/netevent.h>
11 #include <net/tcp.h>
12 #include <net/ip6_route.h>
13 #include <net/flow.h>
14 #include <net/secure_seq.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/inetdevice.h>
18 #include <linux/spinlock.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/workqueue.h>
24 #include <linux/slab.h>
25 #include <linux/io.h>
26 #include <linux/crc32c.h>
27 #include <linux/kthread.h>
28 #ifndef CONFIG_64BIT
29 #include <linux/io-64-nonatomic-lo-hi.h>
30 #endif
31 #include <linux/auxiliary_bus.h>
32 #include <linux/net/intel/iidc.h>
33 #include <crypto/hash.h>
34 #include <rdma/ib_smi.h>
35 #include <rdma/ib_verbs.h>
36 #include <rdma/ib_pack.h>
37 #include <rdma/rdma_cm.h>
38 #include <rdma/iw_cm.h>
39 #include <rdma/ib_user_verbs.h>
40 #include <rdma/ib_umem.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/uverbs_ioctl.h>
43 #include "osdep.h"
44 #include "defs.h"
45 #include "hmc.h"
46 #include "type.h"
47 #include "ws.h"
48 #include "protos.h"
49 #include "pble.h"
50 #include "cm.h"
51 #include <rdma/irdma-abi.h>
52 #include "verbs.h"
53 #include "user.h"
54 #include "puda.h"
55 
56 extern struct auxiliary_driver i40iw_auxiliary_drv;
57 
58 #define IRDMA_FW_VER_DEFAULT	2
59 #define IRDMA_HW_VER	        2
60 
61 #define IRDMA_ARP_ADD		1
62 #define IRDMA_ARP_DELETE	2
63 #define IRDMA_ARP_RESOLVE	3
64 
65 #define IRDMA_MACIP_ADD		1
66 #define IRDMA_MACIP_DELETE	2
67 
68 #define IW_CCQ_SIZE	(IRDMA_CQP_SW_SQSIZE_2048 + 1)
69 #define IW_CEQ_SIZE	2048
70 #define IW_AEQ_SIZE	2048
71 
72 #define RX_BUF_SIZE	(1536 + 8)
73 #define IW_REG0_SIZE	(4 * 1024)
74 #define IW_TX_TIMEOUT	(6 * HZ)
75 #define IW_FIRST_QPN	1
76 
77 #define IW_SW_CONTEXT_ALIGN	1024
78 
79 #define MAX_DPC_ITERATIONS	128
80 
81 #define IRDMA_EVENT_TIMEOUT		50000
82 #define IRDMA_VCHNL_EVENT_TIMEOUT	100000
83 #define IRDMA_RST_TIMEOUT_HZ		4
84 
85 #define	IRDMA_NO_QSET	0xffff
86 
87 #define IW_CFG_FPM_QP_COUNT		32768
88 #define IRDMA_MAX_PAGES_PER_FMR		262144
89 #define IRDMA_MIN_PAGES_PER_FMR		1
90 #define IRDMA_CQP_COMPL_RQ_WQE_FLUSHED	2
91 #define IRDMA_CQP_COMPL_SQ_WQE_FLUSHED	3
92 
93 #define IRDMA_Q_TYPE_PE_AEQ	0x80
94 #define IRDMA_Q_INVALID_IDX	0xffff
95 #define IRDMA_REM_ENDPOINT_TRK_QPID	3
96 
97 #define IRDMA_DRV_OPT_ENA_MPA_VER_0		0x00000001
98 #define IRDMA_DRV_OPT_DISABLE_MPA_CRC		0x00000002
99 #define IRDMA_DRV_OPT_DISABLE_FIRST_WRITE	0x00000004
100 #define IRDMA_DRV_OPT_DISABLE_INTF		0x00000008
101 #define IRDMA_DRV_OPT_ENA_MSI			0x00000010
102 #define IRDMA_DRV_OPT_DUAL_LOGICAL_PORT		0x00000020
103 #define IRDMA_DRV_OPT_NO_INLINE_DATA		0x00000080
104 #define IRDMA_DRV_OPT_DISABLE_INT_MOD		0x00000100
105 #define IRDMA_DRV_OPT_DISABLE_VIRT_WQ		0x00000200
106 #define IRDMA_DRV_OPT_ENA_PAU			0x00000400
107 #define IRDMA_DRV_OPT_MCAST_LOGPORT_MAP		0x00000800
108 
109 #define IW_HMC_OBJ_TYPE_NUM	ARRAY_SIZE(iw_hmc_obj_types)
110 #define IRDMA_ROCE_CWND_DEFAULT			0x400
111 #define IRDMA_ROCE_ACKCREDS_DEFAULT		0x1E
112 
113 #define IRDMA_FLUSH_SQ		BIT(0)
114 #define IRDMA_FLUSH_RQ		BIT(1)
115 #define IRDMA_REFLUSH		BIT(2)
116 #define IRDMA_FLUSH_WAIT	BIT(3)
117 
118 enum init_completion_state {
119 	INVALID_STATE = 0,
120 	INITIAL_STATE,
121 	CQP_CREATED,
122 	HMC_OBJS_CREATED,
123 	HW_RSRC_INITIALIZED,
124 	CCQ_CREATED,
125 	CEQ0_CREATED, /* Last state of probe */
126 	ILQ_CREATED,
127 	IEQ_CREATED,
128 	CEQS_CREATED,
129 	PBLE_CHUNK_MEM,
130 	AEQ_CREATED,
131 	IP_ADDR_REGISTERED,  /* Last state of open */
132 };
133 
134 struct irdma_rsrc_limits {
135 	u32 qplimit;
136 	u32 mrlimit;
137 	u32 cqlimit;
138 };
139 
140 struct irdma_cqp_err_info {
141 	u16 maj;
142 	u16 min;
143 	const char *desc;
144 };
145 
146 struct irdma_cqp_compl_info {
147 	u32 op_ret_val;
148 	u16 maj_err_code;
149 	u16 min_err_code;
150 	bool error;
151 	u8 op_code;
152 };
153 
154 struct irdma_cqp_request {
155 	struct cqp_cmds_info info;
156 	wait_queue_head_t waitq;
157 	struct list_head list;
158 	refcount_t refcnt;
159 	void (*callback_fcn)(struct irdma_cqp_request *cqp_request);
160 	void *param;
161 	struct irdma_cqp_compl_info compl_info;
162 	bool waiting:1;
163 	bool request_done:1;
164 	bool dynamic:1;
165 };
166 
167 struct irdma_cqp {
168 	struct irdma_sc_cqp sc_cqp;
169 	spinlock_t req_lock; /* protect CQP request list */
170 	spinlock_t compl_lock; /* protect CQP completion processing */
171 	wait_queue_head_t waitq;
172 	wait_queue_head_t remove_wq;
173 	struct irdma_dma_mem sq;
174 	struct irdma_dma_mem host_ctx;
175 	u64 *scratch_array;
176 	struct irdma_cqp_request *cqp_requests;
177 	struct list_head cqp_avail_reqs;
178 	struct list_head cqp_pending_reqs;
179 };
180 
181 struct irdma_ccq {
182 	struct irdma_sc_cq sc_cq;
183 	struct irdma_dma_mem mem_cq;
184 	struct irdma_dma_mem shadow_area;
185 };
186 
187 struct irdma_ceq {
188 	struct irdma_sc_ceq sc_ceq;
189 	struct irdma_dma_mem mem;
190 	u32 irq;
191 	u32 msix_idx;
192 	struct irdma_pci_f *rf;
193 	struct tasklet_struct dpc_tasklet;
194 	spinlock_t ce_lock; /* sync cq destroy with cq completion event notification */
195 };
196 
197 struct irdma_aeq {
198 	struct irdma_sc_aeq sc_aeq;
199 	struct irdma_dma_mem mem;
200 	struct irdma_pble_alloc palloc;
201 	bool virtual_map;
202 };
203 
204 struct irdma_arp_entry {
205 	u32 ip_addr[4];
206 	u8 mac_addr[ETH_ALEN];
207 };
208 
209 struct irdma_msix_vector {
210 	u32 idx;
211 	u32 irq;
212 	u32 cpu_affinity;
213 	u32 ceq_id;
214 	cpumask_t mask;
215 };
216 
217 struct irdma_mc_table_info {
218 	u32 mgn;
219 	u32 dest_ip[4];
220 	bool lan_fwd:1;
221 	bool ipv4_valid:1;
222 };
223 
224 struct mc_table_list {
225 	struct list_head list;
226 	struct irdma_mc_table_info mc_info;
227 	struct irdma_mcast_grp_info mc_grp_ctx;
228 };
229 
230 struct irdma_qv_info {
231 	u32 v_idx; /* msix_vector */
232 	u16 ceq_idx;
233 	u16 aeq_idx;
234 	u8 itr_idx;
235 };
236 
237 struct irdma_qvlist_info {
238 	u32 num_vectors;
239 	struct irdma_qv_info qv_info[1];
240 };
241 
242 struct irdma_gen_ops {
243 	void (*request_reset)(struct irdma_pci_f *rf);
244 	int (*register_qset)(struct irdma_sc_vsi *vsi,
245 			     struct irdma_ws_node *tc_node);
246 	void (*unregister_qset)(struct irdma_sc_vsi *vsi,
247 				struct irdma_ws_node *tc_node);
248 };
249 
250 struct irdma_pci_f {
251 	bool reset:1;
252 	bool rsrc_created:1;
253 	bool msix_shared:1;
254 	u8 rsrc_profile;
255 	u8 *hmc_info_mem;
256 	u8 *mem_rsrc;
257 	u8 rdma_ver;
258 	u8 rst_to;
259 	u8 pf_id;
260 	enum irdma_protocol_used protocol_used;
261 	u32 sd_type;
262 	u32 msix_count;
263 	u32 max_mr;
264 	u32 max_qp;
265 	u32 max_cq;
266 	u32 max_ah;
267 	u32 next_ah;
268 	u32 max_mcg;
269 	u32 next_mcg;
270 	u32 max_pd;
271 	u32 next_qp;
272 	u32 next_cq;
273 	u32 next_pd;
274 	u32 max_mr_size;
275 	u32 max_cqe;
276 	u32 mr_stagmask;
277 	u32 used_pds;
278 	u32 used_cqs;
279 	u32 used_mrs;
280 	u32 used_qps;
281 	u32 arp_table_size;
282 	u32 next_arp_index;
283 	u32 ceqs_count;
284 	u32 next_ws_node_id;
285 	u32 max_ws_node_id;
286 	u32 limits_sel;
287 	unsigned long *allocated_ws_nodes;
288 	unsigned long *allocated_qps;
289 	unsigned long *allocated_cqs;
290 	unsigned long *allocated_mrs;
291 	unsigned long *allocated_pds;
292 	unsigned long *allocated_mcgs;
293 	unsigned long *allocated_ahs;
294 	unsigned long *allocated_arps;
295 	enum init_completion_state init_state;
296 	struct irdma_sc_dev sc_dev;
297 	struct pci_dev *pcidev;
298 	void *cdev;
299 	struct irdma_hw hw;
300 	struct irdma_cqp cqp;
301 	struct irdma_ccq ccq;
302 	struct irdma_aeq aeq;
303 	struct irdma_ceq *ceqlist;
304 	struct irdma_hmc_pble_rsrc *pble_rsrc;
305 	struct irdma_arp_entry *arp_table;
306 	spinlock_t arp_lock; /*protect ARP table access*/
307 	spinlock_t rsrc_lock; /* protect HW resource array access */
308 	spinlock_t qptable_lock; /*protect QP table access*/
309 	struct irdma_qp **qp_table;
310 	spinlock_t qh_list_lock; /* protect mc_qht_list */
311 	struct mc_table_list mc_qht_list;
312 	struct irdma_msix_vector *iw_msixtbl;
313 	struct irdma_qvlist_info *iw_qvlist;
314 	struct tasklet_struct dpc_tasklet;
315 	struct msix_entry *msix_entries;
316 	struct irdma_dma_mem obj_mem;
317 	struct irdma_dma_mem obj_next;
318 	atomic_t vchnl_msgs;
319 	wait_queue_head_t vchnl_waitq;
320 	struct workqueue_struct *cqp_cmpl_wq;
321 	struct work_struct cqp_cmpl_work;
322 	struct irdma_sc_vsi default_vsi;
323 	void *back_fcn;
324 	struct irdma_gen_ops gen_ops;
325 	struct irdma_device *iwdev;
326 };
327 
328 struct irdma_device {
329 	struct ib_device ibdev;
330 	struct irdma_pci_f *rf;
331 	struct net_device *netdev;
332 	struct workqueue_struct *cleanup_wq;
333 	struct irdma_sc_vsi vsi;
334 	struct irdma_cm_core cm_core;
335 	DECLARE_HASHTABLE(ah_hash_tbl, 8);
336 	struct mutex ah_tbl_lock; /* protect AH hash table access */
337 	u32 roce_cwnd;
338 	u32 roce_ackcreds;
339 	u32 vendor_id;
340 	u32 vendor_part_id;
341 	u32 push_mode;
342 	u32 rcv_wnd;
343 	u16 mac_ip_table_idx;
344 	u16 vsi_num;
345 	u8 rcv_wscale;
346 	u8 iw_status;
347 	bool roce_mode:1;
348 	bool roce_dcqcn_en:1;
349 	bool dcb_vlan_mode:1;
350 	bool iw_ooo:1;
351 	enum init_completion_state init_state;
352 
353 	wait_queue_head_t suspend_wq;
354 };
355 
to_iwdev(struct ib_device * ibdev)356 static inline struct irdma_device *to_iwdev(struct ib_device *ibdev)
357 {
358 	return container_of(ibdev, struct irdma_device, ibdev);
359 }
360 
to_ucontext(struct ib_ucontext * ibucontext)361 static inline struct irdma_ucontext *to_ucontext(struct ib_ucontext *ibucontext)
362 {
363 	return container_of(ibucontext, struct irdma_ucontext, ibucontext);
364 }
365 
366 static inline struct irdma_user_mmap_entry *
to_irdma_mmap_entry(struct rdma_user_mmap_entry * rdma_entry)367 to_irdma_mmap_entry(struct rdma_user_mmap_entry *rdma_entry)
368 {
369 	return container_of(rdma_entry, struct irdma_user_mmap_entry,
370 			    rdma_entry);
371 }
372 
to_iwpd(struct ib_pd * ibpd)373 static inline struct irdma_pd *to_iwpd(struct ib_pd *ibpd)
374 {
375 	return container_of(ibpd, struct irdma_pd, ibpd);
376 }
377 
to_iwah(struct ib_ah * ibah)378 static inline struct irdma_ah *to_iwah(struct ib_ah *ibah)
379 {
380 	return container_of(ibah, struct irdma_ah, ibah);
381 }
382 
to_iwmr(struct ib_mr * ibmr)383 static inline struct irdma_mr *to_iwmr(struct ib_mr *ibmr)
384 {
385 	return container_of(ibmr, struct irdma_mr, ibmr);
386 }
387 
to_iwmw(struct ib_mw * ibmw)388 static inline struct irdma_mr *to_iwmw(struct ib_mw *ibmw)
389 {
390 	return container_of(ibmw, struct irdma_mr, ibmw);
391 }
392 
to_iwcq(struct ib_cq * ibcq)393 static inline struct irdma_cq *to_iwcq(struct ib_cq *ibcq)
394 {
395 	return container_of(ibcq, struct irdma_cq, ibcq);
396 }
397 
to_iwqp(struct ib_qp * ibqp)398 static inline struct irdma_qp *to_iwqp(struct ib_qp *ibqp)
399 {
400 	return container_of(ibqp, struct irdma_qp, ibqp);
401 }
402 
dev_to_rf(struct irdma_sc_dev * dev)403 static inline struct irdma_pci_f *dev_to_rf(struct irdma_sc_dev *dev)
404 {
405 	return container_of(dev, struct irdma_pci_f, sc_dev);
406 }
407 
408 /**
409  * irdma_alloc_resource - allocate a resource
410  * @iwdev: device pointer
411  * @resource_array: resource bit array:
412  * @max_resources: maximum resource number
413  * @req_resources_num: Allocated resource number
414  * @next: next free id
415  **/
irdma_alloc_rsrc(struct irdma_pci_f * rf,unsigned long * rsrc_array,u32 max_rsrc,u32 * req_rsrc_num,u32 * next)416 static inline int irdma_alloc_rsrc(struct irdma_pci_f *rf,
417 				   unsigned long *rsrc_array, u32 max_rsrc,
418 				   u32 *req_rsrc_num, u32 *next)
419 {
420 	u32 rsrc_num;
421 	unsigned long flags;
422 
423 	spin_lock_irqsave(&rf->rsrc_lock, flags);
424 	rsrc_num = find_next_zero_bit(rsrc_array, max_rsrc, *next);
425 	if (rsrc_num >= max_rsrc) {
426 		rsrc_num = find_first_zero_bit(rsrc_array, max_rsrc);
427 		if (rsrc_num >= max_rsrc) {
428 			spin_unlock_irqrestore(&rf->rsrc_lock, flags);
429 			ibdev_dbg(&rf->iwdev->ibdev,
430 				  "ERR: resource [%d] allocation failed\n",
431 				  rsrc_num);
432 			return -EOVERFLOW;
433 		}
434 	}
435 	__set_bit(rsrc_num, rsrc_array);
436 	*next = rsrc_num + 1;
437 	if (*next == max_rsrc)
438 		*next = 0;
439 	*req_rsrc_num = rsrc_num;
440 	spin_unlock_irqrestore(&rf->rsrc_lock, flags);
441 
442 	return 0;
443 }
444 
445 /**
446  * irdma_free_resource - free a resource
447  * @iwdev: device pointer
448  * @resource_array: resource array for the resource_num
449  * @resource_num: resource number to free
450  **/
irdma_free_rsrc(struct irdma_pci_f * rf,unsigned long * rsrc_array,u32 rsrc_num)451 static inline void irdma_free_rsrc(struct irdma_pci_f *rf,
452 				   unsigned long *rsrc_array, u32 rsrc_num)
453 {
454 	unsigned long flags;
455 
456 	spin_lock_irqsave(&rf->rsrc_lock, flags);
457 	__clear_bit(rsrc_num, rsrc_array);
458 	spin_unlock_irqrestore(&rf->rsrc_lock, flags);
459 }
460 
461 int irdma_ctrl_init_hw(struct irdma_pci_f *rf);
462 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf);
463 int irdma_rt_init_hw(struct irdma_device *iwdev,
464 		     struct irdma_l2params *l2params);
465 void irdma_rt_deinit_hw(struct irdma_device *iwdev);
466 void irdma_qp_add_ref(struct ib_qp *ibqp);
467 void irdma_qp_rem_ref(struct ib_qp *ibqp);
468 void irdma_free_lsmm_rsrc(struct irdma_qp *iwqp);
469 struct ib_qp *irdma_get_qp(struct ib_device *ibdev, int qpn);
470 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask);
471 void irdma_manage_arp_cache(struct irdma_pci_f *rf,
472 			    const unsigned char *mac_addr,
473 			    u32 *ip_addr, bool ipv4, u32 action);
474 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port);
475 void irdma_del_apbvt(struct irdma_device *iwdev,
476 		     struct irdma_apbvt_entry *entry);
477 struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp,
478 							  bool wait);
479 void irdma_free_cqp_request(struct irdma_cqp *cqp,
480 			    struct irdma_cqp_request *cqp_request);
481 void irdma_put_cqp_request(struct irdma_cqp *cqp,
482 			   struct irdma_cqp_request *cqp_request);
483 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx);
484 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx);
485 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx);
486 
487 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf);
488 void irdma_port_ibevent(struct irdma_device *iwdev);
489 void irdma_cm_disconn(struct irdma_qp *qp);
490 
491 bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd,
492 			u16 maj_err_code, u16 min_err_code);
493 int irdma_handle_cqp_op(struct irdma_pci_f *rf,
494 			struct irdma_cqp_request *cqp_request);
495 
496 int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
497 		    struct ib_udata *udata);
498 int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,
499 			 int attr_mask, struct ib_udata *udata);
500 void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq);
501 
502 void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf);
503 int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp,
504 		       struct irdma_modify_qp_info *info, bool wait);
505 int irdma_qp_suspend_resume(struct irdma_sc_qp *qp, bool suspend);
506 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
507 		       enum irdma_quad_entry_type etype,
508 		       enum irdma_quad_hash_manage_type mtype, void *cmnode,
509 		       bool wait);
510 void irdma_receive_ilq(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *rbuf);
511 void irdma_free_sqbuf(struct irdma_sc_vsi *vsi, void *bufp);
512 void irdma_free_qp_rsrc(struct irdma_qp *iwqp);
513 int irdma_setup_cm_core(struct irdma_device *iwdev, u8 ver);
514 void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core);
515 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
516 			 u8 term_len);
517 int irdma_send_syn(struct irdma_cm_node *cm_node, u32 sendack);
518 int irdma_send_reset(struct irdma_cm_node *cm_node);
519 struct irdma_cm_node *irdma_find_node(struct irdma_cm_core *cm_core,
520 				      u16 rem_port, u32 *rem_addr, u16 loc_port,
521 				      u32 *loc_addr, u16 vlan_id);
522 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
523 			struct irdma_qp_flush_info *info, bool wait);
524 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
525 		  struct irdma_gen_ae_info *info, bool wait);
526 void irdma_copy_ip_ntohl(u32 *dst, __be32 *src);
527 void irdma_copy_ip_htonl(__be32 *dst, u32 *src);
528 u16 irdma_get_vlan_ipv4(u32 *addr);
529 struct net_device *irdma_netdev_vlan_ipv6(u32 *addr, u16 *vlan_id, u8 *mac);
530 struct ib_mr *irdma_reg_phys_mr(struct ib_pd *ib_pd, u64 addr, u64 size,
531 				int acc, u64 *iova_start);
532 int irdma_upload_qp_context(struct irdma_qp *iwqp, bool freeze, bool raw);
533 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq);
534 int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd,
535 		    bool wait,
536 		    void (*callback_fcn)(struct irdma_cqp_request *cqp_request),
537 		    void *cb_param);
538 void irdma_gsi_ud_qp_ah_cb(struct irdma_cqp_request *cqp_request);
539 bool irdma_cq_empty(struct irdma_cq *iwcq);
540 int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event,
541 			 void *ptr);
542 int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event,
543 			  void *ptr);
544 int irdma_net_event(struct notifier_block *notifier, unsigned long event,
545 		    void *ptr);
546 int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event,
547 			  void *ptr);
548 void irdma_add_ip(struct irdma_device *iwdev);
549 void cqp_compl_worker(struct work_struct *work);
550 #endif /* IRDMA_MAIN_H */
551