1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * TI Camera Access Layer (CAL) - Driver
4  *
5  * Copyright (c) 2015-2020 Texas Instruments Inc.
6  *
7  * Authors:
8  *	Benoit Parrot <bparrot@ti.com>
9  *	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 
23 #include <media/media-device.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-common.h>
26 #include <media/v4l2-device.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
29 
30 #include "cal.h"
31 #include "cal_regs.h"
32 
33 MODULE_DESCRIPTION("TI CAL driver");
34 MODULE_AUTHOR("Benoit Parrot, <bparrot@ti.com>");
35 MODULE_LICENSE("GPL v2");
36 MODULE_VERSION("0.1.0");
37 
38 int cal_video_nr = -1;
39 module_param_named(video_nr, cal_video_nr, uint, 0644);
40 MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect");
41 
42 unsigned int cal_debug;
43 module_param_named(debug, cal_debug, uint, 0644);
44 MODULE_PARM_DESC(debug, "activates debug info");
45 
46 #ifdef CONFIG_VIDEO_TI_CAL_MC
47 #define CAL_MC_API_DEFAULT 1
48 #else
49 #define CAL_MC_API_DEFAULT 0
50 #endif
51 
52 bool cal_mc_api = CAL_MC_API_DEFAULT;
53 module_param_named(mc_api, cal_mc_api, bool, 0444);
54 MODULE_PARM_DESC(mc_api, "activates the MC API");
55 
56 /* ------------------------------------------------------------------
57  *	Format Handling
58  * ------------------------------------------------------------------
59  */
60 
61 const struct cal_format_info cal_formats[] = {
62 	{
63 		.fourcc		= V4L2_PIX_FMT_YUYV,
64 		.code		= MEDIA_BUS_FMT_YUYV8_1X16,
65 		.bpp		= 16,
66 	}, {
67 		.fourcc		= V4L2_PIX_FMT_UYVY,
68 		.code		= MEDIA_BUS_FMT_UYVY8_1X16,
69 		.bpp		= 16,
70 	}, {
71 		.fourcc		= V4L2_PIX_FMT_YVYU,
72 		.code		= MEDIA_BUS_FMT_YVYU8_1X16,
73 		.bpp		= 16,
74 	}, {
75 		.fourcc		= V4L2_PIX_FMT_VYUY,
76 		.code		= MEDIA_BUS_FMT_VYUY8_1X16,
77 		.bpp		= 16,
78 	}, {
79 		.fourcc		= V4L2_PIX_FMT_RGB565,
80 		.code		= MEDIA_BUS_FMT_RGB565_1X16,
81 		.bpp		= 16,
82 	}, {
83 		.fourcc		= V4L2_PIX_FMT_SBGGR8,
84 		.code		= MEDIA_BUS_FMT_SBGGR8_1X8,
85 		.bpp		= 8,
86 	}, {
87 		.fourcc		= V4L2_PIX_FMT_SGBRG8,
88 		.code		= MEDIA_BUS_FMT_SGBRG8_1X8,
89 		.bpp		= 8,
90 	}, {
91 		.fourcc		= V4L2_PIX_FMT_SGRBG8,
92 		.code		= MEDIA_BUS_FMT_SGRBG8_1X8,
93 		.bpp		= 8,
94 	}, {
95 		.fourcc		= V4L2_PIX_FMT_SRGGB8,
96 		.code		= MEDIA_BUS_FMT_SRGGB8_1X8,
97 		.bpp		= 8,
98 	}, {
99 		.fourcc		= V4L2_PIX_FMT_SBGGR10,
100 		.code		= MEDIA_BUS_FMT_SBGGR10_1X10,
101 		.bpp		= 10,
102 	}, {
103 		.fourcc		= V4L2_PIX_FMT_SGBRG10,
104 		.code		= MEDIA_BUS_FMT_SGBRG10_1X10,
105 		.bpp		= 10,
106 	}, {
107 		.fourcc		= V4L2_PIX_FMT_SGRBG10,
108 		.code		= MEDIA_BUS_FMT_SGRBG10_1X10,
109 		.bpp		= 10,
110 	}, {
111 		.fourcc		= V4L2_PIX_FMT_SRGGB10,
112 		.code		= MEDIA_BUS_FMT_SRGGB10_1X10,
113 		.bpp		= 10,
114 	}, {
115 		.fourcc		= V4L2_PIX_FMT_SBGGR12,
116 		.code		= MEDIA_BUS_FMT_SBGGR12_1X12,
117 		.bpp		= 12,
118 	}, {
119 		.fourcc		= V4L2_PIX_FMT_SGBRG12,
120 		.code		= MEDIA_BUS_FMT_SGBRG12_1X12,
121 		.bpp		= 12,
122 	}, {
123 		.fourcc		= V4L2_PIX_FMT_SGRBG12,
124 		.code		= MEDIA_BUS_FMT_SGRBG12_1X12,
125 		.bpp		= 12,
126 	}, {
127 		.fourcc		= V4L2_PIX_FMT_SRGGB12,
128 		.code		= MEDIA_BUS_FMT_SRGGB12_1X12,
129 		.bpp		= 12,
130 	},
131 };
132 
133 const unsigned int cal_num_formats = ARRAY_SIZE(cal_formats);
134 
cal_format_by_fourcc(u32 fourcc)135 const struct cal_format_info *cal_format_by_fourcc(u32 fourcc)
136 {
137 	unsigned int i;
138 
139 	for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) {
140 		if (cal_formats[i].fourcc == fourcc)
141 			return &cal_formats[i];
142 	}
143 
144 	return NULL;
145 }
146 
cal_format_by_code(u32 code)147 const struct cal_format_info *cal_format_by_code(u32 code)
148 {
149 	unsigned int i;
150 
151 	for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) {
152 		if (cal_formats[i].code == code)
153 			return &cal_formats[i];
154 	}
155 
156 	return NULL;
157 }
158 
159 /* ------------------------------------------------------------------
160  *	Platform Data
161  * ------------------------------------------------------------------
162  */
163 
164 static const struct cal_camerarx_data dra72x_cal_camerarx[] = {
165 	{
166 		.fields = {
167 			[F_CTRLCLKEN] = { 10, 10 },
168 			[F_CAMMODE] = { 11, 12 },
169 			[F_LANEENABLE] = { 13, 16 },
170 			[F_CSI_MODE] = { 17, 17 },
171 		},
172 		.num_lanes = 4,
173 	},
174 	{
175 		.fields = {
176 			[F_CTRLCLKEN] = { 0, 0 },
177 			[F_CAMMODE] = { 1, 2 },
178 			[F_LANEENABLE] = { 3, 4 },
179 			[F_CSI_MODE] = { 5, 5 },
180 		},
181 		.num_lanes = 2,
182 	},
183 };
184 
185 static const struct cal_data dra72x_cal_data = {
186 	.camerarx = dra72x_cal_camerarx,
187 	.num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
188 };
189 
190 static const struct cal_data dra72x_es1_cal_data = {
191 	.camerarx = dra72x_cal_camerarx,
192 	.num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
193 	.flags = DRA72_CAL_PRE_ES2_LDO_DISABLE,
194 };
195 
196 static const struct cal_camerarx_data dra76x_cal_csi_phy[] = {
197 	{
198 		.fields = {
199 			[F_CTRLCLKEN] = { 8, 8 },
200 			[F_CAMMODE] = { 9, 10 },
201 			[F_CSI_MODE] = { 11, 11 },
202 			[F_LANEENABLE] = { 27, 31 },
203 		},
204 		.num_lanes = 5,
205 	},
206 	{
207 		.fields = {
208 			[F_CTRLCLKEN] = { 0, 0 },
209 			[F_CAMMODE] = { 1, 2 },
210 			[F_CSI_MODE] = { 3, 3 },
211 			[F_LANEENABLE] = { 24, 26 },
212 		},
213 		.num_lanes = 3,
214 	},
215 };
216 
217 static const struct cal_data dra76x_cal_data = {
218 	.camerarx = dra76x_cal_csi_phy,
219 	.num_csi2_phy = ARRAY_SIZE(dra76x_cal_csi_phy),
220 };
221 
222 static const struct cal_camerarx_data am654_cal_csi_phy[] = {
223 	{
224 		.fields = {
225 			[F_CTRLCLKEN] = { 15, 15 },
226 			[F_CAMMODE] = { 24, 25 },
227 			[F_LANEENABLE] = { 0, 4 },
228 		},
229 		.num_lanes = 5,
230 	},
231 };
232 
233 static const struct cal_data am654_cal_data = {
234 	.camerarx = am654_cal_csi_phy,
235 	.num_csi2_phy = ARRAY_SIZE(am654_cal_csi_phy),
236 };
237 
238 /* ------------------------------------------------------------------
239  *	I/O Register Accessors
240  * ------------------------------------------------------------------
241  */
242 
cal_quickdump_regs(struct cal_dev * cal)243 void cal_quickdump_regs(struct cal_dev *cal)
244 {
245 	unsigned int i;
246 
247 	cal_info(cal, "CAL Registers @ 0x%pa:\n", &cal->res->start);
248 	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
249 		       (__force const void *)cal->base,
250 		       resource_size(cal->res), false);
251 
252 	for (i = 0; i < cal->data->num_csi2_phy; ++i) {
253 		struct cal_camerarx *phy = cal->phy[i];
254 
255 		cal_info(cal, "CSI2 Core %u Registers @ %pa:\n", i,
256 			 &phy->res->start);
257 		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
258 			       (__force const void *)phy->base,
259 			       resource_size(phy->res),
260 			       false);
261 	}
262 }
263 
264 /* ------------------------------------------------------------------
265  *	Context Management
266  * ------------------------------------------------------------------
267  */
268 
269 #define CAL_MAX_PIX_PROC 4
270 
cal_reserve_pix_proc(struct cal_dev * cal)271 static int cal_reserve_pix_proc(struct cal_dev *cal)
272 {
273 	unsigned long ret;
274 
275 	spin_lock(&cal->v4l2_dev.lock);
276 
277 	ret = find_first_zero_bit(&cal->reserved_pix_proc_mask, CAL_MAX_PIX_PROC);
278 
279 	if (ret == CAL_MAX_PIX_PROC) {
280 		spin_unlock(&cal->v4l2_dev.lock);
281 		return -ENOSPC;
282 	}
283 
284 	cal->reserved_pix_proc_mask |= BIT(ret);
285 
286 	spin_unlock(&cal->v4l2_dev.lock);
287 
288 	return ret;
289 }
290 
cal_release_pix_proc(struct cal_dev * cal,unsigned int pix_proc_num)291 static void cal_release_pix_proc(struct cal_dev *cal, unsigned int pix_proc_num)
292 {
293 	spin_lock(&cal->v4l2_dev.lock);
294 
295 	cal->reserved_pix_proc_mask &= ~BIT(pix_proc_num);
296 
297 	spin_unlock(&cal->v4l2_dev.lock);
298 }
299 
cal_ctx_csi2_config(struct cal_ctx * ctx)300 static void cal_ctx_csi2_config(struct cal_ctx *ctx)
301 {
302 	u32 val;
303 
304 	val = cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx));
305 	cal_set_field(&val, ctx->cport, CAL_CSI2_CTX_CPORT_MASK);
306 	/*
307 	 * DT type: MIPI CSI-2 Specs
308 	 *   0x1: All - DT filter is disabled
309 	 *  0x24: RGB888 1 pixel  = 3 bytes
310 	 *  0x2B: RAW10  4 pixels = 5 bytes
311 	 *  0x2A: RAW8   1 pixel  = 1 byte
312 	 *  0x1E: YUV422 2 pixels = 4 bytes
313 	 */
314 	cal_set_field(&val, ctx->datatype, CAL_CSI2_CTX_DT_MASK);
315 	cal_set_field(&val, ctx->vc, CAL_CSI2_CTX_VC_MASK);
316 	cal_set_field(&val, ctx->v_fmt.fmt.pix.height, CAL_CSI2_CTX_LINES_MASK);
317 	cal_set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);
318 	cal_set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,
319 		      CAL_CSI2_CTX_PACK_MODE_MASK);
320 	cal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), val);
321 	ctx_dbg(3, ctx, "CAL_CSI2_CTX(%u, %u) = 0x%08x\n",
322 		ctx->phy->instance, ctx->csi2_ctx,
323 		cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx)));
324 }
325 
cal_ctx_pix_proc_config(struct cal_ctx * ctx)326 static void cal_ctx_pix_proc_config(struct cal_ctx *ctx)
327 {
328 	u32 val, extract, pack;
329 
330 	switch (ctx->fmtinfo->bpp) {
331 	case 8:
332 		extract = CAL_PIX_PROC_EXTRACT_B8;
333 		pack = CAL_PIX_PROC_PACK_B8;
334 		break;
335 	case 10:
336 		extract = CAL_PIX_PROC_EXTRACT_B10_MIPI;
337 		pack = CAL_PIX_PROC_PACK_B16;
338 		break;
339 	case 12:
340 		extract = CAL_PIX_PROC_EXTRACT_B12_MIPI;
341 		pack = CAL_PIX_PROC_PACK_B16;
342 		break;
343 	case 16:
344 		extract = CAL_PIX_PROC_EXTRACT_B16_LE;
345 		pack = CAL_PIX_PROC_PACK_B16;
346 		break;
347 	default:
348 		/*
349 		 * If you see this warning then it means that you added
350 		 * some new entry in the cal_formats[] array with a different
351 		 * bit per pixel values then the one supported below.
352 		 * Either add support for the new bpp value below or adjust
353 		 * the new entry to use one of the value below.
354 		 *
355 		 * Instead of failing here just use 8 bpp as a default.
356 		 */
357 		dev_warn_once(ctx->cal->dev,
358 			      "%s:%d:%s: bpp:%d unsupported! Overwritten with 8.\n",
359 			      __FILE__, __LINE__, __func__, ctx->fmtinfo->bpp);
360 		extract = CAL_PIX_PROC_EXTRACT_B8;
361 		pack = CAL_PIX_PROC_PACK_B8;
362 		break;
363 	}
364 
365 	val = cal_read(ctx->cal, CAL_PIX_PROC(ctx->pix_proc));
366 	cal_set_field(&val, extract, CAL_PIX_PROC_EXTRACT_MASK);
367 	cal_set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK);
368 	cal_set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);
369 	cal_set_field(&val, pack, CAL_PIX_PROC_PACK_MASK);
370 	cal_set_field(&val, ctx->cport, CAL_PIX_PROC_CPORT_MASK);
371 	cal_set_field(&val, 1, CAL_PIX_PROC_EN_MASK);
372 	cal_write(ctx->cal, CAL_PIX_PROC(ctx->pix_proc), val);
373 	ctx_dbg(3, ctx, "CAL_PIX_PROC(%u) = 0x%08x\n", ctx->pix_proc,
374 		cal_read(ctx->cal, CAL_PIX_PROC(ctx->pix_proc)));
375 }
376 
cal_ctx_wr_dma_config(struct cal_ctx * ctx)377 static void cal_ctx_wr_dma_config(struct cal_ctx *ctx)
378 {
379 	unsigned int stride = ctx->v_fmt.fmt.pix.bytesperline;
380 	u32 val;
381 
382 	val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
383 	cal_set_field(&val, ctx->cport, CAL_WR_DMA_CTRL_CPORT_MASK);
384 	cal_set_field(&val, ctx->v_fmt.fmt.pix.height,
385 		      CAL_WR_DMA_CTRL_YSIZE_MASK);
386 	cal_set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,
387 		      CAL_WR_DMA_CTRL_DTAG_MASK);
388 	cal_set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
389 		      CAL_WR_DMA_CTRL_PATTERN_MASK);
390 	cal_set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK);
391 	cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val);
392 	ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->dma_ctx,
393 		cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx)));
394 
395 	cal_write_field(ctx->cal, CAL_WR_DMA_OFST(ctx->dma_ctx),
396 			stride / 16, CAL_WR_DMA_OFST_MASK);
397 	ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->dma_ctx,
398 		cal_read(ctx->cal, CAL_WR_DMA_OFST(ctx->dma_ctx)));
399 
400 	val = cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx));
401 	/* 64 bit word means no skipping */
402 	cal_set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK);
403 	/*
404 	 * The XSIZE field is expressed in 64-bit units and prevents overflows
405 	 * in case of synchronization issues by limiting the number of bytes
406 	 * written per line.
407 	 */
408 	cal_set_field(&val, stride / 8, CAL_WR_DMA_XSIZE_MASK);
409 	cal_write(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx), val);
410 	ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->dma_ctx,
411 		cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx)));
412 }
413 
cal_ctx_set_dma_addr(struct cal_ctx * ctx,dma_addr_t addr)414 void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr)
415 {
416 	cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->dma_ctx), addr);
417 }
418 
cal_ctx_wr_dma_enable(struct cal_ctx * ctx)419 static void cal_ctx_wr_dma_enable(struct cal_ctx *ctx)
420 {
421 	u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
422 
423 	cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
424 		      CAL_WR_DMA_CTRL_MODE_MASK);
425 	cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val);
426 }
427 
cal_ctx_wr_dma_disable(struct cal_ctx * ctx)428 static void cal_ctx_wr_dma_disable(struct cal_ctx *ctx)
429 {
430 	u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
431 
432 	cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_DIS,
433 		      CAL_WR_DMA_CTRL_MODE_MASK);
434 	cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val);
435 }
436 
cal_ctx_wr_dma_stopped(struct cal_ctx * ctx)437 static bool cal_ctx_wr_dma_stopped(struct cal_ctx *ctx)
438 {
439 	bool stopped;
440 
441 	spin_lock_irq(&ctx->dma.lock);
442 	stopped = ctx->dma.state == CAL_DMA_STOPPED;
443 	spin_unlock_irq(&ctx->dma.lock);
444 
445 	return stopped;
446 }
447 
448 static int
cal_get_remote_frame_desc_entry(struct cal_ctx * ctx,struct v4l2_mbus_frame_desc_entry * entry)449 cal_get_remote_frame_desc_entry(struct cal_ctx *ctx,
450 				struct v4l2_mbus_frame_desc_entry *entry)
451 {
452 	struct v4l2_mbus_frame_desc fd;
453 	struct media_pad *phy_source_pad;
454 	int ret;
455 
456 	phy_source_pad = media_pad_remote_pad_first(&ctx->pad);
457 	if (!phy_source_pad)
458 		return -ENODEV;
459 
460 	ret = v4l2_subdev_call(&ctx->phy->subdev, pad, get_frame_desc,
461 			       phy_source_pad->index, &fd);
462 	if (ret)
463 		return ret;
464 
465 	if (fd.num_entries != 1)
466 		return -EINVAL;
467 
468 	*entry = fd.entry[0];
469 
470 	return 0;
471 }
472 
cal_ctx_prepare(struct cal_ctx * ctx)473 int cal_ctx_prepare(struct cal_ctx *ctx)
474 {
475 	struct v4l2_mbus_frame_desc_entry entry;
476 	int ret;
477 
478 	ret = cal_get_remote_frame_desc_entry(ctx, &entry);
479 
480 	if (ret == -ENOIOCTLCMD) {
481 		ctx->vc = 0;
482 		ctx->datatype = CAL_CSI2_CTX_DT_ANY;
483 	} else if (!ret) {
484 		ctx_dbg(2, ctx, "Framedesc: len %u, vc %u, dt %#x\n",
485 			entry.length, entry.bus.csi2.vc, entry.bus.csi2.dt);
486 
487 		ctx->vc = entry.bus.csi2.vc;
488 		ctx->datatype = entry.bus.csi2.dt;
489 	} else {
490 		return ret;
491 	}
492 
493 	ctx->use_pix_proc = !ctx->fmtinfo->meta;
494 
495 	if (ctx->use_pix_proc) {
496 		ret = cal_reserve_pix_proc(ctx->cal);
497 		if (ret < 0) {
498 			ctx_err(ctx, "Failed to reserve pix proc: %d\n", ret);
499 			return ret;
500 		}
501 
502 		ctx->pix_proc = ret;
503 	}
504 
505 	return 0;
506 }
507 
cal_ctx_unprepare(struct cal_ctx * ctx)508 void cal_ctx_unprepare(struct cal_ctx *ctx)
509 {
510 	if (ctx->use_pix_proc)
511 		cal_release_pix_proc(ctx->cal, ctx->pix_proc);
512 }
513 
cal_ctx_start(struct cal_ctx * ctx)514 void cal_ctx_start(struct cal_ctx *ctx)
515 {
516 	struct cal_camerarx *phy = ctx->phy;
517 
518 	/*
519 	 * Reset the frame number & sequence number, but only if the
520 	 * virtual channel is not already in use.
521 	 */
522 
523 	spin_lock(&phy->vc_lock);
524 
525 	if (phy->vc_enable_count[ctx->vc]++ == 0) {
526 		phy->vc_frame_number[ctx->vc] = 0;
527 		phy->vc_sequence[ctx->vc] = 0;
528 	}
529 
530 	spin_unlock(&phy->vc_lock);
531 
532 	ctx->dma.state = CAL_DMA_RUNNING;
533 
534 	/* Configure the CSI-2, pixel processing and write DMA contexts. */
535 	cal_ctx_csi2_config(ctx);
536 	if (ctx->use_pix_proc)
537 		cal_ctx_pix_proc_config(ctx);
538 	cal_ctx_wr_dma_config(ctx);
539 
540 	/* Enable IRQ_WDMA_END and IRQ_WDMA_START. */
541 	cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(1),
542 		  CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx));
543 	cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2),
544 		  CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx));
545 
546 	cal_ctx_wr_dma_enable(ctx);
547 }
548 
cal_ctx_stop(struct cal_ctx * ctx)549 void cal_ctx_stop(struct cal_ctx *ctx)
550 {
551 	struct cal_camerarx *phy = ctx->phy;
552 	long timeout;
553 
554 	WARN_ON(phy->vc_enable_count[ctx->vc] == 0);
555 
556 	spin_lock(&phy->vc_lock);
557 	phy->vc_enable_count[ctx->vc]--;
558 	spin_unlock(&phy->vc_lock);
559 
560 	/*
561 	 * Request DMA stop and wait until it completes. If completion times
562 	 * out, forcefully disable the DMA.
563 	 */
564 	spin_lock_irq(&ctx->dma.lock);
565 	ctx->dma.state = CAL_DMA_STOP_REQUESTED;
566 	spin_unlock_irq(&ctx->dma.lock);
567 
568 	timeout = wait_event_timeout(ctx->dma.wait, cal_ctx_wr_dma_stopped(ctx),
569 				     msecs_to_jiffies(500));
570 	if (!timeout) {
571 		ctx_err(ctx, "failed to disable dma cleanly\n");
572 		cal_ctx_wr_dma_disable(ctx);
573 	}
574 
575 	/* Disable IRQ_WDMA_END and IRQ_WDMA_START. */
576 	cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(1),
577 		  CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx));
578 	cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(2),
579 		  CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx));
580 
581 	ctx->dma.state = CAL_DMA_STOPPED;
582 
583 	/* Disable CSI2 context */
584 	cal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), 0);
585 
586 	/* Disable pix proc */
587 	if (ctx->use_pix_proc)
588 		cal_write(ctx->cal, CAL_PIX_PROC(ctx->pix_proc), 0);
589 }
590 
591 /* ------------------------------------------------------------------
592  *	IRQ Handling
593  * ------------------------------------------------------------------
594  */
595 
596 /*
597  * Track a sequence number for each virtual channel, which is shared by
598  * all contexts using the same virtual channel. This is done using the
599  * CSI-2 frame number as a base.
600  */
cal_update_seq_number(struct cal_ctx * ctx)601 static void cal_update_seq_number(struct cal_ctx *ctx)
602 {
603 	struct cal_dev *cal = ctx->cal;
604 	struct cal_camerarx *phy = ctx->phy;
605 	u16 prev_frame_num, frame_num;
606 	u8 vc = ctx->vc;
607 
608 	frame_num =
609 		cal_read(cal, CAL_CSI2_STATUS(phy->instance, ctx->csi2_ctx)) &
610 		0xffff;
611 
612 	if (phy->vc_frame_number[vc] != frame_num) {
613 		prev_frame_num = phy->vc_frame_number[vc];
614 
615 		if (prev_frame_num >= frame_num)
616 			phy->vc_sequence[vc] += 1;
617 		else
618 			phy->vc_sequence[vc] += frame_num - prev_frame_num;
619 
620 		phy->vc_frame_number[vc] = frame_num;
621 	}
622 }
623 
cal_irq_wdma_start(struct cal_ctx * ctx)624 static inline void cal_irq_wdma_start(struct cal_ctx *ctx)
625 {
626 	spin_lock(&ctx->dma.lock);
627 
628 	if (ctx->dma.state == CAL_DMA_STOP_REQUESTED) {
629 		/*
630 		 * If a stop is requested, disable the write DMA context
631 		 * immediately. The CAL_WR_DMA_CTRL_j.MODE field is shadowed,
632 		 * the current frame will complete and the DMA will then stop.
633 		 */
634 		cal_ctx_wr_dma_disable(ctx);
635 		ctx->dma.state = CAL_DMA_STOP_PENDING;
636 	} else if (!list_empty(&ctx->dma.queue) && !ctx->dma.pending) {
637 		/*
638 		 * Otherwise, if a new buffer is available, queue it to the
639 		 * hardware.
640 		 */
641 		struct cal_buffer *buf;
642 		dma_addr_t addr;
643 
644 		buf = list_first_entry(&ctx->dma.queue, struct cal_buffer,
645 				       list);
646 		addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
647 		cal_ctx_set_dma_addr(ctx, addr);
648 
649 		ctx->dma.pending = buf;
650 		list_del(&buf->list);
651 	}
652 
653 	spin_unlock(&ctx->dma.lock);
654 
655 	cal_update_seq_number(ctx);
656 }
657 
cal_irq_wdma_end(struct cal_ctx * ctx)658 static inline void cal_irq_wdma_end(struct cal_ctx *ctx)
659 {
660 	struct cal_buffer *buf = NULL;
661 
662 	spin_lock(&ctx->dma.lock);
663 
664 	/* If the DMA context was stopping, it is now stopped. */
665 	if (ctx->dma.state == CAL_DMA_STOP_PENDING) {
666 		ctx->dma.state = CAL_DMA_STOPPED;
667 		wake_up(&ctx->dma.wait);
668 	}
669 
670 	/* If a new buffer was queued, complete the current buffer. */
671 	if (ctx->dma.pending) {
672 		buf = ctx->dma.active;
673 		ctx->dma.active = ctx->dma.pending;
674 		ctx->dma.pending = NULL;
675 	}
676 
677 	spin_unlock(&ctx->dma.lock);
678 
679 	if (buf) {
680 		buf->vb.vb2_buf.timestamp = ktime_get_ns();
681 		buf->vb.field = ctx->v_fmt.fmt.pix.field;
682 		buf->vb.sequence = ctx->phy->vc_sequence[ctx->vc];
683 
684 		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
685 	}
686 }
687 
cal_irq_handle_wdma(struct cal_ctx * ctx,bool start,bool end)688 static void cal_irq_handle_wdma(struct cal_ctx *ctx, bool start, bool end)
689 {
690 	/*
691 	 * CAL HW interrupts are inherently racy. If we get both start and end
692 	 * interrupts, we don't know what has happened: did the DMA for a single
693 	 * frame start and end, or did one frame end and a new frame start?
694 	 *
695 	 * Usually for normal pixel frames we get the interrupts separately. If
696 	 * we do get both, we have to guess. The assumption in the code below is
697 	 * that the active vertical area is larger than the blanking vertical
698 	 * area, and thus it is more likely that we get the end of the old frame
699 	 * and the start of a new frame.
700 	 *
701 	 * However, for embedded data, which is only a few lines high, we always
702 	 * get both interrupts. Here the assumption is that we get both for the
703 	 * same frame.
704 	 */
705 	if (ctx->v_fmt.fmt.pix.height < 10) {
706 		if (start)
707 			cal_irq_wdma_start(ctx);
708 
709 		if (end)
710 			cal_irq_wdma_end(ctx);
711 	} else {
712 		if (end)
713 			cal_irq_wdma_end(ctx);
714 
715 		if (start)
716 			cal_irq_wdma_start(ctx);
717 	}
718 }
719 
cal_irq(int irq_cal,void * data)720 static irqreturn_t cal_irq(int irq_cal, void *data)
721 {
722 	struct cal_dev *cal = data;
723 	u32 status[3];
724 	unsigned int i;
725 
726 	for (i = 0; i < 3; ++i) {
727 		status[i] = cal_read(cal, CAL_HL_IRQSTATUS(i));
728 		if (status[i])
729 			cal_write(cal, CAL_HL_IRQSTATUS(i), status[i]);
730 	}
731 
732 	if (status[0]) {
733 		if (status[0] & CAL_HL_IRQ_OCPO_ERR_MASK)
734 			dev_err_ratelimited(cal->dev, "OCPO ERROR\n");
735 
736 		for (i = 0; i < cal->data->num_csi2_phy; ++i) {
737 			if (status[0] & CAL_HL_IRQ_CIO_MASK(i)) {
738 				u32 cio_stat = cal_read(cal,
739 							CAL_CSI2_COMPLEXIO_IRQSTATUS(i));
740 
741 				dev_err_ratelimited(cal->dev,
742 						    "CIO%u error: %#08x\n", i, cio_stat);
743 
744 				cal_write(cal, CAL_CSI2_COMPLEXIO_IRQSTATUS(i),
745 					  cio_stat);
746 			}
747 
748 			if (status[0] & CAL_HL_IRQ_VC_MASK(i)) {
749 				u32 vc_stat = cal_read(cal, CAL_CSI2_VC_IRQSTATUS(i));
750 
751 				dev_err_ratelimited(cal->dev,
752 						    "CIO%u VC error: %#08x\n",
753 						    i, vc_stat);
754 
755 				cal_write(cal, CAL_CSI2_VC_IRQSTATUS(i), vc_stat);
756 			}
757 		}
758 	}
759 
760 	for (i = 0; i < cal->num_contexts; ++i) {
761 		bool end = !!(status[1] & CAL_HL_IRQ_WDMA_END_MASK(i));
762 		bool start = !!(status[2] & CAL_HL_IRQ_WDMA_START_MASK(i));
763 
764 		if (start || end)
765 			cal_irq_handle_wdma(cal->ctx[i], start, end);
766 	}
767 
768 	return IRQ_HANDLED;
769 }
770 
771 /* ------------------------------------------------------------------
772  *	Asynchronous V4L2 subdev binding
773  * ------------------------------------------------------------------
774  */
775 
776 struct cal_v4l2_async_subdev {
777 	struct v4l2_async_connection asd; /* Must be first */
778 	struct cal_camerarx *phy;
779 };
780 
781 static inline struct cal_v4l2_async_subdev *
to_cal_asd(struct v4l2_async_connection * asd)782 to_cal_asd(struct v4l2_async_connection *asd)
783 {
784 	return container_of(asd, struct cal_v4l2_async_subdev, asd);
785 }
786 
cal_async_notifier_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asd)787 static int cal_async_notifier_bound(struct v4l2_async_notifier *notifier,
788 				    struct v4l2_subdev *subdev,
789 				    struct v4l2_async_connection *asd)
790 {
791 	struct cal_camerarx *phy = to_cal_asd(asd)->phy;
792 	int pad;
793 	int ret;
794 
795 	if (phy->source) {
796 		phy_info(phy, "Rejecting subdev %s (Already set!!)",
797 			 subdev->name);
798 		return 0;
799 	}
800 
801 	phy->source = subdev;
802 	phy_dbg(1, phy, "Using source %s for capture\n", subdev->name);
803 
804 	pad = media_entity_get_fwnode_pad(&subdev->entity,
805 					  of_fwnode_handle(phy->source_ep_node),
806 					  MEDIA_PAD_FL_SOURCE);
807 	if (pad < 0) {
808 		phy_err(phy, "Source %s has no connected source pad\n",
809 			subdev->name);
810 		return pad;
811 	}
812 
813 	ret = media_create_pad_link(&subdev->entity, pad,
814 				    &phy->subdev.entity, CAL_CAMERARX_PAD_SINK,
815 				    MEDIA_LNK_FL_IMMUTABLE |
816 				    MEDIA_LNK_FL_ENABLED);
817 	if (ret) {
818 		phy_err(phy, "Failed to create media link for source %s\n",
819 			subdev->name);
820 		return ret;
821 	}
822 
823 	return 0;
824 }
825 
cal_async_notifier_complete(struct v4l2_async_notifier * notifier)826 static int cal_async_notifier_complete(struct v4l2_async_notifier *notifier)
827 {
828 	struct cal_dev *cal = container_of(notifier, struct cal_dev, notifier);
829 	unsigned int i;
830 	int ret;
831 
832 	for (i = 0; i < cal->num_contexts; ++i) {
833 		ret = cal_ctx_v4l2_register(cal->ctx[i]);
834 		if (ret)
835 			goto err_ctx_unreg;
836 	}
837 
838 	if (!cal_mc_api)
839 		return 0;
840 
841 	ret = v4l2_device_register_subdev_nodes(&cal->v4l2_dev);
842 	if (ret)
843 		goto err_ctx_unreg;
844 
845 	return 0;
846 
847 err_ctx_unreg:
848 	for (; i > 0; --i) {
849 		if (!cal->ctx[i - 1])
850 			continue;
851 
852 		cal_ctx_v4l2_unregister(cal->ctx[i - 1]);
853 	}
854 
855 	return ret;
856 }
857 
858 static const struct v4l2_async_notifier_operations cal_async_notifier_ops = {
859 	.bound = cal_async_notifier_bound,
860 	.complete = cal_async_notifier_complete,
861 };
862 
cal_async_notifier_register(struct cal_dev * cal)863 static int cal_async_notifier_register(struct cal_dev *cal)
864 {
865 	unsigned int i;
866 	int ret;
867 
868 	v4l2_async_nf_init(&cal->notifier, &cal->v4l2_dev);
869 	cal->notifier.ops = &cal_async_notifier_ops;
870 
871 	for (i = 0; i < cal->data->num_csi2_phy; ++i) {
872 		struct cal_camerarx *phy = cal->phy[i];
873 		struct cal_v4l2_async_subdev *casd;
874 		struct fwnode_handle *fwnode;
875 
876 		if (!phy->source_node)
877 			continue;
878 
879 		fwnode = of_fwnode_handle(phy->source_node);
880 		casd = v4l2_async_nf_add_fwnode(&cal->notifier,
881 						fwnode,
882 						struct cal_v4l2_async_subdev);
883 		if (IS_ERR(casd)) {
884 			phy_err(phy, "Failed to add subdev to notifier\n");
885 			ret = PTR_ERR(casd);
886 			goto error;
887 		}
888 
889 		casd->phy = phy;
890 	}
891 
892 	ret = v4l2_async_nf_register(&cal->notifier);
893 	if (ret) {
894 		cal_err(cal, "Error registering async notifier\n");
895 		goto error;
896 	}
897 
898 	return 0;
899 
900 error:
901 	v4l2_async_nf_cleanup(&cal->notifier);
902 	return ret;
903 }
904 
cal_async_notifier_unregister(struct cal_dev * cal)905 static void cal_async_notifier_unregister(struct cal_dev *cal)
906 {
907 	v4l2_async_nf_unregister(&cal->notifier);
908 	v4l2_async_nf_cleanup(&cal->notifier);
909 }
910 
911 /* ------------------------------------------------------------------
912  *	Media and V4L2 device handling
913  * ------------------------------------------------------------------
914  */
915 
916 /*
917  * Register user-facing devices. To be called at the end of the probe function
918  * when all resources are initialized and ready.
919  */
cal_media_register(struct cal_dev * cal)920 static int cal_media_register(struct cal_dev *cal)
921 {
922 	int ret;
923 
924 	ret = media_device_register(&cal->mdev);
925 	if (ret) {
926 		cal_err(cal, "Failed to register media device\n");
927 		return ret;
928 	}
929 
930 	/*
931 	 * Register the async notifier. This may trigger registration of the
932 	 * V4L2 video devices if all subdevs are ready.
933 	 */
934 	ret = cal_async_notifier_register(cal);
935 	if (ret) {
936 		media_device_unregister(&cal->mdev);
937 		return ret;
938 	}
939 
940 	return 0;
941 }
942 
943 /*
944  * Unregister the user-facing devices, but don't free memory yet. To be called
945  * at the beginning of the remove function, to disallow access from userspace.
946  */
cal_media_unregister(struct cal_dev * cal)947 static void cal_media_unregister(struct cal_dev *cal)
948 {
949 	unsigned int i;
950 
951 	/* Unregister all the V4L2 video devices. */
952 	for (i = 0; i < cal->num_contexts; i++)
953 		cal_ctx_v4l2_unregister(cal->ctx[i]);
954 
955 	cal_async_notifier_unregister(cal);
956 	media_device_unregister(&cal->mdev);
957 }
958 
959 /*
960  * Initialize the in-kernel objects. To be called at the beginning of the probe
961  * function, before the V4L2 device is used by the driver.
962  */
cal_media_init(struct cal_dev * cal)963 static int cal_media_init(struct cal_dev *cal)
964 {
965 	struct media_device *mdev = &cal->mdev;
966 	int ret;
967 
968 	mdev->dev = cal->dev;
969 	mdev->hw_revision = cal->revision;
970 	strscpy(mdev->model, "CAL", sizeof(mdev->model));
971 	media_device_init(mdev);
972 
973 	/*
974 	 * Initialize the V4L2 device (despite the function name, this performs
975 	 * initialization, not registration).
976 	 */
977 	cal->v4l2_dev.mdev = mdev;
978 	ret = v4l2_device_register(cal->dev, &cal->v4l2_dev);
979 	if (ret) {
980 		cal_err(cal, "Failed to register V4L2 device\n");
981 		return ret;
982 	}
983 
984 	vb2_dma_contig_set_max_seg_size(cal->dev, DMA_BIT_MASK(32));
985 
986 	return 0;
987 }
988 
989 /*
990  * Cleanup the in-kernel objects, freeing memory. To be called at the very end
991  * of the remove sequence, when nothing (including userspace) can access the
992  * objects anymore.
993  */
cal_media_cleanup(struct cal_dev * cal)994 static void cal_media_cleanup(struct cal_dev *cal)
995 {
996 	v4l2_device_unregister(&cal->v4l2_dev);
997 	media_device_cleanup(&cal->mdev);
998 
999 	vb2_dma_contig_clear_max_seg_size(cal->dev);
1000 }
1001 
1002 /* ------------------------------------------------------------------
1003  *	Initialization and module stuff
1004  * ------------------------------------------------------------------
1005  */
1006 
cal_ctx_create(struct cal_dev * cal,int inst)1007 static struct cal_ctx *cal_ctx_create(struct cal_dev *cal, int inst)
1008 {
1009 	struct cal_ctx *ctx;
1010 	int ret;
1011 
1012 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1013 	if (!ctx)
1014 		return NULL;
1015 
1016 	ctx->cal = cal;
1017 	ctx->phy = cal->phy[inst];
1018 	ctx->dma_ctx = inst;
1019 	ctx->csi2_ctx = inst;
1020 	ctx->cport = inst;
1021 
1022 	ret = cal_ctx_v4l2_init(ctx);
1023 	if (ret) {
1024 		kfree(ctx);
1025 		return NULL;
1026 	}
1027 
1028 	return ctx;
1029 }
1030 
cal_ctx_destroy(struct cal_ctx * ctx)1031 static void cal_ctx_destroy(struct cal_ctx *ctx)
1032 {
1033 	cal_ctx_v4l2_cleanup(ctx);
1034 
1035 	kfree(ctx);
1036 }
1037 
1038 static const struct of_device_id cal_of_match[] = {
1039 	{
1040 		.compatible = "ti,dra72-cal",
1041 		.data = (void *)&dra72x_cal_data,
1042 	},
1043 	{
1044 		.compatible = "ti,dra72-pre-es2-cal",
1045 		.data = (void *)&dra72x_es1_cal_data,
1046 	},
1047 	{
1048 		.compatible = "ti,dra76-cal",
1049 		.data = (void *)&dra76x_cal_data,
1050 	},
1051 	{
1052 		.compatible = "ti,am654-cal",
1053 		.data = (void *)&am654_cal_data,
1054 	},
1055 	{},
1056 };
1057 MODULE_DEVICE_TABLE(of, cal_of_match);
1058 
1059 /* Get hardware revision and info. */
1060 
1061 #define CAL_HL_HWINFO_VALUE		0xa3c90469
1062 
cal_get_hwinfo(struct cal_dev * cal)1063 static void cal_get_hwinfo(struct cal_dev *cal)
1064 {
1065 	u32 hwinfo;
1066 
1067 	cal->revision = cal_read(cal, CAL_HL_REVISION);
1068 	switch (FIELD_GET(CAL_HL_REVISION_SCHEME_MASK, cal->revision)) {
1069 	case CAL_HL_REVISION_SCHEME_H08:
1070 		cal_dbg(3, cal, "CAL HW revision %lu.%lu.%lu (0x%08x)\n",
1071 			FIELD_GET(CAL_HL_REVISION_MAJOR_MASK, cal->revision),
1072 			FIELD_GET(CAL_HL_REVISION_MINOR_MASK, cal->revision),
1073 			FIELD_GET(CAL_HL_REVISION_RTL_MASK, cal->revision),
1074 			cal->revision);
1075 		break;
1076 
1077 	case CAL_HL_REVISION_SCHEME_LEGACY:
1078 	default:
1079 		cal_info(cal, "Unexpected CAL HW revision 0x%08x\n",
1080 			 cal->revision);
1081 		break;
1082 	}
1083 
1084 	hwinfo = cal_read(cal, CAL_HL_HWINFO);
1085 	if (hwinfo != CAL_HL_HWINFO_VALUE)
1086 		cal_info(cal, "CAL_HL_HWINFO = 0x%08x, expected 0x%08x\n",
1087 			 hwinfo, CAL_HL_HWINFO_VALUE);
1088 }
1089 
cal_init_camerarx_regmap(struct cal_dev * cal)1090 static int cal_init_camerarx_regmap(struct cal_dev *cal)
1091 {
1092 	struct platform_device *pdev = to_platform_device(cal->dev);
1093 	struct device_node *np = cal->dev->of_node;
1094 	struct regmap_config config = { };
1095 	struct regmap *syscon;
1096 	struct resource *res;
1097 	unsigned int offset;
1098 	void __iomem *base;
1099 
1100 	syscon = syscon_regmap_lookup_by_phandle_args(np, "ti,camerrx-control",
1101 						      1, &offset);
1102 	if (!IS_ERR(syscon)) {
1103 		cal->syscon_camerrx = syscon;
1104 		cal->syscon_camerrx_offset = offset;
1105 		return 0;
1106 	}
1107 
1108 	dev_warn(cal->dev, "failed to get ti,camerrx-control: %ld\n",
1109 		 PTR_ERR(syscon));
1110 
1111 	/*
1112 	 * Backward DTS compatibility. If syscon entry is not present then
1113 	 * check if the camerrx_control resource is present.
1114 	 */
1115 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1116 					   "camerrx_control");
1117 	base = devm_ioremap_resource(cal->dev, res);
1118 	if (IS_ERR(base)) {
1119 		cal_err(cal, "failed to ioremap camerrx_control\n");
1120 		return PTR_ERR(base);
1121 	}
1122 
1123 	cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
1124 		res->name, &res->start, &res->end);
1125 
1126 	config.reg_bits = 32;
1127 	config.reg_stride = 4;
1128 	config.val_bits = 32;
1129 	config.max_register = resource_size(res) - 4;
1130 
1131 	syscon = regmap_init_mmio(NULL, base, &config);
1132 	if (IS_ERR(syscon)) {
1133 		pr_err("regmap init failed\n");
1134 		return PTR_ERR(syscon);
1135 	}
1136 
1137 	/*
1138 	 * In this case the base already point to the direct CM register so no
1139 	 * need for an offset.
1140 	 */
1141 	cal->syscon_camerrx = syscon;
1142 	cal->syscon_camerrx_offset = 0;
1143 
1144 	return 0;
1145 }
1146 
cal_probe(struct platform_device * pdev)1147 static int cal_probe(struct platform_device *pdev)
1148 {
1149 	struct cal_dev *cal;
1150 	bool connected = false;
1151 	unsigned int i;
1152 	int ret;
1153 	int irq;
1154 
1155 	cal = devm_kzalloc(&pdev->dev, sizeof(*cal), GFP_KERNEL);
1156 	if (!cal)
1157 		return -ENOMEM;
1158 
1159 	cal->data = of_device_get_match_data(&pdev->dev);
1160 	if (!cal->data) {
1161 		dev_err(&pdev->dev, "Could not get feature data based on compatible version\n");
1162 		return -ENODEV;
1163 	}
1164 
1165 	cal->dev = &pdev->dev;
1166 	platform_set_drvdata(pdev, cal);
1167 
1168 	/* Acquire resources: clocks, CAMERARX regmap, I/O memory and IRQ. */
1169 	cal->fclk = devm_clk_get(&pdev->dev, "fck");
1170 	if (IS_ERR(cal->fclk)) {
1171 		dev_err(&pdev->dev, "cannot get CAL fclk\n");
1172 		return PTR_ERR(cal->fclk);
1173 	}
1174 
1175 	ret = cal_init_camerarx_regmap(cal);
1176 	if (ret < 0)
1177 		return ret;
1178 
1179 	cal->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1180 						"cal_top");
1181 	cal->base = devm_ioremap_resource(&pdev->dev, cal->res);
1182 	if (IS_ERR(cal->base))
1183 		return PTR_ERR(cal->base);
1184 
1185 	cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
1186 		cal->res->name, &cal->res->start, &cal->res->end);
1187 
1188 	irq = platform_get_irq(pdev, 0);
1189 	cal_dbg(1, cal, "got irq# %d\n", irq);
1190 	ret = devm_request_irq(&pdev->dev, irq, cal_irq, 0, CAL_MODULE_NAME,
1191 			       cal);
1192 	if (ret)
1193 		return ret;
1194 
1195 	/* Read the revision and hardware info to verify hardware access. */
1196 	pm_runtime_enable(&pdev->dev);
1197 	ret = pm_runtime_resume_and_get(&pdev->dev);
1198 	if (ret)
1199 		goto error_pm_runtime;
1200 
1201 	cal_get_hwinfo(cal);
1202 	pm_runtime_put_sync(&pdev->dev);
1203 
1204 	/* Initialize the media device. */
1205 	ret = cal_media_init(cal);
1206 	if (ret < 0)
1207 		goto error_pm_runtime;
1208 
1209 	/* Create CAMERARX PHYs. */
1210 	for (i = 0; i < cal->data->num_csi2_phy; ++i) {
1211 		cal->phy[i] = cal_camerarx_create(cal, i);
1212 		if (IS_ERR(cal->phy[i])) {
1213 			ret = PTR_ERR(cal->phy[i]);
1214 			cal->phy[i] = NULL;
1215 			goto error_camerarx;
1216 		}
1217 
1218 		if (cal->phy[i]->source_node)
1219 			connected = true;
1220 	}
1221 
1222 	if (!connected) {
1223 		cal_err(cal, "Neither port is configured, no point in staying up\n");
1224 		ret = -ENODEV;
1225 		goto error_camerarx;
1226 	}
1227 
1228 	/* Create contexts. */
1229 	for (i = 0; i < cal->data->num_csi2_phy; ++i) {
1230 		if (!cal->phy[i]->source_node)
1231 			continue;
1232 
1233 		cal->ctx[cal->num_contexts] = cal_ctx_create(cal, i);
1234 		if (!cal->ctx[cal->num_contexts]) {
1235 			cal_err(cal, "Failed to create context %u\n", cal->num_contexts);
1236 			ret = -ENODEV;
1237 			goto error_context;
1238 		}
1239 
1240 		cal->num_contexts++;
1241 	}
1242 
1243 	/* Register the media device. */
1244 	ret = cal_media_register(cal);
1245 	if (ret)
1246 		goto error_context;
1247 
1248 	return 0;
1249 
1250 error_context:
1251 	for (i = 0; i < cal->num_contexts; i++)
1252 		cal_ctx_destroy(cal->ctx[i]);
1253 
1254 error_camerarx:
1255 	for (i = 0; i < cal->data->num_csi2_phy; i++)
1256 		cal_camerarx_destroy(cal->phy[i]);
1257 
1258 	cal_media_cleanup(cal);
1259 
1260 error_pm_runtime:
1261 	pm_runtime_disable(&pdev->dev);
1262 
1263 	return ret;
1264 }
1265 
cal_remove(struct platform_device * pdev)1266 static void cal_remove(struct platform_device *pdev)
1267 {
1268 	struct cal_dev *cal = platform_get_drvdata(pdev);
1269 	unsigned int i;
1270 	int ret;
1271 
1272 	cal_dbg(1, cal, "Removing %s\n", CAL_MODULE_NAME);
1273 
1274 	ret = pm_runtime_resume_and_get(&pdev->dev);
1275 
1276 	cal_media_unregister(cal);
1277 
1278 	for (i = 0; i < cal->data->num_csi2_phy; i++)
1279 		cal_camerarx_disable(cal->phy[i]);
1280 
1281 	for (i = 0; i < cal->num_contexts; i++)
1282 		cal_ctx_destroy(cal->ctx[i]);
1283 
1284 	for (i = 0; i < cal->data->num_csi2_phy; i++)
1285 		cal_camerarx_destroy(cal->phy[i]);
1286 
1287 	cal_media_cleanup(cal);
1288 
1289 	if (ret >= 0)
1290 		pm_runtime_put_sync(&pdev->dev);
1291 	pm_runtime_disable(&pdev->dev);
1292 }
1293 
cal_runtime_resume(struct device * dev)1294 static int cal_runtime_resume(struct device *dev)
1295 {
1296 	struct cal_dev *cal = dev_get_drvdata(dev);
1297 	unsigned int i;
1298 	u32 val;
1299 
1300 	if (cal->data->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) {
1301 		/*
1302 		 * Apply errata on both port everytime we (re-)enable
1303 		 * the clock
1304 		 */
1305 		for (i = 0; i < cal->data->num_csi2_phy; i++)
1306 			cal_camerarx_i913_errata(cal->phy[i]);
1307 	}
1308 
1309 	/*
1310 	 * Enable global interrupts that are not related to a particular
1311 	 * CAMERARAX or context.
1312 	 */
1313 	cal_write(cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK);
1314 
1315 	val = cal_read(cal, CAL_CTRL);
1316 	cal_set_field(&val, CAL_CTRL_BURSTSIZE_BURST128,
1317 		      CAL_CTRL_BURSTSIZE_MASK);
1318 	cal_set_field(&val, 0xf, CAL_CTRL_TAGCNT_MASK);
1319 	cal_set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED,
1320 		      CAL_CTRL_POSTED_WRITES_MASK);
1321 	cal_set_field(&val, 0xff, CAL_CTRL_MFLAGL_MASK);
1322 	cal_set_field(&val, 0xff, CAL_CTRL_MFLAGH_MASK);
1323 	cal_write(cal, CAL_CTRL, val);
1324 	cal_dbg(3, cal, "CAL_CTRL = 0x%08x\n", cal_read(cal, CAL_CTRL));
1325 
1326 	return 0;
1327 }
1328 
1329 static const struct dev_pm_ops cal_pm_ops = {
1330 	.runtime_resume = cal_runtime_resume,
1331 };
1332 
1333 static struct platform_driver cal_pdrv = {
1334 	.probe		= cal_probe,
1335 	.remove_new	= cal_remove,
1336 	.driver		= {
1337 		.name	= CAL_MODULE_NAME,
1338 		.pm	= &cal_pm_ops,
1339 		.of_match_table = cal_of_match,
1340 	},
1341 };
1342 
1343 module_platform_driver(cal_pdrv);
1344