1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
13 */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22
23 #include <asm/bootinfo.h>
24 #include <asm/branch.h>
25 #include <asm/break.h>
26 #include <asm/cpu.h>
27 #include <asm/fpu.h>
28 #include <asm/cachectl.h>
29 #include <asm/inst.h>
30 #include <asm/jazz.h>
31 #include <asm/module.h>
32 #include <asm/pgtable.h>
33 #include <asm/io.h>
34 #include <asm/siginfo.h>
35 #include <asm/watch.h>
36 #include <asm/tlbdebug.h>
37 #include <asm/types.h>
38 #include <asm/system.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42
43 extern asmlinkage void handle_mod(void);
44 extern asmlinkage void handle_tlbl(void);
45 extern asmlinkage void handle_tlbs(void);
46 extern asmlinkage void handle_adel(void);
47 extern asmlinkage void handle_ades(void);
48 extern asmlinkage void handle_ibe(void);
49 extern asmlinkage void handle_dbe(void);
50 extern asmlinkage void handle_sys(void);
51 extern asmlinkage void handle_bp(void);
52 extern asmlinkage void handle_ri(void);
53 extern asmlinkage void handle_cpu(void);
54 extern asmlinkage void handle_ov(void);
55 extern asmlinkage void handle_tr(void);
56 extern asmlinkage void handle_fpe(void);
57 extern asmlinkage void handle_mdmx(void);
58 extern asmlinkage void handle_watch(void);
59 extern asmlinkage void handle_mcheck(void);
60 extern asmlinkage void handle_reserved(void);
61
62 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
63 struct mips_fpu_soft_struct *ctx);
64
65 void (*board_be_init)(void);
66 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
67 void (*board_nmi_handler_setup)(void);
68
69 int kstack_depth_to_print = 24;
70
71 /*
72 * These constant is for searching for possible module text segments.
73 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
74 */
75 #define MODULE_RANGE (8*1024*1024)
76
77 /*
78 * If the address is either in the .text section of the
79 * kernel, or in the vmalloc'ed module regions, it *may*
80 * be the address of a calling routine
81 */
82
83 #ifdef CONFIG_MODULES
84
85 extern struct module *module_list;
86 extern struct module kernel_module;
87
kernel_text_address(long addr)88 static inline int kernel_text_address(long addr)
89 {
90 extern char _stext, _etext;
91 int retval = 0;
92 struct module *mod;
93
94 if (addr >= (long) &_stext && addr <= (long) &_etext)
95 return 1;
96
97 for (mod = module_list; mod != &kernel_module; mod = mod->next) {
98 /* mod_bound tests for addr being inside the vmalloc'ed
99 * module area. Of course it'd be better to test only
100 * for the .text subset... */
101 if (mod_bound(addr, 0, mod)) {
102 retval = 1;
103 break;
104 }
105 }
106
107 return retval;
108 }
109
110 #else
111
kernel_text_address(long addr)112 static inline int kernel_text_address(long addr)
113 {
114 extern char _stext, _etext;
115
116 return (addr >= (long) &_stext && addr <= (long) &_etext);
117 }
118
119 #endif
120
121 /*
122 * This routine abuses get_user()/put_user() to reference pointers
123 * with at least a bit of error checking ...
124 */
show_stack(long * sp)125 void show_stack(long *sp)
126 {
127 int i;
128 long stackdata;
129
130 sp = sp ? sp : (long *)&sp;
131
132 printk("Stack: ");
133 i = 1;
134 while ((long) sp & (PAGE_SIZE - 1)) {
135 if (i && ((i % 8) == 0))
136 printk("\n");
137 if (i > 40) {
138 printk(" ...");
139 break;
140 }
141
142 if (__get_user(stackdata, sp++)) {
143 printk(" (Bad stack address)");
144 break;
145 }
146
147 printk(" %08lx", stackdata);
148 i++;
149 }
150 printk("\n");
151 }
152
show_trace(long * sp)153 void show_trace(long *sp)
154 {
155 int i;
156 long addr;
157
158 sp = sp ? sp : (long *) &sp;
159
160 printk("Call Trace: ");
161 i = 1;
162 while ((long) sp & (PAGE_SIZE - 1)) {
163
164 if (__get_user(addr, sp++)) {
165 if (i && ((i % 6) == 0))
166 printk("\n");
167 printk(" (Bad stack address)\n");
168 break;
169 }
170
171 /*
172 * If the address is either in the text segment of the
173 * kernel, or in the region which contains vmalloc'ed
174 * memory, it *may* be the address of a calling
175 * routine; if so, print it so that someone tracing
176 * down the cause of the crash will be able to figure
177 * out the call path that was taken.
178 */
179
180 if (kernel_text_address(addr)) {
181 if (i && ((i % 6) == 0))
182 printk("\n");
183 if (i > 40) {
184 printk(" ...");
185 break;
186 }
187
188 printk(" [<%08lx>]", addr);
189 i++;
190 }
191 }
192 printk("\n");
193 }
194
show_trace_task(struct task_struct * tsk)195 void show_trace_task(struct task_struct *tsk)
196 {
197 show_trace((long *)tsk->thread.reg29);
198 }
199
show_code(unsigned int * pc)200 void show_code(unsigned int *pc)
201 {
202 long i;
203
204 printk("\nCode:");
205
206 for(i = -3 ; i < 6 ; i++) {
207 unsigned long insn;
208 if (__get_user(insn, pc + i)) {
209 printk(" (Bad address in epc)\n");
210 break;
211 }
212 printk("%c%08lx%c",(i?' ':'<'),insn,(i?' ':'>'));
213 }
214 }
215
show_regs(struct pt_regs * regs)216 void show_regs(struct pt_regs *regs)
217 {
218 /*
219 * Saved main processor registers
220 */
221 printk("$0 : %08x %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
222 0, regs->regs[1], regs->regs[2], regs->regs[3],
223 regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
224 printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
225 regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11],
226 regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
227 printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
228 regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19],
229 regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
230 printk("$24: %08lx %08lx %08lx %08lx %08lx %08lx\n",
231 regs->regs[24], regs->regs[25],
232 regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
233 printk("Hi : %08lx\n", regs->hi);
234 printk("Lo : %08lx\n", regs->lo);
235
236 /*
237 * Saved cp0 registers
238 */
239 printk("epc : %08lx %s\n", regs->cp0_epc, print_tainted());
240 printk("Status: %08lx\n", regs->cp0_status);
241 printk("Cause : %08lx\n", regs->cp0_cause);
242 printk("PrId : %08x\n", read_c0_prid());
243 }
244
show_registers(struct pt_regs * regs)245 void show_registers(struct pt_regs *regs)
246 {
247 show_regs(regs);
248 printk("Process %s (pid: %d, stackpage=%08lx)\n",
249 current->comm, current->pid, (unsigned long) current);
250 show_stack((long *) regs->regs[29]);
251 show_trace((long *) regs->regs[29]);
252 show_code((unsigned int *) regs->cp0_epc);
253 printk("\n");
254 }
255
256 static spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
257
__die(const char * str,struct pt_regs * regs,const char * file,const char * func,unsigned long line)258 void __die(const char * str, struct pt_regs * regs, const char * file,
259 const char * func, unsigned long line)
260 {
261 console_verbose();
262 spin_lock_irq(&die_lock);
263 printk("%s", str);
264 if (file && func)
265 printk(" in %s:%s, line %ld", file, func, line);
266 printk(":\n");
267 show_registers(regs);
268 spin_unlock_irq(&die_lock);
269 do_exit(SIGSEGV);
270 }
271
__die_if_kernel(const char * str,struct pt_regs * regs,const char * file,const char * func,unsigned long line)272 void __die_if_kernel(const char * str, struct pt_regs * regs,
273 const char * file, const char * func, unsigned long line)
274 {
275 if (!user_mode(regs))
276 __die(str, regs, file, func, line);
277 }
278
279 extern const struct exception_table_entry __start___dbe_table[];
280 extern const struct exception_table_entry __stop___dbe_table[];
281
__declare_dbe_table(void)282 void __declare_dbe_table(void)
283 {
284 __asm__ __volatile__(
285 ".section\t__dbe_table,\"a\"\n\t"
286 ".previous"
287 );
288 }
289
290 static inline unsigned long
search_one_table(const struct exception_table_entry * first,const struct exception_table_entry * last,unsigned long value)291 search_one_table(const struct exception_table_entry *first,
292 const struct exception_table_entry *last,
293 unsigned long value)
294 {
295 const struct exception_table_entry *mid;
296 long diff;
297
298 while (first < last) {
299 mid = (last - first) / 2 + first;
300 diff = mid->insn - value;
301 if (diff < 0)
302 first = mid + 1;
303 else
304 last = mid;
305 }
306 return (first == last && first->insn == value) ? first->nextinsn : 0;
307 }
308
309 extern spinlock_t modlist_lock;
310
311 static inline unsigned long
search_dbe_table(unsigned long addr)312 search_dbe_table(unsigned long addr)
313 {
314 unsigned long ret = 0;
315
316 #ifndef CONFIG_MODULES
317 /* There is only the kernel to search. */
318 ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr);
319 return ret;
320 #else
321 unsigned long flags;
322
323 /* The kernel is the last "module" -- no need to treat it special. */
324 struct module *mp;
325 struct archdata *ap;
326
327 spin_lock_irqsave(&modlist_lock, flags);
328 for (mp = module_list; mp != NULL; mp = mp->next) {
329 if (!mod_member_present(mp, archdata_end) ||
330 !mod_archdata_member_present(mp, struct archdata,
331 dbe_table_end))
332 continue;
333 ap = (struct archdata *)(mp->archdata_start);
334
335 if (ap->dbe_table_start == NULL ||
336 !(mp->flags & (MOD_RUNNING | MOD_INITIALIZING)))
337 continue;
338 ret = search_one_table(ap->dbe_table_start,
339 ap->dbe_table_end - 1, addr);
340 if (ret)
341 break;
342 }
343 spin_unlock_irqrestore(&modlist_lock, flags);
344 return ret;
345 #endif
346 }
347
do_be(struct pt_regs * regs)348 asmlinkage void do_be(struct pt_regs *regs)
349 {
350 unsigned long new_epc;
351 unsigned long fixup = 0;
352 int data = regs->cp0_cause & 4;
353 int action = MIPS_BE_FATAL;
354
355 if (data && !user_mode(regs))
356 fixup = search_dbe_table(exception_epc(regs));
357
358 if (fixup)
359 action = MIPS_BE_FIXUP;
360
361 if (board_be_handler)
362 action = board_be_handler(regs, fixup != 0);
363
364 switch (action) {
365 case MIPS_BE_DISCARD:
366 return;
367 case MIPS_BE_FIXUP:
368 if (fixup) {
369 new_epc = fixup_exception(dpf_reg, fixup,
370 regs->cp0_epc);
371 regs->cp0_epc = new_epc;
372 return;
373 }
374 break;
375 default:
376 break;
377 }
378
379 /*
380 * Assume it would be too dangerous to continue ...
381 */
382 printk(KERN_ALERT "%s bus error, epc == %08lx, ra == %08lx\n",
383 data ? "Data" : "Instruction",
384 regs->cp0_epc, regs->regs[31]);
385 die_if_kernel("Oops", regs);
386 force_sig(SIGBUS, current);
387 }
388
get_insn_opcode(struct pt_regs * regs,unsigned int * opcode)389 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
390 {
391 unsigned int *epc;
392
393 epc = (unsigned int *) regs->cp0_epc +
394 ((regs->cp0_cause & CAUSEF_BD) != 0);
395 if (!get_user(*opcode, epc))
396 return 0;
397
398 force_sig(SIGSEGV, current);
399 return 1;
400 }
401
402 /*
403 * ll/sc emulation
404 */
405
406 #define OPCODE 0xfc000000
407 #define BASE 0x03e00000
408 #define RT 0x001f0000
409 #define OFFSET 0x0000ffff
410 #define LL 0xc0000000
411 #define SC 0xe0000000
412
413 /*
414 * The ll_bit is cleared by r*_switch.S
415 */
416
417 unsigned long ll_bit;
418
419 static struct task_struct *ll_task = NULL;
420
simulate_ll(struct pt_regs * regs,unsigned int opcode)421 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
422 {
423 unsigned long value, *vaddr;
424 long offset;
425 int signal = 0;
426
427 /*
428 * analyse the ll instruction that just caused a ri exception
429 * and put the referenced address to addr.
430 */
431
432 /* sign extend offset */
433 offset = opcode & OFFSET;
434 offset <<= 16;
435 offset >>= 16;
436
437 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
438
439 if ((unsigned long)vaddr & 3) {
440 signal = SIGBUS;
441 goto sig;
442 }
443 if (get_user(value, vaddr)) {
444 signal = SIGSEGV;
445 goto sig;
446 }
447
448 if (ll_task == NULL || ll_task == current) {
449 ll_bit = 1;
450 } else {
451 ll_bit = 0;
452 }
453 ll_task = current;
454
455 regs->regs[(opcode & RT) >> 16] = value;
456
457 compute_return_epc(regs);
458 return;
459
460 sig:
461 force_sig(signal, current);
462 }
463
simulate_sc(struct pt_regs * regs,unsigned int opcode)464 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
465 {
466 unsigned long *vaddr, reg;
467 long offset;
468 int signal = 0;
469
470 /*
471 * analyse the sc instruction that just caused a ri exception
472 * and put the referenced address to addr.
473 */
474
475 /* sign extend offset */
476 offset = opcode & OFFSET;
477 offset <<= 16;
478 offset >>= 16;
479
480 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
481 reg = (opcode & RT) >> 16;
482
483 if ((unsigned long)vaddr & 3) {
484 signal = SIGBUS;
485 goto sig;
486 }
487 if (ll_bit == 0 || ll_task != current) {
488 regs->regs[reg] = 0;
489 compute_return_epc(regs);
490 return;
491 }
492
493 if (put_user(regs->regs[reg], vaddr)) {
494 signal = SIGSEGV;
495 goto sig;
496 }
497
498 regs->regs[reg] = 1;
499
500 compute_return_epc(regs);
501 return;
502
503 sig:
504 force_sig(signal, current);
505 }
506
507 /*
508 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
509 * opcodes are supposed to result in coprocessor unusable exceptions if
510 * executed on ll/sc-less processors. That's the theory. In practice a
511 * few processors such as NEC's VR4100 throw reserved instruction exceptions
512 * instead, so we're doing the emulation thing in both exception handlers.
513 */
simulate_llsc(struct pt_regs * regs)514 static inline int simulate_llsc(struct pt_regs *regs)
515 {
516 unsigned int opcode;
517
518 if (unlikely(get_insn_opcode(regs, &opcode)))
519 return -EFAULT;
520
521 if ((opcode & OPCODE) == LL) {
522 simulate_ll(regs, opcode);
523 return 0;
524 }
525 if ((opcode & OPCODE) == SC) {
526 simulate_sc(regs, opcode);
527 return 0;
528 }
529
530 return -EFAULT; /* Strange things going on ... */
531 }
532
do_ov(struct pt_regs * regs)533 asmlinkage void do_ov(struct pt_regs *regs)
534 {
535 siginfo_t info;
536
537 info.si_code = FPE_INTOVF;
538 info.si_signo = SIGFPE;
539 info.si_errno = 0;
540 info.si_addr = (void *)regs->cp0_epc;
541 force_sig_info(SIGFPE, &info, current);
542 }
543
544 /*
545 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
546 */
do_fpe(struct pt_regs * regs,unsigned long fcr31)547 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
548 {
549 if (fcr31 & FPU_CSR_UNI_X) {
550 int sig;
551
552 /*
553 * Unimplemented operation exception. If we've got the full
554 * software emulator on-board, let's use it...
555 *
556 * Force FPU to dump state into task/thread context. We're
557 * moving a lot of data here for what is probably a single
558 * instruction, but the alternative is to pre-decode the FP
559 * register operands before invoking the emulator, which seems
560 * a bit extreme for what should be an infrequent event.
561 */
562 save_fp(current);
563
564 /* Run the emulator */
565 sig = fpu_emulator_cop1Handler (0, regs,
566 ¤t->thread.fpu.soft);
567
568 /*
569 * We can't allow the emulated instruction to leave any of
570 * the cause bit set in $fcr31.
571 */
572 current->thread.fpu.soft.sr &= ~FPU_CSR_ALL_X;
573
574 /* Restore the hardware register state */
575 restore_fp(current);
576
577 /* If something went wrong, signal */
578 if (sig)
579 force_sig(sig, current);
580
581 return;
582 }
583
584 force_sig(SIGFPE, current);
585 }
586
do_bp(struct pt_regs * regs)587 asmlinkage void do_bp(struct pt_regs *regs)
588 {
589 unsigned int opcode, bcode;
590 siginfo_t info;
591
592 die_if_kernel("Break instruction in kernel code", regs);
593
594 if (get_insn_opcode(regs, &opcode))
595 return;
596
597 /*
598 * There is the ancient bug in the MIPS assemblers that the break
599 * code starts left to bit 16 instead to bit 6 in the opcode.
600 * Gas is bug-compatible, but not always, grrr...
601 * We handle both cases with a simple heuristics. --macro
602 */
603 bcode = ((opcode >> 6) & ((1 << 20) - 1));
604 if (bcode < (1 << 10))
605 bcode <<= 10;
606
607 /*
608 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
609 * insns, even for break codes that indicate arithmetic failures.
610 * Weird ...)
611 * But should we continue the brokenness??? --macro
612 */
613 switch (bcode) {
614 case BRK_OVERFLOW << 10:
615 case BRK_DIVZERO << 10:
616 if (bcode == (BRK_DIVZERO << 10))
617 info.si_code = FPE_INTDIV;
618 else
619 info.si_code = FPE_INTOVF;
620 info.si_signo = SIGFPE;
621 info.si_errno = 0;
622 info.si_addr = (void *)regs->cp0_epc;
623 force_sig_info(SIGFPE, &info, current);
624 break;
625 default:
626 force_sig(SIGTRAP, current);
627 }
628 }
629
do_tr(struct pt_regs * regs)630 asmlinkage void do_tr(struct pt_regs *regs)
631 {
632 unsigned int opcode, tcode = 0;
633 siginfo_t info;
634
635 if (get_insn_opcode(regs, &opcode))
636 return;
637
638 /* Immediate versions don't provide a code. */
639 if (!(opcode & OPCODE))
640 tcode = ((opcode >> 6) & ((1 << 10) - 1));
641
642 /*
643 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
644 * insns, even for trap codes that indicate arithmetic failures.
645 * Weird ...)
646 * But should we continue the brokenness??? --macro
647 */
648 switch (tcode) {
649 case BRK_OVERFLOW:
650 case BRK_DIVZERO:
651 if (tcode == BRK_DIVZERO)
652 info.si_code = FPE_INTDIV;
653 else
654 info.si_code = FPE_INTOVF;
655 info.si_signo = SIGFPE;
656 info.si_errno = 0;
657 info.si_addr = (void *)regs->cp0_epc;
658 force_sig_info(SIGFPE, &info, current);
659 break;
660 default:
661 force_sig(SIGTRAP, current);
662 }
663 }
664
do_ri(struct pt_regs * regs)665 asmlinkage void do_ri(struct pt_regs *regs)
666 {
667 die_if_kernel("Reserved instruction in kernel code", regs);
668
669 if (!cpu_has_llsc)
670 if (!simulate_llsc(regs))
671 return;
672
673 force_sig(SIGILL, current);
674 }
675
do_cpu(struct pt_regs * regs)676 asmlinkage void do_cpu(struct pt_regs *regs)
677 {
678 unsigned int cpid;
679
680 die_if_kernel("do_cpu invoked from kernel context!", regs);
681
682 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
683
684 switch (cpid) {
685 case 0:
686 if (cpu_has_llsc)
687 break;
688
689 if (!simulate_llsc(regs))
690 return;
691 break;
692
693 case 1:
694 own_fpu();
695 if (current->used_math) { /* Using the FPU again. */
696 restore_fp(current);
697 } else { /* First time FPU user. */
698 init_fpu();
699 current->used_math = 1;
700 }
701
702 if (!cpu_has_fpu) {
703 int sig = fpu_emulator_cop1Handler(0, regs,
704 ¤t->thread.fpu.soft);
705 if (sig)
706 force_sig(sig, current);
707 }
708
709 return;
710
711 case 2:
712 case 3:
713 break;
714 }
715
716 force_sig(SIGILL, current);
717 }
718
do_mdmx(struct pt_regs * regs)719 asmlinkage void do_mdmx(struct pt_regs *regs)
720 {
721 force_sig(SIGILL, current);
722 }
723
do_watch(struct pt_regs * regs)724 asmlinkage void do_watch(struct pt_regs *regs)
725 {
726 /*
727 * We use the watch exception where available to detect stack
728 * overflows.
729 */
730 dump_tlb_all();
731 show_regs(regs);
732 panic("Caught WATCH exception - probably caused by stack overflow.");
733 }
734
do_mcheck(struct pt_regs * regs)735 asmlinkage void do_mcheck(struct pt_regs *regs)
736 {
737 show_regs(regs);
738 dump_tlb_all();
739 /*
740 * Some chips may have other causes of machine check (e.g. SB1
741 * graduation timer)
742 */
743 panic("Caught Machine Check exception - %scaused by multiple "
744 "matching entries in the TLB.",
745 (regs->cp0_status & ST0_TS) ? "" : "not ");
746 }
747
do_reserved(struct pt_regs * regs)748 asmlinkage void do_reserved(struct pt_regs *regs)
749 {
750 /*
751 * Game over - no way to handle this if it ever occurs. Most probably
752 * caused by a new unknown cpu type or after another deadly
753 * hard/software error.
754 */
755 show_regs(regs);
756 panic("Caught reserved exception %ld - should not happen.",
757 (regs->cp0_cause & 0x7f) >> 2);
758 }
759
760 /*
761 * Some MIPS CPUs can enable/disable for cache parity detection, but do
762 * it different ways.
763 */
parity_protection_init(void)764 static inline void parity_protection_init(void)
765 {
766 switch (current_cpu_data.cputype) {
767 case CPU_5KC:
768 /* Set the PE bit (bit 31) in the c0_ecc register. */
769 printk(KERN_INFO "Enable the cache parity protection for "
770 "MIPS 5KC CPUs.\n");
771 write_c0_ecc(read_c0_ecc() | 0x80000000);
772 break;
773 default:
774 break;
775 }
776 }
777
cache_parity_error(void)778 asmlinkage void cache_parity_error(void)
779 {
780 unsigned int reg_val;
781
782 /* For the moment, report the problem and hang. */
783 printk("Cache error exception:\n");
784 printk("cp0_errorepc == %08lx\n", read_c0_errorepc());
785 reg_val = read_c0_cacheerr();
786 printk("c0_cacheerr == %08x\n", reg_val);
787
788 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
789 reg_val & (1<<30) ? "secondary" : "primary",
790 reg_val & (1<<31) ? "data" : "insn");
791 printk("Error bits: %s%s%s%s%s%s%s\n",
792 reg_val & (1<<29) ? "ED " : "",
793 reg_val & (1<<28) ? "ET " : "",
794 reg_val & (1<<26) ? "EE " : "",
795 reg_val & (1<<25) ? "EB " : "",
796 reg_val & (1<<24) ? "EI " : "",
797 reg_val & (1<<23) ? "E1 " : "",
798 reg_val & (1<<22) ? "E0 " : "");
799 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
800
801 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
802 if (reg_val & (1<<22))
803 printk("DErrAddr0: 0x%08lx\n", read_c0_derraddr0());
804
805 if (reg_val & (1<<23))
806 printk("DErrAddr1: 0x%08lx\n", read_c0_derraddr1());
807 #endif
808
809 panic("Can't handle the cache error!");
810 }
811
812 /*
813 * SDBBP EJTAG debug exception handler.
814 * We skip the instruction and return to the next instruction.
815 */
ejtag_exception_handler(struct pt_regs * regs)816 void ejtag_exception_handler(struct pt_regs *regs)
817 {
818 unsigned long depc, old_epc;
819 unsigned int debug;
820
821 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
822 depc = read_c0_depc();
823 debug = read_c0_debug();
824 printk("c0_depc = %08lx, DEBUG = %08x\n", depc, debug);
825 if (debug & 0x80000000) {
826 /*
827 * In branch delay slot.
828 * We cheat a little bit here and use EPC to calculate the
829 * debug return address (DEPC). EPC is restored after the
830 * calculation.
831 */
832 old_epc = regs->cp0_epc;
833 regs->cp0_epc = depc;
834 __compute_return_epc(regs);
835 depc = regs->cp0_epc;
836 regs->cp0_epc = old_epc;
837 } else
838 depc += 4;
839 write_c0_depc(depc);
840
841 #if 0
842 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
843 write_c0_debug(debug | 0x100);
844 #endif
845 }
846
847 /*
848 * NMI exception handler.
849 */
nmi_exception_handler(struct pt_regs * regs)850 void nmi_exception_handler(struct pt_regs *regs)
851 {
852 printk("NMI taken!!!!\n");
853 die("NMI", regs);
854 while(1) ;
855 }
856
857 unsigned long exception_handlers[32];
858
859 /*
860 * As a side effect of the way this is implemented we're limited
861 * to interrupt handlers in the address range from
862 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
863 */
set_except_vector(int n,void * addr)864 void *set_except_vector(int n, void *addr)
865 {
866 unsigned long handler = (unsigned long) addr;
867 unsigned long old_handler = exception_handlers[n];
868
869 exception_handlers[n] = handler;
870 if (n == 0 && cpu_has_divec) {
871 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
872 (0x03ffffff & (handler >> 2));
873 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
874 }
875 return (void *)old_handler;
876 }
877
878 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
879 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
880
881 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
882 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
883
884 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
885 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
886
per_cpu_trap_init(void)887 void __init per_cpu_trap_init(void)
888 {
889 unsigned int cpu = smp_processor_id();
890
891 /* Some firmware leaves the BEV flag set, clear it. */
892 clear_c0_status(ST0_CU3|ST0_CU2|ST0_CU1|ST0_BEV|ST0_KX|ST0_SX|ST0_UX);
893
894 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
895 set_c0_status(ST0_XX);
896
897 /*
898 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
899 * interrupt processing overhead. Use it where available.
900 */
901 if (cpu_has_divec)
902 set_c0_cause(CAUSEF_IV);
903
904 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
905 write_c0_context(cpu << 23);
906
907 atomic_inc(&init_mm.mm_count);
908 current->active_mm = &init_mm;
909 BUG_ON(current->mm);
910 enter_lazy_tlb(&init_mm, current, cpu);
911 }
912
trap_init(void)913 void __init trap_init(void)
914 {
915 extern char except_vec1_generic;
916 extern char except_vec3_generic, except_vec3_r4000;
917 extern char except_vec_ejtag_debug;
918 extern char except_vec4;
919 unsigned long i;
920
921 per_cpu_trap_init();
922
923 /* Copy the generic exception handler code to it's final destination. */
924 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
925
926 /*
927 * Setup default vectors
928 */
929 for (i = 0; i <= 31; i++)
930 set_except_vector(i, handle_reserved);
931
932 /*
933 * Copy the EJTAG debug exception vector handler code to it's final
934 * destination.
935 */
936 if (cpu_has_ejtag)
937 memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
938
939 /*
940 * Only some CPUs have the watch exceptions.
941 */
942 if (cpu_has_watch)
943 set_except_vector(23, handle_watch);
944
945 /*
946 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
947 * interrupt processing overhead. Use it where available.
948 */
949 if (cpu_has_divec)
950 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
951
952 /*
953 * Some CPUs can enable/disable for cache parity detection, but does
954 * it different ways.
955 */
956 parity_protection_init();
957
958 /*
959 * The Data Bus Errors / Instruction Bus Errors are signaled
960 * by external hardware. Therefore these two exceptions
961 * may have board specific handlers.
962 */
963 if (board_be_init)
964 board_be_init();
965
966 set_except_vector(1, handle_mod);
967 set_except_vector(2, handle_tlbl);
968 set_except_vector(3, handle_tlbs);
969 set_except_vector(4, handle_adel);
970 set_except_vector(5, handle_ades);
971
972 set_except_vector(6, handle_ibe);
973 set_except_vector(7, handle_dbe);
974
975 set_except_vector(8, handle_sys);
976 set_except_vector(9, handle_bp);
977 set_except_vector(10, handle_ri);
978 set_except_vector(11, handle_cpu);
979 set_except_vector(12, handle_ov);
980 set_except_vector(13, handle_tr);
981 set_except_vector(22, handle_mdmx);
982
983 if (cpu_has_fpu && !cpu_has_nofpuex)
984 set_except_vector(15, handle_fpe);
985
986 if (cpu_has_mcheck)
987 set_except_vector(24, handle_mcheck);
988
989 if (cpu_has_vce)
990 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
991 else if (cpu_has_4kex)
992 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
993 else
994 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
995
996 if (current_cpu_data.cputype == CPU_R6000 ||
997 current_cpu_data.cputype == CPU_R6000A) {
998 /*
999 * The R6000 is the only R-series CPU that features a machine
1000 * check exception (similar to the R4000 cache error) and
1001 * unaligned ldc1/sdc1 exception. The handlers have not been
1002 * written yet. Well, anyway there is no R6000 machine on the
1003 * current list of targets for Linux/MIPS.
1004 * (Duh, crap, there is someone with a tripple R6k machine)
1005 */
1006 //set_except_vector(14, handle_mc);
1007 //set_except_vector(15, handle_ndc);
1008 }
1009
1010 if (cpu_has_fpu) {
1011 save_fp_context = _save_fp_context;
1012 restore_fp_context = _restore_fp_context;
1013 } else {
1014 save_fp_context = fpu_emulator_save_context;
1015 restore_fp_context = fpu_emulator_restore_context;
1016 }
1017
1018 if (board_nmi_handler_setup)
1019 board_nmi_handler_setup();
1020
1021 flush_icache_range(KSEG0, KSEG0 + 0x400);
1022
1023 atomic_inc(&init_mm.mm_count); /* XXX UP? */
1024 current->active_mm = &init_mm;
1025
1026 /* XXX Must be done for all CPUs */
1027 current_cpu_data.asid_cache = ASID_FIRST_VERSION;
1028 TLBMISS_HANDLER_SETUP();
1029 }
1030