1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2010 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 14 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 15 16 struct license_key { 17 u32 reserved[6]; 18 19 u32 max_iscsi_conn; 20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 24 25 u32 reserved_a; 26 27 u32 max_fcoe_conn; 28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 32 33 u32 reserved_b[4]; 34 }; 35 36 #define PORT_0 0 37 #define PORT_1 1 38 #define PORT_MAX 2 39 40 /**************************************************************************** 41 * Shared HW configuration * 42 ****************************************************************************/ 43 struct shared_hw_cfg { /* NVRAM Offset */ 44 /* Up to 16 bytes of NULL-terminated string */ 45 u8 part_num[16]; /* 0x104 */ 46 47 u32 config; /* 0x114 */ 48 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 49 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 50 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 51 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 52 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 53 54 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 55 56 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 57 58 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 59 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 60 /* Whatever MFW found in NVM 61 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 62 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 63 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 64 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 65 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 66 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 67 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 68 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 69 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 70 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 71 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 72 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 73 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 74 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 75 76 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 77 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 78 #define SHARED_HW_CFG_LED_MAC1 0x00000000 79 #define SHARED_HW_CFG_LED_PHY1 0x00010000 80 #define SHARED_HW_CFG_LED_PHY2 0x00020000 81 #define SHARED_HW_CFG_LED_PHY3 0x00030000 82 #define SHARED_HW_CFG_LED_MAC2 0x00040000 83 #define SHARED_HW_CFG_LED_PHY4 0x00050000 84 #define SHARED_HW_CFG_LED_PHY5 0x00060000 85 #define SHARED_HW_CFG_LED_PHY6 0x00070000 86 #define SHARED_HW_CFG_LED_MAC3 0x00080000 87 #define SHARED_HW_CFG_LED_PHY7 0x00090000 88 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 89 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 90 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 91 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 92 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 93 94 95 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 96 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 97 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 98 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 99 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 100 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 101 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 102 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 103 104 u32 config2; /* 0x118 */ 105 /* one time auto detect grace period (in sec) */ 106 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 107 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 108 109 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 110 111 /* The default value for the core clock is 250MHz and it is 112 achieved by setting the clock change to 4 */ 113 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 114 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 115 116 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 117 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 118 119 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 120 121 /* The fan failure mechanism is usually related to the PHY type 122 since the power consumption of the board is determined by the PHY. 123 Currently, fan is required for most designs with SFX7101, BCM8727 124 and BCM8481. If a fan is not required for a board which uses one 125 of those PHYs, this field should be set to "Disabled". If a fan is 126 required for a different PHY type, this option should be set to 127 "Enabled". 128 The fan failure indication is expected on 129 SPIO5 */ 130 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 131 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 132 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 133 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 134 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 135 136 /* Set the MDC/MDIO access for the first external phy */ 137 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 138 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 139 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 140 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 141 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 142 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 143 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 144 145 /* Set the MDC/MDIO access for the second external phy */ 146 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 147 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 148 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 149 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 150 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 151 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 152 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 153 u32 power_dissipated; /* 0x11c */ 154 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 155 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 156 157 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 158 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 159 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 160 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 161 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 162 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 163 164 u32 ump_nc_si_config; /* 0x120 */ 165 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 166 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 167 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 168 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 169 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 170 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 171 172 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 173 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 174 175 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 176 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 177 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 178 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 179 180 u32 board; /* 0x124 */ 181 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 182 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 183 184 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 185 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 186 187 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 188 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 189 190 u32 reserved; /* 0x128 */ 191 192 }; 193 194 195 /**************************************************************************** 196 * Port HW configuration * 197 ****************************************************************************/ 198 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 199 200 u32 pci_id; 201 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 202 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 203 204 u32 pci_sub_id; 205 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 206 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 207 208 u32 power_dissipated; 209 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 210 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 211 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 212 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 213 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 214 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 215 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 216 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 217 218 u32 power_consumed; 219 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 220 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 221 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 222 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 223 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 224 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 225 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 226 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 227 228 u32 mac_upper; 229 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 230 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 231 u32 mac_lower; 232 233 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 234 u32 iscsi_mac_lower; 235 236 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 237 u32 rdma_mac_lower; 238 239 u32 serdes_config; 240 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 241 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 242 243 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 244 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 245 246 247 u32 Reserved0[3]; /* 0x158 */ 248 /* Controls the TX laser of the SFP+ module */ 249 u32 sfp_ctrl; /* 0x164 */ 250 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 251 #define PORT_HW_CFG_TX_LASER_SHIFT 0 252 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 253 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 254 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 255 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 256 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 257 258 /* Controls the fault module LED of the SFP+ */ 259 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 260 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 261 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 262 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 263 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 264 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 265 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 266 u32 Reserved01[12]; /* 0x158 */ 267 /* for external PHY, or forced mode or during AN */ 268 u16 xgxs_config_rx[4]; /* 0x198 */ 269 270 u16 xgxs_config_tx[4]; /* 0x1A0 */ 271 272 u32 Reserved1[56]; /* 0x1A8 */ 273 u32 default_cfg; /* 0x288 */ 274 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 275 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 276 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 277 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 278 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 279 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 280 281 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 282 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 283 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 284 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 285 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 286 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 287 288 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 289 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 290 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 291 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 292 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 293 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 294 295 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 296 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 297 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 298 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 299 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 300 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 301 302 /* 303 * When KR link is required to be set to force which is not 304 * KR-compliant, this parameter determine what is the trigger for it. 305 * When GPIO is selected, low input will force the speed. Currently 306 * default speed is 1G. In the future, it may be widen to select the 307 * forced speed in with another parameter. Note when force-1G is 308 * enabled, it override option 56: Link Speed option. 309 */ 310 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 311 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 312 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 313 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 314 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 315 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 316 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 317 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 318 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 319 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 320 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 321 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 322 /* Enable to determine with which GPIO to reset the external phy */ 323 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 324 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 325 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 326 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 327 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 328 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 329 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 330 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 331 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 332 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 333 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 334 /* Enable BAM on KR */ 335 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 336 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 337 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 338 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 339 340 /* Enable Common Mode Sense */ 341 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 342 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 343 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 344 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 345 346 u32 speed_capability_mask2; /* 0x28C */ 347 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 348 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 349 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 350 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 351 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 352 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 353 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 354 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 355 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 356 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080 357 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100 358 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200 359 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400 360 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800 361 362 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 363 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 364 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 365 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 366 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 367 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 368 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 369 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 370 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 371 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000 372 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000 373 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000 374 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000 375 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000 376 377 /* In the case where two media types (e.g. copper and fiber) are 378 present and electrically active at the same time, PHY Selection 379 will determine which of the two PHYs will be designated as the 380 Active PHY and used for a connection to the network. */ 381 u32 multi_phy_config; /* 0x290 */ 382 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 383 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 384 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 385 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 386 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 387 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 388 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 389 390 /* When enabled, all second phy nvram parameters will be swapped 391 with the first phy parameters */ 392 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 393 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 394 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 395 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 396 397 398 /* Address of the second external phy */ 399 u32 external_phy_config2; /* 0x294 */ 400 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 401 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 402 403 /* The second XGXS external PHY type */ 404 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 405 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 406 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 407 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 408 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 409 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 410 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 411 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 412 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 413 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 414 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 415 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 416 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 417 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 418 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 419 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 420 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 421 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 422 423 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 424 8706, 8726 and 8727) not all 4 values are needed. */ 425 u16 xgxs_config2_rx[4]; /* 0x296 */ 426 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 427 428 u32 lane_config; 429 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 430 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 431 432 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 433 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 434 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 435 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 436 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 437 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 438 /* AN and forced */ 439 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 440 /* forced only */ 441 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 442 /* forced only */ 443 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 444 /* forced only */ 445 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 446 /* Indicate whether to swap the external phy polarity */ 447 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 448 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 449 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 450 451 u32 external_phy_config; 452 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 453 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 454 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 455 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 456 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 457 458 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 459 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 460 461 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 462 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 463 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 464 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 465 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 466 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 467 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 468 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 469 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 470 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 471 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 472 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 473 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 474 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 475 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 476 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 477 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 478 479 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 480 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 481 482 u32 speed_capability_mask; 483 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 484 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 485 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 486 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 487 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 488 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 489 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 490 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 491 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 492 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000 493 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000 494 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000 495 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000 496 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000 497 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 498 499 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 500 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 501 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 502 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 503 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 504 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 505 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 506 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 507 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 508 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080 509 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100 510 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200 511 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400 512 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800 513 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 514 515 u32 reserved[2]; 516 517 }; 518 519 520 /**************************************************************************** 521 * Shared Feature configuration * 522 ****************************************************************************/ 523 struct shared_feat_cfg { /* NVRAM Offset */ 524 525 u32 config; /* 0x450 */ 526 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 527 528 /* Use the values from options 47 and 48 instead of the HW default 529 values */ 530 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000 531 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002 532 533 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 534 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 535 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 536 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 537 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 538 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 539 540 }; 541 542 543 /**************************************************************************** 544 * Port Feature configuration * 545 ****************************************************************************/ 546 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 547 548 u32 config; 549 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 550 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 551 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 552 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 553 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 554 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 555 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 556 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 557 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 558 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 559 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 560 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 561 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 562 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 563 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 564 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 565 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 566 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 567 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 568 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 569 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 570 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 571 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 572 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 573 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 574 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 575 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 576 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 577 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 578 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 579 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 580 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 581 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 582 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 583 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 584 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 585 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000 586 #define PORT_FEATURE_EN_SIZE_SHIFT 24 587 #define PORT_FEATURE_WOL_ENABLED 0x01000000 588 #define PORT_FEATURE_MBA_ENABLED 0x02000000 589 #define PORT_FEATURE_MFW_ENABLED 0x04000000 590 591 /* Reserved bits: 28-29 */ 592 /* Check the optic vendor via i2c against a list of approved modules 593 in a separate nvram image */ 594 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 595 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 596 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000 597 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000 598 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 599 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 600 601 602 u32 wol_config; 603 /* Default is used when driver sets to "auto" mode */ 604 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 605 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 606 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 607 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 608 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 609 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 610 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 611 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 612 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 613 614 u32 mba_config; 615 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003 616 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 617 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 618 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 619 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 620 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 621 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 622 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 623 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 624 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 625 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 626 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 627 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 628 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 629 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 630 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 631 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 632 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 633 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 634 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 635 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 636 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 637 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 638 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 639 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 640 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 641 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 642 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 643 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 644 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 645 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 646 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 647 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 648 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 649 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 650 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 651 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 652 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 653 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 654 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 655 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 656 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 657 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 658 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 659 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 660 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 661 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 662 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000 663 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000 664 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000 665 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000 666 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000 667 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000 668 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000 669 670 u32 bmc_config; 671 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 672 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 673 674 u32 mba_vlan_cfg; 675 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 676 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 677 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 678 679 u32 resource_cfg; 680 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 681 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 682 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 683 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 684 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 685 686 u32 smbus_config; 687 /* Obsolete */ 688 #define PORT_FEATURE_SMBUS_EN 0x00000001 689 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 690 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 691 692 u32 reserved1; 693 694 u32 link_config; /* Used as HW defaults for the driver */ 695 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 696 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 697 /* (forced) low speed switch (< 10G) */ 698 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 699 /* (forced) high speed switch (>= 10G) */ 700 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 701 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 702 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 703 704 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 705 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 706 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 707 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 708 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 709 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 710 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 711 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 712 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 713 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 714 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000 715 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000 716 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000 717 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000 718 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000 719 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000 720 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000 721 722 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 723 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 724 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 725 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 726 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 727 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 728 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 729 730 /* The default for MCP link configuration, 731 uses the same defines as link_config */ 732 u32 mfw_wol_link_cfg; 733 /* The default for the driver of the second external phy, 734 uses the same defines as link_config */ 735 u32 link_config2; /* 0x47C */ 736 737 /* The default for MCP of the second external phy, 738 uses the same defines as link_config */ 739 u32 mfw_wol_link_cfg2; /* 0x480 */ 740 741 u32 Reserved2[17]; /* 0x484 */ 742 743 }; 744 745 746 /**************************************************************************** 747 * Device Information * 748 ****************************************************************************/ 749 struct shm_dev_info { /* size */ 750 751 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 752 753 struct shared_hw_cfg shared_hw_config; /* 40 */ 754 755 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 756 757 struct shared_feat_cfg shared_feature_config; /* 4 */ 758 759 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 760 761 }; 762 763 764 #define FUNC_0 0 765 #define FUNC_1 1 766 #define FUNC_2 2 767 #define FUNC_3 3 768 #define FUNC_4 4 769 #define FUNC_5 5 770 #define FUNC_6 6 771 #define FUNC_7 7 772 #define E1_FUNC_MAX 2 773 #define E1H_FUNC_MAX 8 774 #define E2_FUNC_MAX 4 /* per path */ 775 776 #define VN_0 0 777 #define VN_1 1 778 #define VN_2 2 779 #define VN_3 3 780 #define E1VN_MAX 1 781 #define E1HVN_MAX 4 782 783 #define E2_VF_MAX 64 784 /* This value (in milliseconds) determines the frequency of the driver 785 * issuing the PULSE message code. The firmware monitors this periodic 786 * pulse to determine when to switch to an OS-absent mode. */ 787 #define DRV_PULSE_PERIOD_MS 250 788 789 /* This value (in milliseconds) determines how long the driver should 790 * wait for an acknowledgement from the firmware before timing out. Once 791 * the firmware has timed out, the driver will assume there is no firmware 792 * running and there won't be any firmware-driver synchronization during a 793 * driver reset. */ 794 #define FW_ACK_TIME_OUT_MS 5000 795 796 #define FW_ACK_POLL_TIME_MS 1 797 798 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 799 800 /* LED Blink rate that will achieve ~15.9Hz */ 801 #define LED_BLINK_RATE_VAL 480 802 803 /**************************************************************************** 804 * Driver <-> FW Mailbox * 805 ****************************************************************************/ 806 struct drv_port_mb { 807 808 u32 link_status; 809 /* Driver should update this field on any link change event */ 810 811 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 812 #define LINK_STATUS_LINK_UP 0x00000001 813 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 814 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 815 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 816 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 817 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 818 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 819 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 820 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 821 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 822 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 823 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 824 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 825 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 826 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 827 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 828 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1) 829 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1) 830 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1) 831 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1) 832 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1) 833 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1) 834 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1) 835 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1) 836 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1) 837 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1) 838 839 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 840 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 841 842 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 843 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 844 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 845 846 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 847 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 848 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 849 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 850 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 851 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 852 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 853 854 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 855 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 856 857 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 858 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 859 860 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 861 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 862 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 863 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 864 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 865 866 #define LINK_STATUS_SERDES_LINK 0x00100000 867 868 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 869 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 870 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 871 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000 872 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000 873 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000 874 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 875 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 876 877 u32 port_stx; 878 879 u32 stat_nig_timer; 880 881 /* MCP firmware does not use this field */ 882 u32 ext_phy_fw_version; 883 884 }; 885 886 887 struct drv_func_mb { 888 889 u32 drv_mb_header; 890 #define DRV_MSG_CODE_MASK 0xffff0000 891 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 892 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 893 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 894 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 895 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 896 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 897 #define DRV_MSG_CODE_DCC_OK 0x30000000 898 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 899 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 900 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 901 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 902 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 903 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 904 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 905 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 906 /* 907 * The optic module verification commands require bootcode 908 * v5.0.6 or later 909 */ 910 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 911 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 912 /* 913 * The specific optic module verification command requires bootcode 914 * v5.2.12 or later 915 */ 916 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 917 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 918 919 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 920 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 921 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 922 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 923 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 924 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 925 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 926 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 927 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 928 929 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 930 931 u32 drv_mb_param; 932 933 u32 fw_mb_header; 934 #define FW_MSG_CODE_MASK 0xffff0000 935 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 936 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 937 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 938 /* Load common chip is supported from bc 6.0.0 */ 939 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 940 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 941 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 942 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 943 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 944 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 945 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 946 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 947 #define FW_MSG_CODE_DCC_DONE 0x30100000 948 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 949 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 950 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 951 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 952 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 953 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 954 #define FW_MSG_CODE_NO_KEY 0x80f00000 955 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 956 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 957 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 958 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 959 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 960 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 961 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 962 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 963 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 964 965 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 966 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 967 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 968 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 969 970 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 971 972 u32 fw_mb_param; 973 974 u32 drv_pulse_mb; 975 #define DRV_PULSE_SEQ_MASK 0x00007fff 976 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 977 /* The system time is in the format of 978 * (year-2001)*12*32 + month*32 + day. */ 979 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 980 /* Indicate to the firmware not to go into the 981 * OS-absent when it is not getting driver pulse. 982 * This is used for debugging as well for PXE(MBA). */ 983 984 u32 mcp_pulse_mb; 985 #define MCP_PULSE_SEQ_MASK 0x00007fff 986 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 987 /* Indicates to the driver not to assert due to lack 988 * of MCP response */ 989 #define MCP_EVENT_MASK 0xffff0000 990 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 991 992 u32 iscsi_boot_signature; 993 u32 iscsi_boot_block_offset; 994 995 u32 drv_status; 996 #define DRV_STATUS_PMF 0x00000001 997 #define DRV_STATUS_SET_MF_BW 0x00000004 998 999 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1000 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1001 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1002 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1003 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1004 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1005 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1006 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1007 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1008 1009 u32 virt_mac_upper; 1010 #define VIRT_MAC_SIGN_MASK 0xffff0000 1011 #define VIRT_MAC_SIGNATURE 0x564d0000 1012 u32 virt_mac_lower; 1013 1014 }; 1015 1016 1017 /**************************************************************************** 1018 * Management firmware state * 1019 ****************************************************************************/ 1020 /* Allocate 440 bytes for management firmware */ 1021 #define MGMTFW_STATE_WORD_SIZE 110 1022 1023 struct mgmtfw_state { 1024 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1025 }; 1026 1027 1028 /**************************************************************************** 1029 * Multi-Function configuration * 1030 ****************************************************************************/ 1031 struct shared_mf_cfg { 1032 1033 u32 clp_mb; 1034 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1035 /* set by CLP */ 1036 #define SHARED_MF_CLP_EXIT 0x00000001 1037 /* set by MCP */ 1038 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1039 1040 }; 1041 1042 struct port_mf_cfg { 1043 1044 u32 dynamic_cfg; /* device control channel */ 1045 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1046 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1047 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1048 1049 u32 reserved[3]; 1050 1051 }; 1052 1053 struct func_mf_cfg { 1054 1055 u32 config; 1056 /* E/R/I/D */ 1057 /* function 0 of each port cannot be hidden */ 1058 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1059 1060 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007 1061 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1062 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1063 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1064 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\ 1065 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1066 1067 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1068 1069 /* PRI */ 1070 /* 0 - low priority, 3 - high priority */ 1071 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1072 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1073 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1074 1075 /* MINBW, MAXBW */ 1076 /* value range - 0..100, increments in 100Mbps */ 1077 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1078 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1079 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1080 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1081 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1082 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1083 1084 u32 mac_upper; /* MAC */ 1085 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1086 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1087 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1088 u32 mac_lower; 1089 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1090 1091 u32 e1hov_tag; /* VNI */ 1092 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1093 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1094 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1095 1096 u32 reserved[2]; 1097 1098 }; 1099 1100 /* This structure is not applicable and should not be accessed on 57711 */ 1101 struct func_ext_cfg { 1102 u32 func_cfg; 1103 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF 1104 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1105 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1106 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1107 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1108 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1109 1110 u32 iscsi_mac_addr_upper; 1111 u32 iscsi_mac_addr_lower; 1112 1113 u32 fcoe_mac_addr_upper; 1114 u32 fcoe_mac_addr_lower; 1115 1116 u32 fcoe_wwn_port_name_upper; 1117 u32 fcoe_wwn_port_name_lower; 1118 1119 u32 fcoe_wwn_node_name_upper; 1120 u32 fcoe_wwn_node_name_lower; 1121 1122 u32 preserve_data; 1123 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1124 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1125 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1126 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1127 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1128 }; 1129 1130 struct mf_cfg { 1131 1132 struct shared_mf_cfg shared_mf_config; 1133 struct port_mf_cfg port_mf_config[PORT_MAX]; 1134 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; 1135 1136 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; 1137 }; 1138 1139 1140 /**************************************************************************** 1141 * Shared Memory Region * 1142 ****************************************************************************/ 1143 struct shmem_region { /* SharedMem Offset (size) */ 1144 1145 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1146 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1147 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1148 /* validity bits */ 1149 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1150 #define SHR_MEM_VALIDITY_MB 0x00200000 1151 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1152 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1153 /* One licensing bit should be set */ 1154 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1155 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1156 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1157 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1158 /* Active MFW */ 1159 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1160 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1161 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1162 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1163 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1164 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1165 1166 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1167 1168 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1169 1170 /* FW information (for internal FW use) */ 1171 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1172 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1173 1174 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1175 struct drv_func_mb func_mb[]; /* 0x684 1176 (44*2/4/8=0x58/0xb0/0x160) */ 1177 1178 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1179 1180 struct fw_flr_ack { 1181 u32 pf_ack; 1182 u32 vf_ack[1]; 1183 u32 iov_dis_ack; 1184 }; 1185 1186 struct fw_flr_mb { 1187 u32 aggint; 1188 u32 opgen_addr; 1189 struct fw_flr_ack ack; 1190 }; 1191 1192 /**** SUPPORT FOR SHMEM ARRRAYS *** 1193 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1194 * define arrays with storage types smaller then unsigned dwords. 1195 * The macros below add generic support for SHMEM arrays with numeric elements 1196 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1197 * array with individual bit-filed elements accessed using shifts and masks. 1198 * 1199 */ 1200 1201 /* eb is the bitwidth of a single element */ 1202 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1203 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1204 1205 /* the bit-position macro allows the used to flip the order of the arrays 1206 * elements on a per byte or word boundary. 1207 * 1208 * example: an array with 8 entries each 4 bit wide. This array will fit into 1209 * a single dword. The diagrmas below show the array order of the nibbles. 1210 * 1211 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1212 * 1213 * | | | | 1214 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1215 * | | | | 1216 * 1217 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1218 * 1219 * | | | | 1220 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1221 * | | | | 1222 * 1223 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1224 * 1225 * | | | | 1226 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1227 * | | | | 1228 */ 1229 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1230 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1231 (((i)%((fb)/(eb))) * (eb))) 1232 1233 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1234 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1235 SHMEM_ARRAY_MASK(eb)) 1236 1237 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1238 do { \ 1239 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1240 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1241 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1242 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1243 } while (0) 1244 1245 1246 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1247 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1248 #define DCBX_PRI_PG_BITWIDTH 4 1249 #define DCBX_PRI_PG_FBITS 8 1250 #define DCBX_PRI_PG_GET(a, i) \ 1251 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1252 #define DCBX_PRI_PG_SET(a, i, val) \ 1253 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1254 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1255 #define DCBX_BW_PG_BITWIDTH 8 1256 #define DCBX_PG_BW_GET(a, i) \ 1257 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1258 #define DCBX_PG_BW_SET(a, i, val) \ 1259 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1260 #define DCBX_STRICT_PRI_PG 15 1261 #define DCBX_MAX_APP_PROTOCOL 16 1262 #define FCOE_APP_IDX 0 1263 #define ISCSI_APP_IDX 1 1264 #define PREDEFINED_APP_IDX_MAX 2 1265 1266 struct dcbx_ets_feature { 1267 u32 enabled; 1268 u32 pg_bw_tbl[2]; 1269 u32 pri_pg_tbl[1]; 1270 }; 1271 1272 struct dcbx_pfc_feature { 1273 #ifdef __BIG_ENDIAN 1274 u8 pri_en_bitmap; 1275 #define DCBX_PFC_PRI_0 0x01 1276 #define DCBX_PFC_PRI_1 0x02 1277 #define DCBX_PFC_PRI_2 0x04 1278 #define DCBX_PFC_PRI_3 0x08 1279 #define DCBX_PFC_PRI_4 0x10 1280 #define DCBX_PFC_PRI_5 0x20 1281 #define DCBX_PFC_PRI_6 0x40 1282 #define DCBX_PFC_PRI_7 0x80 1283 u8 pfc_caps; 1284 u8 reserved; 1285 u8 enabled; 1286 #elif defined(__LITTLE_ENDIAN) 1287 u8 enabled; 1288 u8 reserved; 1289 u8 pfc_caps; 1290 u8 pri_en_bitmap; 1291 #define DCBX_PFC_PRI_0 0x01 1292 #define DCBX_PFC_PRI_1 0x02 1293 #define DCBX_PFC_PRI_2 0x04 1294 #define DCBX_PFC_PRI_3 0x08 1295 #define DCBX_PFC_PRI_4 0x10 1296 #define DCBX_PFC_PRI_5 0x20 1297 #define DCBX_PFC_PRI_6 0x40 1298 #define DCBX_PFC_PRI_7 0x80 1299 #endif 1300 }; 1301 1302 struct dcbx_app_priority_entry { 1303 #ifdef __BIG_ENDIAN 1304 u16 app_id; 1305 u8 pri_bitmap; 1306 u8 appBitfield; 1307 #define DCBX_APP_ENTRY_VALID 0x01 1308 #define DCBX_APP_ENTRY_SF_MASK 0x30 1309 #define DCBX_APP_ENTRY_SF_SHIFT 4 1310 #define DCBX_APP_SF_ETH_TYPE 0x10 1311 #define DCBX_APP_SF_PORT 0x20 1312 #elif defined(__LITTLE_ENDIAN) 1313 u8 appBitfield; 1314 #define DCBX_APP_ENTRY_VALID 0x01 1315 #define DCBX_APP_ENTRY_SF_MASK 0x30 1316 #define DCBX_APP_ENTRY_SF_SHIFT 4 1317 #define DCBX_APP_SF_ETH_TYPE 0x10 1318 #define DCBX_APP_SF_PORT 0x20 1319 u8 pri_bitmap; 1320 u16 app_id; 1321 #endif 1322 }; 1323 1324 struct dcbx_app_priority_feature { 1325 #ifdef __BIG_ENDIAN 1326 u8 reserved; 1327 u8 default_pri; 1328 u8 tc_supported; 1329 u8 enabled; 1330 #elif defined(__LITTLE_ENDIAN) 1331 u8 enabled; 1332 u8 tc_supported; 1333 u8 default_pri; 1334 u8 reserved; 1335 #endif 1336 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1337 }; 1338 1339 struct dcbx_features { 1340 struct dcbx_ets_feature ets; 1341 struct dcbx_pfc_feature pfc; 1342 struct dcbx_app_priority_feature app; 1343 }; 1344 1345 struct lldp_params { 1346 #ifdef __BIG_ENDIAN 1347 u8 msg_fast_tx_interval; 1348 u8 msg_tx_hold; 1349 u8 msg_tx_interval; 1350 u8 admin_status; 1351 #define LLDP_TX_ONLY 0x01 1352 #define LLDP_RX_ONLY 0x02 1353 #define LLDP_TX_RX 0x03 1354 #define LLDP_DISABLED 0x04 1355 u8 reserved1; 1356 u8 tx_fast; 1357 u8 tx_crd_max; 1358 u8 tx_crd; 1359 #elif defined(__LITTLE_ENDIAN) 1360 u8 admin_status; 1361 #define LLDP_TX_ONLY 0x01 1362 #define LLDP_RX_ONLY 0x02 1363 #define LLDP_TX_RX 0x03 1364 #define LLDP_DISABLED 0x04 1365 u8 msg_tx_interval; 1366 u8 msg_tx_hold; 1367 u8 msg_fast_tx_interval; 1368 u8 tx_crd; 1369 u8 tx_crd_max; 1370 u8 tx_fast; 1371 u8 reserved1; 1372 #endif 1373 #define REM_CHASSIS_ID_STAT_LEN 4 1374 #define REM_PORT_ID_STAT_LEN 4 1375 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1376 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1377 }; 1378 1379 struct lldp_dcbx_stat { 1380 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1381 #define LOCAL_PORT_ID_STAT_LEN 2 1382 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1383 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1384 u32 num_tx_dcbx_pkts; 1385 u32 num_rx_dcbx_pkts; 1386 }; 1387 1388 struct lldp_admin_mib { 1389 u32 ver_cfg_flags; 1390 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1391 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1392 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1393 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1394 #define DCBX_ETS_RECO_VALID 0x00000010 1395 #define DCBX_ETS_WILLING 0x00000020 1396 #define DCBX_PFC_WILLING 0x00000040 1397 #define DCBX_APP_WILLING 0x00000080 1398 #define DCBX_VERSION_CEE 0x00000100 1399 #define DCBX_VERSION_IEEE 0x00000200 1400 #define DCBX_DCBX_ENABLED 0x00000400 1401 #define DCBX_CEE_VERSION_MASK 0x0000f000 1402 #define DCBX_CEE_VERSION_SHIFT 12 1403 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1404 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1405 struct dcbx_features features; 1406 }; 1407 1408 struct lldp_remote_mib { 1409 u32 prefix_seq_num; 1410 u32 flags; 1411 #define DCBX_ETS_TLV_RX 0x00000001 1412 #define DCBX_PFC_TLV_RX 0x00000002 1413 #define DCBX_APP_TLV_RX 0x00000004 1414 #define DCBX_ETS_RX_ERROR 0x00000010 1415 #define DCBX_PFC_RX_ERROR 0x00000020 1416 #define DCBX_APP_RX_ERROR 0x00000040 1417 #define DCBX_ETS_REM_WILLING 0x00000100 1418 #define DCBX_PFC_REM_WILLING 0x00000200 1419 #define DCBX_APP_REM_WILLING 0x00000400 1420 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1421 struct dcbx_features features; 1422 u32 suffix_seq_num; 1423 }; 1424 1425 struct lldp_local_mib { 1426 u32 prefix_seq_num; 1427 u32 error; 1428 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1429 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1430 #define DCBX_LOCAL_APP_ERROR 0x00000004 1431 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1432 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1433 struct dcbx_features features; 1434 u32 suffix_seq_num; 1435 }; 1436 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1437 1438 struct shmem2_region { 1439 1440 u32 size; 1441 1442 u32 dcc_support; 1443 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 1444 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 1445 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 1446 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 1447 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 1448 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 1449 #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE 1450 u32 ext_phy_fw_version2[PORT_MAX]; 1451 /* 1452 * For backwards compatibility, if the mf_cfg_addr does not exist 1453 * (the size filed is smaller than 0xc) the mf_cfg resides at the 1454 * end of struct shmem_region 1455 */ 1456 u32 mf_cfg_addr; 1457 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 1458 1459 struct fw_flr_mb flr_mb; 1460 u32 dcbx_lldp_params_offset; 1461 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 1462 u32 dcbx_neg_res_offset; 1463 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 1464 u32 dcbx_remote_mib_offset; 1465 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 1466 /* 1467 * The other shmemX_base_addr holds the other path's shmem address 1468 * required for example in case of common phy init, or for path1 to know 1469 * the address of mcp debug trace which is located in offset from shmem 1470 * of path0 1471 */ 1472 u32 other_shmem_base_addr; 1473 u32 other_shmem2_base_addr; 1474 u32 reserved1[E2_VF_MAX / 32]; 1475 u32 reserved2[E2_FUNC_MAX][E2_VF_MAX / 32]; 1476 u32 dcbx_lldp_dcbx_stat_offset; 1477 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 1478 }; 1479 1480 1481 struct emac_stats { 1482 u32 rx_stat_ifhcinoctets; 1483 u32 rx_stat_ifhcinbadoctets; 1484 u32 rx_stat_etherstatsfragments; 1485 u32 rx_stat_ifhcinucastpkts; 1486 u32 rx_stat_ifhcinmulticastpkts; 1487 u32 rx_stat_ifhcinbroadcastpkts; 1488 u32 rx_stat_dot3statsfcserrors; 1489 u32 rx_stat_dot3statsalignmenterrors; 1490 u32 rx_stat_dot3statscarriersenseerrors; 1491 u32 rx_stat_xonpauseframesreceived; 1492 u32 rx_stat_xoffpauseframesreceived; 1493 u32 rx_stat_maccontrolframesreceived; 1494 u32 rx_stat_xoffstateentered; 1495 u32 rx_stat_dot3statsframestoolong; 1496 u32 rx_stat_etherstatsjabbers; 1497 u32 rx_stat_etherstatsundersizepkts; 1498 u32 rx_stat_etherstatspkts64octets; 1499 u32 rx_stat_etherstatspkts65octetsto127octets; 1500 u32 rx_stat_etherstatspkts128octetsto255octets; 1501 u32 rx_stat_etherstatspkts256octetsto511octets; 1502 u32 rx_stat_etherstatspkts512octetsto1023octets; 1503 u32 rx_stat_etherstatspkts1024octetsto1522octets; 1504 u32 rx_stat_etherstatspktsover1522octets; 1505 1506 u32 rx_stat_falsecarriererrors; 1507 1508 u32 tx_stat_ifhcoutoctets; 1509 u32 tx_stat_ifhcoutbadoctets; 1510 u32 tx_stat_etherstatscollisions; 1511 u32 tx_stat_outxonsent; 1512 u32 tx_stat_outxoffsent; 1513 u32 tx_stat_flowcontroldone; 1514 u32 tx_stat_dot3statssinglecollisionframes; 1515 u32 tx_stat_dot3statsmultiplecollisionframes; 1516 u32 tx_stat_dot3statsdeferredtransmissions; 1517 u32 tx_stat_dot3statsexcessivecollisions; 1518 u32 tx_stat_dot3statslatecollisions; 1519 u32 tx_stat_ifhcoutucastpkts; 1520 u32 tx_stat_ifhcoutmulticastpkts; 1521 u32 tx_stat_ifhcoutbroadcastpkts; 1522 u32 tx_stat_etherstatspkts64octets; 1523 u32 tx_stat_etherstatspkts65octetsto127octets; 1524 u32 tx_stat_etherstatspkts128octetsto255octets; 1525 u32 tx_stat_etherstatspkts256octetsto511octets; 1526 u32 tx_stat_etherstatspkts512octetsto1023octets; 1527 u32 tx_stat_etherstatspkts1024octetsto1522octets; 1528 u32 tx_stat_etherstatspktsover1522octets; 1529 u32 tx_stat_dot3statsinternalmactransmiterrors; 1530 }; 1531 1532 1533 struct bmac1_stats { 1534 u32 tx_stat_gtpkt_lo; 1535 u32 tx_stat_gtpkt_hi; 1536 u32 tx_stat_gtxpf_lo; 1537 u32 tx_stat_gtxpf_hi; 1538 u32 tx_stat_gtfcs_lo; 1539 u32 tx_stat_gtfcs_hi; 1540 u32 tx_stat_gtmca_lo; 1541 u32 tx_stat_gtmca_hi; 1542 u32 tx_stat_gtbca_lo; 1543 u32 tx_stat_gtbca_hi; 1544 u32 tx_stat_gtfrg_lo; 1545 u32 tx_stat_gtfrg_hi; 1546 u32 tx_stat_gtovr_lo; 1547 u32 tx_stat_gtovr_hi; 1548 u32 tx_stat_gt64_lo; 1549 u32 tx_stat_gt64_hi; 1550 u32 tx_stat_gt127_lo; 1551 u32 tx_stat_gt127_hi; 1552 u32 tx_stat_gt255_lo; 1553 u32 tx_stat_gt255_hi; 1554 u32 tx_stat_gt511_lo; 1555 u32 tx_stat_gt511_hi; 1556 u32 tx_stat_gt1023_lo; 1557 u32 tx_stat_gt1023_hi; 1558 u32 tx_stat_gt1518_lo; 1559 u32 tx_stat_gt1518_hi; 1560 u32 tx_stat_gt2047_lo; 1561 u32 tx_stat_gt2047_hi; 1562 u32 tx_stat_gt4095_lo; 1563 u32 tx_stat_gt4095_hi; 1564 u32 tx_stat_gt9216_lo; 1565 u32 tx_stat_gt9216_hi; 1566 u32 tx_stat_gt16383_lo; 1567 u32 tx_stat_gt16383_hi; 1568 u32 tx_stat_gtmax_lo; 1569 u32 tx_stat_gtmax_hi; 1570 u32 tx_stat_gtufl_lo; 1571 u32 tx_stat_gtufl_hi; 1572 u32 tx_stat_gterr_lo; 1573 u32 tx_stat_gterr_hi; 1574 u32 tx_stat_gtbyt_lo; 1575 u32 tx_stat_gtbyt_hi; 1576 1577 u32 rx_stat_gr64_lo; 1578 u32 rx_stat_gr64_hi; 1579 u32 rx_stat_gr127_lo; 1580 u32 rx_stat_gr127_hi; 1581 u32 rx_stat_gr255_lo; 1582 u32 rx_stat_gr255_hi; 1583 u32 rx_stat_gr511_lo; 1584 u32 rx_stat_gr511_hi; 1585 u32 rx_stat_gr1023_lo; 1586 u32 rx_stat_gr1023_hi; 1587 u32 rx_stat_gr1518_lo; 1588 u32 rx_stat_gr1518_hi; 1589 u32 rx_stat_gr2047_lo; 1590 u32 rx_stat_gr2047_hi; 1591 u32 rx_stat_gr4095_lo; 1592 u32 rx_stat_gr4095_hi; 1593 u32 rx_stat_gr9216_lo; 1594 u32 rx_stat_gr9216_hi; 1595 u32 rx_stat_gr16383_lo; 1596 u32 rx_stat_gr16383_hi; 1597 u32 rx_stat_grmax_lo; 1598 u32 rx_stat_grmax_hi; 1599 u32 rx_stat_grpkt_lo; 1600 u32 rx_stat_grpkt_hi; 1601 u32 rx_stat_grfcs_lo; 1602 u32 rx_stat_grfcs_hi; 1603 u32 rx_stat_grmca_lo; 1604 u32 rx_stat_grmca_hi; 1605 u32 rx_stat_grbca_lo; 1606 u32 rx_stat_grbca_hi; 1607 u32 rx_stat_grxcf_lo; 1608 u32 rx_stat_grxcf_hi; 1609 u32 rx_stat_grxpf_lo; 1610 u32 rx_stat_grxpf_hi; 1611 u32 rx_stat_grxuo_lo; 1612 u32 rx_stat_grxuo_hi; 1613 u32 rx_stat_grjbr_lo; 1614 u32 rx_stat_grjbr_hi; 1615 u32 rx_stat_grovr_lo; 1616 u32 rx_stat_grovr_hi; 1617 u32 rx_stat_grflr_lo; 1618 u32 rx_stat_grflr_hi; 1619 u32 rx_stat_grmeg_lo; 1620 u32 rx_stat_grmeg_hi; 1621 u32 rx_stat_grmeb_lo; 1622 u32 rx_stat_grmeb_hi; 1623 u32 rx_stat_grbyt_lo; 1624 u32 rx_stat_grbyt_hi; 1625 u32 rx_stat_grund_lo; 1626 u32 rx_stat_grund_hi; 1627 u32 rx_stat_grfrg_lo; 1628 u32 rx_stat_grfrg_hi; 1629 u32 rx_stat_grerb_lo; 1630 u32 rx_stat_grerb_hi; 1631 u32 rx_stat_grfre_lo; 1632 u32 rx_stat_grfre_hi; 1633 u32 rx_stat_gripj_lo; 1634 u32 rx_stat_gripj_hi; 1635 }; 1636 1637 struct bmac2_stats { 1638 u32 tx_stat_gtpk_lo; /* gtpok */ 1639 u32 tx_stat_gtpk_hi; /* gtpok */ 1640 u32 tx_stat_gtxpf_lo; /* gtpf */ 1641 u32 tx_stat_gtxpf_hi; /* gtpf */ 1642 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 1643 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 1644 u32 tx_stat_gtfcs_lo; 1645 u32 tx_stat_gtfcs_hi; 1646 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 1647 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 1648 u32 tx_stat_gtmca_lo; 1649 u32 tx_stat_gtmca_hi; 1650 u32 tx_stat_gtbca_lo; 1651 u32 tx_stat_gtbca_hi; 1652 u32 tx_stat_gtovr_lo; 1653 u32 tx_stat_gtovr_hi; 1654 u32 tx_stat_gtfrg_lo; 1655 u32 tx_stat_gtfrg_hi; 1656 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 1657 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 1658 u32 tx_stat_gt64_lo; 1659 u32 tx_stat_gt64_hi; 1660 u32 tx_stat_gt127_lo; 1661 u32 tx_stat_gt127_hi; 1662 u32 tx_stat_gt255_lo; 1663 u32 tx_stat_gt255_hi; 1664 u32 tx_stat_gt511_lo; 1665 u32 tx_stat_gt511_hi; 1666 u32 tx_stat_gt1023_lo; 1667 u32 tx_stat_gt1023_hi; 1668 u32 tx_stat_gt1518_lo; 1669 u32 tx_stat_gt1518_hi; 1670 u32 tx_stat_gt2047_lo; 1671 u32 tx_stat_gt2047_hi; 1672 u32 tx_stat_gt4095_lo; 1673 u32 tx_stat_gt4095_hi; 1674 u32 tx_stat_gt9216_lo; 1675 u32 tx_stat_gt9216_hi; 1676 u32 tx_stat_gt16383_lo; 1677 u32 tx_stat_gt16383_hi; 1678 u32 tx_stat_gtmax_lo; 1679 u32 tx_stat_gtmax_hi; 1680 u32 tx_stat_gtufl_lo; 1681 u32 tx_stat_gtufl_hi; 1682 u32 tx_stat_gterr_lo; 1683 u32 tx_stat_gterr_hi; 1684 u32 tx_stat_gtbyt_lo; 1685 u32 tx_stat_gtbyt_hi; 1686 1687 u32 rx_stat_gr64_lo; 1688 u32 rx_stat_gr64_hi; 1689 u32 rx_stat_gr127_lo; 1690 u32 rx_stat_gr127_hi; 1691 u32 rx_stat_gr255_lo; 1692 u32 rx_stat_gr255_hi; 1693 u32 rx_stat_gr511_lo; 1694 u32 rx_stat_gr511_hi; 1695 u32 rx_stat_gr1023_lo; 1696 u32 rx_stat_gr1023_hi; 1697 u32 rx_stat_gr1518_lo; 1698 u32 rx_stat_gr1518_hi; 1699 u32 rx_stat_gr2047_lo; 1700 u32 rx_stat_gr2047_hi; 1701 u32 rx_stat_gr4095_lo; 1702 u32 rx_stat_gr4095_hi; 1703 u32 rx_stat_gr9216_lo; 1704 u32 rx_stat_gr9216_hi; 1705 u32 rx_stat_gr16383_lo; 1706 u32 rx_stat_gr16383_hi; 1707 u32 rx_stat_grmax_lo; 1708 u32 rx_stat_grmax_hi; 1709 u32 rx_stat_grpkt_lo; 1710 u32 rx_stat_grpkt_hi; 1711 u32 rx_stat_grfcs_lo; 1712 u32 rx_stat_grfcs_hi; 1713 u32 rx_stat_gruca_lo; 1714 u32 rx_stat_gruca_hi; 1715 u32 rx_stat_grmca_lo; 1716 u32 rx_stat_grmca_hi; 1717 u32 rx_stat_grbca_lo; 1718 u32 rx_stat_grbca_hi; 1719 u32 rx_stat_grxpf_lo; /* grpf */ 1720 u32 rx_stat_grxpf_hi; /* grpf */ 1721 u32 rx_stat_grpp_lo; 1722 u32 rx_stat_grpp_hi; 1723 u32 rx_stat_grxuo_lo; /* gruo */ 1724 u32 rx_stat_grxuo_hi; /* gruo */ 1725 u32 rx_stat_grjbr_lo; 1726 u32 rx_stat_grjbr_hi; 1727 u32 rx_stat_grovr_lo; 1728 u32 rx_stat_grovr_hi; 1729 u32 rx_stat_grxcf_lo; /* grcf */ 1730 u32 rx_stat_grxcf_hi; /* grcf */ 1731 u32 rx_stat_grflr_lo; 1732 u32 rx_stat_grflr_hi; 1733 u32 rx_stat_grpok_lo; 1734 u32 rx_stat_grpok_hi; 1735 u32 rx_stat_grmeg_lo; 1736 u32 rx_stat_grmeg_hi; 1737 u32 rx_stat_grmeb_lo; 1738 u32 rx_stat_grmeb_hi; 1739 u32 rx_stat_grbyt_lo; 1740 u32 rx_stat_grbyt_hi; 1741 u32 rx_stat_grund_lo; 1742 u32 rx_stat_grund_hi; 1743 u32 rx_stat_grfrg_lo; 1744 u32 rx_stat_grfrg_hi; 1745 u32 rx_stat_grerb_lo; /* grerrbyt */ 1746 u32 rx_stat_grerb_hi; /* grerrbyt */ 1747 u32 rx_stat_grfre_lo; /* grfrerr */ 1748 u32 rx_stat_grfre_hi; /* grfrerr */ 1749 u32 rx_stat_gripj_lo; 1750 u32 rx_stat_gripj_hi; 1751 }; 1752 1753 union mac_stats { 1754 struct emac_stats emac_stats; 1755 struct bmac1_stats bmac1_stats; 1756 struct bmac2_stats bmac2_stats; 1757 }; 1758 1759 1760 struct mac_stx { 1761 /* in_bad_octets */ 1762 u32 rx_stat_ifhcinbadoctets_hi; 1763 u32 rx_stat_ifhcinbadoctets_lo; 1764 1765 /* out_bad_octets */ 1766 u32 tx_stat_ifhcoutbadoctets_hi; 1767 u32 tx_stat_ifhcoutbadoctets_lo; 1768 1769 /* crc_receive_errors */ 1770 u32 rx_stat_dot3statsfcserrors_hi; 1771 u32 rx_stat_dot3statsfcserrors_lo; 1772 /* alignment_errors */ 1773 u32 rx_stat_dot3statsalignmenterrors_hi; 1774 u32 rx_stat_dot3statsalignmenterrors_lo; 1775 /* carrier_sense_errors */ 1776 u32 rx_stat_dot3statscarriersenseerrors_hi; 1777 u32 rx_stat_dot3statscarriersenseerrors_lo; 1778 /* false_carrier_detections */ 1779 u32 rx_stat_falsecarriererrors_hi; 1780 u32 rx_stat_falsecarriererrors_lo; 1781 1782 /* runt_packets_received */ 1783 u32 rx_stat_etherstatsundersizepkts_hi; 1784 u32 rx_stat_etherstatsundersizepkts_lo; 1785 /* jabber_packets_received */ 1786 u32 rx_stat_dot3statsframestoolong_hi; 1787 u32 rx_stat_dot3statsframestoolong_lo; 1788 1789 /* error_runt_packets_received */ 1790 u32 rx_stat_etherstatsfragments_hi; 1791 u32 rx_stat_etherstatsfragments_lo; 1792 /* error_jabber_packets_received */ 1793 u32 rx_stat_etherstatsjabbers_hi; 1794 u32 rx_stat_etherstatsjabbers_lo; 1795 1796 /* control_frames_received */ 1797 u32 rx_stat_maccontrolframesreceived_hi; 1798 u32 rx_stat_maccontrolframesreceived_lo; 1799 u32 rx_stat_bmac_xpf_hi; 1800 u32 rx_stat_bmac_xpf_lo; 1801 u32 rx_stat_bmac_xcf_hi; 1802 u32 rx_stat_bmac_xcf_lo; 1803 1804 /* xoff_state_entered */ 1805 u32 rx_stat_xoffstateentered_hi; 1806 u32 rx_stat_xoffstateentered_lo; 1807 /* pause_xon_frames_received */ 1808 u32 rx_stat_xonpauseframesreceived_hi; 1809 u32 rx_stat_xonpauseframesreceived_lo; 1810 /* pause_xoff_frames_received */ 1811 u32 rx_stat_xoffpauseframesreceived_hi; 1812 u32 rx_stat_xoffpauseframesreceived_lo; 1813 /* pause_xon_frames_transmitted */ 1814 u32 tx_stat_outxonsent_hi; 1815 u32 tx_stat_outxonsent_lo; 1816 /* pause_xoff_frames_transmitted */ 1817 u32 tx_stat_outxoffsent_hi; 1818 u32 tx_stat_outxoffsent_lo; 1819 /* flow_control_done */ 1820 u32 tx_stat_flowcontroldone_hi; 1821 u32 tx_stat_flowcontroldone_lo; 1822 1823 /* ether_stats_collisions */ 1824 u32 tx_stat_etherstatscollisions_hi; 1825 u32 tx_stat_etherstatscollisions_lo; 1826 /* single_collision_transmit_frames */ 1827 u32 tx_stat_dot3statssinglecollisionframes_hi; 1828 u32 tx_stat_dot3statssinglecollisionframes_lo; 1829 /* multiple_collision_transmit_frames */ 1830 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 1831 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 1832 /* deferred_transmissions */ 1833 u32 tx_stat_dot3statsdeferredtransmissions_hi; 1834 u32 tx_stat_dot3statsdeferredtransmissions_lo; 1835 /* excessive_collision_frames */ 1836 u32 tx_stat_dot3statsexcessivecollisions_hi; 1837 u32 tx_stat_dot3statsexcessivecollisions_lo; 1838 /* late_collision_frames */ 1839 u32 tx_stat_dot3statslatecollisions_hi; 1840 u32 tx_stat_dot3statslatecollisions_lo; 1841 1842 /* frames_transmitted_64_bytes */ 1843 u32 tx_stat_etherstatspkts64octets_hi; 1844 u32 tx_stat_etherstatspkts64octets_lo; 1845 /* frames_transmitted_65_127_bytes */ 1846 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 1847 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 1848 /* frames_transmitted_128_255_bytes */ 1849 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 1850 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 1851 /* frames_transmitted_256_511_bytes */ 1852 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 1853 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 1854 /* frames_transmitted_512_1023_bytes */ 1855 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 1856 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 1857 /* frames_transmitted_1024_1522_bytes */ 1858 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 1859 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 1860 /* frames_transmitted_1523_9022_bytes */ 1861 u32 tx_stat_etherstatspktsover1522octets_hi; 1862 u32 tx_stat_etherstatspktsover1522octets_lo; 1863 u32 tx_stat_bmac_2047_hi; 1864 u32 tx_stat_bmac_2047_lo; 1865 u32 tx_stat_bmac_4095_hi; 1866 u32 tx_stat_bmac_4095_lo; 1867 u32 tx_stat_bmac_9216_hi; 1868 u32 tx_stat_bmac_9216_lo; 1869 u32 tx_stat_bmac_16383_hi; 1870 u32 tx_stat_bmac_16383_lo; 1871 1872 /* internal_mac_transmit_errors */ 1873 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 1874 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 1875 1876 /* if_out_discards */ 1877 u32 tx_stat_bmac_ufl_hi; 1878 u32 tx_stat_bmac_ufl_lo; 1879 }; 1880 1881 1882 #define MAC_STX_IDX_MAX 2 1883 1884 struct host_port_stats { 1885 u32 host_port_stats_start; 1886 1887 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 1888 1889 u32 brb_drop_hi; 1890 u32 brb_drop_lo; 1891 1892 u32 host_port_stats_end; 1893 }; 1894 1895 1896 struct host_func_stats { 1897 u32 host_func_stats_start; 1898 1899 u32 total_bytes_received_hi; 1900 u32 total_bytes_received_lo; 1901 1902 u32 total_bytes_transmitted_hi; 1903 u32 total_bytes_transmitted_lo; 1904 1905 u32 total_unicast_packets_received_hi; 1906 u32 total_unicast_packets_received_lo; 1907 1908 u32 total_multicast_packets_received_hi; 1909 u32 total_multicast_packets_received_lo; 1910 1911 u32 total_broadcast_packets_received_hi; 1912 u32 total_broadcast_packets_received_lo; 1913 1914 u32 total_unicast_packets_transmitted_hi; 1915 u32 total_unicast_packets_transmitted_lo; 1916 1917 u32 total_multicast_packets_transmitted_hi; 1918 u32 total_multicast_packets_transmitted_lo; 1919 1920 u32 total_broadcast_packets_transmitted_hi; 1921 u32 total_broadcast_packets_transmitted_lo; 1922 1923 u32 valid_bytes_received_hi; 1924 u32 valid_bytes_received_lo; 1925 1926 u32 host_func_stats_end; 1927 }; 1928 1929 1930 #define BCM_5710_FW_MAJOR_VERSION 6 1931 #define BCM_5710_FW_MINOR_VERSION 2 1932 #define BCM_5710_FW_REVISION_VERSION 5 1933 #define BCM_5710_FW_ENGINEERING_VERSION 0 1934 #define BCM_5710_FW_COMPILE_FLAGS 1 1935 1936 1937 /* 1938 * attention bits 1939 */ 1940 struct atten_sp_status_block { 1941 __le32 attn_bits; 1942 __le32 attn_bits_ack; 1943 u8 status_block_id; 1944 u8 reserved0; 1945 __le16 attn_bits_index; 1946 __le32 reserved1; 1947 }; 1948 1949 1950 /* 1951 * common data for all protocols 1952 */ 1953 struct doorbell_hdr { 1954 u8 header; 1955 #define DOORBELL_HDR_RX (0x1<<0) 1956 #define DOORBELL_HDR_RX_SHIFT 0 1957 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 1958 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 1959 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 1960 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 1961 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 1962 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 1963 }; 1964 1965 /* 1966 * doorbell message sent to the chip 1967 */ 1968 struct doorbell { 1969 #if defined(__BIG_ENDIAN) 1970 u16 zero_fill2; 1971 u8 zero_fill1; 1972 struct doorbell_hdr header; 1973 #elif defined(__LITTLE_ENDIAN) 1974 struct doorbell_hdr header; 1975 u8 zero_fill1; 1976 u16 zero_fill2; 1977 #endif 1978 }; 1979 1980 1981 /* 1982 * doorbell message sent to the chip 1983 */ 1984 struct doorbell_set_prod { 1985 #if defined(__BIG_ENDIAN) 1986 u16 prod; 1987 u8 zero_fill1; 1988 struct doorbell_hdr header; 1989 #elif defined(__LITTLE_ENDIAN) 1990 struct doorbell_hdr header; 1991 u8 zero_fill1; 1992 u16 prod; 1993 #endif 1994 }; 1995 1996 1997 /* 1998 * 3 lines. status block 1999 */ 2000 struct hc_status_block_e1x { 2001 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 2002 __le16 running_index[HC_SB_MAX_SM]; 2003 u32 rsrv; 2004 }; 2005 2006 /* 2007 * host status block 2008 */ 2009 struct host_hc_status_block_e1x { 2010 struct hc_status_block_e1x sb; 2011 }; 2012 2013 2014 /* 2015 * 3 lines. status block 2016 */ 2017 struct hc_status_block_e2 { 2018 __le16 index_values[HC_SB_MAX_INDICES_E2]; 2019 __le16 running_index[HC_SB_MAX_SM]; 2020 u32 reserved; 2021 }; 2022 2023 /* 2024 * host status block 2025 */ 2026 struct host_hc_status_block_e2 { 2027 struct hc_status_block_e2 sb; 2028 }; 2029 2030 2031 /* 2032 * 5 lines. slow-path status block 2033 */ 2034 struct hc_sp_status_block { 2035 __le16 index_values[HC_SP_SB_MAX_INDICES]; 2036 __le16 running_index; 2037 __le16 rsrv; 2038 u32 rsrv1; 2039 }; 2040 2041 /* 2042 * host status block 2043 */ 2044 struct host_sp_status_block { 2045 struct atten_sp_status_block atten_status_block; 2046 struct hc_sp_status_block sp_sb; 2047 }; 2048 2049 2050 /* 2051 * IGU driver acknowledgment register 2052 */ 2053 struct igu_ack_register { 2054 #if defined(__BIG_ENDIAN) 2055 u16 sb_id_and_flags; 2056 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2057 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2058 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2059 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2060 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2061 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2062 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2063 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2064 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2065 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2066 u16 status_block_index; 2067 #elif defined(__LITTLE_ENDIAN) 2068 u16 status_block_index; 2069 u16 sb_id_and_flags; 2070 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2071 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2072 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2073 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2074 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2075 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2076 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2077 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2078 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2079 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2080 #endif 2081 }; 2082 2083 2084 /* 2085 * IGU driver acknowledgement register 2086 */ 2087 struct igu_backward_compatible { 2088 u32 sb_id_and_flags; 2089 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 2090 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 2091 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 2092 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 2093 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 2094 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 2095 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 2096 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 2097 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 2098 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 2099 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 2100 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 2101 u32 reserved_2; 2102 }; 2103 2104 2105 /* 2106 * IGU driver acknowledgement register 2107 */ 2108 struct igu_regular { 2109 u32 sb_id_and_flags; 2110 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 2111 #define IGU_REGULAR_SB_INDEX_SHIFT 0 2112 #define IGU_REGULAR_RESERVED0 (0x1<<20) 2113 #define IGU_REGULAR_RESERVED0_SHIFT 20 2114 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 2115 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 2116 #define IGU_REGULAR_BUPDATE (0x1<<24) 2117 #define IGU_REGULAR_BUPDATE_SHIFT 24 2118 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 2119 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 2120 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 2121 #define IGU_REGULAR_RESERVED_1_SHIFT 27 2122 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 2123 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 2124 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 2125 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 2126 #define IGU_REGULAR_BCLEANUP (0x1<<31) 2127 #define IGU_REGULAR_BCLEANUP_SHIFT 31 2128 u32 reserved_2; 2129 }; 2130 2131 /* 2132 * IGU driver acknowledgement register 2133 */ 2134 union igu_consprod_reg { 2135 struct igu_regular regular; 2136 struct igu_backward_compatible backward_compatible; 2137 }; 2138 2139 2140 /* 2141 * Control register for the IGU command register 2142 */ 2143 struct igu_ctrl_reg { 2144 u32 ctrl_data; 2145 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 2146 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 2147 #define IGU_CTRL_REG_FID (0x7F<<12) 2148 #define IGU_CTRL_REG_FID_SHIFT 12 2149 #define IGU_CTRL_REG_RESERVED (0x1<<19) 2150 #define IGU_CTRL_REG_RESERVED_SHIFT 19 2151 #define IGU_CTRL_REG_TYPE (0x1<<20) 2152 #define IGU_CTRL_REG_TYPE_SHIFT 20 2153 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 2154 #define IGU_CTRL_REG_UNUSED_SHIFT 21 2155 }; 2156 2157 2158 /* 2159 * Parser parsing flags field 2160 */ 2161 struct parsing_flags { 2162 __le16 flags; 2163 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 2164 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 2165 #define PARSING_FLAGS_VLAN (0x1<<1) 2166 #define PARSING_FLAGS_VLAN_SHIFT 1 2167 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 2168 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 2169 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 2170 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 2171 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 2172 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 2173 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 2174 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 2175 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 2176 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 2177 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 2178 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 2179 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 2180 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 2181 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 2182 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 2183 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 2184 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 2185 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 2186 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 2187 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 2188 #define PARSING_FLAGS_RESERVED0_SHIFT 14 2189 }; 2190 2191 2192 struct regpair { 2193 __le32 lo; 2194 __le32 hi; 2195 }; 2196 2197 2198 /* 2199 * dmae command structure 2200 */ 2201 struct dmae_command { 2202 u32 opcode; 2203 #define DMAE_COMMAND_SRC (0x1<<0) 2204 #define DMAE_COMMAND_SRC_SHIFT 0 2205 #define DMAE_COMMAND_DST (0x3<<1) 2206 #define DMAE_COMMAND_DST_SHIFT 1 2207 #define DMAE_COMMAND_C_DST (0x1<<3) 2208 #define DMAE_COMMAND_C_DST_SHIFT 3 2209 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2210 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2211 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2212 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2213 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2214 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2215 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2216 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2217 #define DMAE_COMMAND_PORT (0x1<<11) 2218 #define DMAE_COMMAND_PORT_SHIFT 11 2219 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2220 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2221 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2222 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2223 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2224 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2225 #define DMAE_COMMAND_E1HVN (0x3<<15) 2226 #define DMAE_COMMAND_E1HVN_SHIFT 15 2227 #define DMAE_COMMAND_DST_VN (0x3<<17) 2228 #define DMAE_COMMAND_DST_VN_SHIFT 17 2229 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2230 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2231 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2232 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2233 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2234 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2235 u32 src_addr_lo; 2236 u32 src_addr_hi; 2237 u32 dst_addr_lo; 2238 u32 dst_addr_hi; 2239 #if defined(__BIG_ENDIAN) 2240 u16 reserved1; 2241 u16 len; 2242 #elif defined(__LITTLE_ENDIAN) 2243 u16 len; 2244 u16 reserved1; 2245 #endif 2246 u32 comp_addr_lo; 2247 u32 comp_addr_hi; 2248 u32 comp_val; 2249 u32 crc32; 2250 u32 crc32_c; 2251 #if defined(__BIG_ENDIAN) 2252 u16 crc16_c; 2253 u16 crc16; 2254 #elif defined(__LITTLE_ENDIAN) 2255 u16 crc16; 2256 u16 crc16_c; 2257 #endif 2258 #if defined(__BIG_ENDIAN) 2259 u16 reserved3; 2260 u16 crc_t10; 2261 #elif defined(__LITTLE_ENDIAN) 2262 u16 crc_t10; 2263 u16 reserved3; 2264 #endif 2265 #if defined(__BIG_ENDIAN) 2266 u16 xsum8; 2267 u16 xsum16; 2268 #elif defined(__LITTLE_ENDIAN) 2269 u16 xsum16; 2270 u16 xsum8; 2271 #endif 2272 }; 2273 2274 2275 struct double_regpair { 2276 u32 regpair0_lo; 2277 u32 regpair0_hi; 2278 u32 regpair1_lo; 2279 u32 regpair1_hi; 2280 }; 2281 2282 2283 /* 2284 * SDM operation gen command (generate aggregative interrupt) 2285 */ 2286 struct sdm_op_gen { 2287 __le32 command; 2288 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 2289 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 2290 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 2291 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 2292 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 2293 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 2294 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 2295 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 2296 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 2297 #define SDM_OP_GEN_RESERVED_SHIFT 17 2298 }; 2299 2300 /* 2301 * The eth Rx Buffer Descriptor 2302 */ 2303 struct eth_rx_bd { 2304 __le32 addr_lo; 2305 __le32 addr_hi; 2306 }; 2307 2308 /* 2309 * The eth Rx SGE Descriptor 2310 */ 2311 struct eth_rx_sge { 2312 __le32 addr_lo; 2313 __le32 addr_hi; 2314 }; 2315 2316 2317 2318 /* 2319 * The eth storm context of Ustorm 2320 */ 2321 struct ustorm_eth_st_context { 2322 u32 reserved0[48]; 2323 }; 2324 2325 /* 2326 * The eth storm context of Tstorm 2327 */ 2328 struct tstorm_eth_st_context { 2329 u32 __reserved0[28]; 2330 }; 2331 2332 /* 2333 * The eth aggregative context of Xstorm 2334 */ 2335 struct xstorm_eth_ag_context { 2336 u32 reserved0; 2337 #if defined(__BIG_ENDIAN) 2338 u8 cdu_reserved; 2339 u8 reserved2; 2340 u16 reserved1; 2341 #elif defined(__LITTLE_ENDIAN) 2342 u16 reserved1; 2343 u8 reserved2; 2344 u8 cdu_reserved; 2345 #endif 2346 u32 reserved3[30]; 2347 }; 2348 2349 /* 2350 * The eth aggregative context of Tstorm 2351 */ 2352 struct tstorm_eth_ag_context { 2353 u32 __reserved0[14]; 2354 }; 2355 2356 2357 /* 2358 * The eth aggregative context of Cstorm 2359 */ 2360 struct cstorm_eth_ag_context { 2361 u32 __reserved0[10]; 2362 }; 2363 2364 2365 /* 2366 * The eth aggregative context of Ustorm 2367 */ 2368 struct ustorm_eth_ag_context { 2369 u32 __reserved0; 2370 #if defined(__BIG_ENDIAN) 2371 u8 cdu_usage; 2372 u8 __reserved2; 2373 u16 __reserved1; 2374 #elif defined(__LITTLE_ENDIAN) 2375 u16 __reserved1; 2376 u8 __reserved2; 2377 u8 cdu_usage; 2378 #endif 2379 u32 __reserved3[6]; 2380 }; 2381 2382 /* 2383 * Timers connection context 2384 */ 2385 struct timers_block_context { 2386 u32 __reserved_0; 2387 u32 __reserved_1; 2388 u32 __reserved_2; 2389 u32 flags; 2390 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 2391 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 2392 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 2393 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 2394 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 2395 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 2396 }; 2397 2398 /* 2399 * structure for easy accessibility to assembler 2400 */ 2401 struct eth_tx_bd_flags { 2402 u8 as_bitfield; 2403 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 2404 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 2405 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 2406 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 2407 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 2408 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 2409 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 2410 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 2411 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 2412 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 2413 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 2414 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 2415 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 2416 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 2417 }; 2418 2419 /* 2420 * The eth Tx Buffer Descriptor 2421 */ 2422 struct eth_tx_start_bd { 2423 __le32 addr_lo; 2424 __le32 addr_hi; 2425 __le16 nbd; 2426 __le16 nbytes; 2427 __le16 vlan_or_ethertype; 2428 struct eth_tx_bd_flags bd_flags; 2429 u8 general_data; 2430 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0) 2431 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 2432 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) 2433 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 2434 }; 2435 2436 /* 2437 * Tx regular BD structure 2438 */ 2439 struct eth_tx_bd { 2440 __le32 addr_lo; 2441 __le32 addr_hi; 2442 __le16 total_pkt_bytes; 2443 __le16 nbytes; 2444 u8 reserved[4]; 2445 }; 2446 2447 /* 2448 * Tx parsing BD structure for ETH E1/E1h 2449 */ 2450 struct eth_tx_parse_bd_e1x { 2451 u8 global_data; 2452 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 2453 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 2454 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) 2455 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 2456 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) 2457 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 2458 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) 2459 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 2460 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) 2461 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 2462 u8 tcp_flags; 2463 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 2464 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 2465 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 2466 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 2467 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 2468 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 2469 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 2470 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 2471 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 2472 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 2473 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 2474 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 2475 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 2476 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 2477 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 2478 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 2479 u8 ip_hlen_w; 2480 s8 reserved; 2481 __le16 total_hlen_w; 2482 __le16 tcp_pseudo_csum; 2483 __le16 lso_mss; 2484 __le16 ip_id; 2485 __le32 tcp_send_seq; 2486 }; 2487 2488 /* 2489 * Tx parsing BD structure for ETH E2 2490 */ 2491 struct eth_tx_parse_bd_e2 { 2492 __le16 dst_mac_addr_lo; 2493 __le16 dst_mac_addr_mid; 2494 __le16 dst_mac_addr_hi; 2495 __le16 src_mac_addr_lo; 2496 __le16 src_mac_addr_mid; 2497 __le16 src_mac_addr_hi; 2498 __le32 parsing_data; 2499 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0) 2500 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 2501 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13) 2502 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13 2503 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17) 2504 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17 2505 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31) 2506 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31 2507 }; 2508 2509 /* 2510 * The last BD in the BD memory will hold a pointer to the next BD memory 2511 */ 2512 struct eth_tx_next_bd { 2513 __le32 addr_lo; 2514 __le32 addr_hi; 2515 u8 reserved[8]; 2516 }; 2517 2518 /* 2519 * union for 4 Bd types 2520 */ 2521 union eth_tx_bd_types { 2522 struct eth_tx_start_bd start_bd; 2523 struct eth_tx_bd reg_bd; 2524 struct eth_tx_parse_bd_e1x parse_bd_e1x; 2525 struct eth_tx_parse_bd_e2 parse_bd_e2; 2526 struct eth_tx_next_bd next_bd; 2527 }; 2528 2529 2530 /* 2531 * The eth storm context of Xstorm 2532 */ 2533 struct xstorm_eth_st_context { 2534 u32 reserved0[60]; 2535 }; 2536 2537 /* 2538 * The eth storm context of Cstorm 2539 */ 2540 struct cstorm_eth_st_context { 2541 u32 __reserved0[4]; 2542 }; 2543 2544 /* 2545 * Ethernet connection context 2546 */ 2547 struct eth_context { 2548 struct ustorm_eth_st_context ustorm_st_context; 2549 struct tstorm_eth_st_context tstorm_st_context; 2550 struct xstorm_eth_ag_context xstorm_ag_context; 2551 struct tstorm_eth_ag_context tstorm_ag_context; 2552 struct cstorm_eth_ag_context cstorm_ag_context; 2553 struct ustorm_eth_ag_context ustorm_ag_context; 2554 struct timers_block_context timers_context; 2555 struct xstorm_eth_st_context xstorm_st_context; 2556 struct cstorm_eth_st_context cstorm_st_context; 2557 }; 2558 2559 2560 /* 2561 * Ethernet doorbell 2562 */ 2563 struct eth_tx_doorbell { 2564 #if defined(__BIG_ENDIAN) 2565 u16 npackets; 2566 u8 params; 2567 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2568 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2569 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2570 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2571 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2572 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2573 struct doorbell_hdr hdr; 2574 #elif defined(__LITTLE_ENDIAN) 2575 struct doorbell_hdr hdr; 2576 u8 params; 2577 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2578 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2579 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2580 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2581 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2582 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2583 u16 npackets; 2584 #endif 2585 }; 2586 2587 2588 /* 2589 * client init fc data 2590 */ 2591 struct client_init_fc_data { 2592 __le16 cqe_pause_thr_low; 2593 __le16 cqe_pause_thr_high; 2594 __le16 bd_pause_thr_low; 2595 __le16 bd_pause_thr_high; 2596 __le16 sge_pause_thr_low; 2597 __le16 sge_pause_thr_high; 2598 __le16 rx_cos_mask; 2599 u8 safc_group_num; 2600 u8 safc_group_en_flg; 2601 u8 traffic_type; 2602 u8 reserved0; 2603 __le16 reserved1; 2604 __le32 reserved2; 2605 }; 2606 2607 2608 /* 2609 * client init ramrod data 2610 */ 2611 struct client_init_general_data { 2612 u8 client_id; 2613 u8 statistics_counter_id; 2614 u8 statistics_en_flg; 2615 u8 is_fcoe_flg; 2616 u8 activate_flg; 2617 u8 sp_client_id; 2618 __le16 reserved0; 2619 __le32 reserved1[2]; 2620 }; 2621 2622 2623 /* 2624 * client init rx data 2625 */ 2626 struct client_init_rx_data { 2627 u8 tpa_en_flg; 2628 u8 vmqueue_mode_en_flg; 2629 u8 extra_data_over_sgl_en_flg; 2630 u8 cache_line_alignment_log_size; 2631 u8 enable_dynamic_hc; 2632 u8 max_sges_for_packet; 2633 u8 client_qzone_id; 2634 u8 drop_ip_cs_err_flg; 2635 u8 drop_tcp_cs_err_flg; 2636 u8 drop_ttl0_flg; 2637 u8 drop_udp_cs_err_flg; 2638 u8 inner_vlan_removal_enable_flg; 2639 u8 outer_vlan_removal_enable_flg; 2640 u8 status_block_id; 2641 u8 rx_sb_index_number; 2642 u8 reserved0[3]; 2643 __le16 bd_buff_size; 2644 __le16 sge_buff_size; 2645 __le16 mtu; 2646 struct regpair bd_page_base; 2647 struct regpair sge_page_base; 2648 struct regpair cqe_page_base; 2649 u8 is_leading_rss; 2650 u8 is_approx_mcast; 2651 __le16 max_agg_size; 2652 __le32 reserved2[3]; 2653 }; 2654 2655 /* 2656 * client init tx data 2657 */ 2658 struct client_init_tx_data { 2659 u8 enforce_security_flg; 2660 u8 tx_status_block_id; 2661 u8 tx_sb_index_number; 2662 u8 reserved0; 2663 __le16 mtu; 2664 __le16 reserved1; 2665 struct regpair tx_bd_page_base; 2666 __le32 reserved2[2]; 2667 }; 2668 2669 /* 2670 * client init ramrod data 2671 */ 2672 struct client_init_ramrod_data { 2673 struct client_init_general_data general; 2674 struct client_init_rx_data rx; 2675 struct client_init_tx_data tx; 2676 struct client_init_fc_data fc; 2677 }; 2678 2679 2680 /* 2681 * The data contain client ID need to the ramrod 2682 */ 2683 struct eth_common_ramrod_data { 2684 u32 client_id; 2685 u32 reserved1; 2686 }; 2687 2688 2689 /* 2690 * union for sgl and raw data. 2691 */ 2692 union eth_sgl_or_raw_data { 2693 __le16 sgl[8]; 2694 u32 raw_data[4]; 2695 }; 2696 2697 /* 2698 * regular eth FP CQE parameters struct 2699 */ 2700 struct eth_fast_path_rx_cqe { 2701 u8 type_error_flags; 2702 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0) 2703 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 2704 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1) 2705 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1 2706 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2) 2707 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2 2708 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3) 2709 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3 2710 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4) 2711 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4 2712 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5) 2713 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5 2714 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6) 2715 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6 2716 u8 status_flags; 2717 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 2718 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 2719 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 2720 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 2721 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 2722 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 2723 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 2724 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 2725 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 2726 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 2727 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 2728 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 2729 u8 placement_offset; 2730 u8 queue_index; 2731 __le32 rss_hash_result; 2732 __le16 vlan_tag; 2733 __le16 pkt_len; 2734 __le16 len_on_bd; 2735 struct parsing_flags pars_flags; 2736 union eth_sgl_or_raw_data sgl_or_raw_data; 2737 }; 2738 2739 2740 /* 2741 * The data for RSS setup ramrod 2742 */ 2743 struct eth_halt_ramrod_data { 2744 u32 client_id; 2745 u32 reserved0; 2746 }; 2747 2748 /* 2749 * The data for statistics query ramrod 2750 */ 2751 struct common_query_ramrod_data { 2752 #if defined(__BIG_ENDIAN) 2753 u8 reserved0; 2754 u8 collect_port; 2755 u16 drv_counter; 2756 #elif defined(__LITTLE_ENDIAN) 2757 u16 drv_counter; 2758 u8 collect_port; 2759 u8 reserved0; 2760 #endif 2761 u32 ctr_id_vector; 2762 }; 2763 2764 2765 /* 2766 * Place holder for ramrods protocol specific data 2767 */ 2768 struct ramrod_data { 2769 __le32 data_lo; 2770 __le32 data_hi; 2771 }; 2772 2773 /* 2774 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 2775 */ 2776 union eth_ramrod_data { 2777 struct ramrod_data general; 2778 }; 2779 2780 2781 /* 2782 * Eth Rx Cqe structure- general structure for ramrods 2783 */ 2784 struct common_ramrod_eth_rx_cqe { 2785 u8 ramrod_type; 2786 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0) 2787 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 2788 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1) 2789 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1 2790 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2) 2791 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2 2792 u8 conn_type; 2793 __le16 reserved1; 2794 __le32 conn_and_cmd_data; 2795 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 2796 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 2797 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 2798 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 2799 struct ramrod_data protocol_data; 2800 __le32 reserved2[4]; 2801 }; 2802 2803 /* 2804 * Rx Last CQE in page (in ETH) 2805 */ 2806 struct eth_rx_cqe_next_page { 2807 __le32 addr_lo; 2808 __le32 addr_hi; 2809 __le32 reserved[6]; 2810 }; 2811 2812 /* 2813 * union for all eth rx cqe types (fix their sizes) 2814 */ 2815 union eth_rx_cqe { 2816 struct eth_fast_path_rx_cqe fast_path_cqe; 2817 struct common_ramrod_eth_rx_cqe ramrod_cqe; 2818 struct eth_rx_cqe_next_page next_page_cqe; 2819 }; 2820 2821 2822 /* 2823 * common data for all protocols 2824 */ 2825 struct spe_hdr { 2826 __le32 conn_and_cmd_data; 2827 #define SPE_HDR_CID (0xFFFFFF<<0) 2828 #define SPE_HDR_CID_SHIFT 0 2829 #define SPE_HDR_CMD_ID (0xFF<<24) 2830 #define SPE_HDR_CMD_ID_SHIFT 24 2831 __le16 type; 2832 #define SPE_HDR_CONN_TYPE (0xFF<<0) 2833 #define SPE_HDR_CONN_TYPE_SHIFT 0 2834 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 2835 #define SPE_HDR_FUNCTION_ID_SHIFT 8 2836 __le16 reserved1; 2837 }; 2838 2839 /* 2840 * Ethernet slow path element 2841 */ 2842 union eth_specific_data { 2843 u8 protocol_data[8]; 2844 struct regpair client_init_ramrod_init_data; 2845 struct eth_halt_ramrod_data halt_ramrod_data; 2846 struct regpair update_data_addr; 2847 struct eth_common_ramrod_data common_ramrod_data; 2848 }; 2849 2850 /* 2851 * Ethernet slow path element 2852 */ 2853 struct eth_spe { 2854 struct spe_hdr hdr; 2855 union eth_specific_data data; 2856 }; 2857 2858 2859 /* 2860 * array of 13 bds as appears in the eth xstorm context 2861 */ 2862 struct eth_tx_bds_array { 2863 union eth_tx_bd_types bds[13]; 2864 }; 2865 2866 2867 /* 2868 * Common configuration parameters per function in Tstorm 2869 */ 2870 struct tstorm_eth_function_common_config { 2871 #if defined(__BIG_ENDIAN) 2872 u8 reserved1; 2873 u8 rss_result_mask; 2874 u16 config_flags; 2875 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 2876 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 2877 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 2878 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 2879 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 2880 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 2881 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 2882 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 2883 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 2884 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 2885 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7) 2886 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7 2887 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8) 2888 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8 2889 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9) 2890 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9 2891 #elif defined(__LITTLE_ENDIAN) 2892 u16 config_flags; 2893 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 2894 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 2895 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 2896 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 2897 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 2898 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 2899 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 2900 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 2901 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 2902 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 2903 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7) 2904 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7 2905 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8) 2906 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8 2907 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9) 2908 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9 2909 u8 rss_result_mask; 2910 u8 reserved1; 2911 #endif 2912 u16 vlan_id[2]; 2913 }; 2914 2915 /* 2916 * RSS idirection table update configuration 2917 */ 2918 struct rss_update_config { 2919 #if defined(__BIG_ENDIAN) 2920 u16 toe_rss_bitmap; 2921 u16 flags; 2922 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) 2923 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 2924 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) 2925 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 2926 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) 2927 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 2928 #elif defined(__LITTLE_ENDIAN) 2929 u16 flags; 2930 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) 2931 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 2932 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) 2933 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 2934 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) 2935 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 2936 u16 toe_rss_bitmap; 2937 #endif 2938 u32 reserved1; 2939 }; 2940 2941 /* 2942 * parameters for eth update ramrod 2943 */ 2944 struct eth_update_ramrod_data { 2945 struct tstorm_eth_function_common_config func_config; 2946 u8 indirectionTable[128]; 2947 struct rss_update_config rss_config; 2948 }; 2949 2950 2951 /* 2952 * MAC filtering configuration command header 2953 */ 2954 struct mac_configuration_hdr { 2955 u8 length; 2956 u8 offset; 2957 u16 client_id; 2958 u16 echo; 2959 u16 reserved1; 2960 }; 2961 2962 /* 2963 * MAC address in list for ramrod 2964 */ 2965 struct mac_configuration_entry { 2966 __le16 lsb_mac_addr; 2967 __le16 middle_mac_addr; 2968 __le16 msb_mac_addr; 2969 __le16 vlan_id; 2970 u8 pf_id; 2971 u8 flags; 2972 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 2973 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 2974 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 2975 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 2976 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 2977 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 2978 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 2979 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 2980 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 2981 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 2982 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 2983 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 2984 u16 reserved0; 2985 u32 clients_bit_vector; 2986 }; 2987 2988 /* 2989 * MAC filtering configuration command 2990 */ 2991 struct mac_configuration_cmd { 2992 struct mac_configuration_hdr hdr; 2993 struct mac_configuration_entry config_table[64]; 2994 }; 2995 2996 2997 /* 2998 * approximate-match multicast filtering for E1H per function in Tstorm 2999 */ 3000 struct tstorm_eth_approximate_match_multicast_filtering { 3001 u32 mcast_add_hash_bit_array[8]; 3002 }; 3003 3004 3005 /* 3006 * MAC filtering configuration parameters per port in Tstorm 3007 */ 3008 struct tstorm_eth_mac_filter_config { 3009 u32 ucast_drop_all; 3010 u32 ucast_accept_all; 3011 u32 mcast_drop_all; 3012 u32 mcast_accept_all; 3013 u32 bcast_drop_all; 3014 u32 bcast_accept_all; 3015 u32 vlan_filter[2]; 3016 u32 unmatched_unicast; 3017 u32 reserved; 3018 }; 3019 3020 3021 /* 3022 * common flag to indicate existence of TPA. 3023 */ 3024 struct tstorm_eth_tpa_exist { 3025 #if defined(__BIG_ENDIAN) 3026 u16 reserved1; 3027 u8 reserved0; 3028 u8 tpa_exist; 3029 #elif defined(__LITTLE_ENDIAN) 3030 u8 tpa_exist; 3031 u8 reserved0; 3032 u16 reserved1; 3033 #endif 3034 u32 reserved2; 3035 }; 3036 3037 3038 /* 3039 * Three RX producers for ETH 3040 */ 3041 struct ustorm_eth_rx_producers { 3042 #if defined(__BIG_ENDIAN) 3043 u16 bd_prod; 3044 u16 cqe_prod; 3045 #elif defined(__LITTLE_ENDIAN) 3046 u16 cqe_prod; 3047 u16 bd_prod; 3048 #endif 3049 #if defined(__BIG_ENDIAN) 3050 u16 reserved; 3051 u16 sge_prod; 3052 #elif defined(__LITTLE_ENDIAN) 3053 u16 sge_prod; 3054 u16 reserved; 3055 #endif 3056 }; 3057 3058 3059 /* 3060 * cfc delete event data 3061 */ 3062 struct cfc_del_event_data { 3063 u32 cid; 3064 u8 error; 3065 u8 reserved0; 3066 u16 reserved1; 3067 u32 reserved2; 3068 }; 3069 3070 3071 /* 3072 * per-port SAFC demo variables 3073 */ 3074 struct cmng_flags_per_port { 3075 u8 con_number[NUM_OF_PROTOCOLS]; 3076 u32 cmng_enables; 3077 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 3078 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 3079 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 3080 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 3081 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2) 3082 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2 3083 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3) 3084 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3 3085 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4) 3086 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4 3087 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5) 3088 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5 3089 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6) 3090 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6 3091 }; 3092 3093 3094 /* 3095 * per-port rate shaping variables 3096 */ 3097 struct rate_shaping_vars_per_port { 3098 u32 rs_periodic_timeout; 3099 u32 rs_threshold; 3100 }; 3101 3102 /* 3103 * per-port fairness variables 3104 */ 3105 struct fairness_vars_per_port { 3106 u32 upper_bound; 3107 u32 fair_threshold; 3108 u32 fairness_timeout; 3109 }; 3110 3111 /* 3112 * per-port SAFC variables 3113 */ 3114 struct safc_struct_per_port { 3115 #if defined(__BIG_ENDIAN) 3116 u16 __reserved1; 3117 u8 __reserved0; 3118 u8 safc_timeout_usec; 3119 #elif defined(__LITTLE_ENDIAN) 3120 u8 safc_timeout_usec; 3121 u8 __reserved0; 3122 u16 __reserved1; 3123 #endif 3124 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 3125 u32 __reserved2; 3126 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 3127 }; 3128 3129 /* 3130 * per-port PFC variables 3131 */ 3132 struct pfc_struct_per_port { 3133 u8 priority_to_traffic_types[MAX_PFC_PRIORITIES]; 3134 #if defined(__BIG_ENDIAN) 3135 u16 pfc_pause_quanta_in_nanosec; 3136 u8 __reserved0; 3137 u8 priority_non_pausable_mask; 3138 #elif defined(__LITTLE_ENDIAN) 3139 u8 priority_non_pausable_mask; 3140 u8 __reserved0; 3141 u16 pfc_pause_quanta_in_nanosec; 3142 #endif 3143 }; 3144 3145 /* 3146 * Priority and cos 3147 */ 3148 struct priority_cos { 3149 #if defined(__BIG_ENDIAN) 3150 u16 reserved1; 3151 u8 cos; 3152 u8 priority; 3153 #elif defined(__LITTLE_ENDIAN) 3154 u8 priority; 3155 u8 cos; 3156 u16 reserved1; 3157 #endif 3158 u32 reserved2; 3159 }; 3160 3161 /* 3162 * Per-port congestion management variables 3163 */ 3164 struct cmng_struct_per_port { 3165 struct rate_shaping_vars_per_port rs_vars; 3166 struct fairness_vars_per_port fair_vars; 3167 struct safc_struct_per_port safc_vars; 3168 struct pfc_struct_per_port pfc_vars; 3169 #if defined(__BIG_ENDIAN) 3170 u16 __reserved1; 3171 u8 dcb_enabled; 3172 u8 llfc_mode; 3173 #elif defined(__LITTLE_ENDIAN) 3174 u8 llfc_mode; 3175 u8 dcb_enabled; 3176 u16 __reserved1; 3177 #endif 3178 struct priority_cos 3179 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES]; 3180 struct cmng_flags_per_port flags; 3181 }; 3182 3183 3184 3185 /* 3186 * Dynamic HC counters set by the driver 3187 */ 3188 struct hc_dynamic_drv_counter { 3189 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 3190 }; 3191 3192 /* 3193 * zone A per-queue data 3194 */ 3195 struct cstorm_queue_zone_data { 3196 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 3197 struct regpair reserved[2]; 3198 }; 3199 3200 /* 3201 * Dynamic host coalescing init parameters 3202 */ 3203 struct dynamic_hc_config { 3204 u32 threshold[3]; 3205 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 3206 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 3207 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 3208 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 3209 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 3210 }; 3211 3212 3213 /* 3214 * Protocol-common statistics collected by the Xstorm (per client) 3215 */ 3216 struct xstorm_per_client_stats { 3217 __le32 reserved0; 3218 __le32 unicast_pkts_sent; 3219 struct regpair unicast_bytes_sent; 3220 struct regpair multicast_bytes_sent; 3221 __le32 multicast_pkts_sent; 3222 __le32 broadcast_pkts_sent; 3223 struct regpair broadcast_bytes_sent; 3224 __le16 stats_counter; 3225 __le16 reserved1; 3226 __le32 reserved2; 3227 }; 3228 3229 /* 3230 * Common statistics collected by the Xstorm (per port) 3231 */ 3232 struct xstorm_common_stats { 3233 struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID]; 3234 }; 3235 3236 /* 3237 * Protocol-common statistics collected by the Tstorm (per port) 3238 */ 3239 struct tstorm_per_port_stats { 3240 __le32 mac_filter_discard; 3241 __le32 xxoverflow_discard; 3242 __le32 brb_truncate_discard; 3243 __le32 mac_discard; 3244 }; 3245 3246 /* 3247 * Protocol-common statistics collected by the Tstorm (per client) 3248 */ 3249 struct tstorm_per_client_stats { 3250 struct regpair rcv_unicast_bytes; 3251 struct regpair rcv_broadcast_bytes; 3252 struct regpair rcv_multicast_bytes; 3253 struct regpair rcv_error_bytes; 3254 __le32 checksum_discard; 3255 __le32 packets_too_big_discard; 3256 __le32 rcv_unicast_pkts; 3257 __le32 rcv_broadcast_pkts; 3258 __le32 rcv_multicast_pkts; 3259 __le32 no_buff_discard; 3260 __le32 ttl0_discard; 3261 __le16 stats_counter; 3262 __le16 reserved0; 3263 }; 3264 3265 /* 3266 * Protocol-common statistics collected by the Tstorm 3267 */ 3268 struct tstorm_common_stats { 3269 struct tstorm_per_port_stats port_statistics; 3270 struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID]; 3271 }; 3272 3273 /* 3274 * Protocol-common statistics collected by the Ustorm (per client) 3275 */ 3276 struct ustorm_per_client_stats { 3277 struct regpair ucast_no_buff_bytes; 3278 struct regpair mcast_no_buff_bytes; 3279 struct regpair bcast_no_buff_bytes; 3280 __le32 ucast_no_buff_pkts; 3281 __le32 mcast_no_buff_pkts; 3282 __le32 bcast_no_buff_pkts; 3283 __le16 stats_counter; 3284 __le16 reserved0; 3285 }; 3286 3287 /* 3288 * Protocol-common statistics collected by the Ustorm 3289 */ 3290 struct ustorm_common_stats { 3291 struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID]; 3292 }; 3293 3294 /* 3295 * Eth statistics query structure for the eth_stats_query ramrod 3296 */ 3297 struct eth_stats_query { 3298 struct xstorm_common_stats xstorm_common; 3299 struct tstorm_common_stats tstorm_common; 3300 struct ustorm_common_stats ustorm_common; 3301 }; 3302 3303 3304 /* 3305 * set mac event data 3306 */ 3307 struct set_mac_event_data { 3308 u16 echo; 3309 u16 reserved0; 3310 u32 reserved1; 3311 u32 reserved2; 3312 }; 3313 3314 /* 3315 * union for all event ring message types 3316 */ 3317 union event_data { 3318 struct set_mac_event_data set_mac_event; 3319 struct cfc_del_event_data cfc_del_event; 3320 }; 3321 3322 3323 /* 3324 * per PF event ring data 3325 */ 3326 struct event_ring_data { 3327 struct regpair base_addr; 3328 #if defined(__BIG_ENDIAN) 3329 u8 index_id; 3330 u8 sb_id; 3331 u16 producer; 3332 #elif defined(__LITTLE_ENDIAN) 3333 u16 producer; 3334 u8 sb_id; 3335 u8 index_id; 3336 #endif 3337 u32 reserved0; 3338 }; 3339 3340 3341 /* 3342 * event ring message element (each element is 128 bits) 3343 */ 3344 struct event_ring_msg { 3345 u8 opcode; 3346 u8 reserved0; 3347 u16 reserved1; 3348 union event_data data; 3349 }; 3350 3351 /* 3352 * event ring next page element (128 bits) 3353 */ 3354 struct event_ring_next { 3355 struct regpair addr; 3356 u32 reserved[2]; 3357 }; 3358 3359 /* 3360 * union for event ring element types (each element is 128 bits) 3361 */ 3362 union event_ring_elem { 3363 struct event_ring_msg message; 3364 struct event_ring_next next_page; 3365 }; 3366 3367 3368 /* 3369 * per-vnic fairness variables 3370 */ 3371 struct fairness_vars_per_vn { 3372 u32 cos_credit_delta[MAX_COS_NUMBER]; 3373 u32 protocol_credit_delta[NUM_OF_PROTOCOLS]; 3374 u32 vn_credit_delta; 3375 u32 __reserved0; 3376 }; 3377 3378 3379 /* 3380 * The data for flow control configuration 3381 */ 3382 struct flow_control_configuration { 3383 struct priority_cos 3384 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES]; 3385 #if defined(__BIG_ENDIAN) 3386 u16 reserved1; 3387 u8 dcb_version; 3388 u8 dcb_enabled; 3389 #elif defined(__LITTLE_ENDIAN) 3390 u8 dcb_enabled; 3391 u8 dcb_version; 3392 u16 reserved1; 3393 #endif 3394 u32 reserved2; 3395 }; 3396 3397 3398 /* 3399 * FW version stored in the Xstorm RAM 3400 */ 3401 struct fw_version { 3402 #if defined(__BIG_ENDIAN) 3403 u8 engineering; 3404 u8 revision; 3405 u8 minor; 3406 u8 major; 3407 #elif defined(__LITTLE_ENDIAN) 3408 u8 major; 3409 u8 minor; 3410 u8 revision; 3411 u8 engineering; 3412 #endif 3413 u32 flags; 3414 #define FW_VERSION_OPTIMIZED (0x1<<0) 3415 #define FW_VERSION_OPTIMIZED_SHIFT 0 3416 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 3417 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 3418 #define FW_VERSION_CHIP_VERSION (0x3<<2) 3419 #define FW_VERSION_CHIP_VERSION_SHIFT 2 3420 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 3421 #define __FW_VERSION_RESERVED_SHIFT 4 3422 }; 3423 3424 3425 /* 3426 * Dynamic Host-Coalescing - Driver(host) counters 3427 */ 3428 struct hc_dynamic_sb_drv_counters { 3429 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 3430 }; 3431 3432 3433 /* 3434 * 2 bytes. configuration/state parameters for a single protocol index 3435 */ 3436 struct hc_index_data { 3437 #if defined(__BIG_ENDIAN) 3438 u8 flags; 3439 #define HC_INDEX_DATA_SM_ID (0x1<<0) 3440 #define HC_INDEX_DATA_SM_ID_SHIFT 0 3441 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 3442 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 3443 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 3444 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 3445 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 3446 #define HC_INDEX_DATA_RESERVE_SHIFT 3 3447 u8 timeout; 3448 #elif defined(__LITTLE_ENDIAN) 3449 u8 timeout; 3450 u8 flags; 3451 #define HC_INDEX_DATA_SM_ID (0x1<<0) 3452 #define HC_INDEX_DATA_SM_ID_SHIFT 0 3453 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 3454 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 3455 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 3456 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 3457 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 3458 #define HC_INDEX_DATA_RESERVE_SHIFT 3 3459 #endif 3460 }; 3461 3462 3463 /* 3464 * HC state-machine 3465 */ 3466 struct hc_status_block_sm { 3467 #if defined(__BIG_ENDIAN) 3468 u8 igu_seg_id; 3469 u8 igu_sb_id; 3470 u8 timer_value; 3471 u8 __flags; 3472 #elif defined(__LITTLE_ENDIAN) 3473 u8 __flags; 3474 u8 timer_value; 3475 u8 igu_sb_id; 3476 u8 igu_seg_id; 3477 #endif 3478 u32 time_to_expire; 3479 }; 3480 3481 /* 3482 * hold PCI identification variables- used in various places in firmware 3483 */ 3484 struct pci_entity { 3485 #if defined(__BIG_ENDIAN) 3486 u8 vf_valid; 3487 u8 vf_id; 3488 u8 vnic_id; 3489 u8 pf_id; 3490 #elif defined(__LITTLE_ENDIAN) 3491 u8 pf_id; 3492 u8 vnic_id; 3493 u8 vf_id; 3494 u8 vf_valid; 3495 #endif 3496 }; 3497 3498 /* 3499 * The fast-path status block meta-data, common to all chips 3500 */ 3501 struct hc_sb_data { 3502 struct regpair host_sb_addr; 3503 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 3504 struct pci_entity p_func; 3505 #if defined(__BIG_ENDIAN) 3506 u8 rsrv0; 3507 u8 dhc_qzone_id; 3508 u8 __dynamic_hc_level; 3509 u8 same_igu_sb_1b; 3510 #elif defined(__LITTLE_ENDIAN) 3511 u8 same_igu_sb_1b; 3512 u8 __dynamic_hc_level; 3513 u8 dhc_qzone_id; 3514 u8 rsrv0; 3515 #endif 3516 struct regpair rsrv1[2]; 3517 }; 3518 3519 3520 /* 3521 * The fast-path status block meta-data 3522 */ 3523 struct hc_sp_status_block_data { 3524 struct regpair host_sb_addr; 3525 #if defined(__BIG_ENDIAN) 3526 u16 rsrv; 3527 u8 igu_seg_id; 3528 u8 igu_sb_id; 3529 #elif defined(__LITTLE_ENDIAN) 3530 u8 igu_sb_id; 3531 u8 igu_seg_id; 3532 u16 rsrv; 3533 #endif 3534 struct pci_entity p_func; 3535 }; 3536 3537 3538 /* 3539 * The fast-path status block meta-data 3540 */ 3541 struct hc_status_block_data_e1x { 3542 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 3543 struct hc_sb_data common; 3544 }; 3545 3546 3547 /* 3548 * The fast-path status block meta-data 3549 */ 3550 struct hc_status_block_data_e2 { 3551 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 3552 struct hc_sb_data common; 3553 }; 3554 3555 3556 /* 3557 * FW version stored in first line of pram 3558 */ 3559 struct pram_fw_version { 3560 u8 major; 3561 u8 minor; 3562 u8 revision; 3563 u8 engineering; 3564 u8 flags; 3565 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 3566 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 3567 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 3568 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 3569 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 3570 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 3571 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 3572 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 3573 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 3574 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 3575 }; 3576 3577 3578 /* 3579 * Ethernet slow path element 3580 */ 3581 union protocol_common_specific_data { 3582 u8 protocol_data[8]; 3583 struct regpair phy_address; 3584 struct regpair mac_config_addr; 3585 struct common_query_ramrod_data query_ramrod_data; 3586 }; 3587 3588 /* 3589 * The send queue element 3590 */ 3591 struct protocol_common_spe { 3592 struct spe_hdr hdr; 3593 union protocol_common_specific_data data; 3594 }; 3595 3596 3597 /* 3598 * a single rate shaping counter. can be used as protocol or vnic counter 3599 */ 3600 struct rate_shaping_counter { 3601 u32 quota; 3602 #if defined(__BIG_ENDIAN) 3603 u16 __reserved0; 3604 u16 rate; 3605 #elif defined(__LITTLE_ENDIAN) 3606 u16 rate; 3607 u16 __reserved0; 3608 #endif 3609 }; 3610 3611 3612 /* 3613 * per-vnic rate shaping variables 3614 */ 3615 struct rate_shaping_vars_per_vn { 3616 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS]; 3617 struct rate_shaping_counter vn_counter; 3618 }; 3619 3620 3621 /* 3622 * The send queue element 3623 */ 3624 struct slow_path_element { 3625 struct spe_hdr hdr; 3626 struct regpair protocol_data; 3627 }; 3628 3629 3630 /* 3631 * eth/toe flags that indicate if to query 3632 */ 3633 struct stats_indication_flags { 3634 u32 collect_eth; 3635 u32 collect_toe; 3636 }; 3637 3638 3639 /* 3640 * per-port PFC variables 3641 */ 3642 struct storm_pfc_struct_per_port { 3643 #if defined(__BIG_ENDIAN) 3644 u16 mid_mac_addr; 3645 u16 msb_mac_addr; 3646 #elif defined(__LITTLE_ENDIAN) 3647 u16 msb_mac_addr; 3648 u16 mid_mac_addr; 3649 #endif 3650 #if defined(__BIG_ENDIAN) 3651 u16 pfc_pause_quanta_in_nanosec; 3652 u16 lsb_mac_addr; 3653 #elif defined(__LITTLE_ENDIAN) 3654 u16 lsb_mac_addr; 3655 u16 pfc_pause_quanta_in_nanosec; 3656 #endif 3657 }; 3658 3659 /* 3660 * Per-port congestion management variables 3661 */ 3662 struct storm_cmng_struct_per_port { 3663 struct storm_pfc_struct_per_port pfc_vars; 3664 }; 3665 3666 3667 /* 3668 * zone A per-queue data 3669 */ 3670 struct tstorm_queue_zone_data { 3671 struct regpair reserved[4]; 3672 }; 3673 3674 3675 /* 3676 * zone B per-VF data 3677 */ 3678 struct tstorm_vf_zone_data { 3679 struct regpair reserved; 3680 }; 3681 3682 3683 /* 3684 * zone A per-queue data 3685 */ 3686 struct ustorm_queue_zone_data { 3687 struct ustorm_eth_rx_producers eth_rx_producers; 3688 struct regpair reserved[3]; 3689 }; 3690 3691 3692 /* 3693 * zone B per-VF data 3694 */ 3695 struct ustorm_vf_zone_data { 3696 struct regpair reserved; 3697 }; 3698 3699 3700 /* 3701 * data per VF-PF channel 3702 */ 3703 struct vf_pf_channel_data { 3704 #if defined(__BIG_ENDIAN) 3705 u16 reserved0; 3706 u8 valid; 3707 u8 state; 3708 #elif defined(__LITTLE_ENDIAN) 3709 u8 state; 3710 u8 valid; 3711 u16 reserved0; 3712 #endif 3713 u32 reserved1; 3714 }; 3715 3716 3717 /* 3718 * zone A per-queue data 3719 */ 3720 struct xstorm_queue_zone_data { 3721 struct regpair reserved[4]; 3722 }; 3723 3724 3725 /* 3726 * zone B per-VF data 3727 */ 3728 struct xstorm_vf_zone_data { 3729 struct regpair reserved; 3730 }; 3731 3732 #endif /* BNX2X_HSI_H */ 3733