1 /* 2 * Copyright (c) 2011 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _BRCMFMAC_SDIO_CHIP_H_ 18 #define _BRCMFMAC_SDIO_CHIP_H_ 19 20 /* 21 * Core reg address translation. 22 * Both macro's returns a 32 bits byte address on the backplane bus. 23 */ 24 #define CORE_CC_REG(base, field) \ 25 (base + offsetof(struct chipcregs, field)) 26 #define CORE_BUS_REG(base, field) \ 27 (base + offsetof(struct sdpcmd_regs, field)) 28 #define CORE_SB(base, field) \ 29 (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) 30 31 /* SDIO function 1 register CHIPCLKCSR */ 32 /* Force ALP request to backplane */ 33 #define SBSDIO_FORCE_ALP 0x01 34 /* Force HT request to backplane */ 35 #define SBSDIO_FORCE_HT 0x02 36 /* Force ILP request to backplane */ 37 #define SBSDIO_FORCE_ILP 0x04 38 /* Make ALP ready (power up xtal) */ 39 #define SBSDIO_ALP_AVAIL_REQ 0x08 40 /* Make HT ready (power up PLL) */ 41 #define SBSDIO_HT_AVAIL_REQ 0x10 42 /* Squelch clock requests from HW */ 43 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 44 /* Status: ALP is ready */ 45 #define SBSDIO_ALP_AVAIL 0x40 46 /* Status: HT is ready */ 47 #define SBSDIO_HT_AVAIL 0x80 48 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 49 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 50 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 51 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 52 #define SBSDIO_CLKAV(regval, alponly) \ 53 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 54 55 #define BRCMF_MAX_CORENUM 6 56 57 struct chip_core_info { 58 u16 id; 59 u16 rev; 60 u32 base; 61 u32 wrapbase; 62 u32 caps; 63 u32 cib; 64 }; 65 66 struct chip_info { 67 u32 chip; 68 u32 chiprev; 69 u32 socitype; 70 /* core info */ 71 /* always put chipcommon core at 0, bus core at 1 */ 72 struct chip_core_info c_inf[BRCMF_MAX_CORENUM]; 73 u32 pmurev; 74 u32 pmucaps; 75 u32 ramsize; 76 77 bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci, 78 u16 coreid); 79 u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci, 80 u16 coreid); 81 void (*coredisable)(struct brcmf_sdio_dev *sdiodev, 82 struct chip_info *ci, u16 coreid); 83 void (*resetcore)(struct brcmf_sdio_dev *sdiodev, 84 struct chip_info *ci, u16 coreid); 85 }; 86 87 struct sbconfig { 88 u32 PAD[2]; 89 u32 sbipsflag; /* initiator port ocp slave flag */ 90 u32 PAD[3]; 91 u32 sbtpsflag; /* target port ocp slave flag */ 92 u32 PAD[11]; 93 u32 sbtmerrloga; /* (sonics >= 2.3) */ 94 u32 PAD; 95 u32 sbtmerrlog; /* (sonics >= 2.3) */ 96 u32 PAD[3]; 97 u32 sbadmatch3; /* address match3 */ 98 u32 PAD; 99 u32 sbadmatch2; /* address match2 */ 100 u32 PAD; 101 u32 sbadmatch1; /* address match1 */ 102 u32 PAD[7]; 103 u32 sbimstate; /* initiator agent state */ 104 u32 sbintvec; /* interrupt mask */ 105 u32 sbtmstatelow; /* target state */ 106 u32 sbtmstatehigh; /* target state */ 107 u32 sbbwa0; /* bandwidth allocation table0 */ 108 u32 PAD; 109 u32 sbimconfiglow; /* initiator configuration */ 110 u32 sbimconfighigh; /* initiator configuration */ 111 u32 sbadmatch0; /* address match0 */ 112 u32 PAD; 113 u32 sbtmconfiglow; /* target configuration */ 114 u32 sbtmconfighigh; /* target configuration */ 115 u32 sbbconfig; /* broadcast configuration */ 116 u32 PAD; 117 u32 sbbstate; /* broadcast state */ 118 u32 PAD[3]; 119 u32 sbactcnfg; /* activate configuration */ 120 u32 PAD[3]; 121 u32 sbflagst; /* current sbflags */ 122 u32 PAD[3]; 123 u32 sbidlow; /* identification */ 124 u32 sbidhigh; /* identification */ 125 }; 126 127 extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev, 128 struct chip_info **ci_ptr, u32 regs); 129 extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr); 130 extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 131 struct chip_info *ci, 132 u32 drivestrength); 133 extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid); 134 135 136 #endif /* _BRCMFMAC_SDIO_CHIP_H_ */ 137