1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * This contains the functions to handle the descriptors for DesignWare databook
4  * 4.xx.
5  *
6  * Copyright (C) 2015  STMicroelectronics Ltd
7  *
8  * Author: Alexandre Torgue <alexandre.torgue@st.com>
9  */
10 
11 #include <linux/stmmac.h>
12 #include "common.h"
13 #include "dwmac4.h"
14 #include "dwmac4_descs.h"
15 
dwmac4_wrback_get_tx_status(void * data,struct stmmac_extra_stats * x,struct dma_desc * p,void __iomem * ioaddr)16 static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
17 				       struct dma_desc *p,
18 				       void __iomem *ioaddr)
19 {
20 	struct net_device_stats *stats = (struct net_device_stats *)data;
21 	unsigned int tdes3;
22 	int ret = tx_done;
23 
24 	tdes3 = le32_to_cpu(p->des3);
25 
26 	/* Get tx owner first */
27 	if (unlikely(tdes3 & TDES3_OWN))
28 		return tx_dma_own;
29 
30 	/* Verify tx error by looking at the last segment. */
31 	if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
32 		return tx_not_ls;
33 
34 	if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
35 		ret = tx_err;
36 
37 		if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
38 			x->tx_jabber++;
39 		if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
40 			x->tx_frame_flushed++;
41 		if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
42 			x->tx_losscarrier++;
43 			stats->tx_carrier_errors++;
44 		}
45 		if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
46 			x->tx_carrier++;
47 			stats->tx_carrier_errors++;
48 		}
49 		if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
50 			     (tdes3 & TDES3_EXCESSIVE_COLLISION)))
51 			stats->collisions +=
52 			    (tdes3 & TDES3_COLLISION_COUNT_MASK)
53 			    >> TDES3_COLLISION_COUNT_SHIFT;
54 
55 		if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
56 			x->tx_deferred++;
57 
58 		if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) {
59 			x->tx_underflow++;
60 			ret |= tx_err_bump_tc;
61 		}
62 
63 		if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
64 			x->tx_ip_header_error++;
65 
66 		if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
67 			x->tx_payload_error++;
68 	}
69 
70 	if (unlikely(tdes3 & TDES3_DEFERRED))
71 		x->tx_deferred++;
72 
73 	return ret;
74 }
75 
dwmac4_wrback_get_rx_status(void * data,struct stmmac_extra_stats * x,struct dma_desc * p)76 static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
77 				       struct dma_desc *p)
78 {
79 	struct net_device_stats *stats = (struct net_device_stats *)data;
80 	unsigned int rdes1 = le32_to_cpu(p->des1);
81 	unsigned int rdes2 = le32_to_cpu(p->des2);
82 	unsigned int rdes3 = le32_to_cpu(p->des3);
83 	int message_type;
84 	int ret = good_frame;
85 
86 	if (unlikely(rdes3 & RDES3_OWN))
87 		return dma_own;
88 
89 	if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
90 		return discard_frame;
91 	if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
92 		return rx_not_ls;
93 
94 	if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
95 		if (unlikely(rdes3 & RDES3_GIANT_PACKET))
96 			stats->rx_length_errors++;
97 		if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
98 			x->rx_gmac_overflow++;
99 
100 		if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
101 			x->rx_watchdog++;
102 
103 		if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
104 			x->rx_mii++;
105 
106 		if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
107 			x->rx_crc_errors++;
108 			stats->rx_crc_errors++;
109 		}
110 
111 		if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
112 			x->dribbling_bit++;
113 
114 		ret = discard_frame;
115 	}
116 
117 	message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
118 
119 	if (rdes1 & RDES1_IP_HDR_ERROR)
120 		x->ip_hdr_err++;
121 	if (rdes1 & RDES1_IP_CSUM_BYPASSED)
122 		x->ip_csum_bypassed++;
123 	if (rdes1 & RDES1_IPV4_HEADER)
124 		x->ipv4_pkt_rcvd++;
125 	if (rdes1 & RDES1_IPV6_HEADER)
126 		x->ipv6_pkt_rcvd++;
127 
128 	if (message_type == RDES_EXT_NO_PTP)
129 		x->no_ptp_rx_msg_type_ext++;
130 	else if (message_type == RDES_EXT_SYNC)
131 		x->ptp_rx_msg_type_sync++;
132 	else if (message_type == RDES_EXT_FOLLOW_UP)
133 		x->ptp_rx_msg_type_follow_up++;
134 	else if (message_type == RDES_EXT_DELAY_REQ)
135 		x->ptp_rx_msg_type_delay_req++;
136 	else if (message_type == RDES_EXT_DELAY_RESP)
137 		x->ptp_rx_msg_type_delay_resp++;
138 	else if (message_type == RDES_EXT_PDELAY_REQ)
139 		x->ptp_rx_msg_type_pdelay_req++;
140 	else if (message_type == RDES_EXT_PDELAY_RESP)
141 		x->ptp_rx_msg_type_pdelay_resp++;
142 	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
143 		x->ptp_rx_msg_type_pdelay_follow_up++;
144 	else if (message_type == RDES_PTP_ANNOUNCE)
145 		x->ptp_rx_msg_type_announce++;
146 	else if (message_type == RDES_PTP_MANAGEMENT)
147 		x->ptp_rx_msg_type_management++;
148 	else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
149 		x->ptp_rx_msg_pkt_reserved_type++;
150 
151 	if (rdes1 & RDES1_PTP_PACKET_TYPE)
152 		x->ptp_frame_type++;
153 	if (rdes1 & RDES1_PTP_VER)
154 		x->ptp_ver++;
155 	if (rdes1 & RDES1_TIMESTAMP_DROPPED)
156 		x->timestamp_dropped++;
157 
158 	if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
159 		x->sa_rx_filter_fail++;
160 		ret = discard_frame;
161 	}
162 	if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
163 		x->da_rx_filter_fail++;
164 		ret = discard_frame;
165 	}
166 
167 	if (rdes2 & RDES2_L3_FILTER_MATCH)
168 		x->l3_filter_match++;
169 	if (rdes2 & RDES2_L4_FILTER_MATCH)
170 		x->l4_filter_match++;
171 	if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
172 	    >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
173 		x->l3_l4_filter_no_match++;
174 
175 	return ret;
176 }
177 
dwmac4_rd_get_tx_len(struct dma_desc * p)178 static int dwmac4_rd_get_tx_len(struct dma_desc *p)
179 {
180 	return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
181 }
182 
dwmac4_get_tx_owner(struct dma_desc * p)183 static int dwmac4_get_tx_owner(struct dma_desc *p)
184 {
185 	return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
186 }
187 
dwmac4_set_tx_owner(struct dma_desc * p)188 static void dwmac4_set_tx_owner(struct dma_desc *p)
189 {
190 	p->des3 |= cpu_to_le32(TDES3_OWN);
191 }
192 
dwmac4_set_rx_owner(struct dma_desc * p,int disable_rx_ic)193 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
194 {
195 	p->des3 |= cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
196 
197 	if (!disable_rx_ic)
198 		p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
199 }
200 
dwmac4_get_tx_ls(struct dma_desc * p)201 static int dwmac4_get_tx_ls(struct dma_desc *p)
202 {
203 	return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
204 		>> TDES3_LAST_DESCRIPTOR_SHIFT;
205 }
206 
dwmac4_wrback_get_rx_frame_len(struct dma_desc * p,int rx_coe)207 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
208 {
209 	return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
210 }
211 
dwmac4_rd_enable_tx_timestamp(struct dma_desc * p)212 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
213 {
214 	p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
215 }
216 
dwmac4_wrback_get_tx_timestamp_status(struct dma_desc * p)217 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
218 {
219 	/* Context type from W/B descriptor must be zero */
220 	if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
221 		return 0;
222 
223 	/* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
224 	if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
225 		return 1;
226 
227 	return 0;
228 }
229 
dwmac4_get_timestamp(void * desc,u32 ats,u64 * ts)230 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
231 {
232 	struct dma_desc *p = (struct dma_desc *)desc;
233 	u64 ns;
234 
235 	ns = le32_to_cpu(p->des0);
236 	/* convert high/sec time stamp value to nanosecond */
237 	ns += le32_to_cpu(p->des1) * 1000000000ULL;
238 
239 	*ts = ns;
240 }
241 
dwmac4_rx_check_timestamp(void * desc)242 static int dwmac4_rx_check_timestamp(void *desc)
243 {
244 	struct dma_desc *p = (struct dma_desc *)desc;
245 	unsigned int rdes0 = le32_to_cpu(p->des0);
246 	unsigned int rdes1 = le32_to_cpu(p->des1);
247 	unsigned int rdes3 = le32_to_cpu(p->des3);
248 	u32 own, ctxt;
249 	int ret = 1;
250 
251 	own = rdes3 & RDES3_OWN;
252 	ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
253 		>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
254 
255 	if (likely(!own && ctxt)) {
256 		if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
257 			/* Corrupted value */
258 			ret = -EINVAL;
259 		else
260 			/* A valid Timestamp is ready to be read */
261 			ret = 0;
262 	}
263 
264 	/* Timestamp not ready */
265 	return ret;
266 }
267 
dwmac4_wrback_get_rx_timestamp_status(void * desc,void * next_desc,u32 ats)268 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
269 						 u32 ats)
270 {
271 	struct dma_desc *p = (struct dma_desc *)desc;
272 	int ret = -EINVAL;
273 
274 	/* Get the status from normal w/b descriptor */
275 	if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
276 		if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
277 			int i = 0;
278 
279 			/* Check if timestamp is OK from context descriptor */
280 			do {
281 				ret = dwmac4_rx_check_timestamp(next_desc);
282 				if (ret < 0)
283 					goto exit;
284 				i++;
285 
286 			} while ((ret == 1) && (i < 10));
287 
288 			if (i == 10)
289 				ret = -EBUSY;
290 		}
291 	}
292 exit:
293 	if (likely(ret == 0))
294 		return 1;
295 
296 	return 0;
297 }
298 
dwmac4_rd_init_rx_desc(struct dma_desc * p,int disable_rx_ic,int mode,int end,int bfsize)299 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
300 				   int mode, int end, int bfsize)
301 {
302 	dwmac4_set_rx_owner(p, disable_rx_ic);
303 }
304 
dwmac4_rd_init_tx_desc(struct dma_desc * p,int mode,int end)305 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
306 {
307 	p->des0 = 0;
308 	p->des1 = 0;
309 	p->des2 = 0;
310 	p->des3 = 0;
311 }
312 
dwmac4_rd_prepare_tx_desc(struct dma_desc * p,int is_fs,int len,bool csum_flag,int mode,bool tx_own,bool ls,unsigned int tot_pkt_len)313 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
314 				      bool csum_flag, int mode, bool tx_own,
315 				      bool ls, unsigned int tot_pkt_len)
316 {
317 	unsigned int tdes3 = le32_to_cpu(p->des3);
318 
319 	p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
320 
321 	tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
322 	if (is_fs)
323 		tdes3 |= TDES3_FIRST_DESCRIPTOR;
324 	else
325 		tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
326 
327 	if (likely(csum_flag))
328 		tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
329 	else
330 		tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
331 
332 	if (ls)
333 		tdes3 |= TDES3_LAST_DESCRIPTOR;
334 	else
335 		tdes3 &= ~TDES3_LAST_DESCRIPTOR;
336 
337 	/* Finally set the OWN bit. Later the DMA will start! */
338 	if (tx_own)
339 		tdes3 |= TDES3_OWN;
340 
341 	if (is_fs && tx_own)
342 		/* When the own bit, for the first frame, has to be set, all
343 		 * descriptors for the same frame has to be set before, to
344 		 * avoid race condition.
345 		 */
346 		dma_wmb();
347 
348 	p->des3 = cpu_to_le32(tdes3);
349 }
350 
dwmac4_rd_prepare_tso_tx_desc(struct dma_desc * p,int is_fs,int len1,int len2,bool tx_own,bool ls,unsigned int tcphdrlen,unsigned int tcppayloadlen)351 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
352 					  int len1, int len2, bool tx_own,
353 					  bool ls, unsigned int tcphdrlen,
354 					  unsigned int tcppayloadlen)
355 {
356 	unsigned int tdes3 = le32_to_cpu(p->des3);
357 
358 	if (len1)
359 		p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
360 
361 	if (len2)
362 		p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
363 			    & TDES2_BUFFER2_SIZE_MASK);
364 
365 	if (is_fs) {
366 		tdes3 |= TDES3_FIRST_DESCRIPTOR |
367 			 TDES3_TCP_SEGMENTATION_ENABLE |
368 			 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
369 			  TDES3_SLOT_NUMBER_MASK) |
370 			 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
371 	} else {
372 		tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
373 	}
374 
375 	if (ls)
376 		tdes3 |= TDES3_LAST_DESCRIPTOR;
377 	else
378 		tdes3 &= ~TDES3_LAST_DESCRIPTOR;
379 
380 	/* Finally set the OWN bit. Later the DMA will start! */
381 	if (tx_own)
382 		tdes3 |= TDES3_OWN;
383 
384 	if (is_fs && tx_own)
385 		/* When the own bit, for the first frame, has to be set, all
386 		 * descriptors for the same frame has to be set before, to
387 		 * avoid race condition.
388 		 */
389 		dma_wmb();
390 
391 	p->des3 = cpu_to_le32(tdes3);
392 }
393 
dwmac4_release_tx_desc(struct dma_desc * p,int mode)394 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
395 {
396 	p->des0 = 0;
397 	p->des1 = 0;
398 	p->des2 = 0;
399 	p->des3 = 0;
400 }
401 
dwmac4_rd_set_tx_ic(struct dma_desc * p)402 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
403 {
404 	p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
405 }
406 
dwmac4_display_ring(void * head,unsigned int size,bool rx,dma_addr_t dma_rx_phy,unsigned int desc_size)407 static void dwmac4_display_ring(void *head, unsigned int size, bool rx,
408 				dma_addr_t dma_rx_phy, unsigned int desc_size)
409 {
410 	dma_addr_t dma_addr;
411 	int i;
412 
413 	pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
414 
415 	if (desc_size == sizeof(struct dma_desc)) {
416 		struct dma_desc *p = (struct dma_desc *)head;
417 
418 		for (i = 0; i < size; i++) {
419 			dma_addr = dma_rx_phy + i * sizeof(*p);
420 			pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
421 				i, &dma_addr,
422 				le32_to_cpu(p->des0), le32_to_cpu(p->des1),
423 				le32_to_cpu(p->des2), le32_to_cpu(p->des3));
424 			p++;
425 		}
426 	} else if (desc_size == sizeof(struct dma_extended_desc)) {
427 		struct dma_extended_desc *extp = (struct dma_extended_desc *)head;
428 
429 		for (i = 0; i < size; i++) {
430 			dma_addr = dma_rx_phy + i * sizeof(*extp);
431 			pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
432 				i, &dma_addr,
433 				le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),
434 				le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),
435 				le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),
436 				le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));
437 			extp++;
438 		}
439 	} else if (desc_size == sizeof(struct dma_edesc)) {
440 		struct dma_edesc *ep = (struct dma_edesc *)head;
441 
442 		for (i = 0; i < size; i++) {
443 			dma_addr = dma_rx_phy + i * sizeof(*ep);
444 			pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
445 				i, &dma_addr,
446 				le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),
447 				le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),
448 				le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),
449 				le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));
450 			ep++;
451 		}
452 	} else {
453 		pr_err("unsupported descriptor!");
454 	}
455 }
456 
dwmac4_set_mss_ctxt(struct dma_desc * p,unsigned int mss)457 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
458 {
459 	p->des0 = 0;
460 	p->des1 = 0;
461 	p->des2 = cpu_to_le32(mss);
462 	p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
463 }
464 
dwmac4_set_addr(struct dma_desc * p,dma_addr_t addr)465 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
466 {
467 	p->des0 = cpu_to_le32(lower_32_bits(addr));
468 	p->des1 = cpu_to_le32(upper_32_bits(addr));
469 }
470 
dwmac4_clear(struct dma_desc * p)471 static void dwmac4_clear(struct dma_desc *p)
472 {
473 	p->des0 = 0;
474 	p->des1 = 0;
475 	p->des2 = 0;
476 	p->des3 = 0;
477 }
478 
dwmac4_set_sarc(struct dma_desc * p,u32 sarc_type)479 static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
480 {
481 	sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
482 
483 	p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
484 }
485 
set_16kib_bfsize(int mtu)486 static int set_16kib_bfsize(int mtu)
487 {
488 	int ret = 0;
489 
490 	if (unlikely(mtu >= BUF_SIZE_8KiB))
491 		ret = BUF_SIZE_16KiB;
492 	return ret;
493 }
494 
dwmac4_set_vlan_tag(struct dma_desc * p,u16 tag,u16 inner_tag,u32 inner_type)495 static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
496 				u32 inner_type)
497 {
498 	p->des0 = 0;
499 	p->des1 = 0;
500 	p->des2 = 0;
501 	p->des3 = 0;
502 
503 	/* Inner VLAN */
504 	if (inner_type) {
505 		u32 des = inner_tag << TDES2_IVT_SHIFT;
506 
507 		des &= TDES2_IVT_MASK;
508 		p->des2 = cpu_to_le32(des);
509 
510 		des = inner_type << TDES3_IVTIR_SHIFT;
511 		des &= TDES3_IVTIR_MASK;
512 		p->des3 = cpu_to_le32(des | TDES3_IVLTV);
513 	}
514 
515 	/* Outer VLAN */
516 	p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
517 	p->des3 |= cpu_to_le32(TDES3_VLTV);
518 
519 	p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
520 }
521 
dwmac4_set_vlan(struct dma_desc * p,u32 type)522 static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
523 {
524 	type <<= TDES2_VLAN_TAG_SHIFT;
525 	p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
526 }
527 
dwmac4_get_rx_header_len(struct dma_desc * p,unsigned int * len)528 static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
529 {
530 	*len = le32_to_cpu(p->des2) & RDES2_HL;
531 }
532 
dwmac4_set_sec_addr(struct dma_desc * p,dma_addr_t addr,bool buf2_valid)533 static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)
534 {
535 	p->des2 = cpu_to_le32(lower_32_bits(addr));
536 	p->des3 = cpu_to_le32(upper_32_bits(addr));
537 
538 	if (buf2_valid)
539 		p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);
540 	else
541 		p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);
542 }
543 
dwmac4_set_tbs(struct dma_edesc * p,u32 sec,u32 nsec)544 static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
545 {
546 	p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
547 	p->des5 = cpu_to_le32(nsec & TDES5_LT);
548 	p->des6 = 0;
549 	p->des7 = 0;
550 }
551 
552 const struct stmmac_desc_ops dwmac4_desc_ops = {
553 	.tx_status = dwmac4_wrback_get_tx_status,
554 	.rx_status = dwmac4_wrback_get_rx_status,
555 	.get_tx_len = dwmac4_rd_get_tx_len,
556 	.get_tx_owner = dwmac4_get_tx_owner,
557 	.set_tx_owner = dwmac4_set_tx_owner,
558 	.set_rx_owner = dwmac4_set_rx_owner,
559 	.get_tx_ls = dwmac4_get_tx_ls,
560 	.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
561 	.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
562 	.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
563 	.get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
564 	.get_timestamp = dwmac4_get_timestamp,
565 	.set_tx_ic = dwmac4_rd_set_tx_ic,
566 	.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
567 	.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
568 	.release_tx_desc = dwmac4_release_tx_desc,
569 	.init_rx_desc = dwmac4_rd_init_rx_desc,
570 	.init_tx_desc = dwmac4_rd_init_tx_desc,
571 	.display_ring = dwmac4_display_ring,
572 	.set_mss = dwmac4_set_mss_ctxt,
573 	.set_addr = dwmac4_set_addr,
574 	.clear = dwmac4_clear,
575 	.set_sarc = dwmac4_set_sarc,
576 	.set_vlan_tag = dwmac4_set_vlan_tag,
577 	.set_vlan = dwmac4_set_vlan,
578 	.get_rx_header_len = dwmac4_get_rx_header_len,
579 	.set_sec_addr = dwmac4_set_sec_addr,
580 	.set_tbs = dwmac4_set_tbs,
581 };
582 
583 const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
584 	.set_16kib_bfsize = set_16kib_bfsize,
585 };
586