1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2014 Broadcom Corporation
4 */
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/list.h>
8 #include <linux/ssb/ssb_regs.h>
9 #include <linux/bcma/bcma.h>
10 #include <linux/bcma/bcma_regs.h>
11
12 #include <defs.h>
13 #include <soc.h>
14 #include <brcm_hw_ids.h>
15 #include <brcmu_utils.h>
16 #include <chipcommon.h>
17 #include "debug.h"
18 #include "chip.h"
19
20 /* SOC Interconnect types (aka chip types) */
21 #define SOCI_SB 0
22 #define SOCI_AI 1
23
24 /* PL-368 DMP definitions */
25 #define DMP_DESC_TYPE_MSK 0x0000000F
26 #define DMP_DESC_EMPTY 0x00000000
27 #define DMP_DESC_VALID 0x00000001
28 #define DMP_DESC_COMPONENT 0x00000001
29 #define DMP_DESC_MASTER_PORT 0x00000003
30 #define DMP_DESC_ADDRESS 0x00000005
31 #define DMP_DESC_ADDRSIZE_GT32 0x00000008
32 #define DMP_DESC_EOT 0x0000000F
33
34 #define DMP_COMP_DESIGNER 0xFFF00000
35 #define DMP_COMP_DESIGNER_S 20
36 #define DMP_COMP_PARTNUM 0x000FFF00
37 #define DMP_COMP_PARTNUM_S 8
38 #define DMP_COMP_CLASS 0x000000F0
39 #define DMP_COMP_CLASS_S 4
40 #define DMP_COMP_REVISION 0xFF000000
41 #define DMP_COMP_REVISION_S 24
42 #define DMP_COMP_NUM_SWRAP 0x00F80000
43 #define DMP_COMP_NUM_SWRAP_S 19
44 #define DMP_COMP_NUM_MWRAP 0x0007C000
45 #define DMP_COMP_NUM_MWRAP_S 14
46 #define DMP_COMP_NUM_SPORT 0x00003E00
47 #define DMP_COMP_NUM_SPORT_S 9
48 #define DMP_COMP_NUM_MPORT 0x000001F0
49 #define DMP_COMP_NUM_MPORT_S 4
50
51 #define DMP_MASTER_PORT_UID 0x0000FF00
52 #define DMP_MASTER_PORT_UID_S 8
53 #define DMP_MASTER_PORT_NUM 0x000000F0
54 #define DMP_MASTER_PORT_NUM_S 4
55
56 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
57 #define DMP_SLAVE_ADDR_BASE_S 12
58 #define DMP_SLAVE_PORT_NUM 0x00000F00
59 #define DMP_SLAVE_PORT_NUM_S 8
60 #define DMP_SLAVE_TYPE 0x000000C0
61 #define DMP_SLAVE_TYPE_S 6
62 #define DMP_SLAVE_TYPE_SLAVE 0
63 #define DMP_SLAVE_TYPE_BRIDGE 1
64 #define DMP_SLAVE_TYPE_SWRAP 2
65 #define DMP_SLAVE_TYPE_MWRAP 3
66 #define DMP_SLAVE_SIZE_TYPE 0x00000030
67 #define DMP_SLAVE_SIZE_TYPE_S 4
68 #define DMP_SLAVE_SIZE_4K 0
69 #define DMP_SLAVE_SIZE_8K 1
70 #define DMP_SLAVE_SIZE_16K 2
71 #define DMP_SLAVE_SIZE_DESC 3
72
73 /* EROM CompIdentB */
74 #define CIB_REV_MASK 0xff000000
75 #define CIB_REV_SHIFT 24
76
77 /* ARM CR4 core specific control flag bits */
78 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
79
80 /* D11 core specific control flag bits */
81 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
82 #define D11_BCMA_IOCTL_PHYRESET 0x0008
83
84 /* chip core base & ramsize */
85 /* bcm4329 */
86 /* SDIO device core, ID 0x829 */
87 #define BCM4329_CORE_BUS_BASE 0x18011000
88 /* internal memory core, ID 0x80e */
89 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
90 /* ARM Cortex M3 core, ID 0x82a */
91 #define BCM4329_CORE_ARM_BASE 0x18002000
92
93 /* Max possibly supported memory size (limited by IO mapped memory) */
94 #define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
95
96 #define CORE_SB(base, field) \
97 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
98 #define SBCOREREV(sbidh) \
99 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
100 ((sbidh) & SSB_IDHIGH_RCLO))
101
102 struct sbconfig {
103 u32 PAD[2];
104 u32 sbipsflag; /* initiator port ocp slave flag */
105 u32 PAD[3];
106 u32 sbtpsflag; /* target port ocp slave flag */
107 u32 PAD[11];
108 u32 sbtmerrloga; /* (sonics >= 2.3) */
109 u32 PAD;
110 u32 sbtmerrlog; /* (sonics >= 2.3) */
111 u32 PAD[3];
112 u32 sbadmatch3; /* address match3 */
113 u32 PAD;
114 u32 sbadmatch2; /* address match2 */
115 u32 PAD;
116 u32 sbadmatch1; /* address match1 */
117 u32 PAD[7];
118 u32 sbimstate; /* initiator agent state */
119 u32 sbintvec; /* interrupt mask */
120 u32 sbtmstatelow; /* target state */
121 u32 sbtmstatehigh; /* target state */
122 u32 sbbwa0; /* bandwidth allocation table0 */
123 u32 PAD;
124 u32 sbimconfiglow; /* initiator configuration */
125 u32 sbimconfighigh; /* initiator configuration */
126 u32 sbadmatch0; /* address match0 */
127 u32 PAD;
128 u32 sbtmconfiglow; /* target configuration */
129 u32 sbtmconfighigh; /* target configuration */
130 u32 sbbconfig; /* broadcast configuration */
131 u32 PAD;
132 u32 sbbstate; /* broadcast state */
133 u32 PAD[3];
134 u32 sbactcnfg; /* activate configuration */
135 u32 PAD[3];
136 u32 sbflagst; /* current sbflags */
137 u32 PAD[3];
138 u32 sbidlow; /* identification */
139 u32 sbidhigh; /* identification */
140 };
141
142 #define INVALID_RAMBASE ((u32)(~0))
143
144 /* bankidx and bankinfo reg defines corerev >= 8 */
145 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
146 #define SOCRAM_BANKINFO_SZMASK 0x0000007f
147 #define SOCRAM_BANKIDX_ROM_MASK 0x00000100
148
149 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
150 /* socram bankinfo memtype */
151 #define SOCRAM_MEMTYPE_RAM 0
152 #define SOCRAM_MEMTYPE_R0M 1
153 #define SOCRAM_MEMTYPE_DEVRAM 2
154
155 #define SOCRAM_BANKINFO_SZBASE 8192
156 #define SRCI_LSS_MASK 0x00f00000
157 #define SRCI_LSS_SHIFT 20
158 #define SRCI_SRNB_MASK 0xf0
159 #define SRCI_SRNB_MASK_EXT 0x100
160 #define SRCI_SRNB_SHIFT 4
161 #define SRCI_SRBSZ_MASK 0xf
162 #define SRCI_SRBSZ_SHIFT 0
163 #define SR_BSZ_BASE 14
164
165 struct sbsocramregs {
166 u32 coreinfo;
167 u32 bwalloc;
168 u32 extracoreinfo;
169 u32 biststat;
170 u32 bankidx;
171 u32 standbyctrl;
172
173 u32 errlogstatus; /* rev 6 */
174 u32 errlogaddr; /* rev 6 */
175 /* used for patching rev 3 & 5 */
176 u32 cambankidx;
177 u32 cambankstandbyctrl;
178 u32 cambankpatchctrl;
179 u32 cambankpatchtblbaseaddr;
180 u32 cambankcmdreg;
181 u32 cambankdatareg;
182 u32 cambankmaskreg;
183 u32 PAD[1];
184 u32 bankinfo; /* corev 8 */
185 u32 bankpda;
186 u32 PAD[14];
187 u32 extmemconfig;
188 u32 extmemparitycsr;
189 u32 extmemparityerrdata;
190 u32 extmemparityerrcnt;
191 u32 extmemwrctrlandsize;
192 u32 PAD[84];
193 u32 workaround;
194 u32 pwrctl; /* corerev >= 2 */
195 u32 PAD[133];
196 u32 sr_control; /* corerev >= 15 */
197 u32 sr_status; /* corerev >= 15 */
198 u32 sr_address; /* corerev >= 15 */
199 u32 sr_data; /* corerev >= 15 */
200 };
201
202 #define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
203 #define SYSMEMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
204
205 #define ARMCR4_CAP (0x04)
206 #define ARMCR4_BANKIDX (0x40)
207 #define ARMCR4_BANKINFO (0x44)
208 #define ARMCR4_BANKPDA (0x4C)
209
210 #define ARMCR4_TCBBNB_MASK 0xf0
211 #define ARMCR4_TCBBNB_SHIFT 4
212 #define ARMCR4_TCBANB_MASK 0xf
213 #define ARMCR4_TCBANB_SHIFT 0
214
215 #define ARMCR4_BSZ_MASK 0x3f
216 #define ARMCR4_BSZ_MULT 8192
217
218 struct brcmf_core_priv {
219 struct brcmf_core pub;
220 u32 wrapbase;
221 struct list_head list;
222 struct brcmf_chip_priv *chip;
223 };
224
225 struct brcmf_chip_priv {
226 struct brcmf_chip pub;
227 const struct brcmf_buscore_ops *ops;
228 void *ctx;
229 /* assured first core is chipcommon, second core is buscore */
230 struct list_head cores;
231 u16 num_cores;
232
233 bool (*iscoreup)(struct brcmf_core_priv *core);
234 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
235 u32 reset);
236 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
237 u32 postreset);
238 };
239
brcmf_chip_sb_corerev(struct brcmf_chip_priv * ci,struct brcmf_core * core)240 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
241 struct brcmf_core *core)
242 {
243 u32 regdata;
244
245 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
246 core->rev = SBCOREREV(regdata);
247 }
248
brcmf_chip_sb_iscoreup(struct brcmf_core_priv * core)249 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
250 {
251 struct brcmf_chip_priv *ci;
252 u32 regdata;
253 u32 address;
254
255 ci = core->chip;
256 address = CORE_SB(core->pub.base, sbtmstatelow);
257 regdata = ci->ops->read32(ci->ctx, address);
258 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
259 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
260 return SSB_TMSLOW_CLOCK == regdata;
261 }
262
brcmf_chip_ai_iscoreup(struct brcmf_core_priv * core)263 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
264 {
265 struct brcmf_chip_priv *ci;
266 u32 regdata;
267 bool ret;
268
269 ci = core->chip;
270 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
271 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
272
273 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
274 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
275
276 return ret;
277 }
278
brcmf_chip_sb_coredisable(struct brcmf_core_priv * core,u32 prereset,u32 reset)279 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
280 u32 prereset, u32 reset)
281 {
282 struct brcmf_chip_priv *ci;
283 u32 val, base;
284
285 ci = core->chip;
286 base = core->pub.base;
287 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
288 if (val & SSB_TMSLOW_RESET)
289 return;
290
291 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
292 if ((val & SSB_TMSLOW_CLOCK) != 0) {
293 /*
294 * set target reject and spin until busy is clear
295 * (preserve core-specific bits)
296 */
297 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
298 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
299 val | SSB_TMSLOW_REJECT);
300
301 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
302 udelay(1);
303 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
304 & SSB_TMSHIGH_BUSY), 100000);
305
306 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
307 if (val & SSB_TMSHIGH_BUSY)
308 brcmf_err("core state still busy\n");
309
310 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
311 if (val & SSB_IDLOW_INITIATOR) {
312 val = ci->ops->read32(ci->ctx,
313 CORE_SB(base, sbimstate));
314 val |= SSB_IMSTATE_REJECT;
315 ci->ops->write32(ci->ctx,
316 CORE_SB(base, sbimstate), val);
317 val = ci->ops->read32(ci->ctx,
318 CORE_SB(base, sbimstate));
319 udelay(1);
320 SPINWAIT((ci->ops->read32(ci->ctx,
321 CORE_SB(base, sbimstate)) &
322 SSB_IMSTATE_BUSY), 100000);
323 }
324
325 /* set reset and reject while enabling the clocks */
326 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
327 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
328 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
329 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
330 udelay(10);
331
332 /* clear the initiator reject bit */
333 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
334 if (val & SSB_IDLOW_INITIATOR) {
335 val = ci->ops->read32(ci->ctx,
336 CORE_SB(base, sbimstate));
337 val &= ~SSB_IMSTATE_REJECT;
338 ci->ops->write32(ci->ctx,
339 CORE_SB(base, sbimstate), val);
340 }
341 }
342
343 /* leave reset and reject asserted */
344 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
345 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
346 udelay(1);
347 }
348
brcmf_chip_ai_coredisable(struct brcmf_core_priv * core,u32 prereset,u32 reset)349 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
350 u32 prereset, u32 reset)
351 {
352 struct brcmf_chip_priv *ci;
353 u32 regdata;
354
355 ci = core->chip;
356
357 /* if core is already in reset, skip reset */
358 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
359 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
360 goto in_reset_configure;
361
362 /* configure reset */
363 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
364 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
365 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
366
367 /* put in reset */
368 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
369 BCMA_RESET_CTL_RESET);
370 usleep_range(10, 20);
371
372 /* wait till reset is 1 */
373 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
374 BCMA_RESET_CTL_RESET, 300);
375
376 in_reset_configure:
377 /* in-reset configure */
378 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
379 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
380 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
381 }
382
brcmf_chip_sb_resetcore(struct brcmf_core_priv * core,u32 prereset,u32 reset,u32 postreset)383 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
384 u32 reset, u32 postreset)
385 {
386 struct brcmf_chip_priv *ci;
387 u32 regdata;
388 u32 base;
389
390 ci = core->chip;
391 base = core->pub.base;
392 /*
393 * Must do the disable sequence first to work for
394 * arbitrary current core state.
395 */
396 brcmf_chip_sb_coredisable(core, 0, 0);
397
398 /*
399 * Now do the initialization sequence.
400 * set reset while enabling the clock and
401 * forcing them on throughout the core
402 */
403 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
404 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
405 SSB_TMSLOW_RESET);
406 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
407 udelay(1);
408
409 /* clear any serror */
410 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
411 if (regdata & SSB_TMSHIGH_SERR)
412 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
413
414 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
415 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
416 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
417 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
418 }
419
420 /* clear reset and allow it to propagate throughout the core */
421 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
422 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
423 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
424 udelay(1);
425
426 /* leave clock enabled */
427 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
428 SSB_TMSLOW_CLOCK);
429 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
430 udelay(1);
431 }
432
brcmf_chip_ai_resetcore(struct brcmf_core_priv * core,u32 prereset,u32 reset,u32 postreset)433 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
434 u32 reset, u32 postreset)
435 {
436 struct brcmf_chip_priv *ci;
437 int count;
438 struct brcmf_core *d11core2 = NULL;
439 struct brcmf_core_priv *d11priv2 = NULL;
440
441 ci = core->chip;
442
443 /* special handle two D11 cores reset */
444 if (core->pub.id == BCMA_CORE_80211) {
445 d11core2 = brcmf_chip_get_d11core(&ci->pub, 1);
446 if (d11core2) {
447 brcmf_dbg(INFO, "found two d11 cores, reset both\n");
448 d11priv2 = container_of(d11core2,
449 struct brcmf_core_priv, pub);
450 }
451 }
452
453 /* must disable first to work for arbitrary current core state */
454 brcmf_chip_ai_coredisable(core, prereset, reset);
455 if (d11priv2)
456 brcmf_chip_ai_coredisable(d11priv2, prereset, reset);
457
458 count = 0;
459 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
460 BCMA_RESET_CTL_RESET) {
461 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
462 count++;
463 if (count > 50)
464 break;
465 usleep_range(40, 60);
466 }
467
468 if (d11priv2) {
469 count = 0;
470 while (ci->ops->read32(ci->ctx,
471 d11priv2->wrapbase + BCMA_RESET_CTL) &
472 BCMA_RESET_CTL_RESET) {
473 ci->ops->write32(ci->ctx,
474 d11priv2->wrapbase + BCMA_RESET_CTL,
475 0);
476 count++;
477 if (count > 50)
478 break;
479 usleep_range(40, 60);
480 }
481 }
482
483 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
484 postreset | BCMA_IOCTL_CLK);
485 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
486
487 if (d11priv2) {
488 ci->ops->write32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL,
489 postreset | BCMA_IOCTL_CLK);
490 ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL);
491 }
492 }
493
brcmf_chip_name(u32 id,u32 rev,char * buf,uint len)494 char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len)
495 {
496 const char *fmt;
497
498 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u";
499 snprintf(buf, len, fmt, id, rev);
500 return buf;
501 }
502
brcmf_chip_add_core(struct brcmf_chip_priv * ci,u16 coreid,u32 base,u32 wrapbase)503 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
504 u16 coreid, u32 base,
505 u32 wrapbase)
506 {
507 struct brcmf_core_priv *core;
508
509 core = kzalloc(sizeof(*core), GFP_KERNEL);
510 if (!core)
511 return ERR_PTR(-ENOMEM);
512
513 core->pub.id = coreid;
514 core->pub.base = base;
515 core->chip = ci;
516 core->wrapbase = wrapbase;
517
518 list_add_tail(&core->list, &ci->cores);
519 return &core->pub;
520 }
521
522 /* safety check for chipinfo */
brcmf_chip_cores_check(struct brcmf_chip_priv * ci)523 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
524 {
525 struct brcmf_core_priv *core;
526 bool need_socram = false;
527 bool has_socram = false;
528 bool cpu_found = false;
529 int idx = 1;
530
531 list_for_each_entry(core, &ci->cores, list) {
532 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-3d base 0x%08x wrap 0x%08x\n",
533 idx++, core->pub.id, core->pub.rev, core->pub.base,
534 core->wrapbase);
535
536 switch (core->pub.id) {
537 case BCMA_CORE_ARM_CM3:
538 cpu_found = true;
539 need_socram = true;
540 break;
541 case BCMA_CORE_INTERNAL_MEM:
542 has_socram = true;
543 break;
544 case BCMA_CORE_ARM_CR4:
545 cpu_found = true;
546 break;
547 case BCMA_CORE_ARM_CA7:
548 cpu_found = true;
549 break;
550 default:
551 break;
552 }
553 }
554
555 if (!cpu_found) {
556 brcmf_err("CPU core not detected\n");
557 return -ENXIO;
558 }
559 /* check RAM core presence for ARM CM3 core */
560 if (need_socram && !has_socram) {
561 brcmf_err("RAM core not provided with ARM CM3 core\n");
562 return -ENODEV;
563 }
564 return 0;
565 }
566
brcmf_chip_core_read32(struct brcmf_core_priv * core,u16 reg)567 static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
568 {
569 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
570 }
571
brcmf_chip_core_write32(struct brcmf_core_priv * core,u16 reg,u32 val)572 static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
573 u16 reg, u32 val)
574 {
575 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
576 }
577
brcmf_chip_socram_banksize(struct brcmf_core_priv * core,u8 idx,u32 * banksize)578 static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
579 u32 *banksize)
580 {
581 u32 bankinfo;
582 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
583
584 bankidx |= idx;
585 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
586 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
587 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
588 *banksize *= SOCRAM_BANKINFO_SZBASE;
589 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
590 }
591
brcmf_chip_socram_ramsize(struct brcmf_core_priv * sr,u32 * ramsize,u32 * srsize)592 static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
593 u32 *srsize)
594 {
595 u32 coreinfo;
596 uint nb, banksize, lss;
597 bool retent;
598 int i;
599
600 *ramsize = 0;
601 *srsize = 0;
602
603 if (WARN_ON(sr->pub.rev < 4))
604 return;
605
606 if (!brcmf_chip_iscoreup(&sr->pub))
607 brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
608
609 /* Get info for determining size */
610 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
611 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
612
613 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
614 banksize = (coreinfo & SRCI_SRBSZ_MASK);
615 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
616 if (lss != 0)
617 nb--;
618 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
619 if (lss != 0)
620 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
621 } else {
622 /* length of SRAM Banks increased for corerev greater than 23 */
623 if (sr->pub.rev >= 23) {
624 nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT))
625 >> SRCI_SRNB_SHIFT;
626 } else {
627 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
628 }
629 for (i = 0; i < nb; i++) {
630 retent = brcmf_chip_socram_banksize(sr, i, &banksize);
631 *ramsize += banksize;
632 if (retent)
633 *srsize += banksize;
634 }
635 }
636
637 /* hardcoded save&restore memory sizes */
638 switch (sr->chip->pub.chip) {
639 case BRCM_CC_4334_CHIP_ID:
640 if (sr->chip->pub.chiprev < 2)
641 *srsize = (32 * 1024);
642 break;
643 case BRCM_CC_43430_CHIP_ID:
644 /* assume sr for now as we can not check
645 * firmware sr capability at this point.
646 */
647 *srsize = (64 * 1024);
648 break;
649 default:
650 break;
651 }
652 }
653
654 /** Return the SYS MEM size */
brcmf_chip_sysmem_ramsize(struct brcmf_core_priv * sysmem)655 static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem)
656 {
657 u32 memsize = 0;
658 u32 coreinfo;
659 u32 idx;
660 u32 nb;
661 u32 banksize;
662
663 if (!brcmf_chip_iscoreup(&sysmem->pub))
664 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0);
665
666 coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo));
667 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
668
669 for (idx = 0; idx < nb; idx++) {
670 brcmf_chip_socram_banksize(sysmem, idx, &banksize);
671 memsize += banksize;
672 }
673
674 return memsize;
675 }
676
677 /** Return the TCM-RAM size of the ARMCR4 core. */
brcmf_chip_tcm_ramsize(struct brcmf_core_priv * cr4)678 static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
679 {
680 u32 corecap;
681 u32 memsize = 0;
682 u32 nab;
683 u32 nbb;
684 u32 totb;
685 u32 bxinfo;
686 u32 idx;
687
688 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
689
690 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
691 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
692 totb = nab + nbb;
693
694 for (idx = 0; idx < totb; idx++) {
695 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
696 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
697 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
698 }
699
700 return memsize;
701 }
702
brcmf_chip_tcm_rambase(struct brcmf_chip_priv * ci)703 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
704 {
705 switch (ci->pub.chip) {
706 case BRCM_CC_4345_CHIP_ID:
707 case BRCM_CC_43454_CHIP_ID:
708 return 0x198000;
709 case BRCM_CC_4335_CHIP_ID:
710 case BRCM_CC_4339_CHIP_ID:
711 case BRCM_CC_4350_CHIP_ID:
712 case BRCM_CC_4354_CHIP_ID:
713 case BRCM_CC_4356_CHIP_ID:
714 case BRCM_CC_43567_CHIP_ID:
715 case BRCM_CC_43569_CHIP_ID:
716 case BRCM_CC_43570_CHIP_ID:
717 case BRCM_CC_4358_CHIP_ID:
718 case BRCM_CC_43602_CHIP_ID:
719 case BRCM_CC_4371_CHIP_ID:
720 return 0x180000;
721 case BRCM_CC_43465_CHIP_ID:
722 case BRCM_CC_43525_CHIP_ID:
723 case BRCM_CC_4365_CHIP_ID:
724 case BRCM_CC_4366_CHIP_ID:
725 case BRCM_CC_43664_CHIP_ID:
726 case BRCM_CC_43666_CHIP_ID:
727 return 0x200000;
728 case BRCM_CC_4359_CHIP_ID:
729 return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000;
730 case BRCM_CC_4364_CHIP_ID:
731 case CY_CC_4373_CHIP_ID:
732 return 0x160000;
733 case CY_CC_43752_CHIP_ID:
734 return 0x170000;
735 default:
736 brcmf_err("unknown chip: %s\n", ci->pub.name);
737 break;
738 }
739 return INVALID_RAMBASE;
740 }
741
brcmf_chip_get_raminfo(struct brcmf_chip * pub)742 int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
743 {
744 struct brcmf_chip_priv *ci = container_of(pub, struct brcmf_chip_priv,
745 pub);
746 struct brcmf_core_priv *mem_core;
747 struct brcmf_core *mem;
748
749 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
750 if (mem) {
751 mem_core = container_of(mem, struct brcmf_core_priv, pub);
752 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
753 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
754 if (ci->pub.rambase == INVALID_RAMBASE) {
755 brcmf_err("RAM base not provided with ARM CR4 core\n");
756 return -EINVAL;
757 }
758 } else {
759 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM);
760 if (mem) {
761 mem_core = container_of(mem, struct brcmf_core_priv,
762 pub);
763 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
764 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
765 if (ci->pub.rambase == INVALID_RAMBASE) {
766 brcmf_err("RAM base not provided with ARM CA7 core\n");
767 return -EINVAL;
768 }
769 } else {
770 mem = brcmf_chip_get_core(&ci->pub,
771 BCMA_CORE_INTERNAL_MEM);
772 if (!mem) {
773 brcmf_err("No memory cores found\n");
774 return -ENOMEM;
775 }
776 mem_core = container_of(mem, struct brcmf_core_priv,
777 pub);
778 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
779 &ci->pub.srsize);
780 }
781 }
782 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
783 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
784 ci->pub.srsize, ci->pub.srsize);
785
786 if (!ci->pub.ramsize) {
787 brcmf_err("RAM size is undetermined\n");
788 return -ENOMEM;
789 }
790
791 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
792 brcmf_err("RAM size is incorrect\n");
793 return -ENOMEM;
794 }
795
796 return 0;
797 }
798
brcmf_chip_dmp_get_desc(struct brcmf_chip_priv * ci,u32 * eromaddr,u8 * type)799 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
800 u8 *type)
801 {
802 u32 val;
803
804 /* read next descriptor */
805 val = ci->ops->read32(ci->ctx, *eromaddr);
806 *eromaddr += 4;
807
808 if (!type)
809 return val;
810
811 /* determine descriptor type */
812 *type = (val & DMP_DESC_TYPE_MSK);
813 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
814 *type = DMP_DESC_ADDRESS;
815
816 return val;
817 }
818
brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv * ci,u32 * eromaddr,u32 * regbase,u32 * wrapbase)819 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
820 u32 *regbase, u32 *wrapbase)
821 {
822 u8 desc;
823 u32 val, szdesc;
824 u8 stype, sztype, wraptype;
825
826 *regbase = 0;
827 *wrapbase = 0;
828
829 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
830 if (desc == DMP_DESC_MASTER_PORT) {
831 wraptype = DMP_SLAVE_TYPE_MWRAP;
832 } else if (desc == DMP_DESC_ADDRESS) {
833 /* revert erom address */
834 *eromaddr -= 4;
835 wraptype = DMP_SLAVE_TYPE_SWRAP;
836 } else {
837 *eromaddr -= 4;
838 return -EILSEQ;
839 }
840
841 do {
842 /* locate address descriptor */
843 do {
844 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
845 /* unexpected table end */
846 if (desc == DMP_DESC_EOT) {
847 *eromaddr -= 4;
848 return -EFAULT;
849 }
850 } while (desc != DMP_DESC_ADDRESS &&
851 desc != DMP_DESC_COMPONENT);
852
853 /* stop if we crossed current component border */
854 if (desc == DMP_DESC_COMPONENT) {
855 *eromaddr -= 4;
856 return 0;
857 }
858
859 /* skip upper 32-bit address descriptor */
860 if (val & DMP_DESC_ADDRSIZE_GT32)
861 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
862
863 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
864
865 /* next size descriptor can be skipped */
866 if (sztype == DMP_SLAVE_SIZE_DESC) {
867 szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
868 /* skip upper size descriptor if present */
869 if (szdesc & DMP_DESC_ADDRSIZE_GT32)
870 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
871 }
872
873 /* look for 4K or 8K register regions */
874 if (sztype != DMP_SLAVE_SIZE_4K &&
875 sztype != DMP_SLAVE_SIZE_8K)
876 continue;
877
878 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
879
880 /* only regular slave and wrapper */
881 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
882 *regbase = val & DMP_SLAVE_ADDR_BASE;
883 if (*wrapbase == 0 && stype == wraptype)
884 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
885 } while (*regbase == 0 || *wrapbase == 0);
886
887 return 0;
888 }
889
890 static
brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv * ci)891 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
892 {
893 struct brcmf_core *core;
894 u32 eromaddr;
895 u8 desc_type = 0;
896 u32 val;
897 u16 id;
898 u8 nmw, nsw, rev;
899 u32 base, wrap;
900 int err;
901
902 eromaddr = ci->ops->read32(ci->ctx,
903 CORE_CC_REG(ci->pub.enum_base, eromptr));
904
905 while (desc_type != DMP_DESC_EOT) {
906 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
907 if (!(val & DMP_DESC_VALID))
908 continue;
909
910 if (desc_type == DMP_DESC_EMPTY)
911 continue;
912
913 /* need a component descriptor */
914 if (desc_type != DMP_DESC_COMPONENT)
915 continue;
916
917 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
918
919 /* next descriptor must be component as well */
920 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
921 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
922 return -EFAULT;
923
924 /* only look at cores with master port(s) */
925 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
926 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
927 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
928
929 /* need core with ports */
930 if (nmw + nsw == 0 &&
931 id != BCMA_CORE_PMU &&
932 id != BCMA_CORE_GCI)
933 continue;
934
935 /* try to obtain register address info */
936 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
937 if (err)
938 continue;
939
940 /* finally a core to be added */
941 core = brcmf_chip_add_core(ci, id, base, wrap);
942 if (IS_ERR(core))
943 return PTR_ERR(core);
944
945 core->rev = rev;
946 }
947
948 return 0;
949 }
950
brcmf_chip_enum_base(u16 devid)951 u32 brcmf_chip_enum_base(u16 devid)
952 {
953 return SI_ENUM_BASE_DEFAULT;
954 }
955
brcmf_chip_recognition(struct brcmf_chip_priv * ci)956 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
957 {
958 struct brcmf_core *core;
959 u32 regdata;
960 u32 socitype;
961 int ret;
962
963 /* Get CC core rev
964 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
965 * For different chiptypes or old sdio hosts w/o chipcommon,
966 * other ways of recognition should be added here.
967 */
968 regdata = ci->ops->read32(ci->ctx,
969 CORE_CC_REG(ci->pub.enum_base, chipid));
970 ci->pub.chip = regdata & CID_ID_MASK;
971 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
972 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
973
974 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev,
975 ci->pub.name, sizeof(ci->pub.name));
976 brcmf_dbg(INFO, "found %s chip: %s\n",
977 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name);
978
979 if (socitype == SOCI_SB) {
980 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
981 brcmf_err("SB chip is not supported\n");
982 return -ENODEV;
983 }
984 ci->iscoreup = brcmf_chip_sb_iscoreup;
985 ci->coredisable = brcmf_chip_sb_coredisable;
986 ci->resetcore = brcmf_chip_sb_resetcore;
987
988 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
989 SI_ENUM_BASE_DEFAULT, 0);
990 brcmf_chip_sb_corerev(ci, core);
991 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
992 BCM4329_CORE_BUS_BASE, 0);
993 brcmf_chip_sb_corerev(ci, core);
994 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
995 BCM4329_CORE_SOCRAM_BASE, 0);
996 brcmf_chip_sb_corerev(ci, core);
997 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
998 BCM4329_CORE_ARM_BASE, 0);
999 brcmf_chip_sb_corerev(ci, core);
1000
1001 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
1002 brcmf_chip_sb_corerev(ci, core);
1003 } else if (socitype == SOCI_AI) {
1004 ci->iscoreup = brcmf_chip_ai_iscoreup;
1005 ci->coredisable = brcmf_chip_ai_coredisable;
1006 ci->resetcore = brcmf_chip_ai_resetcore;
1007
1008 brcmf_chip_dmp_erom_scan(ci);
1009 } else {
1010 brcmf_err("chip backplane type %u is not supported\n",
1011 socitype);
1012 return -ENODEV;
1013 }
1014
1015 ret = brcmf_chip_cores_check(ci);
1016 if (ret)
1017 return ret;
1018
1019 /* assure chip is passive for core access */
1020 brcmf_chip_set_passive(&ci->pub);
1021
1022 /* Call bus specific reset function now. Cores have been determined
1023 * but further access may require a chip specific reset at this point.
1024 */
1025 if (ci->ops->reset) {
1026 ci->ops->reset(ci->ctx, &ci->pub);
1027 brcmf_chip_set_passive(&ci->pub);
1028 }
1029
1030 return brcmf_chip_get_raminfo(&ci->pub);
1031 }
1032
brcmf_chip_disable_arm(struct brcmf_chip_priv * chip,u16 id)1033 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
1034 {
1035 struct brcmf_core *core;
1036 struct brcmf_core_priv *cpu;
1037 u32 val;
1038
1039
1040 core = brcmf_chip_get_core(&chip->pub, id);
1041 if (!core)
1042 return;
1043
1044 switch (id) {
1045 case BCMA_CORE_ARM_CM3:
1046 brcmf_chip_coredisable(core, 0, 0);
1047 break;
1048 case BCMA_CORE_ARM_CR4:
1049 case BCMA_CORE_ARM_CA7:
1050 cpu = container_of(core, struct brcmf_core_priv, pub);
1051
1052 /* clear all IOCTL bits except HALT bit */
1053 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
1054 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
1055 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
1056 ARMCR4_BCMA_IOCTL_CPUHALT);
1057 break;
1058 default:
1059 brcmf_err("unknown id: %u\n", id);
1060 break;
1061 }
1062 }
1063
brcmf_chip_setup(struct brcmf_chip_priv * chip)1064 static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
1065 {
1066 struct brcmf_chip *pub;
1067 struct brcmf_core_priv *cc;
1068 struct brcmf_core *pmu;
1069 u32 base;
1070 u32 val;
1071 int ret = 0;
1072
1073 pub = &chip->pub;
1074 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1075 base = cc->pub.base;
1076
1077 /* get chipcommon capabilites */
1078 pub->cc_caps = chip->ops->read32(chip->ctx,
1079 CORE_CC_REG(base, capabilities));
1080 pub->cc_caps_ext = chip->ops->read32(chip->ctx,
1081 CORE_CC_REG(base,
1082 capabilities_ext));
1083
1084 /* get pmu caps & rev */
1085 pmu = brcmf_chip_get_pmu(pub); /* after reading cc_caps_ext */
1086 if (pub->cc_caps & CC_CAP_PMU) {
1087 val = chip->ops->read32(chip->ctx,
1088 CORE_CC_REG(pmu->base, pmucapabilities));
1089 pub->pmurev = val & PCAP_REV_MASK;
1090 pub->pmucaps = val;
1091 }
1092
1093 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
1094 cc->pub.rev, pub->pmurev, pub->pmucaps);
1095
1096 /* execute bus core specific setup */
1097 if (chip->ops->setup)
1098 ret = chip->ops->setup(chip->ctx, pub);
1099
1100 return ret;
1101 }
1102
brcmf_chip_attach(void * ctx,u16 devid,const struct brcmf_buscore_ops * ops)1103 struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
1104 const struct brcmf_buscore_ops *ops)
1105 {
1106 struct brcmf_chip_priv *chip;
1107 int err = 0;
1108
1109 if (WARN_ON(!ops->read32))
1110 err = -EINVAL;
1111 if (WARN_ON(!ops->write32))
1112 err = -EINVAL;
1113 if (WARN_ON(!ops->prepare))
1114 err = -EINVAL;
1115 if (WARN_ON(!ops->activate))
1116 err = -EINVAL;
1117 if (err < 0)
1118 return ERR_PTR(-EINVAL);
1119
1120 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1121 if (!chip)
1122 return ERR_PTR(-ENOMEM);
1123
1124 INIT_LIST_HEAD(&chip->cores);
1125 chip->num_cores = 0;
1126 chip->ops = ops;
1127 chip->ctx = ctx;
1128 chip->pub.enum_base = brcmf_chip_enum_base(devid);
1129
1130 err = ops->prepare(ctx);
1131 if (err < 0)
1132 goto fail;
1133
1134 err = brcmf_chip_recognition(chip);
1135 if (err < 0)
1136 goto fail;
1137
1138 err = brcmf_chip_setup(chip);
1139 if (err < 0)
1140 goto fail;
1141
1142 return &chip->pub;
1143
1144 fail:
1145 brcmf_chip_detach(&chip->pub);
1146 return ERR_PTR(err);
1147 }
1148
brcmf_chip_detach(struct brcmf_chip * pub)1149 void brcmf_chip_detach(struct brcmf_chip *pub)
1150 {
1151 struct brcmf_chip_priv *chip;
1152 struct brcmf_core_priv *core;
1153 struct brcmf_core_priv *tmp;
1154
1155 chip = container_of(pub, struct brcmf_chip_priv, pub);
1156 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
1157 list_del(&core->list);
1158 kfree(core);
1159 }
1160 kfree(chip);
1161 }
1162
brcmf_chip_get_d11core(struct brcmf_chip * pub,u8 unit)1163 struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit)
1164 {
1165 struct brcmf_chip_priv *chip;
1166 struct brcmf_core_priv *core;
1167
1168 chip = container_of(pub, struct brcmf_chip_priv, pub);
1169 list_for_each_entry(core, &chip->cores, list) {
1170 if (core->pub.id == BCMA_CORE_80211) {
1171 if (unit-- == 0)
1172 return &core->pub;
1173 }
1174 }
1175 return NULL;
1176 }
1177
brcmf_chip_get_core(struct brcmf_chip * pub,u16 coreid)1178 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
1179 {
1180 struct brcmf_chip_priv *chip;
1181 struct brcmf_core_priv *core;
1182
1183 chip = container_of(pub, struct brcmf_chip_priv, pub);
1184 list_for_each_entry(core, &chip->cores, list)
1185 if (core->pub.id == coreid)
1186 return &core->pub;
1187
1188 return NULL;
1189 }
1190
brcmf_chip_get_chipcommon(struct brcmf_chip * pub)1191 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
1192 {
1193 struct brcmf_chip_priv *chip;
1194 struct brcmf_core_priv *cc;
1195
1196 chip = container_of(pub, struct brcmf_chip_priv, pub);
1197 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1198 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
1199 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
1200 return &cc->pub;
1201 }
1202
brcmf_chip_get_pmu(struct brcmf_chip * pub)1203 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub)
1204 {
1205 struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub);
1206 struct brcmf_core *pmu;
1207
1208 /* See if there is separated PMU core available */
1209 if (cc->rev >= 35 &&
1210 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
1211 pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU);
1212 if (pmu)
1213 return pmu;
1214 }
1215
1216 /* Fallback to ChipCommon core for older hardware */
1217 return cc;
1218 }
1219
brcmf_chip_iscoreup(struct brcmf_core * pub)1220 bool brcmf_chip_iscoreup(struct brcmf_core *pub)
1221 {
1222 struct brcmf_core_priv *core;
1223
1224 core = container_of(pub, struct brcmf_core_priv, pub);
1225 return core->chip->iscoreup(core);
1226 }
1227
brcmf_chip_coredisable(struct brcmf_core * pub,u32 prereset,u32 reset)1228 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
1229 {
1230 struct brcmf_core_priv *core;
1231
1232 core = container_of(pub, struct brcmf_core_priv, pub);
1233 core->chip->coredisable(core, prereset, reset);
1234 }
1235
brcmf_chip_resetcore(struct brcmf_core * pub,u32 prereset,u32 reset,u32 postreset)1236 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
1237 u32 postreset)
1238 {
1239 struct brcmf_core_priv *core;
1240
1241 core = container_of(pub, struct brcmf_core_priv, pub);
1242 core->chip->resetcore(core, prereset, reset, postreset);
1243 }
1244
1245 static void
brcmf_chip_cm3_set_passive(struct brcmf_chip_priv * chip)1246 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
1247 {
1248 struct brcmf_core *core;
1249 struct brcmf_core_priv *sr;
1250
1251 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
1252 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1253 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1254 D11_BCMA_IOCTL_PHYCLOCKEN,
1255 D11_BCMA_IOCTL_PHYCLOCKEN,
1256 D11_BCMA_IOCTL_PHYCLOCKEN);
1257 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1258 brcmf_chip_resetcore(core, 0, 0, 0);
1259
1260 /* disable bank #3 remap for this device */
1261 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
1262 sr = container_of(core, struct brcmf_core_priv, pub);
1263 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
1264 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
1265 }
1266 }
1267
brcmf_chip_cm3_set_active(struct brcmf_chip_priv * chip)1268 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
1269 {
1270 struct brcmf_core *core;
1271
1272 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1273 if (!brcmf_chip_iscoreup(core)) {
1274 brcmf_err("SOCRAM core is down after reset?\n");
1275 return false;
1276 }
1277
1278 chip->ops->activate(chip->ctx, &chip->pub, 0);
1279
1280 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
1281 brcmf_chip_resetcore(core, 0, 0, 0);
1282
1283 return true;
1284 }
1285
1286 static inline void
brcmf_chip_cr4_set_passive(struct brcmf_chip_priv * chip)1287 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
1288 {
1289 struct brcmf_core *core;
1290
1291 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
1292
1293 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1294 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1295 D11_BCMA_IOCTL_PHYCLOCKEN,
1296 D11_BCMA_IOCTL_PHYCLOCKEN,
1297 D11_BCMA_IOCTL_PHYCLOCKEN);
1298 }
1299
brcmf_chip_cr4_set_active(struct brcmf_chip_priv * chip,u32 rstvec)1300 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1301 {
1302 struct brcmf_core *core;
1303
1304 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1305
1306 /* restore ARM */
1307 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
1308 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1309
1310 return true;
1311 }
1312
1313 static inline void
brcmf_chip_ca7_set_passive(struct brcmf_chip_priv * chip)1314 brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip)
1315 {
1316 struct brcmf_core *core;
1317
1318 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7);
1319
1320 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1321 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1322 D11_BCMA_IOCTL_PHYCLOCKEN,
1323 D11_BCMA_IOCTL_PHYCLOCKEN,
1324 D11_BCMA_IOCTL_PHYCLOCKEN);
1325 }
1326
brcmf_chip_ca7_set_active(struct brcmf_chip_priv * chip,u32 rstvec)1327 static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1328 {
1329 struct brcmf_core *core;
1330
1331 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1332
1333 /* restore ARM */
1334 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7);
1335 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1336
1337 return true;
1338 }
1339
brcmf_chip_set_passive(struct brcmf_chip * pub)1340 void brcmf_chip_set_passive(struct brcmf_chip *pub)
1341 {
1342 struct brcmf_chip_priv *chip;
1343 struct brcmf_core *arm;
1344
1345 brcmf_dbg(TRACE, "Enter\n");
1346
1347 chip = container_of(pub, struct brcmf_chip_priv, pub);
1348 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1349 if (arm) {
1350 brcmf_chip_cr4_set_passive(chip);
1351 return;
1352 }
1353 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1354 if (arm) {
1355 brcmf_chip_ca7_set_passive(chip);
1356 return;
1357 }
1358 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1359 if (arm) {
1360 brcmf_chip_cm3_set_passive(chip);
1361 return;
1362 }
1363 }
1364
brcmf_chip_set_active(struct brcmf_chip * pub,u32 rstvec)1365 bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
1366 {
1367 struct brcmf_chip_priv *chip;
1368 struct brcmf_core *arm;
1369
1370 brcmf_dbg(TRACE, "Enter\n");
1371
1372 chip = container_of(pub, struct brcmf_chip_priv, pub);
1373 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1374 if (arm)
1375 return brcmf_chip_cr4_set_active(chip, rstvec);
1376 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1377 if (arm)
1378 return brcmf_chip_ca7_set_active(chip, rstvec);
1379 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1380 if (arm)
1381 return brcmf_chip_cm3_set_active(chip);
1382
1383 return false;
1384 }
1385
brcmf_chip_sr_capable(struct brcmf_chip * pub)1386 bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1387 {
1388 u32 base, addr, reg, pmu_cc3_mask = ~0;
1389 struct brcmf_chip_priv *chip;
1390 struct brcmf_core *pmu = brcmf_chip_get_pmu(pub);
1391
1392 brcmf_dbg(TRACE, "Enter\n");
1393
1394 /* old chips with PMU version less than 17 don't support save restore */
1395 if (pub->pmurev < 17)
1396 return false;
1397
1398 base = brcmf_chip_get_chipcommon(pub)->base;
1399 chip = container_of(pub, struct brcmf_chip_priv, pub);
1400
1401 switch (pub->chip) {
1402 case BRCM_CC_4354_CHIP_ID:
1403 case BRCM_CC_4356_CHIP_ID:
1404 case BRCM_CC_4345_CHIP_ID:
1405 case BRCM_CC_43454_CHIP_ID:
1406 /* explicitly check SR engine enable bit */
1407 pmu_cc3_mask = BIT(2);
1408 fallthrough;
1409 case BRCM_CC_43241_CHIP_ID:
1410 case BRCM_CC_4335_CHIP_ID:
1411 case BRCM_CC_4339_CHIP_ID:
1412 /* read PMU chipcontrol register 3 */
1413 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
1414 chip->ops->write32(chip->ctx, addr, 3);
1415 addr = CORE_CC_REG(pmu->base, chipcontrol_data);
1416 reg = chip->ops->read32(chip->ctx, addr);
1417 return (reg & pmu_cc3_mask) != 0;
1418 case BRCM_CC_43430_CHIP_ID:
1419 addr = CORE_CC_REG(base, sr_control1);
1420 reg = chip->ops->read32(chip->ctx, addr);
1421 return reg != 0;
1422 case CY_CC_4373_CHIP_ID:
1423 /* explicitly check SR engine enable bit */
1424 addr = CORE_CC_REG(base, sr_control0);
1425 reg = chip->ops->read32(chip->ctx, addr);
1426 return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
1427 case BRCM_CC_4359_CHIP_ID:
1428 case CY_CC_43752_CHIP_ID:
1429 case CY_CC_43012_CHIP_ID:
1430 addr = CORE_CC_REG(pmu->base, retention_ctl);
1431 reg = chip->ops->read32(chip->ctx, addr);
1432 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1433 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1434 default:
1435 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
1436 reg = chip->ops->read32(chip->ctx, addr);
1437 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1438 return false;
1439
1440 addr = CORE_CC_REG(pmu->base, retention_ctl);
1441 reg = chip->ops->read32(chip->ctx, addr);
1442 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1443 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1444 }
1445 }
1446