1 /*
2 * SBE 2T3E3 synchronous serial card driver for Linux
3 *
4 * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * This code is based on a driver written by SBE Inc.
11 */
12
13 #include <linux/ip.h>
14 #include <asm/system.h>
15 #include "2t3e3.h"
16 #include "ctrl.h"
17
18 /* All access to registers done via the 21143 on port 0 must be
19 * protected via the card->bootrom_lock. */
20
21 /* priviate define to be used here only - must be protected by card->bootrom_lock */
22 #define cpld_write_nolock(channel, reg, val) \
23 bootrom_write((channel), CPLD_MAP_REG(reg, channel), val)
24
cpld_read(struct channel * channel,u32 reg)25 u32 cpld_read(struct channel *channel, u32 reg)
26 {
27 unsigned long flags;
28 u32 val;
29
30 spin_lock_irqsave(&channel->card->bootrom_lock, flags);
31 val = bootrom_read((channel), CPLD_MAP_REG(reg, channel));
32 spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
33 return val;
34 }
35
36 /****************************************
37 * Access via BootROM port
38 ****************************************/
39
bootrom_read(struct channel * channel,u32 reg)40 u32 bootrom_read(struct channel *channel, u32 reg)
41 {
42 unsigned long addr = channel->card->bootrom_addr;
43 u32 result;
44
45 /* select BootROM address */
46 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS, reg & 0x3FFFF);
47
48 /* select reading from BootROM */
49 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
50 SBE_2T3E3_21143_VAL_READ_OPERATION |
51 SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT);
52
53 udelay(2); /* 20 PCI cycles */
54
55 /* read from BootROM */
56 result = dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) & 0xff;
57
58 /* reset CSR9 */
59 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
60
61 return result;
62 }
63
bootrom_write(struct channel * channel,u32 reg,u32 val)64 void bootrom_write(struct channel *channel, u32 reg, u32 val)
65 {
66 unsigned long addr = channel->card->bootrom_addr;
67
68 /* select BootROM address */
69 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS, reg & 0x3FFFF);
70
71 /* select writting to BootROM */
72 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
73 SBE_2T3E3_21143_VAL_WRITE_OPERATION |
74 SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT |
75 (val & 0xff));
76
77 udelay(2); /* 20 PCI cycles */
78
79 /* reset CSR9 */
80 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
81 }
82
83
84 /****************************************
85 * Access via Serial I/O port
86 ****************************************/
87
serialrom_read_bit(struct channel * channel)88 static u32 serialrom_read_bit(struct channel *channel)
89 {
90 unsigned long addr = channel->card->bootrom_addr;
91 u32 bit;
92
93 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
94 SBE_2T3E3_21143_VAL_READ_OPERATION |
95 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
96 SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK |
97 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock high */
98
99 bit = (dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) &
100 SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_OUT) > 0 ? 1 : 0;
101
102 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
103 SBE_2T3E3_21143_VAL_READ_OPERATION |
104 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
105 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
106
107 return bit;
108 }
109
serialrom_write_bit(struct channel * channel,u32 bit)110 static void serialrom_write_bit(struct channel *channel, u32 bit)
111 {
112 unsigned long addr = channel->card->bootrom_addr;
113 u32 lastbit = -1;
114
115 bit &= 1;
116
117 if (bit != lastbit) {
118 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
119 SBE_2T3E3_21143_VAL_WRITE_OPERATION |
120 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
121 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
122 (bit << 2)); /* clock low */
123
124 lastbit = bit;
125 }
126
127 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
128 SBE_2T3E3_21143_VAL_WRITE_OPERATION |
129 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
130 SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK |
131 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
132 (bit << 2)); /* clock high */
133
134 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
135 SBE_2T3E3_21143_VAL_WRITE_OPERATION |
136 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
137 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
138 (bit << 2)); /* clock low */
139 }
140
141 /****************************************
142 * Access to SerialROM (eeprom)
143 ****************************************/
144
t3e3_eeprom_read_word(struct channel * channel,u32 address)145 u32 t3e3_eeprom_read_word(struct channel *channel, u32 address)
146 {
147 unsigned long addr = channel->card->bootrom_addr;
148 u32 i, val;
149 unsigned long flags;
150
151 address &= 0x3f;
152
153 spin_lock_irqsave(&channel->card->bootrom_lock, flags);
154
155 /* select correct Serial Chip */
156 cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
157 SBE_2T3E3_CPLD_VAL_EEPROM_SELECT);
158
159 /* select reading from Serial I/O Bus */
160 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
161 SBE_2T3E3_21143_VAL_READ_OPERATION |
162 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
163 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
164
165 /* select read operation */
166 serialrom_write_bit(channel, 0);
167 serialrom_write_bit(channel, 1);
168 serialrom_write_bit(channel, 1);
169 serialrom_write_bit(channel, 0);
170
171 for (i = 0x20; i; i >>= 1)
172 serialrom_write_bit(channel, address & i ? 1 : 0);
173
174 val = 0;
175 for (i = 0x8000; i; i >>= 1)
176 val |= (serialrom_read_bit(channel) ? i : 0);
177
178 /* Reset 21143's CSR9 */
179 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
180 SBE_2T3E3_21143_VAL_READ_OPERATION |
181 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
182 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
183 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
184
185 /* Unselect Serial Chip */
186 cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
187
188 spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
189
190 return ntohs(val);
191 }
192
193
194 /****************************************
195 * Access to Framer
196 ****************************************/
197
exar7250_read(struct channel * channel,u32 reg)198 u32 exar7250_read(struct channel *channel, u32 reg)
199 {
200 u32 result;
201 unsigned long flags;
202
203 #if 0
204 switch (reg) {
205 case SBE_2T3E3_FRAMER_REG_OPERATING_MODE:
206 return channel->framer_regs[reg];
207 break;
208 default:
209 }
210 #endif
211
212 spin_lock_irqsave(&channel->card->bootrom_lock, flags);
213
214 result = bootrom_read(channel, cpld_reg_map[SBE_2T3E3_CPLD_REG_FRAMER_BASE_ADDRESS]
215 [channel->h.slot] + (t3e3_framer_reg_map[reg] << 2));
216
217 spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
218
219 return result;
220 }
221
exar7250_write(struct channel * channel,u32 reg,u32 val)222 void exar7250_write(struct channel *channel, u32 reg, u32 val)
223 {
224 unsigned long flags;
225
226 val &= 0xff;
227 channel->framer_regs[reg] = val;
228
229 spin_lock_irqsave(&channel->card->bootrom_lock, flags);
230
231 bootrom_write(channel, cpld_reg_map[SBE_2T3E3_CPLD_REG_FRAMER_BASE_ADDRESS]
232 [channel->h.slot] + (t3e3_framer_reg_map[reg] << 2), val);
233
234 spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
235 }
236
237
238 /****************************************
239 * Access to LIU
240 ****************************************/
241
exar7300_read(struct channel * channel,u32 reg)242 u32 exar7300_read(struct channel *channel, u32 reg)
243 {
244 unsigned long addr = channel->card->bootrom_addr, flags;
245 u32 i, val;
246
247 #if 0
248 switch (reg) {
249 case SBE_2T3E3_LIU_REG_REG1:
250 case SBE_2T3E3_LIU_REG_REG2:
251 case SBE_2T3E3_LIU_REG_REG3:
252 case SBE_2T3E3_LIU_REG_REG4:
253 return channel->liu_regs[reg];
254 break;
255 default:
256 }
257 #endif
258
259 /* select correct Serial Chip */
260
261 spin_lock_irqsave(&channel->card->bootrom_lock, flags);
262
263 cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
264 cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_SELECT][channel->h.slot]);
265
266 /* select reading from Serial I/O Bus */
267 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
268 SBE_2T3E3_21143_VAL_READ_OPERATION |
269 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
270 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
271
272 /* select read operation */
273 serialrom_write_bit(channel, 1);
274
275 /* Exar7300 register address is 4 bit long */
276 reg = t3e3_liu_reg_map[reg];
277 for (i = 0; i < 4; i++, reg >>= 1) /* 4 bits of SerialROM address */
278 serialrom_write_bit(channel, reg & 1);
279 for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM address */
280 serialrom_write_bit(channel, 0);
281
282 val = 0; /* Exar7300 register value is 5 bit long */
283 for (i = 0; i < 8; i++) /* 8 bits of SerialROM value */
284 val += (serialrom_read_bit(channel) << i);
285
286 /* Reset 21143's CSR9 */
287 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
288 SBE_2T3E3_21143_VAL_READ_OPERATION |
289 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
290 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
291 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
292
293 /* Unselect Serial Chip */
294 cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
295
296 spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
297
298 return val;
299 }
300
exar7300_write(struct channel * channel,u32 reg,u32 val)301 void exar7300_write(struct channel *channel, u32 reg, u32 val)
302 {
303 unsigned long addr = channel->card->bootrom_addr, flags;
304 u32 i;
305
306 channel->liu_regs[reg] = val;
307
308 /* select correct Serial Chip */
309
310 spin_lock_irqsave(&channel->card->bootrom_lock, flags);
311
312 cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
313 cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_SELECT][channel->h.slot]);
314
315 /* select writting to Serial I/O Bus */
316 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
317 SBE_2T3E3_21143_VAL_WRITE_OPERATION |
318 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
319 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
320
321 /* select write operation */
322 serialrom_write_bit(channel, 0);
323
324 /* Exar7300 register address is 4 bit long */
325 reg = t3e3_liu_reg_map[reg];
326 for (i = 0; i < 4; i++) { /* 4 bits */
327 serialrom_write_bit(channel, reg & 1);
328 reg >>= 1;
329 }
330 for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM address */
331 serialrom_write_bit(channel, 0);
332
333 /* Exar7300 register value is 5 bit long */
334 for (i = 0; i < 5; i++) {
335 serialrom_write_bit(channel, val & 1);
336 val >>= 1;
337 }
338 for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM value */
339 serialrom_write_bit(channel, 0);
340
341 /* Reset 21143_CSR9 */
342 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
343 SBE_2T3E3_21143_VAL_WRITE_OPERATION |
344 SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
345 SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
346 dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
347
348 /* Unselect Serial Chip */
349 cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
350
351 spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
352 }
353