1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2021 Broadcom Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/timekeeping.h>
16 #include <linux/ptp_classify.h>
17 #include <linux/clocksource.h>
18 #include "bnxt_hsi.h"
19 #include "bnxt.h"
20 #include "bnxt_hwrm.h"
21 #include "bnxt_ptp.h"
22
bnxt_ptp_cfg_settime(struct bnxt * bp,u64 time)23 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time)
24 {
25 struct hwrm_func_ptp_cfg_input *req;
26 int rc;
27
28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
29 if (rc)
30 return rc;
31
32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME);
33 req->ptp_set_time = cpu_to_le64(time);
34 return hwrm_req_send(bp, req);
35 }
36
bnxt_ptp_parse(struct sk_buff * skb,u16 * seq_id,u16 * hdr_off)37 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
38 {
39 unsigned int ptp_class;
40 struct ptp_header *hdr;
41
42 ptp_class = ptp_classify_raw(skb);
43
44 switch (ptp_class & PTP_CLASS_VMASK) {
45 case PTP_CLASS_V1:
46 case PTP_CLASS_V2:
47 hdr = ptp_parse_header(skb, ptp_class);
48 if (!hdr)
49 return -EINVAL;
50
51 *hdr_off = (u8 *)hdr - skb->data;
52 *seq_id = ntohs(hdr->sequence_id);
53 return 0;
54 default:
55 return -ERANGE;
56 }
57 }
58
bnxt_ptp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)59 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
60 const struct timespec64 *ts)
61 {
62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
63 ptp_info);
64 u64 ns = timespec64_to_ns(ts);
65
66 if (BNXT_PTP_USE_RTC(ptp->bp))
67 return bnxt_ptp_cfg_settime(ptp->bp, ns);
68
69 spin_lock_bh(&ptp->ptp_lock);
70 timecounter_init(&ptp->tc, &ptp->cc, ns);
71 spin_unlock_bh(&ptp->ptp_lock);
72 return 0;
73 }
74
75 /* Caller holds ptp_lock */
bnxt_refclk_read(struct bnxt * bp,struct ptp_system_timestamp * sts,u64 * ns)76 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
77 u64 *ns)
78 {
79 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
80 u32 high_before, high_now, low;
81
82 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
83 return -EIO;
84
85 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
86 ptp_read_system_prets(sts);
87 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
88 ptp_read_system_postts(sts);
89 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
90 if (high_now != high_before) {
91 ptp_read_system_prets(sts);
92 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
93 ptp_read_system_postts(sts);
94 }
95 *ns = ((u64)high_now << 32) | low;
96
97 return 0;
98 }
99
bnxt_ptp_get_current_time(struct bnxt * bp)100 static void bnxt_ptp_get_current_time(struct bnxt *bp)
101 {
102 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
103
104 if (!ptp)
105 return;
106 spin_lock_bh(&ptp->ptp_lock);
107 WRITE_ONCE(ptp->old_time, ptp->current_time);
108 bnxt_refclk_read(bp, NULL, &ptp->current_time);
109 spin_unlock_bh(&ptp->ptp_lock);
110 }
111
bnxt_hwrm_port_ts_query(struct bnxt * bp,u32 flags,u64 * ts)112 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)
113 {
114 struct hwrm_port_ts_query_output *resp;
115 struct hwrm_port_ts_query_input *req;
116 int rc;
117
118 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
119 if (rc)
120 return rc;
121
122 req->flags = cpu_to_le32(flags);
123 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
124 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
125 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
126 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid);
127 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off);
128 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT);
129 }
130 resp = hwrm_req_hold(bp, req);
131
132 rc = hwrm_req_send(bp, req);
133 if (!rc)
134 *ts = le64_to_cpu(resp->ptp_msg_ts);
135 hwrm_req_drop(bp, req);
136 return rc;
137 }
138
bnxt_ptp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)139 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
140 struct timespec64 *ts,
141 struct ptp_system_timestamp *sts)
142 {
143 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
144 ptp_info);
145 u64 ns, cycles;
146 int rc;
147
148 spin_lock_bh(&ptp->ptp_lock);
149 rc = bnxt_refclk_read(ptp->bp, sts, &cycles);
150 if (rc) {
151 spin_unlock_bh(&ptp->ptp_lock);
152 return rc;
153 }
154 ns = timecounter_cyc2time(&ptp->tc, cycles);
155 spin_unlock_bh(&ptp->ptp_lock);
156 *ts = ns_to_timespec64(ns);
157
158 return 0;
159 }
160
161 /* Caller holds ptp_lock */
bnxt_ptp_update_current_time(struct bnxt * bp)162 void bnxt_ptp_update_current_time(struct bnxt *bp)
163 {
164 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
165
166 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time);
167 WRITE_ONCE(ptp->old_time, ptp->current_time);
168 }
169
bnxt_ptp_adjphc(struct bnxt_ptp_cfg * ptp,s64 delta)170 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta)
171 {
172 struct hwrm_port_mac_cfg_input *req;
173 int rc;
174
175 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG);
176 if (rc)
177 return rc;
178
179 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE);
180 req->ptp_adj_phase = cpu_to_le64(delta);
181
182 rc = hwrm_req_send(ptp->bp, req);
183 if (rc) {
184 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc);
185 } else {
186 spin_lock_bh(&ptp->ptp_lock);
187 bnxt_ptp_update_current_time(ptp->bp);
188 spin_unlock_bh(&ptp->ptp_lock);
189 }
190
191 return rc;
192 }
193
bnxt_ptp_adjtime(struct ptp_clock_info * ptp_info,s64 delta)194 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
195 {
196 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
197 ptp_info);
198
199 if (BNXT_PTP_USE_RTC(ptp->bp))
200 return bnxt_ptp_adjphc(ptp, delta);
201
202 spin_lock_bh(&ptp->ptp_lock);
203 timecounter_adjtime(&ptp->tc, delta);
204 spin_unlock_bh(&ptp->ptp_lock);
205 return 0;
206 }
207
bnxt_ptp_adjfine_rtc(struct bnxt * bp,long scaled_ppm)208 static int bnxt_ptp_adjfine_rtc(struct bnxt *bp, long scaled_ppm)
209 {
210 s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
211 struct hwrm_port_mac_cfg_input *req;
212 int rc;
213
214 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
215 if (rc)
216 return rc;
217
218 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
219 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
220 rc = hwrm_req_send(bp, req);
221 if (rc)
222 netdev_err(bp->dev,
223 "ptp adjfine failed. rc = %d\n", rc);
224 return rc;
225 }
226
bnxt_ptp_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)227 static int bnxt_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
228 {
229 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
230 ptp_info);
231 struct bnxt *bp = ptp->bp;
232
233 if (!BNXT_MH(bp))
234 return bnxt_ptp_adjfine_rtc(bp, scaled_ppm);
235
236 spin_lock_bh(&ptp->ptp_lock);
237 timecounter_read(&ptp->tc);
238 ptp->cc.mult = adjust_by_scaled_ppm(ptp->cmult, scaled_ppm);
239 spin_unlock_bh(&ptp->ptp_lock);
240 return 0;
241 }
242
bnxt_ptp_pps_event(struct bnxt * bp,u32 data1,u32 data2)243 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
244 {
245 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
246 struct ptp_clock_event event;
247 u64 ns, pps_ts;
248
249 pps_ts = EVENT_PPS_TS(data2, data1);
250 spin_lock_bh(&ptp->ptp_lock);
251 ns = timecounter_cyc2time(&ptp->tc, pps_ts);
252 spin_unlock_bh(&ptp->ptp_lock);
253
254 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
255 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
256 event.pps_times.ts_real = ns_to_timespec64(ns);
257 event.type = PTP_CLOCK_PPSUSR;
258 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
259 break;
260 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
261 event.timestamp = ns;
262 event.type = PTP_CLOCK_EXTTS;
263 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
264 break;
265 }
266
267 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
268 }
269
bnxt_ptp_cfg_pin(struct bnxt * bp,u8 pin,u8 usage)270 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
271 {
272 struct hwrm_func_ptp_pin_cfg_input *req;
273 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
274 u8 state = usage != BNXT_PPS_PIN_NONE;
275 u8 *pin_state, *pin_usg;
276 u32 enables;
277 int rc;
278
279 if (!TSIO_PIN_VALID(pin)) {
280 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
281 return -EOPNOTSUPP;
282 }
283
284 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
285 if (rc)
286 return rc;
287
288 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
289 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
290 req->enables = cpu_to_le32(enables);
291
292 pin_state = &req->pin0_state;
293 pin_usg = &req->pin0_usage;
294
295 *(pin_state + (pin * 2)) = state;
296 *(pin_usg + (pin * 2)) = usage;
297
298 rc = hwrm_req_send(ptp->bp, req);
299 if (rc)
300 return rc;
301
302 ptp->pps_info.pins[pin].usage = usage;
303 ptp->pps_info.pins[pin].state = state;
304
305 return 0;
306 }
307
bnxt_ptp_cfg_event(struct bnxt * bp,u8 event)308 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
309 {
310 struct hwrm_func_ptp_cfg_input *req;
311 int rc;
312
313 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
314 if (rc)
315 return rc;
316
317 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
318 req->ptp_pps_event = event;
319 return hwrm_req_send(bp, req);
320 }
321
bnxt_ptp_cfg_tstamp_filters(struct bnxt * bp)322 void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)
323 {
324 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
325 struct hwrm_port_mac_cfg_input *req;
326
327 if (!ptp || !ptp->tstamp_filters)
328 return;
329
330 if (hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG))
331 goto out;
332
333 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters &
334 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
335 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) {
336 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
337 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE);
338 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n");
339 }
340
341 req->flags = cpu_to_le32(ptp->tstamp_filters);
342 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
343 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
344
345 if (!hwrm_req_send(bp, req)) {
346 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters &
347 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE);
348 return;
349 }
350 ptp->tstamp_filters = 0;
351 out:
352 bp->ptp_all_rx_tstamp = 0;
353 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n");
354 }
355
bnxt_ptp_reapply_pps(struct bnxt * bp)356 void bnxt_ptp_reapply_pps(struct bnxt *bp)
357 {
358 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
359 struct bnxt_pps *pps;
360 u32 pin = 0;
361 int rc;
362
363 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
364 !(ptp->ptp_info.pin_config))
365 return;
366 pps = &ptp->pps_info;
367 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
368 if (pps->pins[pin].state) {
369 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
370 if (!rc && pps->pins[pin].event)
371 rc = bnxt_ptp_cfg_event(bp,
372 pps->pins[pin].event);
373 if (rc)
374 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
375 pin);
376 }
377 }
378 }
379
bnxt_get_target_cycles(struct bnxt_ptp_cfg * ptp,u64 target_ns,u64 * cycles_delta)380 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
381 u64 *cycles_delta)
382 {
383 u64 cycles_now;
384 u64 nsec_now, nsec_delta;
385 int rc;
386
387 spin_lock_bh(&ptp->ptp_lock);
388 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
389 if (rc) {
390 spin_unlock_bh(&ptp->ptp_lock);
391 return rc;
392 }
393 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now);
394 spin_unlock_bh(&ptp->ptp_lock);
395
396 nsec_delta = target_ns - nsec_now;
397 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
398 return 0;
399 }
400
bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg * ptp,struct ptp_clock_request * rq)401 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
402 struct ptp_clock_request *rq)
403 {
404 struct hwrm_func_ptp_cfg_input *req;
405 struct bnxt *bp = ptp->bp;
406 struct timespec64 ts;
407 u64 target_ns, delta;
408 u16 enables;
409 int rc;
410
411 ts.tv_sec = rq->perout.start.sec;
412 ts.tv_nsec = rq->perout.start.nsec;
413 target_ns = timespec64_to_ns(&ts);
414
415 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
416 if (rc)
417 return rc;
418
419 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
420 if (rc)
421 return rc;
422
423 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
424 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
425 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
426 req->enables = cpu_to_le16(enables);
427 req->ptp_pps_event = 0;
428 req->ptp_freq_adj_dll_source = 0;
429 req->ptp_freq_adj_dll_phase = 0;
430 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
431 req->ptp_freq_adj_ext_up = 0;
432 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
433
434 return hwrm_req_send(bp, req);
435 }
436
bnxt_ptp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)437 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
438 struct ptp_clock_request *rq, int on)
439 {
440 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
441 ptp_info);
442 struct bnxt *bp = ptp->bp;
443 int pin_id;
444 int rc;
445
446 switch (rq->type) {
447 case PTP_CLK_REQ_EXTTS:
448 /* Configure an External PPS IN */
449 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
450 rq->extts.index);
451 if (!TSIO_PIN_VALID(pin_id))
452 return -EOPNOTSUPP;
453 if (!on)
454 break;
455 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
456 if (rc)
457 return rc;
458 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
459 if (!rc)
460 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
461 return rc;
462 case PTP_CLK_REQ_PEROUT:
463 /* Configure a Periodic PPS OUT */
464 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
465 rq->perout.index);
466 if (!TSIO_PIN_VALID(pin_id))
467 return -EOPNOTSUPP;
468 if (!on)
469 break;
470
471 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
472 if (!rc)
473 rc = bnxt_ptp_perout_cfg(ptp, rq);
474
475 return rc;
476 case PTP_CLK_REQ_PPS:
477 /* Configure PHC PPS IN */
478 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
479 if (rc)
480 return rc;
481 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
482 if (!rc)
483 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
484 return rc;
485 default:
486 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
487 return -EOPNOTSUPP;
488 }
489
490 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
491 }
492
bnxt_hwrm_ptp_cfg(struct bnxt * bp)493 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
494 {
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
496 u32 flags = 0;
497 int rc = 0;
498
499 switch (ptp->rx_filter) {
500 case HWTSTAMP_FILTER_ALL:
501 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
502 break;
503 case HWTSTAMP_FILTER_NONE:
504 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
505 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
506 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
507 break;
508 case HWTSTAMP_FILTER_PTP_V2_EVENT:
509 case HWTSTAMP_FILTER_PTP_V2_SYNC:
510 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
511 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
512 break;
513 }
514
515 if (ptp->tx_tstamp_en)
516 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
517 else
518 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
519
520 ptp->tstamp_filters = flags;
521
522 if (netif_running(bp->dev)) {
523 if (ptp->rx_filter == HWTSTAMP_FILTER_ALL) {
524 bnxt_close_nic(bp, false, false);
525 rc = bnxt_open_nic(bp, false, false);
526 } else {
527 bnxt_ptp_cfg_tstamp_filters(bp);
528 }
529 if (!rc && !ptp->tstamp_filters)
530 rc = -EIO;
531 }
532
533 return rc;
534 }
535
bnxt_hwtstamp_set(struct net_device * dev,struct ifreq * ifr)536 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
537 {
538 struct bnxt *bp = netdev_priv(dev);
539 struct hwtstamp_config stmpconf;
540 struct bnxt_ptp_cfg *ptp;
541 u16 old_rxctl;
542 int old_rx_filter, rc;
543 u8 old_tx_tstamp_en;
544
545 ptp = bp->ptp_cfg;
546 if (!ptp)
547 return -EOPNOTSUPP;
548
549 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
550 return -EFAULT;
551
552 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
553 stmpconf.tx_type != HWTSTAMP_TX_OFF)
554 return -ERANGE;
555
556 old_rx_filter = ptp->rx_filter;
557 old_rxctl = ptp->rxctl;
558 old_tx_tstamp_en = ptp->tx_tstamp_en;
559 switch (stmpconf.rx_filter) {
560 case HWTSTAMP_FILTER_NONE:
561 ptp->rxctl = 0;
562 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
563 break;
564 case HWTSTAMP_FILTER_ALL:
565 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) {
566 ptp->rx_filter = HWTSTAMP_FILTER_ALL;
567 break;
568 }
569 return -EOPNOTSUPP;
570 case HWTSTAMP_FILTER_PTP_V2_EVENT:
571 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
572 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
573 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
574 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
575 break;
576 case HWTSTAMP_FILTER_PTP_V2_SYNC:
577 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
578 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
579 ptp->rxctl = BNXT_PTP_MSG_SYNC;
580 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
581 break;
582 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
583 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
584 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
585 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
586 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
587 break;
588 default:
589 return -ERANGE;
590 }
591
592 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
593 ptp->tx_tstamp_en = 1;
594 else
595 ptp->tx_tstamp_en = 0;
596
597 rc = bnxt_hwrm_ptp_cfg(bp);
598 if (rc)
599 goto ts_set_err;
600
601 stmpconf.rx_filter = ptp->rx_filter;
602 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
603 -EFAULT : 0;
604
605 ts_set_err:
606 ptp->rx_filter = old_rx_filter;
607 ptp->rxctl = old_rxctl;
608 ptp->tx_tstamp_en = old_tx_tstamp_en;
609 return rc;
610 }
611
bnxt_hwtstamp_get(struct net_device * dev,struct ifreq * ifr)612 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
613 {
614 struct bnxt *bp = netdev_priv(dev);
615 struct hwtstamp_config stmpconf;
616 struct bnxt_ptp_cfg *ptp;
617
618 ptp = bp->ptp_cfg;
619 if (!ptp)
620 return -EOPNOTSUPP;
621
622 stmpconf.flags = 0;
623 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
624
625 stmpconf.rx_filter = ptp->rx_filter;
626 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
627 -EFAULT : 0;
628 }
629
bnxt_map_regs(struct bnxt * bp,u32 * reg_arr,int count,int reg_win)630 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
631 {
632 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
633 u32 win_off;
634 int i;
635
636 for (i = 0; i < count; i++) {
637 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
638 return -ERANGE;
639 }
640 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
641 writel(reg_base, bp->bar0 + win_off);
642 return 0;
643 }
644
bnxt_map_ptp_regs(struct bnxt * bp)645 static int bnxt_map_ptp_regs(struct bnxt *bp)
646 {
647 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
648 u32 *reg_arr;
649 int rc, i;
650
651 reg_arr = ptp->refclk_regs;
652 if (bp->flags & BNXT_FLAG_CHIP_P5) {
653 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
654 if (rc)
655 return rc;
656 for (i = 0; i < 2; i++)
657 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
658 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
659 return 0;
660 }
661 return -ENODEV;
662 }
663
bnxt_unmap_ptp_regs(struct bnxt * bp)664 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
665 {
666 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
667 (BNXT_PTP_GRC_WIN - 1) * 4);
668 }
669
bnxt_cc_read(const struct cyclecounter * cc)670 static u64 bnxt_cc_read(const struct cyclecounter *cc)
671 {
672 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
673 u64 ns = 0;
674
675 bnxt_refclk_read(ptp->bp, NULL, &ns);
676 return ns;
677 }
678
bnxt_stamp_tx_skb(struct bnxt * bp,struct sk_buff * skb)679 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)
680 {
681 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
682 struct skb_shared_hwtstamps timestamp;
683 u64 ts = 0, ns = 0;
684 int rc;
685
686 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts);
687 if (!rc) {
688 memset(×tamp, 0, sizeof(timestamp));
689 spin_lock_bh(&ptp->ptp_lock);
690 ns = timecounter_cyc2time(&ptp->tc, ts);
691 spin_unlock_bh(&ptp->ptp_lock);
692 timestamp.hwtstamp = ns_to_ktime(ns);
693 skb_tstamp_tx(ptp->tx_skb, ×tamp);
694 } else {
695 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n",
696 rc);
697 }
698
699 dev_kfree_skb_any(ptp->tx_skb);
700 ptp->tx_skb = NULL;
701 atomic_inc(&ptp->tx_avail);
702 }
703
bnxt_ptp_ts_aux_work(struct ptp_clock_info * ptp_info)704 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
705 {
706 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
707 ptp_info);
708 unsigned long now = jiffies;
709 struct bnxt *bp = ptp->bp;
710
711 if (ptp->tx_skb)
712 bnxt_stamp_tx_skb(bp, ptp->tx_skb);
713
714 if (!time_after_eq(now, ptp->next_period))
715 return ptp->next_period - now;
716
717 bnxt_ptp_get_current_time(bp);
718 ptp->next_period = now + HZ;
719 if (time_after_eq(now, ptp->next_overflow_check)) {
720 spin_lock_bh(&ptp->ptp_lock);
721 timecounter_read(&ptp->tc);
722 spin_unlock_bh(&ptp->ptp_lock);
723 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
724 }
725 return HZ;
726 }
727
bnxt_get_tx_ts_p5(struct bnxt * bp,struct sk_buff * skb)728 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb)
729 {
730 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
731
732 if (ptp->tx_skb) {
733 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n");
734 return -EBUSY;
735 }
736 ptp->tx_skb = skb;
737 ptp_schedule_worker(ptp->ptp_clock, 0);
738 return 0;
739 }
740
bnxt_get_rx_ts_p5(struct bnxt * bp,u64 * ts,u32 pkt_ts)741 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
742 {
743 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
744 u64 time;
745
746 if (!ptp)
747 return -ENODEV;
748
749 BNXT_READ_TIME64(ptp, time, ptp->old_time);
750 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
751 if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
752 *ts += BNXT_LO_TIMER_MASK + 1;
753
754 return 0;
755 }
756
757 static const struct ptp_clock_info bnxt_ptp_caps = {
758 .owner = THIS_MODULE,
759 .name = "bnxt clock",
760 .max_adj = BNXT_MAX_PHC_DRIFT,
761 .n_alarm = 0,
762 .n_ext_ts = 0,
763 .n_per_out = 0,
764 .n_pins = 0,
765 .pps = 0,
766 .adjfine = bnxt_ptp_adjfine,
767 .adjtime = bnxt_ptp_adjtime,
768 .do_aux_work = bnxt_ptp_ts_aux_work,
769 .gettimex64 = bnxt_ptp_gettimex,
770 .settime64 = bnxt_ptp_settime,
771 .enable = bnxt_ptp_enable,
772 };
773
bnxt_ptp_verify(struct ptp_clock_info * ptp_info,unsigned int pin,enum ptp_pin_function func,unsigned int chan)774 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
775 enum ptp_pin_function func, unsigned int chan)
776 {
777 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
778 ptp_info);
779 /* Allow only PPS pin function configuration */
780 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
781 func != PTP_PF_PHYSYNC)
782 return 0;
783 else
784 return -EOPNOTSUPP;
785 }
786
bnxt_ptp_pps_init(struct bnxt * bp)787 static int bnxt_ptp_pps_init(struct bnxt *bp)
788 {
789 struct hwrm_func_ptp_pin_qcfg_output *resp;
790 struct hwrm_func_ptp_pin_qcfg_input *req;
791 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
792 struct ptp_clock_info *ptp_info;
793 struct bnxt_pps *pps_info;
794 u8 *pin_usg;
795 u32 i, rc;
796
797 /* Query current/default PIN CFG */
798 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
799 if (rc)
800 return rc;
801
802 resp = hwrm_req_hold(bp, req);
803 rc = hwrm_req_send(bp, req);
804 if (rc || !resp->num_pins) {
805 hwrm_req_drop(bp, req);
806 return -EOPNOTSUPP;
807 }
808
809 ptp_info = &ptp->ptp_info;
810 pps_info = &ptp->pps_info;
811 pps_info->num_pins = resp->num_pins;
812 ptp_info->n_pins = pps_info->num_pins;
813 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
814 sizeof(*ptp_info->pin_config),
815 GFP_KERNEL);
816 if (!ptp_info->pin_config) {
817 hwrm_req_drop(bp, req);
818 return -ENOMEM;
819 }
820
821 /* Report the TSIO capability to kernel */
822 pin_usg = &resp->pin0_usage;
823 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
824 snprintf(ptp_info->pin_config[i].name,
825 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
826 ptp_info->pin_config[i].index = i;
827 ptp_info->pin_config[i].chan = i;
828 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
829 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
830 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
831 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
832 else
833 ptp_info->pin_config[i].func = PTP_PF_NONE;
834
835 pps_info->pins[i].usage = *pin_usg;
836 }
837 hwrm_req_drop(bp, req);
838
839 /* Only 1 each of ext_ts and per_out pins is available in HW */
840 ptp_info->n_ext_ts = 1;
841 ptp_info->n_per_out = 1;
842 ptp_info->pps = 1;
843 ptp_info->verify = bnxt_ptp_verify;
844
845 return 0;
846 }
847
bnxt_pps_config_ok(struct bnxt * bp)848 static bool bnxt_pps_config_ok(struct bnxt *bp)
849 {
850 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
851
852 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
853 }
854
bnxt_ptp_timecounter_init(struct bnxt * bp,bool init_tc)855 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc)
856 {
857 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
858
859 if (!ptp->ptp_clock) {
860 memset(&ptp->cc, 0, sizeof(ptp->cc));
861 ptp->cc.read = bnxt_cc_read;
862 ptp->cc.mask = CYCLECOUNTER_MASK(48);
863 if (BNXT_MH(bp)) {
864 /* Use timecounter based non-real time mode */
865 ptp->cc.shift = BNXT_CYCLES_SHIFT;
866 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift);
867 ptp->cmult = ptp->cc.mult;
868 } else {
869 ptp->cc.shift = 0;
870 ptp->cc.mult = 1;
871 }
872 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
873 }
874 if (init_tc)
875 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
876 }
877
878 /* Caller holds ptp_lock */
bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg * ptp,u64 ns)879 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns)
880 {
881 timecounter_init(&ptp->tc, &ptp->cc, ns);
882 /* For RTC, cycle_last must be in sync with the timecounter value. */
883 ptp->tc.cycle_last = ns & ptp->cc.mask;
884 }
885
bnxt_ptp_init_rtc(struct bnxt * bp,bool phc_cfg)886 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg)
887 {
888 struct timespec64 tsp;
889 u64 ns;
890 int rc;
891
892 if (!bp->ptp_cfg || !BNXT_PTP_USE_RTC(bp))
893 return -ENODEV;
894
895 if (!phc_cfg) {
896 ktime_get_real_ts64(&tsp);
897 ns = timespec64_to_ns(&tsp);
898 rc = bnxt_ptp_cfg_settime(bp, ns);
899 if (rc)
900 return rc;
901 } else {
902 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, &ns);
903 if (rc)
904 return rc;
905 }
906 spin_lock_bh(&bp->ptp_cfg->ptp_lock);
907 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns);
908 spin_unlock_bh(&bp->ptp_cfg->ptp_lock);
909
910 return 0;
911 }
912
bnxt_ptp_free(struct bnxt * bp)913 static void bnxt_ptp_free(struct bnxt *bp)
914 {
915 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
916
917 if (ptp->ptp_clock) {
918 ptp_clock_unregister(ptp->ptp_clock);
919 ptp->ptp_clock = NULL;
920 kfree(ptp->ptp_info.pin_config);
921 ptp->ptp_info.pin_config = NULL;
922 }
923 }
924
bnxt_ptp_init(struct bnxt * bp,bool phc_cfg)925 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg)
926 {
927 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
928 int rc;
929
930 if (!ptp)
931 return 0;
932
933 rc = bnxt_map_ptp_regs(bp);
934 if (rc)
935 return rc;
936
937 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
938 return 0;
939
940 bnxt_ptp_free(bp);
941
942 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
943 spin_lock_init(&ptp->ptp_lock);
944
945 if (BNXT_PTP_USE_RTC(bp)) {
946 bnxt_ptp_timecounter_init(bp, false);
947 rc = bnxt_ptp_init_rtc(bp, phc_cfg);
948 if (rc)
949 goto out;
950 } else {
951 bnxt_ptp_timecounter_init(bp, true);
952 bnxt_ptp_adjfine_rtc(bp, 0);
953 }
954 bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, true);
955
956 ptp->ptp_info = bnxt_ptp_caps;
957 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
958 if (bnxt_ptp_pps_init(bp))
959 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
960 }
961 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
962 if (IS_ERR(ptp->ptp_clock)) {
963 int err = PTR_ERR(ptp->ptp_clock);
964
965 ptp->ptp_clock = NULL;
966 rc = err;
967 goto out;
968 }
969 if (bp->flags & BNXT_FLAG_CHIP_P5) {
970 spin_lock_bh(&ptp->ptp_lock);
971 bnxt_refclk_read(bp, NULL, &ptp->current_time);
972 WRITE_ONCE(ptp->old_time, ptp->current_time);
973 spin_unlock_bh(&ptp->ptp_lock);
974 ptp_schedule_worker(ptp->ptp_clock, 0);
975 }
976 return 0;
977
978 out:
979 bnxt_ptp_free(bp);
980 bnxt_unmap_ptp_regs(bp);
981 return rc;
982 }
983
bnxt_ptp_clear(struct bnxt * bp)984 void bnxt_ptp_clear(struct bnxt *bp)
985 {
986 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
987
988 if (!ptp)
989 return;
990
991 if (ptp->ptp_clock)
992 ptp_clock_unregister(ptp->ptp_clock);
993
994 ptp->ptp_clock = NULL;
995 kfree(ptp->ptp_info.pin_config);
996 ptp->ptp_info.pin_config = NULL;
997
998 if (ptp->tx_skb) {
999 dev_kfree_skb_any(ptp->tx_skb);
1000 ptp->tx_skb = NULL;
1001 }
1002 bnxt_unmap_ptp_regs(bp);
1003 }
1004