1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/arm/coresight-cti-dt.h>
7#include <dt-bindings/clock/qcom,gcc-msm8916.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/interconnect/qcom,msm8916.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/power/qcom-rpmpd.h>
12#include <dt-bindings/reset/qcom,gcc-msm8916.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&intc>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		mmc0 = &sdhc_1; /* SDC1 eMMC slot */
23		mmc1 = &sdhc_2; /* SDC2 SD card slot */
24	};
25
26	chosen { };
27
28	memory@80000000 {
29		device_type = "memory";
30		/* We expect the bootloader to fill in the reg */
31		reg = <0 0x80000000 0 0>;
32	};
33
34	reserved-memory {
35		#address-cells = <2>;
36		#size-cells = <2>;
37		ranges;
38
39		tz-apps@86000000 {
40			reg = <0x0 0x86000000 0x0 0x300000>;
41			no-map;
42		};
43
44		smem@86300000 {
45			compatible = "qcom,smem";
46			reg = <0x0 0x86300000 0x0 0x100000>;
47			no-map;
48
49			hwlocks = <&tcsr_mutex 3>;
50			qcom,rpm-msg-ram = <&rpm_msg_ram>;
51		};
52
53		hypervisor@86400000 {
54			reg = <0x0 0x86400000 0x0 0x100000>;
55			no-map;
56		};
57
58		tz@86500000 {
59			reg = <0x0 0x86500000 0x0 0x180000>;
60			no-map;
61		};
62
63		reserved@86680000 {
64			reg = <0x0 0x86680000 0x0 0x80000>;
65			no-map;
66		};
67
68		rmtfs@86700000 {
69			compatible = "qcom,rmtfs-mem";
70			reg = <0x0 0x86700000 0x0 0xe0000>;
71			no-map;
72
73			qcom,client-id = <1>;
74		};
75
76		rfsa@867e0000 {
77			reg = <0x0 0x867e0000 0x0 0x20000>;
78			no-map;
79		};
80
81		mpss_mem: mpss@86800000 {
82			reg = <0x0 0x86800000 0x0 0x2b00000>;
83			no-map;
84		};
85
86		wcnss_mem: wcnss@89300000 {
87			reg = <0x0 0x89300000 0x0 0x600000>;
88			no-map;
89		};
90
91		venus_mem: venus@89900000 {
92			reg = <0x0 0x89900000 0x0 0x600000>;
93			no-map;
94		};
95
96		mba_mem: mba@8ea00000 {
97			no-map;
98			reg = <0 0x8ea00000 0 0x100000>;
99		};
100	};
101
102	clocks {
103		xo_board: xo-board {
104			compatible = "fixed-clock";
105			#clock-cells = <0>;
106			clock-frequency = <19200000>;
107		};
108
109		sleep_clk: sleep-clk {
110			compatible = "fixed-clock";
111			#clock-cells = <0>;
112			clock-frequency = <32768>;
113		};
114	};
115
116	cpus {
117		#address-cells = <1>;
118		#size-cells = <0>;
119
120		CPU0: cpu@0 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a53";
123			reg = <0x0>;
124			next-level-cache = <&L2_0>;
125			enable-method = "psci";
126			clocks = <&apcs>;
127			operating-points-v2 = <&cpu_opp_table>;
128			#cooling-cells = <2>;
129			power-domains = <&CPU_PD0>;
130			power-domain-names = "psci";
131			qcom,acc = <&cpu0_acc>;
132			qcom,saw = <&cpu0_saw>;
133		};
134
135		CPU1: cpu@1 {
136			device_type = "cpu";
137			compatible = "arm,cortex-a53";
138			reg = <0x1>;
139			next-level-cache = <&L2_0>;
140			enable-method = "psci";
141			clocks = <&apcs>;
142			operating-points-v2 = <&cpu_opp_table>;
143			#cooling-cells = <2>;
144			power-domains = <&CPU_PD1>;
145			power-domain-names = "psci";
146			qcom,acc = <&cpu1_acc>;
147			qcom,saw = <&cpu1_saw>;
148		};
149
150		CPU2: cpu@2 {
151			device_type = "cpu";
152			compatible = "arm,cortex-a53";
153			reg = <0x2>;
154			next-level-cache = <&L2_0>;
155			enable-method = "psci";
156			clocks = <&apcs>;
157			operating-points-v2 = <&cpu_opp_table>;
158			#cooling-cells = <2>;
159			power-domains = <&CPU_PD2>;
160			power-domain-names = "psci";
161			qcom,acc = <&cpu2_acc>;
162			qcom,saw = <&cpu2_saw>;
163		};
164
165		CPU3: cpu@3 {
166			device_type = "cpu";
167			compatible = "arm,cortex-a53";
168			reg = <0x3>;
169			next-level-cache = <&L2_0>;
170			enable-method = "psci";
171			clocks = <&apcs>;
172			operating-points-v2 = <&cpu_opp_table>;
173			#cooling-cells = <2>;
174			power-domains = <&CPU_PD3>;
175			power-domain-names = "psci";
176			qcom,acc = <&cpu3_acc>;
177			qcom,saw = <&cpu3_saw>;
178		};
179
180		L2_0: l2-cache {
181			compatible = "cache";
182			cache-level = <2>;
183		};
184
185		idle-states {
186			entry-method = "psci";
187
188			CPU_SLEEP_0: cpu-sleep-0 {
189				compatible = "arm,idle-state";
190				idle-state-name = "standalone-power-collapse";
191				arm,psci-suspend-param = <0x40000002>;
192				entry-latency-us = <130>;
193				exit-latency-us = <150>;
194				min-residency-us = <2000>;
195				local-timer-stop;
196			};
197		};
198
199		domain-idle-states {
200
201			CLUSTER_RET: cluster-retention {
202				compatible = "domain-idle-state";
203				arm,psci-suspend-param = <0x41000012>;
204				entry-latency-us = <500>;
205				exit-latency-us = <500>;
206				min-residency-us = <2000>;
207			};
208
209			CLUSTER_PWRDN: cluster-gdhs {
210				compatible = "domain-idle-state";
211				arm,psci-suspend-param = <0x41000032>;
212				entry-latency-us = <2000>;
213				exit-latency-us = <2000>;
214				min-residency-us = <6000>;
215			};
216		};
217	};
218
219	cpu_opp_table: opp-table-cpu {
220		compatible = "operating-points-v2";
221		opp-shared;
222
223		opp-200000000 {
224			opp-hz = /bits/ 64 <200000000>;
225		};
226		opp-400000000 {
227			opp-hz = /bits/ 64 <400000000>;
228		};
229		opp-800000000 {
230			opp-hz = /bits/ 64 <800000000>;
231		};
232		opp-998400000 {
233			opp-hz = /bits/ 64 <998400000>;
234		};
235	};
236
237	firmware {
238		scm: scm {
239			compatible = "qcom,scm-msm8916", "qcom,scm";
240			clocks = <&gcc GCC_CRYPTO_CLK>,
241				 <&gcc GCC_CRYPTO_AXI_CLK>,
242				 <&gcc GCC_CRYPTO_AHB_CLK>;
243			clock-names = "core", "bus", "iface";
244			#reset-cells = <1>;
245
246			qcom,dload-mode = <&tcsr 0x6100>;
247		};
248	};
249
250	pmu {
251		compatible = "arm,cortex-a53-pmu";
252		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
253	};
254
255	psci {
256		compatible = "arm,psci-1.0";
257		method = "smc";
258
259		CPU_PD0: power-domain-cpu0 {
260			#power-domain-cells = <0>;
261			power-domains = <&CLUSTER_PD>;
262			domain-idle-states = <&CPU_SLEEP_0>;
263		};
264
265		CPU_PD1: power-domain-cpu1 {
266			#power-domain-cells = <0>;
267			power-domains = <&CLUSTER_PD>;
268			domain-idle-states = <&CPU_SLEEP_0>;
269		};
270
271		CPU_PD2: power-domain-cpu2 {
272			#power-domain-cells = <0>;
273			power-domains = <&CLUSTER_PD>;
274			domain-idle-states = <&CPU_SLEEP_0>;
275		};
276
277		CPU_PD3: power-domain-cpu3 {
278			#power-domain-cells = <0>;
279			power-domains = <&CLUSTER_PD>;
280			domain-idle-states = <&CPU_SLEEP_0>;
281		};
282
283		CLUSTER_PD: power-domain-cluster {
284			#power-domain-cells = <0>;
285			domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
286		};
287	};
288
289	smd {
290		compatible = "qcom,smd";
291
292		rpm {
293			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
294			qcom,ipc = <&apcs 8 0>;
295			qcom,smd-edge = <15>;
296
297			rpm_requests: rpm-requests {
298				compatible = "qcom,rpm-msm8916";
299				qcom,smd-channels = "rpm_requests";
300
301				rpmcc: clock-controller {
302					compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
303					#clock-cells = <1>;
304					clocks = <&xo_board>;
305					clock-names = "xo";
306				};
307
308				rpmpd: power-controller {
309					compatible = "qcom,msm8916-rpmpd";
310					#power-domain-cells = <1>;
311					operating-points-v2 = <&rpmpd_opp_table>;
312
313					rpmpd_opp_table: opp-table {
314						compatible = "operating-points-v2";
315
316						rpmpd_opp_ret: opp1 {
317							opp-level = <1>;
318						};
319						rpmpd_opp_svs_krait: opp2 {
320							opp-level = <2>;
321						};
322						rpmpd_opp_svs_soc: opp3 {
323							opp-level = <3>;
324						};
325						rpmpd_opp_nom: opp4 {
326							opp-level = <4>;
327						};
328						rpmpd_opp_turbo: opp5 {
329							opp-level = <5>;
330						};
331						rpmpd_opp_super_turbo: opp6 {
332							opp-level = <6>;
333						};
334					};
335				};
336			};
337		};
338	};
339
340	smp2p-hexagon {
341		compatible = "qcom,smp2p";
342		qcom,smem = <435>, <428>;
343
344		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
345
346		qcom,ipc = <&apcs 8 14>;
347
348		qcom,local-pid = <0>;
349		qcom,remote-pid = <1>;
350
351		hexagon_smp2p_out: master-kernel {
352			qcom,entry-name = "master-kernel";
353
354			#qcom,smem-state-cells = <1>;
355		};
356
357		hexagon_smp2p_in: slave-kernel {
358			qcom,entry-name = "slave-kernel";
359
360			interrupt-controller;
361			#interrupt-cells = <2>;
362		};
363	};
364
365	smp2p-wcnss {
366		compatible = "qcom,smp2p";
367		qcom,smem = <451>, <431>;
368
369		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
370
371		qcom,ipc = <&apcs 8 18>;
372
373		qcom,local-pid = <0>;
374		qcom,remote-pid = <4>;
375
376		wcnss_smp2p_out: master-kernel {
377			qcom,entry-name = "master-kernel";
378
379			#qcom,smem-state-cells = <1>;
380		};
381
382		wcnss_smp2p_in: slave-kernel {
383			qcom,entry-name = "slave-kernel";
384
385			interrupt-controller;
386			#interrupt-cells = <2>;
387		};
388	};
389
390	smsm {
391		compatible = "qcom,smsm";
392
393		#address-cells = <1>;
394		#size-cells = <0>;
395
396		qcom,ipc-1 = <&apcs 8 13>;
397		qcom,ipc-3 = <&apcs 8 19>;
398
399		apps_smsm: apps@0 {
400			reg = <0>;
401
402			#qcom,smem-state-cells = <1>;
403		};
404
405		hexagon_smsm: hexagon@1 {
406			reg = <1>;
407			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
408
409			interrupt-controller;
410			#interrupt-cells = <2>;
411		};
412
413		wcnss_smsm: wcnss@6 {
414			reg = <6>;
415			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
416
417			interrupt-controller;
418			#interrupt-cells = <2>;
419		};
420	};
421
422	soc: soc@0 {
423		#address-cells = <1>;
424		#size-cells = <1>;
425		ranges = <0 0 0 0xffffffff>;
426		compatible = "simple-bus";
427
428		rng@22000 {
429			compatible = "qcom,prng";
430			reg = <0x00022000 0x200>;
431			clocks = <&gcc GCC_PRNG_AHB_CLK>;
432			clock-names = "core";
433		};
434
435		restart@4ab000 {
436			compatible = "qcom,pshold";
437			reg = <0x004ab000 0x4>;
438		};
439
440		qfprom: qfprom@5c000 {
441			compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
442			reg = <0x0005c000 0x1000>;
443			#address-cells = <1>;
444			#size-cells = <1>;
445			tsens_caldata: caldata@d0 {
446				reg = <0xd0 0x8>;
447			};
448			tsens_calsel: calsel@ec {
449				reg = <0xec 0x4>;
450			};
451		};
452
453		rpm_msg_ram: sram@60000 {
454			compatible = "qcom,rpm-msg-ram";
455			reg = <0x00060000 0x8000>;
456		};
457
458		sram@290000 {
459			compatible = "qcom,msm8916-rpm-stats";
460			reg = <0x00290000 0x10000>;
461		};
462
463		bimc: interconnect@400000 {
464			compatible = "qcom,msm8916-bimc";
465			reg = <0x00400000 0x62000>;
466			#interconnect-cells = <1>;
467			clock-names = "bus", "bus_a";
468			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
469				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
470		};
471
472		tsens: thermal-sensor@4a9000 {
473			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
474			reg = <0x004a9000 0x1000>, /* TM */
475			      <0x004a8000 0x1000>; /* SROT */
476			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
477			nvmem-cell-names = "calib", "calib_sel";
478			#qcom,sensors = <5>;
479			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
480			interrupt-names = "uplow";
481			#thermal-sensor-cells = <1>;
482		};
483
484		pcnoc: interconnect@500000 {
485			compatible = "qcom,msm8916-pcnoc";
486			reg = <0x00500000 0x11000>;
487			#interconnect-cells = <1>;
488			clock-names = "bus", "bus_a";
489			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
490				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
491		};
492
493		snoc: interconnect@580000 {
494			compatible = "qcom,msm8916-snoc";
495			reg = <0x00580000 0x14000>;
496			#interconnect-cells = <1>;
497			clock-names = "bus", "bus_a";
498			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
499				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
500		};
501
502		stm: stm@802000 {
503			compatible = "arm,coresight-stm", "arm,primecell";
504			reg = <0x00802000 0x1000>,
505			      <0x09280000 0x180000>;
506			reg-names = "stm-base", "stm-stimulus-base";
507
508			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
509			clock-names = "apb_pclk", "atclk";
510
511			status = "disabled";
512
513			out-ports {
514				port {
515					stm_out: endpoint {
516						remote-endpoint = <&funnel0_in7>;
517					};
518				};
519			};
520		};
521
522		/* System CTIs */
523		/* CTI 0 - TMC connections */
524		cti0: cti@810000 {
525			compatible = "arm,coresight-cti", "arm,primecell";
526			reg = <0x00810000 0x1000>;
527
528			clocks = <&rpmcc RPM_QDSS_CLK>;
529			clock-names = "apb_pclk";
530
531			status = "disabled";
532		};
533
534		/* CTI 1 - TPIU connections */
535		cti1: cti@811000 {
536			compatible = "arm,coresight-cti", "arm,primecell";
537			reg = <0x00811000 0x1000>;
538
539			clocks = <&rpmcc RPM_QDSS_CLK>;
540			clock-names = "apb_pclk";
541
542			status = "disabled";
543		};
544
545		/* CTIs 2-11 - no information - not instantiated */
546
547		tpiu: tpiu@820000 {
548			compatible = "arm,coresight-tpiu", "arm,primecell";
549			reg = <0x00820000 0x1000>;
550
551			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
552			clock-names = "apb_pclk", "atclk";
553
554			status = "disabled";
555
556			in-ports {
557				port {
558					tpiu_in: endpoint {
559						remote-endpoint = <&replicator_out1>;
560					};
561				};
562			};
563		};
564
565		funnel0: funnel@821000 {
566			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
567			reg = <0x00821000 0x1000>;
568
569			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
570			clock-names = "apb_pclk", "atclk";
571
572			status = "disabled";
573
574			in-ports {
575				#address-cells = <1>;
576				#size-cells = <0>;
577
578				/*
579				 * Not described input ports:
580				 * 0 - connected to Resource and Power Manger CPU ETM
581				 * 1 - not-connected
582				 * 2 - connected to Modem CPU ETM
583				 * 3 - not-connected
584				 * 5 - not-connected
585				 * 6 - connected trought funnel to Wireless CPU ETM
586				 * 7 - connected to STM component
587				 */
588
589				port@4 {
590					reg = <4>;
591					funnel0_in4: endpoint {
592						remote-endpoint = <&funnel1_out>;
593					};
594				};
595
596				port@7 {
597					reg = <7>;
598					funnel0_in7: endpoint {
599						remote-endpoint = <&stm_out>;
600					};
601				};
602			};
603
604			out-ports {
605				port {
606					funnel0_out: endpoint {
607						remote-endpoint = <&etf_in>;
608					};
609				};
610			};
611		};
612
613		replicator: replicator@824000 {
614			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
615			reg = <0x00824000 0x1000>;
616
617			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
618			clock-names = "apb_pclk", "atclk";
619
620			status = "disabled";
621
622			out-ports {
623				#address-cells = <1>;
624				#size-cells = <0>;
625
626				port@0 {
627					reg = <0>;
628					replicator_out0: endpoint {
629						remote-endpoint = <&etr_in>;
630					};
631				};
632				port@1 {
633					reg = <1>;
634					replicator_out1: endpoint {
635						remote-endpoint = <&tpiu_in>;
636					};
637				};
638			};
639
640			in-ports {
641				port {
642					replicator_in: endpoint {
643						remote-endpoint = <&etf_out>;
644					};
645				};
646			};
647		};
648
649		etf: etf@825000 {
650			compatible = "arm,coresight-tmc", "arm,primecell";
651			reg = <0x00825000 0x1000>;
652
653			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
654			clock-names = "apb_pclk", "atclk";
655
656			status = "disabled";
657
658			in-ports {
659				port {
660					etf_in: endpoint {
661						remote-endpoint = <&funnel0_out>;
662					};
663				};
664			};
665
666			out-ports {
667				port {
668					etf_out: endpoint {
669						remote-endpoint = <&replicator_in>;
670					};
671				};
672			};
673		};
674
675		etr: etr@826000 {
676			compatible = "arm,coresight-tmc", "arm,primecell";
677			reg = <0x00826000 0x1000>;
678
679			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
680			clock-names = "apb_pclk", "atclk";
681
682			status = "disabled";
683
684			in-ports {
685				port {
686					etr_in: endpoint {
687						remote-endpoint = <&replicator_out0>;
688					};
689				};
690			};
691		};
692
693		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
694			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
695			reg = <0x00841000 0x1000>;
696
697			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
698			clock-names = "apb_pclk", "atclk";
699
700			status = "disabled";
701
702			in-ports {
703				#address-cells = <1>;
704				#size-cells = <0>;
705
706				port@0 {
707					reg = <0>;
708					funnel1_in0: endpoint {
709						remote-endpoint = <&etm0_out>;
710					};
711				};
712				port@1 {
713					reg = <1>;
714					funnel1_in1: endpoint {
715						remote-endpoint = <&etm1_out>;
716					};
717				};
718				port@2 {
719					reg = <2>;
720					funnel1_in2: endpoint {
721						remote-endpoint = <&etm2_out>;
722					};
723				};
724				port@3 {
725					reg = <3>;
726					funnel1_in3: endpoint {
727						remote-endpoint = <&etm3_out>;
728					};
729				};
730			};
731
732			out-ports {
733				port {
734					funnel1_out: endpoint {
735						remote-endpoint = <&funnel0_in4>;
736					};
737				};
738			};
739		};
740
741		debug0: debug@850000 {
742			compatible = "arm,coresight-cpu-debug", "arm,primecell";
743			reg = <0x00850000 0x1000>;
744			clocks = <&rpmcc RPM_QDSS_CLK>;
745			clock-names = "apb_pclk";
746			cpu = <&CPU0>;
747			status = "disabled";
748		};
749
750		debug1: debug@852000 {
751			compatible = "arm,coresight-cpu-debug", "arm,primecell";
752			reg = <0x00852000 0x1000>;
753			clocks = <&rpmcc RPM_QDSS_CLK>;
754			clock-names = "apb_pclk";
755			cpu = <&CPU1>;
756			status = "disabled";
757		};
758
759		debug2: debug@854000 {
760			compatible = "arm,coresight-cpu-debug", "arm,primecell";
761			reg = <0x00854000 0x1000>;
762			clocks = <&rpmcc RPM_QDSS_CLK>;
763			clock-names = "apb_pclk";
764			cpu = <&CPU2>;
765			status = "disabled";
766		};
767
768		debug3: debug@856000 {
769			compatible = "arm,coresight-cpu-debug", "arm,primecell";
770			reg = <0x00856000 0x1000>;
771			clocks = <&rpmcc RPM_QDSS_CLK>;
772			clock-names = "apb_pclk";
773			cpu = <&CPU3>;
774			status = "disabled";
775		};
776
777		/* Core CTIs; CTIs 12-15 */
778		/* CTI - CPU-0 */
779		cti12: cti@858000 {
780			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
781				     "arm,primecell";
782			reg = <0x00858000 0x1000>;
783
784			clocks = <&rpmcc RPM_QDSS_CLK>;
785			clock-names = "apb_pclk";
786
787			cpu = <&CPU0>;
788			arm,cs-dev-assoc = <&etm0>;
789
790			status = "disabled";
791		};
792
793		/* CTI - CPU-1 */
794		cti13: cti@859000 {
795			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
796				     "arm,primecell";
797			reg = <0x00859000 0x1000>;
798
799			clocks = <&rpmcc RPM_QDSS_CLK>;
800			clock-names = "apb_pclk";
801
802			cpu = <&CPU1>;
803			arm,cs-dev-assoc = <&etm1>;
804
805			status = "disabled";
806		};
807
808		/* CTI - CPU-2 */
809		cti14: cti@85a000 {
810			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
811				     "arm,primecell";
812			reg = <0x0085a000 0x1000>;
813
814			clocks = <&rpmcc RPM_QDSS_CLK>;
815			clock-names = "apb_pclk";
816
817			cpu = <&CPU2>;
818			arm,cs-dev-assoc = <&etm2>;
819
820			status = "disabled";
821		};
822
823		/* CTI - CPU-3 */
824		cti15: cti@85b000 {
825			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
826				     "arm,primecell";
827			reg = <0x0085b000 0x1000>;
828
829			clocks = <&rpmcc RPM_QDSS_CLK>;
830			clock-names = "apb_pclk";
831
832			cpu = <&CPU3>;
833			arm,cs-dev-assoc = <&etm3>;
834
835			status = "disabled";
836		};
837
838		etm0: etm@85c000 {
839			compatible = "arm,coresight-etm4x", "arm,primecell";
840			reg = <0x0085c000 0x1000>;
841
842			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
843			clock-names = "apb_pclk", "atclk";
844			arm,coresight-loses-context-with-cpu;
845
846			cpu = <&CPU0>;
847
848			status = "disabled";
849
850			out-ports {
851				port {
852					etm0_out: endpoint {
853						remote-endpoint = <&funnel1_in0>;
854					};
855				};
856			};
857		};
858
859		etm1: etm@85d000 {
860			compatible = "arm,coresight-etm4x", "arm,primecell";
861			reg = <0x0085d000 0x1000>;
862
863			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
864			clock-names = "apb_pclk", "atclk";
865			arm,coresight-loses-context-with-cpu;
866
867			cpu = <&CPU1>;
868
869			status = "disabled";
870
871			out-ports {
872				port {
873					etm1_out: endpoint {
874						remote-endpoint = <&funnel1_in1>;
875					};
876				};
877			};
878		};
879
880		etm2: etm@85e000 {
881			compatible = "arm,coresight-etm4x", "arm,primecell";
882			reg = <0x0085e000 0x1000>;
883
884			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
885			clock-names = "apb_pclk", "atclk";
886			arm,coresight-loses-context-with-cpu;
887
888			cpu = <&CPU2>;
889
890			status = "disabled";
891
892			out-ports {
893				port {
894					etm2_out: endpoint {
895						remote-endpoint = <&funnel1_in2>;
896					};
897				};
898			};
899		};
900
901		etm3: etm@85f000 {
902			compatible = "arm,coresight-etm4x", "arm,primecell";
903			reg = <0x0085f000 0x1000>;
904
905			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
906			clock-names = "apb_pclk", "atclk";
907			arm,coresight-loses-context-with-cpu;
908
909			cpu = <&CPU3>;
910
911			status = "disabled";
912
913			out-ports {
914				port {
915					etm3_out: endpoint {
916						remote-endpoint = <&funnel1_in3>;
917					};
918				};
919			};
920		};
921
922		msmgpio: pinctrl@1000000 {
923			compatible = "qcom,msm8916-pinctrl";
924			reg = <0x01000000 0x300000>;
925			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
926			gpio-controller;
927			gpio-ranges = <&msmgpio 0 0 122>;
928			#gpio-cells = <2>;
929			interrupt-controller;
930			#interrupt-cells = <2>;
931		};
932
933		gcc: clock-controller@1800000 {
934			compatible = "qcom,gcc-msm8916";
935			#clock-cells = <1>;
936			#reset-cells = <1>;
937			#power-domain-cells = <1>;
938			reg = <0x01800000 0x80000>;
939			clocks = <&xo_board>,
940				 <&sleep_clk>,
941				 <&dsi_phy0 1>,
942				 <&dsi_phy0 0>,
943				 <0>,
944				 <0>,
945				 <0>;
946			clock-names = "xo",
947				      "sleep_clk",
948				      "dsi0pll",
949				      "dsi0pllbyte",
950				      "ext_mclk",
951				      "ext_pri_i2s",
952				      "ext_sec_i2s";
953		};
954
955		tcsr_mutex: hwlock@1905000 {
956			compatible = "qcom,tcsr-mutex";
957			reg = <0x01905000 0x20000>;
958			#hwlock-cells = <1>;
959		};
960
961		tcsr: syscon@1937000 {
962			compatible = "qcom,tcsr-msm8916", "syscon";
963			reg = <0x01937000 0x30000>;
964		};
965
966		mdss: mdss@1a00000 {
967			status = "disabled";
968			compatible = "qcom,mdss";
969			reg = <0x01a00000 0x1000>,
970			      <0x01ac8000 0x3000>;
971			reg-names = "mdss_phys", "vbif_phys";
972
973			power-domains = <&gcc MDSS_GDSC>;
974
975			clocks = <&gcc GCC_MDSS_AHB_CLK>,
976				 <&gcc GCC_MDSS_AXI_CLK>,
977				 <&gcc GCC_MDSS_VSYNC_CLK>;
978			clock-names = "iface",
979				      "bus",
980				      "vsync";
981
982			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
983
984			interrupt-controller;
985			#interrupt-cells = <1>;
986
987			#address-cells = <1>;
988			#size-cells = <1>;
989			ranges;
990
991			mdp: mdp@1a01000 {
992				compatible = "qcom,mdp5";
993				reg = <0x01a01000 0x89000>;
994				reg-names = "mdp_phys";
995
996				interrupt-parent = <&mdss>;
997				interrupts = <0>;
998
999				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1000					 <&gcc GCC_MDSS_AXI_CLK>,
1001					 <&gcc GCC_MDSS_MDP_CLK>,
1002					 <&gcc GCC_MDSS_VSYNC_CLK>;
1003				clock-names = "iface",
1004					      "bus",
1005					      "core",
1006					      "vsync";
1007
1008				iommus = <&apps_iommu 4>;
1009
1010				ports {
1011					#address-cells = <1>;
1012					#size-cells = <0>;
1013
1014					port@0 {
1015						reg = <0>;
1016						mdp5_intf1_out: endpoint {
1017							remote-endpoint = <&dsi0_in>;
1018						};
1019					};
1020				};
1021			};
1022
1023			dsi0: dsi@1a98000 {
1024				compatible = "qcom,mdss-dsi-ctrl";
1025				reg = <0x01a98000 0x25c>;
1026				reg-names = "dsi_ctrl";
1027
1028				interrupt-parent = <&mdss>;
1029				interrupts = <4>;
1030
1031				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1032						  <&gcc PCLK0_CLK_SRC>;
1033				assigned-clock-parents = <&dsi_phy0 0>,
1034							 <&dsi_phy0 1>;
1035
1036				clocks = <&gcc GCC_MDSS_MDP_CLK>,
1037					 <&gcc GCC_MDSS_AHB_CLK>,
1038					 <&gcc GCC_MDSS_AXI_CLK>,
1039					 <&gcc GCC_MDSS_BYTE0_CLK>,
1040					 <&gcc GCC_MDSS_PCLK0_CLK>,
1041					 <&gcc GCC_MDSS_ESC0_CLK>;
1042				clock-names = "mdp_core",
1043					      "iface",
1044					      "bus",
1045					      "byte",
1046					      "pixel",
1047					      "core";
1048				phys = <&dsi_phy0>;
1049				phy-names = "dsi-phy";
1050
1051				#address-cells = <1>;
1052				#size-cells = <0>;
1053
1054				ports {
1055					#address-cells = <1>;
1056					#size-cells = <0>;
1057
1058					port@0 {
1059						reg = <0>;
1060						dsi0_in: endpoint {
1061							remote-endpoint = <&mdp5_intf1_out>;
1062						};
1063					};
1064
1065					port@1 {
1066						reg = <1>;
1067						dsi0_out: endpoint {
1068						};
1069					};
1070				};
1071			};
1072
1073			dsi_phy0: dsi-phy@1a98300 {
1074				compatible = "qcom,dsi-phy-28nm-lp";
1075				reg = <0x01a98300 0xd4>,
1076				      <0x01a98500 0x280>,
1077				      <0x01a98780 0x30>;
1078				reg-names = "dsi_pll",
1079					    "dsi_phy",
1080					    "dsi_phy_regulator";
1081
1082				#clock-cells = <1>;
1083				#phy-cells = <0>;
1084
1085				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1086					 <&xo_board>;
1087				clock-names = "iface", "ref";
1088			};
1089		};
1090
1091		camss: camss@1b00000 {
1092			compatible = "qcom,msm8916-camss";
1093			reg = <0x01b0ac00 0x200>,
1094				<0x01b00030 0x4>,
1095				<0x01b0b000 0x200>,
1096				<0x01b00038 0x4>,
1097				<0x01b08000 0x100>,
1098				<0x01b08400 0x100>,
1099				<0x01b0a000 0x500>,
1100				<0x01b00020 0x10>,
1101				<0x01b10000 0x1000>;
1102			reg-names = "csiphy0",
1103				"csiphy0_clk_mux",
1104				"csiphy1",
1105				"csiphy1_clk_mux",
1106				"csid0",
1107				"csid1",
1108				"ispif",
1109				"csi_clk_mux",
1110				"vfe0";
1111			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1112				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1113				<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1114				<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1115				<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1116				<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1117			interrupt-names = "csiphy0",
1118				"csiphy1",
1119				"csid0",
1120				"csid1",
1121				"ispif",
1122				"vfe0";
1123			power-domains = <&gcc VFE_GDSC>;
1124			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1125				<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1126				<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1127				<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1128				<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1129				<&gcc GCC_CAMSS_CSI0_CLK>,
1130				<&gcc GCC_CAMSS_CSI0PHY_CLK>,
1131				<&gcc GCC_CAMSS_CSI0PIX_CLK>,
1132				<&gcc GCC_CAMSS_CSI0RDI_CLK>,
1133				<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1134				<&gcc GCC_CAMSS_CSI1_CLK>,
1135				<&gcc GCC_CAMSS_CSI1PHY_CLK>,
1136				<&gcc GCC_CAMSS_CSI1PIX_CLK>,
1137				<&gcc GCC_CAMSS_CSI1RDI_CLK>,
1138				<&gcc GCC_CAMSS_AHB_CLK>,
1139				<&gcc GCC_CAMSS_VFE0_CLK>,
1140				<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1141				<&gcc GCC_CAMSS_VFE_AHB_CLK>,
1142				<&gcc GCC_CAMSS_VFE_AXI_CLK>;
1143			clock-names = "top_ahb",
1144				"ispif_ahb",
1145				"csiphy0_timer",
1146				"csiphy1_timer",
1147				"csi0_ahb",
1148				"csi0",
1149				"csi0_phy",
1150				"csi0_pix",
1151				"csi0_rdi",
1152				"csi1_ahb",
1153				"csi1",
1154				"csi1_phy",
1155				"csi1_pix",
1156				"csi1_rdi",
1157				"ahb",
1158				"vfe0",
1159				"csi_vfe0",
1160				"vfe_ahb",
1161				"vfe_axi";
1162			iommus = <&apps_iommu 3>;
1163			status = "disabled";
1164			ports {
1165				#address-cells = <1>;
1166				#size-cells = <0>;
1167			};
1168		};
1169
1170		cci: cci@1b0c000 {
1171			compatible = "qcom,msm8916-cci";
1172			#address-cells = <1>;
1173			#size-cells = <0>;
1174			reg = <0x01b0c000 0x1000>;
1175			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1176			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1177				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
1178				<&gcc GCC_CAMSS_CCI_CLK>,
1179				<&gcc GCC_CAMSS_AHB_CLK>;
1180			clock-names = "camss_top_ahb", "cci_ahb",
1181					  "cci", "camss_ahb";
1182			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1183					  <&gcc GCC_CAMSS_CCI_CLK>;
1184			assigned-clock-rates = <80000000>, <19200000>;
1185			pinctrl-names = "default";
1186			pinctrl-0 = <&cci0_default>;
1187			status = "disabled";
1188
1189			cci_i2c0: i2c-bus@0 {
1190				reg = <0>;
1191				clock-frequency = <400000>;
1192				#address-cells = <1>;
1193				#size-cells = <0>;
1194			};
1195		};
1196
1197		gpu@1c00000 {
1198			compatible = "qcom,adreno-306.0", "qcom,adreno";
1199			reg = <0x01c00000 0x20000>;
1200			reg-names = "kgsl_3d0_reg_memory";
1201			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1202			interrupt-names = "kgsl_3d0_irq";
1203			clock-names =
1204			    "core",
1205			    "iface",
1206			    "mem",
1207			    "mem_iface",
1208			    "alt_mem_iface",
1209			    "gfx3d";
1210			clocks =
1211			    <&gcc GCC_OXILI_GFX3D_CLK>,
1212			    <&gcc GCC_OXILI_AHB_CLK>,
1213			    <&gcc GCC_OXILI_GMEM_CLK>,
1214			    <&gcc GCC_BIMC_GFX_CLK>,
1215			    <&gcc GCC_BIMC_GPU_CLK>,
1216			    <&gcc GFX3D_CLK_SRC>;
1217			power-domains = <&gcc OXILI_GDSC>;
1218			operating-points-v2 = <&gpu_opp_table>;
1219			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1220
1221			gpu_opp_table: opp-table {
1222				compatible = "operating-points-v2";
1223
1224				opp-400000000 {
1225					opp-hz = /bits/ 64 <400000000>;
1226				};
1227				opp-19200000 {
1228					opp-hz = /bits/ 64 <19200000>;
1229				};
1230			};
1231		};
1232
1233		venus: video-codec@1d00000 {
1234			compatible = "qcom,msm8916-venus";
1235			reg = <0x01d00000 0xff000>;
1236			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1237			power-domains = <&gcc VENUS_GDSC>;
1238			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1239				 <&gcc GCC_VENUS0_AHB_CLK>,
1240				 <&gcc GCC_VENUS0_AXI_CLK>;
1241			clock-names = "core", "iface", "bus";
1242			iommus = <&apps_iommu 5>;
1243			memory-region = <&venus_mem>;
1244			status = "okay";
1245
1246			video-decoder {
1247				compatible = "venus-decoder";
1248			};
1249
1250			video-encoder {
1251				compatible = "venus-encoder";
1252			};
1253		};
1254
1255		apps_iommu: iommu@1ef0000 {
1256			#address-cells = <1>;
1257			#size-cells = <1>;
1258			#iommu-cells = <1>;
1259			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1260			ranges = <0 0x01e20000 0x40000>;
1261			reg = <0x01ef0000 0x3000>;
1262			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1263				 <&gcc GCC_APSS_TCU_CLK>;
1264			clock-names = "iface", "bus";
1265			qcom,iommu-secure-id = <17>;
1266
1267			// vfe:
1268			iommu-ctx@3000 {
1269				compatible = "qcom,msm-iommu-v1-sec";
1270				reg = <0x3000 0x1000>;
1271				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1272			};
1273
1274			// mdp_0:
1275			iommu-ctx@4000 {
1276				compatible = "qcom,msm-iommu-v1-ns";
1277				reg = <0x4000 0x1000>;
1278				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1279			};
1280
1281			// venus_ns:
1282			iommu-ctx@5000 {
1283				compatible = "qcom,msm-iommu-v1-sec";
1284				reg = <0x5000 0x1000>;
1285				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1286			};
1287		};
1288
1289		gpu_iommu: iommu@1f08000 {
1290			#address-cells = <1>;
1291			#size-cells = <1>;
1292			#iommu-cells = <1>;
1293			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1294			ranges = <0 0x01f08000 0x10000>;
1295			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1296				 <&gcc GCC_GFX_TCU_CLK>;
1297			clock-names = "iface", "bus";
1298			qcom,iommu-secure-id = <18>;
1299
1300			// gfx3d_user:
1301			iommu-ctx@1000 {
1302				compatible = "qcom,msm-iommu-v1-ns";
1303				reg = <0x1000 0x1000>;
1304				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1305			};
1306
1307			// gfx3d_priv:
1308			iommu-ctx@2000 {
1309				compatible = "qcom,msm-iommu-v1-ns";
1310				reg = <0x2000 0x1000>;
1311				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1312			};
1313		};
1314
1315		spmi_bus: spmi@200f000 {
1316			compatible = "qcom,spmi-pmic-arb";
1317			reg = <0x0200f000 0x001000>,
1318			      <0x02400000 0x400000>,
1319			      <0x02c00000 0x400000>,
1320			      <0x03800000 0x200000>,
1321			      <0x0200a000 0x002100>;
1322			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1323			interrupt-names = "periph_irq";
1324			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1325			qcom,ee = <0>;
1326			qcom,channel = <0>;
1327			#address-cells = <2>;
1328			#size-cells = <0>;
1329			interrupt-controller;
1330			#interrupt-cells = <4>;
1331		};
1332
1333		bam_dmux_dma: dma-controller@4044000 {
1334			compatible = "qcom,bam-v1.7.0";
1335			reg = <0x04044000 0x19000>;
1336			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1337			#dma-cells = <1>;
1338			qcom,ee = <0>;
1339
1340			num-channels = <6>;
1341			qcom,num-ees = <1>;
1342			qcom,powered-remotely;
1343
1344			status = "disabled";
1345		};
1346
1347		mpss: remoteproc@4080000 {
1348			compatible = "qcom,msm8916-mss-pil";
1349			reg = <0x04080000 0x100>,
1350			      <0x04020000 0x040>;
1351
1352			reg-names = "qdsp6", "rmb";
1353
1354			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1355					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1356					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1357					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1358					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1359			interrupt-names = "wdog", "fatal", "ready",
1360					  "handover", "stop-ack";
1361
1362			power-domains = <&rpmpd MSM8916_VDDCX>,
1363					<&rpmpd MSM8916_VDDMX>;
1364			power-domain-names = "cx", "mx";
1365
1366			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1367				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1368				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1369				 <&xo_board>;
1370			clock-names = "iface", "bus", "mem", "xo";
1371
1372			qcom,smem-states = <&hexagon_smp2p_out 0>;
1373			qcom,smem-state-names = "stop";
1374
1375			resets = <&scm 0>;
1376			reset-names = "mss_restart";
1377
1378			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1379
1380			status = "disabled";
1381
1382			mba {
1383				memory-region = <&mba_mem>;
1384			};
1385
1386			mpss {
1387				memory-region = <&mpss_mem>;
1388			};
1389
1390			bam_dmux: bam-dmux {
1391				compatible = "qcom,bam-dmux";
1392
1393				interrupt-parent = <&hexagon_smsm>;
1394				interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1395				interrupt-names = "pc", "pc-ack";
1396
1397				qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1398				qcom,smem-state-names = "pc", "pc-ack";
1399
1400				dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1401				dma-names = "tx", "rx";
1402
1403				status = "disabled";
1404			};
1405
1406			smd-edge {
1407				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1408
1409				qcom,smd-edge = <0>;
1410				qcom,ipc = <&apcs 8 12>;
1411				qcom,remote-pid = <1>;
1412
1413				label = "hexagon";
1414
1415				fastrpc {
1416					compatible = "qcom,fastrpc";
1417					qcom,smd-channels = "fastrpcsmd-apps-dsp";
1418					label = "adsp";
1419					qcom,non-secure-domain;
1420
1421					#address-cells = <1>;
1422					#size-cells = <0>;
1423
1424					cb@1 {
1425						compatible = "qcom,fastrpc-compute-cb";
1426						reg = <1>;
1427					};
1428				};
1429			};
1430		};
1431
1432		sound: sound@7702000 {
1433			status = "disabled";
1434			compatible = "qcom,apq8016-sbc-sndcard";
1435			reg = <0x07702000 0x4>, <0x07702004 0x4>;
1436			reg-names = "mic-iomux", "spkr-iomux";
1437		};
1438
1439		lpass: audio-controller@7708000 {
1440			status = "disabled";
1441			compatible = "qcom,lpass-cpu-apq8016";
1442
1443			/*
1444			 * Note: Unlike the name would suggest, the SEC_I2S_CLK
1445			 * is actually only used by Tertiary MI2S while
1446			 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
1447			 */
1448			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1449				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1450				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1451				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1452				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1453				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1454				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1455
1456			clock-names = "ahbix-clk",
1457					"pcnoc-mport-clk",
1458					"pcnoc-sway-clk",
1459					"mi2s-bit-clk0",
1460					"mi2s-bit-clk1",
1461					"mi2s-bit-clk2",
1462					"mi2s-bit-clk3";
1463			#sound-dai-cells = <1>;
1464
1465			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1466			interrupt-names = "lpass-irq-lpaif";
1467			reg = <0x07708000 0x10000>;
1468			reg-names = "lpass-lpaif";
1469
1470			#address-cells = <1>;
1471			#size-cells = <0>;
1472		};
1473
1474		lpass_codec: audio-codec@771c000 {
1475			compatible = "qcom,msm8916-wcd-digital-codec";
1476			reg = <0x0771c000 0x400>;
1477			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1478				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1479			clock-names = "ahbix-clk", "mclk";
1480			#sound-dai-cells = <1>;
1481		};
1482
1483		sdhc_1: mmc@7824000 {
1484			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1485			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1486			reg-names = "hc", "core";
1487
1488			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1489				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1490			interrupt-names = "hc_irq", "pwr_irq";
1491			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1492				 <&gcc GCC_SDCC1_APPS_CLK>,
1493				 <&xo_board>;
1494			clock-names = "iface", "core", "xo";
1495			mmc-ddr-1_8v;
1496			bus-width = <8>;
1497			non-removable;
1498			status = "disabled";
1499		};
1500
1501		sdhc_2: mmc@7864000 {
1502			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1503			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1504			reg-names = "hc", "core";
1505
1506			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1507				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1508			interrupt-names = "hc_irq", "pwr_irq";
1509			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1510				 <&gcc GCC_SDCC2_APPS_CLK>,
1511				 <&xo_board>;
1512			clock-names = "iface", "core", "xo";
1513			bus-width = <4>;
1514			status = "disabled";
1515		};
1516
1517		blsp_dma: dma-controller@7884000 {
1518			compatible = "qcom,bam-v1.7.0";
1519			reg = <0x07884000 0x23000>;
1520			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1521			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1522			clock-names = "bam_clk";
1523			#dma-cells = <1>;
1524			qcom,ee = <0>;
1525			status = "disabled";
1526		};
1527
1528		blsp1_uart1: serial@78af000 {
1529			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1530			reg = <0x078af000 0x200>;
1531			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1532			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1533			clock-names = "core", "iface";
1534			dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1535			dma-names = "tx", "rx";
1536			pinctrl-names = "default", "sleep";
1537			pinctrl-0 = <&blsp1_uart1_default>;
1538			pinctrl-1 = <&blsp1_uart1_sleep>;
1539			status = "disabled";
1540		};
1541
1542		blsp1_uart2: serial@78b0000 {
1543			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1544			reg = <0x078b0000 0x200>;
1545			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1546			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1547			clock-names = "core", "iface";
1548			dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1549			dma-names = "tx", "rx";
1550			pinctrl-names = "default", "sleep";
1551			pinctrl-0 = <&blsp1_uart2_default>;
1552			pinctrl-1 = <&blsp1_uart2_sleep>;
1553			status = "disabled";
1554		};
1555
1556		blsp_i2c1: i2c@78b5000 {
1557			compatible = "qcom,i2c-qup-v2.2.1";
1558			reg = <0x078b5000 0x500>;
1559			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1560			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1561				 <&gcc GCC_BLSP1_AHB_CLK>;
1562			clock-names = "core", "iface";
1563			pinctrl-names = "default", "sleep";
1564			pinctrl-0 = <&i2c1_default>;
1565			pinctrl-1 = <&i2c1_sleep>;
1566			#address-cells = <1>;
1567			#size-cells = <0>;
1568			status = "disabled";
1569		};
1570
1571		blsp_spi1: spi@78b5000 {
1572			compatible = "qcom,spi-qup-v2.2.1";
1573			reg = <0x078b5000 0x500>;
1574			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1575			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1576				 <&gcc GCC_BLSP1_AHB_CLK>;
1577			clock-names = "core", "iface";
1578			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1579			dma-names = "tx", "rx";
1580			pinctrl-names = "default", "sleep";
1581			pinctrl-0 = <&spi1_default>;
1582			pinctrl-1 = <&spi1_sleep>;
1583			#address-cells = <1>;
1584			#size-cells = <0>;
1585			status = "disabled";
1586		};
1587
1588		blsp_i2c2: i2c@78b6000 {
1589			compatible = "qcom,i2c-qup-v2.2.1";
1590			reg = <0x078b6000 0x500>;
1591			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1592			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1593				 <&gcc GCC_BLSP1_AHB_CLK>;
1594			clock-names = "core", "iface";
1595			pinctrl-names = "default", "sleep";
1596			pinctrl-0 = <&i2c2_default>;
1597			pinctrl-1 = <&i2c2_sleep>;
1598			#address-cells = <1>;
1599			#size-cells = <0>;
1600			status = "disabled";
1601		};
1602
1603		blsp_spi2: spi@78b6000 {
1604			compatible = "qcom,spi-qup-v2.2.1";
1605			reg = <0x078b6000 0x500>;
1606			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1607			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1608				 <&gcc GCC_BLSP1_AHB_CLK>;
1609			clock-names = "core", "iface";
1610			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1611			dma-names = "tx", "rx";
1612			pinctrl-names = "default", "sleep";
1613			pinctrl-0 = <&spi2_default>;
1614			pinctrl-1 = <&spi2_sleep>;
1615			#address-cells = <1>;
1616			#size-cells = <0>;
1617			status = "disabled";
1618		};
1619
1620		blsp_i2c3: i2c@78b7000 {
1621			compatible = "qcom,i2c-qup-v2.2.1";
1622			reg = <0x078b7000 0x500>;
1623			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1624			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1625				 <&gcc GCC_BLSP1_AHB_CLK>;
1626			clock-names = "core", "iface";
1627			pinctrl-names = "default", "sleep";
1628			pinctrl-0 = <&i2c3_default>;
1629			pinctrl-1 = <&i2c3_sleep>;
1630			#address-cells = <1>;
1631			#size-cells = <0>;
1632			status = "disabled";
1633		};
1634
1635		blsp_spi3: spi@78b7000 {
1636			compatible = "qcom,spi-qup-v2.2.1";
1637			reg = <0x078b7000 0x500>;
1638			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1639			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1640				 <&gcc GCC_BLSP1_AHB_CLK>;
1641			clock-names = "core", "iface";
1642			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1643			dma-names = "tx", "rx";
1644			pinctrl-names = "default", "sleep";
1645			pinctrl-0 = <&spi3_default>;
1646			pinctrl-1 = <&spi3_sleep>;
1647			#address-cells = <1>;
1648			#size-cells = <0>;
1649			status = "disabled";
1650		};
1651
1652		blsp_i2c4: i2c@78b8000 {
1653			compatible = "qcom,i2c-qup-v2.2.1";
1654			reg = <0x078b8000 0x500>;
1655			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1656			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1657				 <&gcc GCC_BLSP1_AHB_CLK>;
1658			clock-names = "core", "iface";
1659			pinctrl-names = "default", "sleep";
1660			pinctrl-0 = <&i2c4_default>;
1661			pinctrl-1 = <&i2c4_sleep>;
1662			#address-cells = <1>;
1663			#size-cells = <0>;
1664			status = "disabled";
1665		};
1666
1667		blsp_spi4: spi@78b8000 {
1668			compatible = "qcom,spi-qup-v2.2.1";
1669			reg = <0x078b8000 0x500>;
1670			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1671			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1672				 <&gcc GCC_BLSP1_AHB_CLK>;
1673			clock-names = "core", "iface";
1674			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1675			dma-names = "tx", "rx";
1676			pinctrl-names = "default", "sleep";
1677			pinctrl-0 = <&spi4_default>;
1678			pinctrl-1 = <&spi4_sleep>;
1679			#address-cells = <1>;
1680			#size-cells = <0>;
1681			status = "disabled";
1682		};
1683
1684		blsp_i2c5: i2c@78b9000 {
1685			compatible = "qcom,i2c-qup-v2.2.1";
1686			reg = <0x078b9000 0x500>;
1687			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1688			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1689				 <&gcc GCC_BLSP1_AHB_CLK>;
1690			clock-names = "core", "iface";
1691			pinctrl-names = "default", "sleep";
1692			pinctrl-0 = <&i2c5_default>;
1693			pinctrl-1 = <&i2c5_sleep>;
1694			#address-cells = <1>;
1695			#size-cells = <0>;
1696			status = "disabled";
1697		};
1698
1699		blsp_spi5: spi@78b9000 {
1700			compatible = "qcom,spi-qup-v2.2.1";
1701			reg = <0x078b9000 0x500>;
1702			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1703			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1704				 <&gcc GCC_BLSP1_AHB_CLK>;
1705			clock-names = "core", "iface";
1706			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1707			dma-names = "tx", "rx";
1708			pinctrl-names = "default", "sleep";
1709			pinctrl-0 = <&spi5_default>;
1710			pinctrl-1 = <&spi5_sleep>;
1711			#address-cells = <1>;
1712			#size-cells = <0>;
1713			status = "disabled";
1714		};
1715
1716		blsp_i2c6: i2c@78ba000 {
1717			compatible = "qcom,i2c-qup-v2.2.1";
1718			reg = <0x078ba000 0x500>;
1719			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1720			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1721				 <&gcc GCC_BLSP1_AHB_CLK>;
1722			clock-names = "core", "iface";
1723			pinctrl-names = "default", "sleep";
1724			pinctrl-0 = <&i2c6_default>;
1725			pinctrl-1 = <&i2c6_sleep>;
1726			#address-cells = <1>;
1727			#size-cells = <0>;
1728			status = "disabled";
1729		};
1730
1731		blsp_spi6: spi@78ba000 {
1732			compatible = "qcom,spi-qup-v2.2.1";
1733			reg = <0x078ba000 0x500>;
1734			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1735			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1736				 <&gcc GCC_BLSP1_AHB_CLK>;
1737			clock-names = "core", "iface";
1738			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1739			dma-names = "tx", "rx";
1740			pinctrl-names = "default", "sleep";
1741			pinctrl-0 = <&spi6_default>;
1742			pinctrl-1 = <&spi6_sleep>;
1743			#address-cells = <1>;
1744			#size-cells = <0>;
1745			status = "disabled";
1746		};
1747
1748		usb: usb@78d9000 {
1749			compatible = "qcom,ci-hdrc";
1750			reg = <0x078d9000 0x200>,
1751			      <0x078d9200 0x200>;
1752			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1753				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1754			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1755				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1756			clock-names = "iface", "core";
1757			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1758			assigned-clock-rates = <80000000>;
1759			resets = <&gcc GCC_USB_HS_BCR>;
1760			reset-names = "core";
1761			phy_type = "ulpi";
1762			dr_mode = "otg";
1763			hnp-disable;
1764			srp-disable;
1765			adp-disable;
1766			ahb-burst-config = <0>;
1767			phy-names = "usb-phy";
1768			phys = <&usb_hs_phy>;
1769			status = "disabled";
1770			#reset-cells = <1>;
1771
1772			ulpi {
1773				usb_hs_phy: phy {
1774					compatible = "qcom,usb-hs-phy-msm8916",
1775						     "qcom,usb-hs-phy";
1776					#phy-cells = <0>;
1777					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1778					clock-names = "ref", "sleep";
1779					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1780					reset-names = "phy", "por";
1781					qcom,init-seq = /bits/ 8 <0x0 0x44>,
1782								 <0x1 0x6b>,
1783								 <0x2 0x24>,
1784								 <0x3 0x13>;
1785				};
1786			};
1787		};
1788
1789		pronto: remoteproc@a21b000 {
1790			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1791			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1792			reg-names = "ccu", "dxe", "pmu";
1793
1794			memory-region = <&wcnss_mem>;
1795
1796			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1797					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1798					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1799					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1800					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1801			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1802
1803			power-domains = <&rpmpd MSM8916_VDDCX>,
1804					<&rpmpd MSM8916_VDDMX>;
1805			power-domain-names = "cx", "mx";
1806
1807			qcom,smem-states = <&wcnss_smp2p_out 0>;
1808			qcom,smem-state-names = "stop";
1809
1810			pinctrl-names = "default";
1811			pinctrl-0 = <&wcnss_pin_a>;
1812
1813			status = "disabled";
1814
1815			iris {
1816				compatible = "qcom,wcn3620";
1817
1818				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1819				clock-names = "xo";
1820			};
1821
1822			smd-edge {
1823				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1824
1825				qcom,ipc = <&apcs 8 17>;
1826				qcom,smd-edge = <6>;
1827				qcom,remote-pid = <4>;
1828
1829				label = "pronto";
1830
1831				wcnss_ctrl: wcnss {
1832					compatible = "qcom,wcnss";
1833					qcom,smd-channels = "WCNSS_CTRL";
1834
1835					qcom,mmio = <&pronto>;
1836
1837					bluetooth {
1838						compatible = "qcom,wcnss-bt";
1839					};
1840
1841					wifi {
1842						compatible = "qcom,wcnss-wlan";
1843
1844						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1845							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1846						interrupt-names = "tx", "rx";
1847
1848						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1849						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1850					};
1851				};
1852			};
1853		};
1854
1855		intc: interrupt-controller@b000000 {
1856			compatible = "qcom,msm-qgic2";
1857			interrupt-controller;
1858			#interrupt-cells = <3>;
1859			reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1860			      <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1861			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1862		};
1863
1864		apcs: mailbox@b011000 {
1865			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1866			reg = <0x0b011000 0x1000>;
1867			#mbox-cells = <1>;
1868			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1869			clock-names = "pll", "aux";
1870			#clock-cells = <0>;
1871		};
1872
1873		a53pll: clock@b016000 {
1874			compatible = "qcom,msm8916-a53pll";
1875			reg = <0x0b016000 0x40>;
1876			#clock-cells = <0>;
1877			clocks = <&xo_board>;
1878			clock-names = "xo";
1879		};
1880
1881		timer@b020000 {
1882			#address-cells = <1>;
1883			#size-cells = <1>;
1884			ranges;
1885			compatible = "arm,armv7-timer-mem";
1886			reg = <0x0b020000 0x1000>;
1887			clock-frequency = <19200000>;
1888
1889			frame@b021000 {
1890				frame-number = <0>;
1891				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1892					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1893				reg = <0x0b021000 0x1000>,
1894				      <0x0b022000 0x1000>;
1895			};
1896
1897			frame@b023000 {
1898				frame-number = <1>;
1899				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1900				reg = <0x0b023000 0x1000>;
1901				status = "disabled";
1902			};
1903
1904			frame@b024000 {
1905				frame-number = <2>;
1906				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1907				reg = <0x0b024000 0x1000>;
1908				status = "disabled";
1909			};
1910
1911			frame@b025000 {
1912				frame-number = <3>;
1913				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1914				reg = <0x0b025000 0x1000>;
1915				status = "disabled";
1916			};
1917
1918			frame@b026000 {
1919				frame-number = <4>;
1920				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1921				reg = <0x0b026000 0x1000>;
1922				status = "disabled";
1923			};
1924
1925			frame@b027000 {
1926				frame-number = <5>;
1927				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1928				reg = <0x0b027000 0x1000>;
1929				status = "disabled";
1930			};
1931
1932			frame@b028000 {
1933				frame-number = <6>;
1934				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1935				reg = <0x0b028000 0x1000>;
1936				status = "disabled";
1937			};
1938		};
1939
1940		cpu0_acc: power-manager@b088000 {
1941			compatible = "qcom,msm8916-acc";
1942			reg = <0x0b088000 0x1000>;
1943			status = "reserved"; /* Controlled by PSCI firmware */
1944		};
1945
1946		cpu0_saw: power-manager@b089000 {
1947			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1948			reg = <0x0b089000 0x1000>;
1949			status = "reserved"; /* Controlled by PSCI firmware */
1950		};
1951
1952		cpu1_acc: power-manager@b098000 {
1953			compatible = "qcom,msm8916-acc";
1954			reg = <0x0b098000 0x1000>;
1955			status = "reserved"; /* Controlled by PSCI firmware */
1956		};
1957
1958		cpu1_saw: power-manager@b099000 {
1959			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1960			reg = <0x0b099000 0x1000>;
1961			status = "reserved"; /* Controlled by PSCI firmware */
1962		};
1963
1964		cpu2_acc: power-manager@b0a8000 {
1965			compatible = "qcom,msm8916-acc";
1966			reg = <0x0b0a8000 0x1000>;
1967			status = "reserved"; /* Controlled by PSCI firmware */
1968		};
1969
1970		cpu2_saw: power-manager@b0a9000 {
1971			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1972			reg = <0x0b0a9000 0x1000>;
1973			status = "reserved"; /* Controlled by PSCI firmware */
1974		};
1975
1976		cpu3_acc: power-manager@b0b8000 {
1977			compatible = "qcom,msm8916-acc";
1978			reg = <0x0b0b8000 0x1000>;
1979			status = "reserved"; /* Controlled by PSCI firmware */
1980		};
1981
1982		cpu3_saw: power-manager@b0b9000 {
1983			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1984			reg = <0x0b0b9000 0x1000>;
1985			status = "reserved"; /* Controlled by PSCI firmware */
1986		};
1987	};
1988
1989	thermal-zones {
1990		cpu0-1-thermal {
1991			polling-delay-passive = <250>;
1992			polling-delay = <1000>;
1993
1994			thermal-sensors = <&tsens 5>;
1995
1996			trips {
1997				cpu0_1_alert0: trip-point0 {
1998					temperature = <75000>;
1999					hysteresis = <2000>;
2000					type = "passive";
2001				};
2002				cpu0_1_crit: cpu_crit {
2003					temperature = <110000>;
2004					hysteresis = <2000>;
2005					type = "critical";
2006				};
2007			};
2008
2009			cooling-maps {
2010				map0 {
2011					trip = <&cpu0_1_alert0>;
2012					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2013							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2014							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2015							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2016				};
2017			};
2018		};
2019
2020		cpu2-3-thermal {
2021			polling-delay-passive = <250>;
2022			polling-delay = <1000>;
2023
2024			thermal-sensors = <&tsens 4>;
2025
2026			trips {
2027				cpu2_3_alert0: trip-point0 {
2028					temperature = <75000>;
2029					hysteresis = <2000>;
2030					type = "passive";
2031				};
2032				cpu2_3_crit: cpu_crit {
2033					temperature = <110000>;
2034					hysteresis = <2000>;
2035					type = "critical";
2036				};
2037			};
2038
2039			cooling-maps {
2040				map0 {
2041					trip = <&cpu2_3_alert0>;
2042					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2043							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2044							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2045							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2046				};
2047			};
2048		};
2049
2050		gpu-thermal {
2051			polling-delay-passive = <250>;
2052			polling-delay = <1000>;
2053
2054			thermal-sensors = <&tsens 2>;
2055
2056			trips {
2057				gpu_alert0: trip-point0 {
2058					temperature = <75000>;
2059					hysteresis = <2000>;
2060					type = "passive";
2061				};
2062				gpu_crit: gpu_crit {
2063					temperature = <95000>;
2064					hysteresis = <2000>;
2065					type = "critical";
2066				};
2067			};
2068		};
2069
2070		camera-thermal {
2071			polling-delay-passive = <250>;
2072			polling-delay = <1000>;
2073
2074			thermal-sensors = <&tsens 1>;
2075
2076			trips {
2077				cam_alert0: trip-point0 {
2078					temperature = <75000>;
2079					hysteresis = <2000>;
2080					type = "hot";
2081				};
2082			};
2083		};
2084
2085		modem-thermal {
2086			polling-delay-passive = <250>;
2087			polling-delay = <1000>;
2088
2089			thermal-sensors = <&tsens 0>;
2090
2091			trips {
2092				modem_alert0: trip-point0 {
2093					temperature = <85000>;
2094					hysteresis = <2000>;
2095					type = "hot";
2096				};
2097			};
2098		};
2099
2100	};
2101
2102	timer {
2103		compatible = "arm,armv8-timer";
2104		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2105			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2106			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2107			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2108	};
2109};
2110
2111#include "msm8916-pins.dtsi"
2112