1 /*
2 * Blackfin cache control code (simpler control-style functions)
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/init.h>
10 #include <asm/blackfin.h>
11 #include <asm/cplbinit.h>
12
13 /* Invalidate the Entire Data cache by
14 * clearing DMC[1:0] bits
15 */
blackfin_invalidate_entire_dcache(void)16 void blackfin_invalidate_entire_dcache(void)
17 {
18 u32 dmem = bfin_read_DMEM_CONTROL();
19 bfin_write_DMEM_CONTROL(dmem & ~0xc);
20 SSYNC();
21 bfin_write_DMEM_CONTROL(dmem);
22 SSYNC();
23 }
24
25 /* Invalidate the Entire Instruction cache by
26 * clearing IMC bit
27 */
blackfin_invalidate_entire_icache(void)28 void blackfin_invalidate_entire_icache(void)
29 {
30 u32 imem = bfin_read_IMEM_CONTROL();
31 bfin_write_IMEM_CONTROL(imem & ~0x4);
32 SSYNC();
33 bfin_write_IMEM_CONTROL(imem);
34 SSYNC();
35 }
36
37 #if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
38
39 static void
bfin_cache_init(struct cplb_entry * cplb_tbl,unsigned long cplb_addr,unsigned long cplb_data,unsigned long mem_control,unsigned long mem_mask)40 bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
41 unsigned long cplb_data, unsigned long mem_control,
42 unsigned long mem_mask)
43 {
44 int i;
45
46 for (i = 0; i < MAX_CPLBS; i++) {
47 bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
48 bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
49 }
50
51 _enable_cplb(mem_control, mem_mask);
52 }
53
54 #ifdef CONFIG_BFIN_ICACHE
bfin_icache_init(struct cplb_entry * icplb_tbl)55 void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
56 {
57 bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
58 (IMC | ENICPLB));
59 }
60 #endif
61
62 #ifdef CONFIG_BFIN_DCACHE
bfin_dcache_init(struct cplb_entry * dcplb_tbl)63 void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
64 {
65 /*
66 * Anomaly notes:
67 * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
68 * register, so that the port preferences for DAG0 and DAG1 are set
69 * to port B
70 */
71 bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
72 (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
73 }
74 #endif
75
76 #endif
77