1 /* $Id: shubio.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 10 #ifndef _ASM_IA64_SN_SN2_SHUBIO_H 11 #define _ASM_IA64_SN_SN2_SHUBIO_H 12 13 #include <asm/sn/arch.h> 14 15 #define HUB_WIDGET_ID_MAX 0xf 16 #define IIO_NUM_ITTES 7 17 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) 18 19 #define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ 20 /* This register is also accessible from 21 * Crosstalk at address 0x0. */ 22 #define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ 23 #define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ 24 #define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ 25 #define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ 26 #define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ 27 #define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ 28 #define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ 29 #define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ 30 #define IIO_ILLR 0x00400130 /* IO LLP Log Register */ 31 #define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ 32 33 #define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ 34 #define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ 35 36 #define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ 37 #define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ 38 39 #define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ 40 #define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ 41 #define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ 42 #define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ 43 #define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ 44 #define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ 45 #define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ 46 47 #define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ 48 #define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ 49 #define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ 50 #define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ 51 #define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ 52 #define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ 53 #define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ 54 #define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ 55 #define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ 56 57 #define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ 58 #define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ 59 #define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ 60 #define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ 61 #define IIO_IBCR 0x00400200 /* IO BTE Control Register */ 62 63 #define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ 64 #define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ 65 66 #define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ 67 68 #define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ 69 #define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ 70 71 72 #define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ 73 #define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ 74 75 #define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ 76 #define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ 77 #define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ 78 #define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ 79 #define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ 80 81 #define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ 82 83 #define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ 84 #define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ 85 #define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ 86 #define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ 87 #define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ 88 #define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ 89 #define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ 90 #define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ 91 92 #define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ 93 #define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ 94 #define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ 95 #define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ 96 #define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ 97 #define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ 98 #define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ 99 #define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ 100 101 #define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ 102 #define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ 103 #define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ 104 #define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ 105 #define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ 106 #define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ 107 #define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ 108 #define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ 109 110 #define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ 111 #define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ 112 #define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ 113 #define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ 114 #define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ 115 116 #define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ 117 #define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ 118 #define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ 119 #define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ 120 #define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ 121 122 #define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ 123 #define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ 124 #define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ 125 #define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ 126 #define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ 127 128 #define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ 129 #define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ 130 #define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ 131 #define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ 132 #define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ 133 134 #define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ 135 #define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ 136 #define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ 137 #define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ 138 #define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ 139 140 #define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ 141 #define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ 142 #define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ 143 #define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ 144 #define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ 145 146 #define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ 147 #define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ 148 #define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ 149 #define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ 150 #define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ 151 152 #define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ 153 #define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ 154 #define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ 155 #define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ 156 #define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ 157 158 #define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ 159 #define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ 160 #define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ 161 #define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ 162 #define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ 163 164 #define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ 165 #define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ 166 #define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ 167 #define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ 168 #define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ 169 170 #define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ 171 #define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ 172 #define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ 173 #define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ 174 #define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ 175 176 #define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ 177 #define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ 178 #define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ 179 #define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ 180 #define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ 181 182 #define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ 183 #define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ 184 #define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ 185 #define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ 186 #define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ 187 188 #define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ 189 #define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ 190 #define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ 191 #define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ 192 #define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ 193 194 #define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ 195 #define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ 196 #define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ 197 #define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ 198 #define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ 199 200 #define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ 201 #define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ 202 #define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ 203 204 #define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ 205 206 #define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ 207 #define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ 208 #define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ 209 #define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ 210 #define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ 211 #define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ 212 #define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ 213 #define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ 214 #define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ 215 #define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ 216 #define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ 217 #define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ 218 219 #define IIO_IPCR 0x00430000 /* IO Performance Control */ 220 #define IIO_IPPR 0x00430008 /* IO Performance Profiling */ 221 222 223 #ifndef __ASSEMBLY__ 224 225 /************************************************************************ 226 * * 227 * Description: This register echoes some information from the * 228 * LB_REV_ID register. It is available through Crosstalk as described * 229 * above. The REV_NUM and MFG_NUM fields receive their values from * 230 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * 231 * The PART_NUM field's value is the Crosstalk device ID number that * 232 * Steve Miller assigned to the SHub chip. * 233 * * 234 ************************************************************************/ 235 236 typedef union ii_wid_u { 237 shubreg_t ii_wid_regval; 238 struct { 239 shubreg_t w_rsvd_1 : 1; 240 shubreg_t w_mfg_num : 11; 241 shubreg_t w_part_num : 16; 242 shubreg_t w_rev_num : 4; 243 shubreg_t w_rsvd : 32; 244 } ii_wid_fld_s; 245 } ii_wid_u_t; 246 247 248 /************************************************************************ 249 * * 250 * The fields in this register are set upon detection of an error * 251 * and cleared by various mechanisms, as explained in the * 252 * description. * 253 * * 254 ************************************************************************/ 255 256 typedef union ii_wstat_u { 257 shubreg_t ii_wstat_regval; 258 struct { 259 shubreg_t w_pending : 4; 260 shubreg_t w_xt_crd_to : 1; 261 shubreg_t w_xt_tail_to : 1; 262 shubreg_t w_rsvd_3 : 3; 263 shubreg_t w_tx_mx_rty : 1; 264 shubreg_t w_rsvd_2 : 6; 265 shubreg_t w_llp_tx_cnt : 8; 266 shubreg_t w_rsvd_1 : 8; 267 shubreg_t w_crazy : 1; 268 shubreg_t w_rsvd : 31; 269 } ii_wstat_fld_s; 270 } ii_wstat_u_t; 271 272 273 /************************************************************************ 274 * * 275 * Description: This is a read-write enabled register. It controls * 276 * various aspects of the Crosstalk flow control. * 277 * * 278 ************************************************************************/ 279 280 typedef union ii_wcr_u { 281 shubreg_t ii_wcr_regval; 282 struct { 283 shubreg_t w_wid : 4; 284 shubreg_t w_tag : 1; 285 shubreg_t w_rsvd_1 : 8; 286 shubreg_t w_dst_crd : 3; 287 shubreg_t w_f_bad_pkt : 1; 288 shubreg_t w_dir_con : 1; 289 shubreg_t w_e_thresh : 5; 290 shubreg_t w_rsvd : 41; 291 } ii_wcr_fld_s; 292 } ii_wcr_u_t; 293 294 295 /************************************************************************ 296 * * 297 * Description: This register's value is a bit vector that guards * 298 * access to local registers within the II as well as to external * 299 * Crosstalk widgets. Each bit in the register corresponds to a * 300 * particular region in the system; a region consists of one, two or * 301 * four nodes (depending on the value of the REGION_SIZE field in the * 302 * LB_REV_ID register, which is documented in Section 8.3.1.1). The * 303 * protection provided by this register applies to PIO read * 304 * operations as well as PIO write operations. The II will perform a * 305 * PIO read or write request only if the bit for the requestor's * 306 * region is set; otherwise, the II will not perform the requested * 307 * operation and will return an error response. When a PIO read or * 308 * write request targets an external Crosstalk widget, then not only * 309 * must the bit for the requestor's region be set in the ILAPR, but * 310 * also the target widget's bit in the IOWA register must be set in * 311 * order for the II to perform the requested operation; otherwise, * 312 * the II will return an error response. Hence, the protection * 313 * provided by the IOWA register supplements the protection provided * 314 * by the ILAPR for requests that target external Crosstalk widgets. * 315 * This register itself can be accessed only by the nodes whose * 316 * region ID bits are enabled in this same register. It can also be * 317 * accessed through the IAlias space by the local processors. * 318 * The reset value of this register allows access by all nodes. * 319 * * 320 ************************************************************************/ 321 322 typedef union ii_ilapr_u { 323 shubreg_t ii_ilapr_regval; 324 struct { 325 shubreg_t i_region : 64; 326 } ii_ilapr_fld_s; 327 } ii_ilapr_u_t; 328 329 330 331 332 /************************************************************************ 333 * * 334 * Description: A write to this register of the 64-bit value * 335 * "SGIrules" in ASCII, will cause the bit in the ILAPR register * 336 * corresponding to the region of the requestor to be set (allow * 337 * access). A write of any other value will be ignored. Access * 338 * protection for this register is "SGIrules". * 339 * This register can also be accessed through the IAlias space. * 340 * However, this access will not change the access permissions in the * 341 * ILAPR. * 342 * * 343 ************************************************************************/ 344 345 typedef union ii_ilapo_u { 346 shubreg_t ii_ilapo_regval; 347 struct { 348 shubreg_t i_io_ovrride : 64; 349 } ii_ilapo_fld_s; 350 } ii_ilapo_u_t; 351 352 353 354 /************************************************************************ 355 * * 356 * This register qualifies all the PIO and Graphics writes launched * 357 * from the SHUB towards a widget. * 358 * * 359 ************************************************************************/ 360 361 typedef union ii_iowa_u { 362 shubreg_t ii_iowa_regval; 363 struct { 364 shubreg_t i_w0_oac : 1; 365 shubreg_t i_rsvd_1 : 7; 366 shubreg_t i_wx_oac : 8; 367 shubreg_t i_rsvd : 48; 368 } ii_iowa_fld_s; 369 } ii_iowa_u_t; 370 371 372 /************************************************************************ 373 * * 374 * Description: This register qualifies all the requests launched * 375 * from a widget towards the Shub. This register is intended to be * 376 * used by software in case of misbehaving widgets. * 377 * * 378 * * 379 ************************************************************************/ 380 381 typedef union ii_iiwa_u { 382 shubreg_t ii_iiwa_regval; 383 struct { 384 shubreg_t i_w0_iac : 1; 385 shubreg_t i_rsvd_1 : 7; 386 shubreg_t i_wx_iac : 8; 387 shubreg_t i_rsvd : 48; 388 } ii_iiwa_fld_s; 389 } ii_iiwa_u_t; 390 391 392 393 /************************************************************************ 394 * * 395 * Description: This register qualifies all the operations launched * 396 * from a widget towards the SHub. It allows individual access * 397 * control for up to 8 devices per widget. A device refers to * 398 * individual DMA master hosted by a widget. * 399 * The bits in each field of this register are cleared by the Shub * 400 * upon detection of an error which requires the device to be * 401 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric * 402 * Crosstalk). Whether or not a device has access rights to this * 403 * Shub is determined by an AND of the device enable bit in the * 404 * appropriate field of this register and the corresponding bit in * 405 * the Wx_IAC field (for the widget which this device belongs to). * 406 * The bits in this field are set by writing a 1 to them. Incoming * 407 * replies from Crosstalk are not subject to this access control * 408 * mechanism. * 409 * * 410 ************************************************************************/ 411 412 typedef union ii_iidem_u { 413 shubreg_t ii_iidem_regval; 414 struct { 415 shubreg_t i_w8_dxs : 8; 416 shubreg_t i_w9_dxs : 8; 417 shubreg_t i_wa_dxs : 8; 418 shubreg_t i_wb_dxs : 8; 419 shubreg_t i_wc_dxs : 8; 420 shubreg_t i_wd_dxs : 8; 421 shubreg_t i_we_dxs : 8; 422 shubreg_t i_wf_dxs : 8; 423 } ii_iidem_fld_s; 424 } ii_iidem_u_t; 425 426 427 /************************************************************************ 428 * * 429 * This register contains the various programmable fields necessary * 430 * for controlling and observing the LLP signals. * 431 * * 432 ************************************************************************/ 433 434 typedef union ii_ilcsr_u { 435 shubreg_t ii_ilcsr_regval; 436 struct { 437 shubreg_t i_nullto : 6; 438 shubreg_t i_rsvd_4 : 2; 439 shubreg_t i_wrmrst : 1; 440 shubreg_t i_rsvd_3 : 1; 441 shubreg_t i_llp_en : 1; 442 shubreg_t i_bm8 : 1; 443 shubreg_t i_llp_stat : 2; 444 shubreg_t i_remote_power : 1; 445 shubreg_t i_rsvd_2 : 1; 446 shubreg_t i_maxrtry : 10; 447 shubreg_t i_d_avail_sel : 2; 448 shubreg_t i_rsvd_1 : 4; 449 shubreg_t i_maxbrst : 10; 450 shubreg_t i_rsvd : 22; 451 452 } ii_ilcsr_fld_s; 453 } ii_ilcsr_u_t; 454 455 456 /************************************************************************ 457 * * 458 * This is simply a status registers that monitors the LLP error * 459 * rate. * 460 * * 461 ************************************************************************/ 462 463 typedef union ii_illr_u { 464 shubreg_t ii_illr_regval; 465 struct { 466 shubreg_t i_sn_cnt : 16; 467 shubreg_t i_cb_cnt : 16; 468 shubreg_t i_rsvd : 32; 469 } ii_illr_fld_s; 470 } ii_illr_u_t; 471 472 473 /************************************************************************ 474 * * 475 * Description: All II-detected non-BTE error interrupts are * 476 * specified via this register. * 477 * NOTE: The PI interrupt register address is hardcoded in the II. If * 478 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI * 479 * packet) to address offset 0x0180_0090 within the local register * 480 * address space of PI0 on the node specified by the NODE field. If * 481 * PI_ID==1, then the II sends the interrupt request to address * 482 * offset 0x01A0_0090 within the local register address space of PI1 * 483 * on the node specified by the NODE field. * 484 * * 485 ************************************************************************/ 486 487 typedef union ii_iidsr_u { 488 shubreg_t ii_iidsr_regval; 489 struct { 490 shubreg_t i_level : 8; 491 shubreg_t i_pi_id : 1; 492 shubreg_t i_node : 11; 493 shubreg_t i_rsvd_3 : 4; 494 shubreg_t i_enable : 1; 495 shubreg_t i_rsvd_2 : 3; 496 shubreg_t i_int_sent : 2; 497 shubreg_t i_rsvd_1 : 2; 498 shubreg_t i_pi0_forward_int : 1; 499 shubreg_t i_pi1_forward_int : 1; 500 shubreg_t i_rsvd : 30; 501 } ii_iidsr_fld_s; 502 } ii_iidsr_u_t; 503 504 505 506 /************************************************************************ 507 * * 508 * There are two instances of this register. This register is used * 509 * for matching up the incoming responses from the graphics widget to * 510 * the processor that initiated the graphics operation. The * 511 * write-responses are converted to graphics credits and returned to * 512 * the processor so that the processor interface can manage the flow * 513 * control. * 514 * * 515 ************************************************************************/ 516 517 typedef union ii_igfx0_u { 518 shubreg_t ii_igfx0_regval; 519 struct { 520 shubreg_t i_w_num : 4; 521 shubreg_t i_pi_id : 1; 522 shubreg_t i_n_num : 12; 523 shubreg_t i_p_num : 1; 524 shubreg_t i_rsvd : 46; 525 } ii_igfx0_fld_s; 526 } ii_igfx0_u_t; 527 528 529 /************************************************************************ 530 * * 531 * There are two instances of this register. This register is used * 532 * for matching up the incoming responses from the graphics widget to * 533 * the processor that initiated the graphics operation. The * 534 * write-responses are converted to graphics credits and returned to * 535 * the processor so that the processor interface can manage the flow * 536 * control. * 537 * * 538 ************************************************************************/ 539 540 typedef union ii_igfx1_u { 541 shubreg_t ii_igfx1_regval; 542 struct { 543 shubreg_t i_w_num : 4; 544 shubreg_t i_pi_id : 1; 545 shubreg_t i_n_num : 12; 546 shubreg_t i_p_num : 1; 547 shubreg_t i_rsvd : 46; 548 } ii_igfx1_fld_s; 549 } ii_igfx1_u_t; 550 551 552 /************************************************************************ 553 * * 554 * There are two instances of this registers. These registers are * 555 * used as scratch registers for software use. * 556 * * 557 ************************************************************************/ 558 559 typedef union ii_iscr0_u { 560 shubreg_t ii_iscr0_regval; 561 struct { 562 shubreg_t i_scratch : 64; 563 } ii_iscr0_fld_s; 564 } ii_iscr0_u_t; 565 566 567 568 /************************************************************************ 569 * * 570 * There are two instances of this registers. These registers are * 571 * used as scratch registers for software use. * 572 * * 573 ************************************************************************/ 574 575 typedef union ii_iscr1_u { 576 shubreg_t ii_iscr1_regval; 577 struct { 578 shubreg_t i_scratch : 64; 579 } ii_iscr1_fld_s; 580 } ii_iscr1_u_t; 581 582 583 /************************************************************************ 584 * * 585 * Description: There are seven instances of translation table entry * 586 * registers. Each register maps a Shub Big Window to a 48-bit * 587 * address on Crosstalk. * 588 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 589 * number) are used to select one of these 7 registers. The Widget * 590 * number field is then derived from the W_NUM field for synthesizing * 591 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 592 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 593 * are padded with zeros. Although the maximum Crosstalk space * 594 * addressable by the SHub is thus the lower 16 GBytes per widget * 595 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 596 * space can be accessed. * 597 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 598 * Window number) are used to select one of these 7 registers. The * 599 * Widget number field is then derived from the W_NUM field for * 600 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 601 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 602 * field is used as Crosstalk[47], and remainder of the Crosstalk * 603 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 604 * Crosstalk space addressable by the Shub is thus the lower * 605 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 606 * of this space can be accessed. * 607 * * 608 ************************************************************************/ 609 610 typedef union ii_itte1_u { 611 shubreg_t ii_itte1_regval; 612 struct { 613 shubreg_t i_offset : 5; 614 shubreg_t i_rsvd_1 : 3; 615 shubreg_t i_w_num : 4; 616 shubreg_t i_iosp : 1; 617 shubreg_t i_rsvd : 51; 618 } ii_itte1_fld_s; 619 } ii_itte1_u_t; 620 621 622 /************************************************************************ 623 * * 624 * Description: There are seven instances of translation table entry * 625 * registers. Each register maps a Shub Big Window to a 48-bit * 626 * address on Crosstalk. * 627 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 628 * number) are used to select one of these 7 registers. The Widget * 629 * number field is then derived from the W_NUM field for synthesizing * 630 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 631 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 632 * are padded with zeros. Although the maximum Crosstalk space * 633 * addressable by the Shub is thus the lower 16 GBytes per widget * 634 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 635 * space can be accessed. * 636 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 637 * Window number) are used to select one of these 7 registers. The * 638 * Widget number field is then derived from the W_NUM field for * 639 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 640 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 641 * field is used as Crosstalk[47], and remainder of the Crosstalk * 642 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 643 * Crosstalk space addressable by the Shub is thus the lower * 644 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 645 * of this space can be accessed. * 646 * * 647 ************************************************************************/ 648 649 typedef union ii_itte2_u { 650 shubreg_t ii_itte2_regval; 651 struct { 652 shubreg_t i_offset : 5; 653 shubreg_t i_rsvd_1 : 3; 654 shubreg_t i_w_num : 4; 655 shubreg_t i_iosp : 1; 656 shubreg_t i_rsvd : 51; 657 } ii_itte2_fld_s; 658 } ii_itte2_u_t; 659 660 661 /************************************************************************ 662 * * 663 * Description: There are seven instances of translation table entry * 664 * registers. Each register maps a Shub Big Window to a 48-bit * 665 * address on Crosstalk. * 666 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 667 * number) are used to select one of these 7 registers. The Widget * 668 * number field is then derived from the W_NUM field for synthesizing * 669 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 670 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 671 * are padded with zeros. Although the maximum Crosstalk space * 672 * addressable by the Shub is thus the lower 16 GBytes per widget * 673 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 674 * space can be accessed. * 675 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 676 * Window number) are used to select one of these 7 registers. The * 677 * Widget number field is then derived from the W_NUM field for * 678 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 679 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 680 * field is used as Crosstalk[47], and remainder of the Crosstalk * 681 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 682 * Crosstalk space addressable by the SHub is thus the lower * 683 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 684 * of this space can be accessed. * 685 * * 686 ************************************************************************/ 687 688 typedef union ii_itte3_u { 689 shubreg_t ii_itte3_regval; 690 struct { 691 shubreg_t i_offset : 5; 692 shubreg_t i_rsvd_1 : 3; 693 shubreg_t i_w_num : 4; 694 shubreg_t i_iosp : 1; 695 shubreg_t i_rsvd : 51; 696 } ii_itte3_fld_s; 697 } ii_itte3_u_t; 698 699 700 /************************************************************************ 701 * * 702 * Description: There are seven instances of translation table entry * 703 * registers. Each register maps a SHub Big Window to a 48-bit * 704 * address on Crosstalk. * 705 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 706 * number) are used to select one of these 7 registers. The Widget * 707 * number field is then derived from the W_NUM field for synthesizing * 708 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 709 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 710 * are padded with zeros. Although the maximum Crosstalk space * 711 * addressable by the SHub is thus the lower 16 GBytes per widget * 712 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 713 * space can be accessed. * 714 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 715 * Window number) are used to select one of these 7 registers. The * 716 * Widget number field is then derived from the W_NUM field for * 717 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 718 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 719 * field is used as Crosstalk[47], and remainder of the Crosstalk * 720 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 721 * Crosstalk space addressable by the SHub is thus the lower * 722 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 723 * of this space can be accessed. * 724 * * 725 ************************************************************************/ 726 727 typedef union ii_itte4_u { 728 shubreg_t ii_itte4_regval; 729 struct { 730 shubreg_t i_offset : 5; 731 shubreg_t i_rsvd_1 : 3; 732 shubreg_t i_w_num : 4; 733 shubreg_t i_iosp : 1; 734 shubreg_t i_rsvd : 51; 735 } ii_itte4_fld_s; 736 } ii_itte4_u_t; 737 738 739 /************************************************************************ 740 * * 741 * Description: There are seven instances of translation table entry * 742 * registers. Each register maps a SHub Big Window to a 48-bit * 743 * address on Crosstalk. * 744 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 745 * number) are used to select one of these 7 registers. The Widget * 746 * number field is then derived from the W_NUM field for synthesizing * 747 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 748 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 749 * are padded with zeros. Although the maximum Crosstalk space * 750 * addressable by the Shub is thus the lower 16 GBytes per widget * 751 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 752 * space can be accessed. * 753 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 754 * Window number) are used to select one of these 7 registers. The * 755 * Widget number field is then derived from the W_NUM field for * 756 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 757 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 758 * field is used as Crosstalk[47], and remainder of the Crosstalk * 759 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 760 * Crosstalk space addressable by the Shub is thus the lower * 761 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 762 * of this space can be accessed. * 763 * * 764 ************************************************************************/ 765 766 typedef union ii_itte5_u { 767 shubreg_t ii_itte5_regval; 768 struct { 769 shubreg_t i_offset : 5; 770 shubreg_t i_rsvd_1 : 3; 771 shubreg_t i_w_num : 4; 772 shubreg_t i_iosp : 1; 773 shubreg_t i_rsvd : 51; 774 } ii_itte5_fld_s; 775 } ii_itte5_u_t; 776 777 778 /************************************************************************ 779 * * 780 * Description: There are seven instances of translation table entry * 781 * registers. Each register maps a Shub Big Window to a 48-bit * 782 * address on Crosstalk. * 783 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 784 * number) are used to select one of these 7 registers. The Widget * 785 * number field is then derived from the W_NUM field for synthesizing * 786 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 787 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 788 * are padded with zeros. Although the maximum Crosstalk space * 789 * addressable by the Shub is thus the lower 16 GBytes per widget * 790 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 791 * space can be accessed. * 792 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 793 * Window number) are used to select one of these 7 registers. The * 794 * Widget number field is then derived from the W_NUM field for * 795 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 796 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 797 * field is used as Crosstalk[47], and remainder of the Crosstalk * 798 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 799 * Crosstalk space addressable by the Shub is thus the lower * 800 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 801 * of this space can be accessed. * 802 * * 803 ************************************************************************/ 804 805 typedef union ii_itte6_u { 806 shubreg_t ii_itte6_regval; 807 struct { 808 shubreg_t i_offset : 5; 809 shubreg_t i_rsvd_1 : 3; 810 shubreg_t i_w_num : 4; 811 shubreg_t i_iosp : 1; 812 shubreg_t i_rsvd : 51; 813 } ii_itte6_fld_s; 814 } ii_itte6_u_t; 815 816 817 /************************************************************************ 818 * * 819 * Description: There are seven instances of translation table entry * 820 * registers. Each register maps a Shub Big Window to a 48-bit * 821 * address on Crosstalk. * 822 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * 823 * number) are used to select one of these 7 registers. The Widget * 824 * number field is then derived from the W_NUM field for synthesizing * 825 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * 826 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * 827 * are padded with zeros. Although the maximum Crosstalk space * 828 * addressable by the Shub is thus the lower 16 GBytes per widget * 829 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * 830 * space can be accessed. * 831 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * 832 * Window number) are used to select one of these 7 registers. The * 833 * Widget number field is then derived from the W_NUM field for * 834 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * 835 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * 836 * field is used as Crosstalk[47], and remainder of the Crosstalk * 837 * address bits (Crosstalk[46:34]) are always zero. While the maximum * 838 * Crosstalk space addressable by the SHub is thus the lower * 839 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * 840 * of this space can be accessed. * 841 * * 842 ************************************************************************/ 843 844 typedef union ii_itte7_u { 845 shubreg_t ii_itte7_regval; 846 struct { 847 shubreg_t i_offset : 5; 848 shubreg_t i_rsvd_1 : 3; 849 shubreg_t i_w_num : 4; 850 shubreg_t i_iosp : 1; 851 shubreg_t i_rsvd : 51; 852 } ii_itte7_fld_s; 853 } ii_itte7_u_t; 854 855 856 /************************************************************************ 857 * * 858 * Description: There are 9 instances of this register, one per * 859 * actual widget in this implementation of SHub and Crossbow. * 860 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 861 * refers to Crossbow's internal space. * 862 * This register contains the state elements per widget that are * 863 * necessary to manage the PIO flow control on Crosstalk and on the * 864 * Router Network. See the PIO Flow Control chapter for a complete * 865 * description of this register * 866 * The SPUR_WR bit requires some explanation. When this register is * 867 * written, the new value of the C field is captured in an internal * 868 * register so the hardware can remember what the programmer wrote * 869 * into the credit counter. The SPUR_WR bit sets whenever the C field * 870 * increments above this stored value, which indicates that there * 871 * have been more responses received than requests sent. The SPUR_WR * 872 * bit cannot be cleared until a value is written to the IPRBx * 873 * register; the write will correct the C field and capture its new * 874 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 875 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 876 * . * 877 * * 878 ************************************************************************/ 879 880 typedef union ii_iprb0_u { 881 shubreg_t ii_iprb0_regval; 882 struct { 883 shubreg_t i_c : 8; 884 shubreg_t i_na : 14; 885 shubreg_t i_rsvd_2 : 2; 886 shubreg_t i_nb : 14; 887 shubreg_t i_rsvd_1 : 2; 888 shubreg_t i_m : 2; 889 shubreg_t i_f : 1; 890 shubreg_t i_of_cnt : 5; 891 shubreg_t i_error : 1; 892 shubreg_t i_rd_to : 1; 893 shubreg_t i_spur_wr : 1; 894 shubreg_t i_spur_rd : 1; 895 shubreg_t i_rsvd : 11; 896 shubreg_t i_mult_err : 1; 897 } ii_iprb0_fld_s; 898 } ii_iprb0_u_t; 899 900 901 /************************************************************************ 902 * * 903 * Description: There are 9 instances of this register, one per * 904 * actual widget in this implementation of SHub and Crossbow. * 905 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 906 * refers to Crossbow's internal space. * 907 * This register contains the state elements per widget that are * 908 * necessary to manage the PIO flow control on Crosstalk and on the * 909 * Router Network. See the PIO Flow Control chapter for a complete * 910 * description of this register * 911 * The SPUR_WR bit requires some explanation. When this register is * 912 * written, the new value of the C field is captured in an internal * 913 * register so the hardware can remember what the programmer wrote * 914 * into the credit counter. The SPUR_WR bit sets whenever the C field * 915 * increments above this stored value, which indicates that there * 916 * have been more responses received than requests sent. The SPUR_WR * 917 * bit cannot be cleared until a value is written to the IPRBx * 918 * register; the write will correct the C field and capture its new * 919 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 920 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 921 * . * 922 * * 923 ************************************************************************/ 924 925 typedef union ii_iprb8_u { 926 shubreg_t ii_iprb8_regval; 927 struct { 928 shubreg_t i_c : 8; 929 shubreg_t i_na : 14; 930 shubreg_t i_rsvd_2 : 2; 931 shubreg_t i_nb : 14; 932 shubreg_t i_rsvd_1 : 2; 933 shubreg_t i_m : 2; 934 shubreg_t i_f : 1; 935 shubreg_t i_of_cnt : 5; 936 shubreg_t i_error : 1; 937 shubreg_t i_rd_to : 1; 938 shubreg_t i_spur_wr : 1; 939 shubreg_t i_spur_rd : 1; 940 shubreg_t i_rsvd : 11; 941 shubreg_t i_mult_err : 1; 942 } ii_iprb8_fld_s; 943 } ii_iprb8_u_t; 944 945 946 /************************************************************************ 947 * * 948 * Description: There are 9 instances of this register, one per * 949 * actual widget in this implementation of SHub and Crossbow. * 950 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 951 * refers to Crossbow's internal space. * 952 * This register contains the state elements per widget that are * 953 * necessary to manage the PIO flow control on Crosstalk and on the * 954 * Router Network. See the PIO Flow Control chapter for a complete * 955 * description of this register * 956 * The SPUR_WR bit requires some explanation. When this register is * 957 * written, the new value of the C field is captured in an internal * 958 * register so the hardware can remember what the programmer wrote * 959 * into the credit counter. The SPUR_WR bit sets whenever the C field * 960 * increments above this stored value, which indicates that there * 961 * have been more responses received than requests sent. The SPUR_WR * 962 * bit cannot be cleared until a value is written to the IPRBx * 963 * register; the write will correct the C field and capture its new * 964 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 965 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 966 * . * 967 * * 968 ************************************************************************/ 969 970 typedef union ii_iprb9_u { 971 shubreg_t ii_iprb9_regval; 972 struct { 973 shubreg_t i_c : 8; 974 shubreg_t i_na : 14; 975 shubreg_t i_rsvd_2 : 2; 976 shubreg_t i_nb : 14; 977 shubreg_t i_rsvd_1 : 2; 978 shubreg_t i_m : 2; 979 shubreg_t i_f : 1; 980 shubreg_t i_of_cnt : 5; 981 shubreg_t i_error : 1; 982 shubreg_t i_rd_to : 1; 983 shubreg_t i_spur_wr : 1; 984 shubreg_t i_spur_rd : 1; 985 shubreg_t i_rsvd : 11; 986 shubreg_t i_mult_err : 1; 987 } ii_iprb9_fld_s; 988 } ii_iprb9_u_t; 989 990 991 /************************************************************************ 992 * * 993 * Description: There are 9 instances of this register, one per * 994 * actual widget in this implementation of SHub and Crossbow. * 995 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 996 * refers to Crossbow's internal space. * 997 * This register contains the state elements per widget that are * 998 * necessary to manage the PIO flow control on Crosstalk and on the * 999 * Router Network. See the PIO Flow Control chapter for a complete * 1000 * description of this register * 1001 * The SPUR_WR bit requires some explanation. When this register is * 1002 * written, the new value of the C field is captured in an internal * 1003 * register so the hardware can remember what the programmer wrote * 1004 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1005 * increments above this stored value, which indicates that there * 1006 * have been more responses received than requests sent. The SPUR_WR * 1007 * bit cannot be cleared until a value is written to the IPRBx * 1008 * register; the write will correct the C field and capture its new * 1009 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1010 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1011 * * 1012 * * 1013 ************************************************************************/ 1014 1015 typedef union ii_iprba_u { 1016 shubreg_t ii_iprba_regval; 1017 struct { 1018 shubreg_t i_c : 8; 1019 shubreg_t i_na : 14; 1020 shubreg_t i_rsvd_2 : 2; 1021 shubreg_t i_nb : 14; 1022 shubreg_t i_rsvd_1 : 2; 1023 shubreg_t i_m : 2; 1024 shubreg_t i_f : 1; 1025 shubreg_t i_of_cnt : 5; 1026 shubreg_t i_error : 1; 1027 shubreg_t i_rd_to : 1; 1028 shubreg_t i_spur_wr : 1; 1029 shubreg_t i_spur_rd : 1; 1030 shubreg_t i_rsvd : 11; 1031 shubreg_t i_mult_err : 1; 1032 } ii_iprba_fld_s; 1033 } ii_iprba_u_t; 1034 1035 1036 /************************************************************************ 1037 * * 1038 * Description: There are 9 instances of this register, one per * 1039 * actual widget in this implementation of SHub and Crossbow. * 1040 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1041 * refers to Crossbow's internal space. * 1042 * This register contains the state elements per widget that are * 1043 * necessary to manage the PIO flow control on Crosstalk and on the * 1044 * Router Network. See the PIO Flow Control chapter for a complete * 1045 * description of this register * 1046 * The SPUR_WR bit requires some explanation. When this register is * 1047 * written, the new value of the C field is captured in an internal * 1048 * register so the hardware can remember what the programmer wrote * 1049 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1050 * increments above this stored value, which indicates that there * 1051 * have been more responses received than requests sent. The SPUR_WR * 1052 * bit cannot be cleared until a value is written to the IPRBx * 1053 * register; the write will correct the C field and capture its new * 1054 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1055 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1056 * . * 1057 * * 1058 ************************************************************************/ 1059 1060 typedef union ii_iprbb_u { 1061 shubreg_t ii_iprbb_regval; 1062 struct { 1063 shubreg_t i_c : 8; 1064 shubreg_t i_na : 14; 1065 shubreg_t i_rsvd_2 : 2; 1066 shubreg_t i_nb : 14; 1067 shubreg_t i_rsvd_1 : 2; 1068 shubreg_t i_m : 2; 1069 shubreg_t i_f : 1; 1070 shubreg_t i_of_cnt : 5; 1071 shubreg_t i_error : 1; 1072 shubreg_t i_rd_to : 1; 1073 shubreg_t i_spur_wr : 1; 1074 shubreg_t i_spur_rd : 1; 1075 shubreg_t i_rsvd : 11; 1076 shubreg_t i_mult_err : 1; 1077 } ii_iprbb_fld_s; 1078 } ii_iprbb_u_t; 1079 1080 1081 /************************************************************************ 1082 * * 1083 * Description: There are 9 instances of this register, one per * 1084 * actual widget in this implementation of SHub and Crossbow. * 1085 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1086 * refers to Crossbow's internal space. * 1087 * This register contains the state elements per widget that are * 1088 * necessary to manage the PIO flow control on Crosstalk and on the * 1089 * Router Network. See the PIO Flow Control chapter for a complete * 1090 * description of this register * 1091 * The SPUR_WR bit requires some explanation. When this register is * 1092 * written, the new value of the C field is captured in an internal * 1093 * register so the hardware can remember what the programmer wrote * 1094 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1095 * increments above this stored value, which indicates that there * 1096 * have been more responses received than requests sent. The SPUR_WR * 1097 * bit cannot be cleared until a value is written to the IPRBx * 1098 * register; the write will correct the C field and capture its new * 1099 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1100 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1101 * . * 1102 * * 1103 ************************************************************************/ 1104 1105 typedef union ii_iprbc_u { 1106 shubreg_t ii_iprbc_regval; 1107 struct { 1108 shubreg_t i_c : 8; 1109 shubreg_t i_na : 14; 1110 shubreg_t i_rsvd_2 : 2; 1111 shubreg_t i_nb : 14; 1112 shubreg_t i_rsvd_1 : 2; 1113 shubreg_t i_m : 2; 1114 shubreg_t i_f : 1; 1115 shubreg_t i_of_cnt : 5; 1116 shubreg_t i_error : 1; 1117 shubreg_t i_rd_to : 1; 1118 shubreg_t i_spur_wr : 1; 1119 shubreg_t i_spur_rd : 1; 1120 shubreg_t i_rsvd : 11; 1121 shubreg_t i_mult_err : 1; 1122 } ii_iprbc_fld_s; 1123 } ii_iprbc_u_t; 1124 1125 1126 /************************************************************************ 1127 * * 1128 * Description: There are 9 instances of this register, one per * 1129 * actual widget in this implementation of SHub and Crossbow. * 1130 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1131 * refers to Crossbow's internal space. * 1132 * This register contains the state elements per widget that are * 1133 * necessary to manage the PIO flow control on Crosstalk and on the * 1134 * Router Network. See the PIO Flow Control chapter for a complete * 1135 * description of this register * 1136 * The SPUR_WR bit requires some explanation. When this register is * 1137 * written, the new value of the C field is captured in an internal * 1138 * register so the hardware can remember what the programmer wrote * 1139 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1140 * increments above this stored value, which indicates that there * 1141 * have been more responses received than requests sent. The SPUR_WR * 1142 * bit cannot be cleared until a value is written to the IPRBx * 1143 * register; the write will correct the C field and capture its new * 1144 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1145 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1146 * . * 1147 * * 1148 ************************************************************************/ 1149 1150 typedef union ii_iprbd_u { 1151 shubreg_t ii_iprbd_regval; 1152 struct { 1153 shubreg_t i_c : 8; 1154 shubreg_t i_na : 14; 1155 shubreg_t i_rsvd_2 : 2; 1156 shubreg_t i_nb : 14; 1157 shubreg_t i_rsvd_1 : 2; 1158 shubreg_t i_m : 2; 1159 shubreg_t i_f : 1; 1160 shubreg_t i_of_cnt : 5; 1161 shubreg_t i_error : 1; 1162 shubreg_t i_rd_to : 1; 1163 shubreg_t i_spur_wr : 1; 1164 shubreg_t i_spur_rd : 1; 1165 shubreg_t i_rsvd : 11; 1166 shubreg_t i_mult_err : 1; 1167 } ii_iprbd_fld_s; 1168 } ii_iprbd_u_t; 1169 1170 1171 /************************************************************************ 1172 * * 1173 * Description: There are 9 instances of this register, one per * 1174 * actual widget in this implementation of SHub and Crossbow. * 1175 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1176 * refers to Crossbow's internal space. * 1177 * This register contains the state elements per widget that are * 1178 * necessary to manage the PIO flow control on Crosstalk and on the * 1179 * Router Network. See the PIO Flow Control chapter for a complete * 1180 * description of this register * 1181 * The SPUR_WR bit requires some explanation. When this register is * 1182 * written, the new value of the C field is captured in an internal * 1183 * register so the hardware can remember what the programmer wrote * 1184 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1185 * increments above this stored value, which indicates that there * 1186 * have been more responses received than requests sent. The SPUR_WR * 1187 * bit cannot be cleared until a value is written to the IPRBx * 1188 * register; the write will correct the C field and capture its new * 1189 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1190 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1191 * . * 1192 * * 1193 ************************************************************************/ 1194 1195 typedef union ii_iprbe_u { 1196 shubreg_t ii_iprbe_regval; 1197 struct { 1198 shubreg_t i_c : 8; 1199 shubreg_t i_na : 14; 1200 shubreg_t i_rsvd_2 : 2; 1201 shubreg_t i_nb : 14; 1202 shubreg_t i_rsvd_1 : 2; 1203 shubreg_t i_m : 2; 1204 shubreg_t i_f : 1; 1205 shubreg_t i_of_cnt : 5; 1206 shubreg_t i_error : 1; 1207 shubreg_t i_rd_to : 1; 1208 shubreg_t i_spur_wr : 1; 1209 shubreg_t i_spur_rd : 1; 1210 shubreg_t i_rsvd : 11; 1211 shubreg_t i_mult_err : 1; 1212 } ii_iprbe_fld_s; 1213 } ii_iprbe_u_t; 1214 1215 1216 /************************************************************************ 1217 * * 1218 * Description: There are 9 instances of this register, one per * 1219 * actual widget in this implementation of Shub and Crossbow. * 1220 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * 1221 * refers to Crossbow's internal space. * 1222 * This register contains the state elements per widget that are * 1223 * necessary to manage the PIO flow control on Crosstalk and on the * 1224 * Router Network. See the PIO Flow Control chapter for a complete * 1225 * description of this register * 1226 * The SPUR_WR bit requires some explanation. When this register is * 1227 * written, the new value of the C field is captured in an internal * 1228 * register so the hardware can remember what the programmer wrote * 1229 * into the credit counter. The SPUR_WR bit sets whenever the C field * 1230 * increments above this stored value, which indicates that there * 1231 * have been more responses received than requests sent. The SPUR_WR * 1232 * bit cannot be cleared until a value is written to the IPRBx * 1233 * register; the write will correct the C field and capture its new * 1234 * value in the internal register. Even if IECLR[E_PRB_x] is set, the * 1235 * SPUR_WR bit will persist if IPRBx hasn't yet been written. * 1236 * . * 1237 * * 1238 ************************************************************************/ 1239 1240 typedef union ii_iprbf_u { 1241 shubreg_t ii_iprbf_regval; 1242 struct { 1243 shubreg_t i_c : 8; 1244 shubreg_t i_na : 14; 1245 shubreg_t i_rsvd_2 : 2; 1246 shubreg_t i_nb : 14; 1247 shubreg_t i_rsvd_1 : 2; 1248 shubreg_t i_m : 2; 1249 shubreg_t i_f : 1; 1250 shubreg_t i_of_cnt : 5; 1251 shubreg_t i_error : 1; 1252 shubreg_t i_rd_to : 1; 1253 shubreg_t i_spur_wr : 1; 1254 shubreg_t i_spur_rd : 1; 1255 shubreg_t i_rsvd : 11; 1256 shubreg_t i_mult_err : 1; 1257 } ii_iprbe_fld_s; 1258 } ii_iprbf_u_t; 1259 1260 1261 /************************************************************************ 1262 * * 1263 * This register specifies the timeout value to use for monitoring * 1264 * Crosstalk credits which are used outbound to Crosstalk. An * 1265 * internal counter called the Crosstalk Credit Timeout Counter * 1266 * increments every 128 II clocks. The counter starts counting * 1267 * anytime the credit count drops below a threshold, and resets to * 1268 * zero (stops counting) anytime the credit count is at or above the * 1269 * threshold. The threshold is 1 credit in direct connect mode and 2 * 1270 * in Crossbow connect mode. When the internal Crosstalk Credit * 1271 * Timeout Counter reaches the value programmed in this register, a * 1272 * Crosstalk Credit Timeout has occurred. The internal counter is not * 1273 * readable from software, and stops counting at its maximum value, * 1274 * so it cannot cause more than one interrupt. * 1275 * * 1276 ************************************************************************/ 1277 1278 typedef union ii_ixcc_u { 1279 shubreg_t ii_ixcc_regval; 1280 struct { 1281 shubreg_t i_time_out : 26; 1282 shubreg_t i_rsvd : 38; 1283 } ii_ixcc_fld_s; 1284 } ii_ixcc_u_t; 1285 1286 1287 /************************************************************************ 1288 * * 1289 * Description: This register qualifies all the PIO and DMA * 1290 * operations launched from widget 0 towards the SHub. In * 1291 * addition, it also qualifies accesses by the BTE streams. * 1292 * The bits in each field of this register are cleared by the SHub * 1293 * upon detection of an error which requires widget 0 or the BTE * 1294 * streams to be terminated. Whether or not widget x has access * 1295 * rights to this SHub is determined by an AND of the device * 1296 * enable bit in the appropriate field of this register and bit 0 in * 1297 * the Wx_IAC field. The bits in this field are set by writing a 1 to * 1298 * them. Incoming replies from Crosstalk are not subject to this * 1299 * access control mechanism. * 1300 * * 1301 ************************************************************************/ 1302 1303 typedef union ii_imem_u { 1304 shubreg_t ii_imem_regval; 1305 struct { 1306 shubreg_t i_w0_esd : 1; 1307 shubreg_t i_rsvd_3 : 3; 1308 shubreg_t i_b0_esd : 1; 1309 shubreg_t i_rsvd_2 : 3; 1310 shubreg_t i_b1_esd : 1; 1311 shubreg_t i_rsvd_1 : 3; 1312 shubreg_t i_clr_precise : 1; 1313 shubreg_t i_rsvd : 51; 1314 } ii_imem_fld_s; 1315 } ii_imem_u_t; 1316 1317 1318 1319 /************************************************************************ 1320 * * 1321 * Description: This register specifies the timeout value to use for * 1322 * monitoring Crosstalk tail flits coming into the Shub in the * 1323 * TAIL_TO field. An internal counter associated with this register * 1324 * is incremented every 128 II internal clocks (7 bits). The counter * 1325 * starts counting anytime a header micropacket is received and stops * 1326 * counting (and resets to zero) any time a micropacket with a Tail * 1327 * bit is received. Once the counter reaches the threshold value * 1328 * programmed in this register, it generates an interrupt to the * 1329 * processor that is programmed into the IIDSR. The counter saturates * 1330 * (does not roll over) at its maximum value, so it cannot cause * 1331 * another interrupt until after it is cleared. * 1332 * The register also contains the Read Response Timeout values. The * 1333 * Prescalar is 23 bits, and counts II clocks. An internal counter * 1334 * increments on every II clock and when it reaches the value in the * 1335 * Prescalar field, all IPRTE registers with their valid bits set * 1336 * have their Read Response timers bumped. Whenever any of them match * 1337 * the value in the RRSP_TO field, a Read Response Timeout has * 1338 * occurred, and error handling occurs as described in the Error * 1339 * Handling section of this document. * 1340 * * 1341 ************************************************************************/ 1342 1343 typedef union ii_ixtt_u { 1344 shubreg_t ii_ixtt_regval; 1345 struct { 1346 shubreg_t i_tail_to : 26; 1347 shubreg_t i_rsvd_1 : 6; 1348 shubreg_t i_rrsp_ps : 23; 1349 shubreg_t i_rrsp_to : 5; 1350 shubreg_t i_rsvd : 4; 1351 } ii_ixtt_fld_s; 1352 } ii_ixtt_u_t; 1353 1354 1355 /************************************************************************ 1356 * * 1357 * Writing a 1 to the fields of this register clears the appropriate * 1358 * error bits in other areas of SHub. Note that when the * 1359 * E_PRB_x bits are used to clear error bits in PRB registers, * 1360 * SPUR_RD and SPUR_WR may persist, because they require additional * 1361 * action to clear them. See the IPRBx and IXSS Register * 1362 * specifications. * 1363 * * 1364 ************************************************************************/ 1365 1366 typedef union ii_ieclr_u { 1367 shubreg_t ii_ieclr_regval; 1368 struct { 1369 shubreg_t i_e_prb_0 : 1; 1370 shubreg_t i_rsvd : 7; 1371 shubreg_t i_e_prb_8 : 1; 1372 shubreg_t i_e_prb_9 : 1; 1373 shubreg_t i_e_prb_a : 1; 1374 shubreg_t i_e_prb_b : 1; 1375 shubreg_t i_e_prb_c : 1; 1376 shubreg_t i_e_prb_d : 1; 1377 shubreg_t i_e_prb_e : 1; 1378 shubreg_t i_e_prb_f : 1; 1379 shubreg_t i_e_crazy : 1; 1380 shubreg_t i_e_bte_0 : 1; 1381 shubreg_t i_e_bte_1 : 1; 1382 shubreg_t i_reserved_1 : 10; 1383 shubreg_t i_spur_rd_hdr : 1; 1384 shubreg_t i_cam_intr_to : 1; 1385 shubreg_t i_cam_overflow : 1; 1386 shubreg_t i_cam_read_miss : 1; 1387 shubreg_t i_ioq_rep_underflow : 1; 1388 shubreg_t i_ioq_req_underflow : 1; 1389 shubreg_t i_ioq_rep_overflow : 1; 1390 shubreg_t i_ioq_req_overflow : 1; 1391 shubreg_t i_iiq_rep_overflow : 1; 1392 shubreg_t i_iiq_req_overflow : 1; 1393 shubreg_t i_ii_xn_rep_cred_overflow : 1; 1394 shubreg_t i_ii_xn_req_cred_overflow : 1; 1395 shubreg_t i_ii_xn_invalid_cmd : 1; 1396 shubreg_t i_xn_ii_invalid_cmd : 1; 1397 shubreg_t i_reserved_2 : 21; 1398 } ii_ieclr_fld_s; 1399 } ii_ieclr_u_t; 1400 1401 1402 /************************************************************************ 1403 * * 1404 * This register controls both BTEs. SOFT_RESET is intended for * 1405 * recovery after an error. COUNT controls the total number of CRBs * 1406 * that both BTEs (combined) can use, which affects total BTE * 1407 * bandwidth. * 1408 * * 1409 ************************************************************************/ 1410 1411 typedef union ii_ibcr_u { 1412 shubreg_t ii_ibcr_regval; 1413 struct { 1414 shubreg_t i_count : 4; 1415 shubreg_t i_rsvd_1 : 4; 1416 shubreg_t i_soft_reset : 1; 1417 shubreg_t i_rsvd : 55; 1418 } ii_ibcr_fld_s; 1419 } ii_ibcr_u_t; 1420 1421 1422 /************************************************************************ 1423 * * 1424 * This register contains the header of a spurious read response * 1425 * received from Crosstalk. A spurious read response is defined as a * 1426 * read response received by II from a widget for which (1) the SIDN * 1427 * has a value between 1 and 7, inclusive (II never sends requests to * 1428 * these widgets (2) there is no valid IPRTE register which * 1429 * corresponds to the TNUM, or (3) the widget indicated in SIDN is * 1430 * not the same as the widget recorded in the IPRTE register * 1431 * referenced by the TNUM. If this condition is true, and if the * 1432 * IXSS[VALID] bit is clear, then the header of the spurious read * 1433 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * 1434 * errant header is thereby captured, and no further spurious read * 1435 * respones are captured until IXSS[VALID] is cleared by setting the * 1436 * appropriate bit in IECLR.Everytime a spurious read response is * 1437 * detected, the SPUR_RD bit of the PRB corresponding to the incoming * 1438 * message's SIDN field is set. This always happens, regarless of * 1439 * whether a header is captured. The programmer should check * 1440 * IXSM[SIDN] to determine which widget sent the spurious response, * 1441 * because there may be more than one SPUR_RD bit set in the PRB * 1442 * registers. The widget indicated by IXSM[SIDN] was the first * 1443 * spurious read response to be received since the last time * 1444 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB * 1445 * will be set. Any SPUR_RD bits in any other PRB registers indicate * 1446 * spurious messages from other widets which were detected after the * 1447 * header was captured.. * 1448 * * 1449 ************************************************************************/ 1450 1451 typedef union ii_ixsm_u { 1452 shubreg_t ii_ixsm_regval; 1453 struct { 1454 shubreg_t i_byte_en : 32; 1455 shubreg_t i_reserved : 1; 1456 shubreg_t i_tag : 3; 1457 shubreg_t i_alt_pactyp : 4; 1458 shubreg_t i_bo : 1; 1459 shubreg_t i_error : 1; 1460 shubreg_t i_vbpm : 1; 1461 shubreg_t i_gbr : 1; 1462 shubreg_t i_ds : 2; 1463 shubreg_t i_ct : 1; 1464 shubreg_t i_tnum : 5; 1465 shubreg_t i_pactyp : 4; 1466 shubreg_t i_sidn : 4; 1467 shubreg_t i_didn : 4; 1468 } ii_ixsm_fld_s; 1469 } ii_ixsm_u_t; 1470 1471 1472 /************************************************************************ 1473 * * 1474 * This register contains the sideband bits of a spurious read * 1475 * response received from Crosstalk. * 1476 * * 1477 ************************************************************************/ 1478 1479 typedef union ii_ixss_u { 1480 shubreg_t ii_ixss_regval; 1481 struct { 1482 shubreg_t i_sideband : 8; 1483 shubreg_t i_rsvd : 55; 1484 shubreg_t i_valid : 1; 1485 } ii_ixss_fld_s; 1486 } ii_ixss_u_t; 1487 1488 1489 /************************************************************************ 1490 * * 1491 * This register enables software to access the II LLP's test port. * 1492 * Refer to the LLP 2.5 documentation for an explanation of the test * 1493 * port. Software can write to this register to program the values * 1494 * for the control fields (TestErrCapture, TestClear, TestFlit, * 1495 * TestMask and TestSeed). Similarly, software can read from this * 1496 * register to obtain the values of the test port's status outputs * 1497 * (TestCBerr, TestValid and TestData). * 1498 * * 1499 ************************************************************************/ 1500 1501 typedef union ii_ilct_u { 1502 shubreg_t ii_ilct_regval; 1503 struct { 1504 shubreg_t i_test_seed : 20; 1505 shubreg_t i_test_mask : 8; 1506 shubreg_t i_test_data : 20; 1507 shubreg_t i_test_valid : 1; 1508 shubreg_t i_test_cberr : 1; 1509 shubreg_t i_test_flit : 3; 1510 shubreg_t i_test_clear : 1; 1511 shubreg_t i_test_err_capture : 1; 1512 shubreg_t i_rsvd : 9; 1513 } ii_ilct_fld_s; 1514 } ii_ilct_u_t; 1515 1516 1517 /************************************************************************ 1518 * * 1519 * If the II detects an illegal incoming Duplonet packet (request or * 1520 * reply) when VALID==0 in the IIEPH1 register, then it saves the * 1521 * contents of the packet's header flit in the IIEPH1 and IIEPH2 * 1522 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, * 1523 * and assigns a value to the ERR_TYPE field which indicates the * 1524 * specific nature of the error. The II recognizes four different * 1525 * types of errors: short request packets (ERR_TYPE==2), short reply * 1526 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long * 1527 * reply packets (ERR_TYPE==5). The encodings for these types of * 1528 * errors were chosen to be consistent with the same types of errors * 1529 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in * 1530 * the LB unit). If the II detects an illegal incoming Duplonet * 1531 * packet when VALID==1 in the IIEPH1 register, then it merely sets * 1532 * the OVERRUN bit to indicate that a subsequent error has happened, * 1533 * and does nothing further. * 1534 * * 1535 ************************************************************************/ 1536 1537 typedef union ii_iieph1_u { 1538 shubreg_t ii_iieph1_regval; 1539 struct { 1540 shubreg_t i_command : 7; 1541 shubreg_t i_rsvd_5 : 1; 1542 shubreg_t i_suppl : 14; 1543 shubreg_t i_rsvd_4 : 1; 1544 shubreg_t i_source : 14; 1545 shubreg_t i_rsvd_3 : 1; 1546 shubreg_t i_err_type : 4; 1547 shubreg_t i_rsvd_2 : 4; 1548 shubreg_t i_overrun : 1; 1549 shubreg_t i_rsvd_1 : 3; 1550 shubreg_t i_valid : 1; 1551 shubreg_t i_rsvd : 13; 1552 } ii_iieph1_fld_s; 1553 } ii_iieph1_u_t; 1554 1555 1556 /************************************************************************ 1557 * * 1558 * This register holds the Address field from the header flit of an * 1559 * incoming erroneous Duplonet packet, along with the tail bit which * 1560 * accompanied this header flit. This register is essentially an * 1561 * extension of IIEPH1. Two registers were necessary because the 64 * 1562 * bits available in only a single register were insufficient to * 1563 * capture the entire header flit of an erroneous packet. * 1564 * * 1565 ************************************************************************/ 1566 1567 typedef union ii_iieph2_u { 1568 shubreg_t ii_iieph2_regval; 1569 struct { 1570 shubreg_t i_rsvd_0 : 3; 1571 shubreg_t i_address : 47; 1572 shubreg_t i_rsvd_1 : 10; 1573 shubreg_t i_tail : 1; 1574 shubreg_t i_rsvd : 3; 1575 } ii_iieph2_fld_s; 1576 } ii_iieph2_u_t; 1577 1578 1579 /******************************/ 1580 1581 1582 1583 /************************************************************************ 1584 * * 1585 * This register's value is a bit vector that guards access from SXBs * 1586 * to local registers within the II as well as to external Crosstalk * 1587 * widgets * 1588 * * 1589 ************************************************************************/ 1590 1591 typedef union ii_islapr_u { 1592 shubreg_t ii_islapr_regval; 1593 struct { 1594 shubreg_t i_region : 64; 1595 } ii_islapr_fld_s; 1596 } ii_islapr_u_t; 1597 1598 1599 /************************************************************************ 1600 * * 1601 * A write to this register of the 56-bit value "Pup+Bun" will cause * 1602 * the bit in the ISLAPR register corresponding to the region of the * 1603 * requestor to be set (access allowed). ( 1604 * * 1605 ************************************************************************/ 1606 1607 typedef union ii_islapo_u { 1608 shubreg_t ii_islapo_regval; 1609 struct { 1610 shubreg_t i_io_sbx_ovrride : 56; 1611 shubreg_t i_rsvd : 8; 1612 } ii_islapo_fld_s; 1613 } ii_islapo_u_t; 1614 1615 /************************************************************************ 1616 * * 1617 * Determines how long the wrapper will wait aftr an interrupt is * 1618 * initially issued from the II before it times out the outstanding * 1619 * interrupt and drops it from the interrupt queue. * 1620 * * 1621 ************************************************************************/ 1622 1623 typedef union ii_iwi_u { 1624 shubreg_t ii_iwi_regval; 1625 struct { 1626 shubreg_t i_prescale : 24; 1627 shubreg_t i_rsvd : 8; 1628 shubreg_t i_timeout : 8; 1629 shubreg_t i_rsvd1 : 8; 1630 shubreg_t i_intrpt_retry_period : 8; 1631 shubreg_t i_rsvd2 : 8; 1632 } ii_iwi_fld_s; 1633 } ii_iwi_u_t; 1634 1635 /************************************************************************ 1636 * * 1637 * Log errors which have occurred in the II wrapper. The errors are * 1638 * cleared by writing to the IECLR register. * 1639 * * 1640 ************************************************************************/ 1641 1642 typedef union ii_iwel_u { 1643 shubreg_t ii_iwel_regval; 1644 struct { 1645 shubreg_t i_intr_timed_out : 1; 1646 shubreg_t i_rsvd : 7; 1647 shubreg_t i_cam_overflow : 1; 1648 shubreg_t i_cam_read_miss : 1; 1649 shubreg_t i_rsvd1 : 2; 1650 shubreg_t i_ioq_rep_underflow : 1; 1651 shubreg_t i_ioq_req_underflow : 1; 1652 shubreg_t i_ioq_rep_overflow : 1; 1653 shubreg_t i_ioq_req_overflow : 1; 1654 shubreg_t i_iiq_rep_overflow : 1; 1655 shubreg_t i_iiq_req_overflow : 1; 1656 shubreg_t i_rsvd2 : 6; 1657 shubreg_t i_ii_xn_rep_cred_over_under: 1; 1658 shubreg_t i_ii_xn_req_cred_over_under: 1; 1659 shubreg_t i_rsvd3 : 6; 1660 shubreg_t i_ii_xn_invalid_cmd : 1; 1661 shubreg_t i_xn_ii_invalid_cmd : 1; 1662 shubreg_t i_rsvd4 : 30; 1663 } ii_iwel_fld_s; 1664 } ii_iwel_u_t; 1665 1666 /************************************************************************ 1667 * * 1668 * Controls the II wrapper. * 1669 * * 1670 ************************************************************************/ 1671 1672 typedef union ii_iwc_u { 1673 shubreg_t ii_iwc_regval; 1674 struct { 1675 shubreg_t i_dma_byte_swap : 1; 1676 shubreg_t i_rsvd : 3; 1677 shubreg_t i_cam_read_lines_reset : 1; 1678 shubreg_t i_rsvd1 : 3; 1679 shubreg_t i_ii_xn_cred_over_under_log: 1; 1680 shubreg_t i_rsvd2 : 19; 1681 shubreg_t i_xn_rep_iq_depth : 5; 1682 shubreg_t i_rsvd3 : 3; 1683 shubreg_t i_xn_req_iq_depth : 5; 1684 shubreg_t i_rsvd4 : 3; 1685 shubreg_t i_iiq_depth : 6; 1686 shubreg_t i_rsvd5 : 12; 1687 shubreg_t i_force_rep_cred : 1; 1688 shubreg_t i_force_req_cred : 1; 1689 } ii_iwc_fld_s; 1690 } ii_iwc_u_t; 1691 1692 /************************************************************************ 1693 * * 1694 * Status in the II wrapper. * 1695 * * 1696 ************************************************************************/ 1697 1698 typedef union ii_iws_u { 1699 shubreg_t ii_iws_regval; 1700 struct { 1701 shubreg_t i_xn_rep_iq_credits : 5; 1702 shubreg_t i_rsvd : 3; 1703 shubreg_t i_xn_req_iq_credits : 5; 1704 shubreg_t i_rsvd1 : 51; 1705 } ii_iws_fld_s; 1706 } ii_iws_u_t; 1707 1708 /************************************************************************ 1709 * * 1710 * Masks errors in the IWEL register. * 1711 * * 1712 ************************************************************************/ 1713 1714 typedef union ii_iweim_u { 1715 shubreg_t ii_iweim_regval; 1716 struct { 1717 shubreg_t i_intr_timed_out : 1; 1718 shubreg_t i_rsvd : 7; 1719 shubreg_t i_cam_overflow : 1; 1720 shubreg_t i_cam_read_miss : 1; 1721 shubreg_t i_rsvd1 : 2; 1722 shubreg_t i_ioq_rep_underflow : 1; 1723 shubreg_t i_ioq_req_underflow : 1; 1724 shubreg_t i_ioq_rep_overflow : 1; 1725 shubreg_t i_ioq_req_overflow : 1; 1726 shubreg_t i_iiq_rep_overflow : 1; 1727 shubreg_t i_iiq_req_overflow : 1; 1728 shubreg_t i_rsvd2 : 6; 1729 shubreg_t i_ii_xn_rep_cred_overflow : 1; 1730 shubreg_t i_ii_xn_req_cred_overflow : 1; 1731 shubreg_t i_rsvd3 : 6; 1732 shubreg_t i_ii_xn_invalid_cmd : 1; 1733 shubreg_t i_xn_ii_invalid_cmd : 1; 1734 shubreg_t i_rsvd4 : 30; 1735 } ii_iweim_fld_s; 1736 } ii_iweim_u_t; 1737 1738 1739 /************************************************************************ 1740 * * 1741 * A write to this register causes a particular field in the * 1742 * corresponding widget's PRB entry to be adjusted up or down by 1. * 1743 * This counter should be used when recovering from error and reset * 1744 * conditions. Note that software would be capable of causing * 1745 * inadvertent overflow or underflow of these counters. * 1746 * * 1747 ************************************************************************/ 1748 1749 typedef union ii_ipca_u { 1750 shubreg_t ii_ipca_regval; 1751 struct { 1752 shubreg_t i_wid : 4; 1753 shubreg_t i_adjust : 1; 1754 shubreg_t i_rsvd_1 : 3; 1755 shubreg_t i_field : 2; 1756 shubreg_t i_rsvd : 54; 1757 } ii_ipca_fld_s; 1758 } ii_ipca_u_t; 1759 1760 1761 /************************************************************************ 1762 * * 1763 * There are 8 instances of this register. This register contains * 1764 * the information that the II has to remember once it has launched a * 1765 * PIO Read operation. The contents are used to form the correct * 1766 * Router Network packet and direct the Crosstalk reply to the * 1767 * appropriate processor. * 1768 * * 1769 ************************************************************************/ 1770 1771 1772 typedef union ii_iprte0a_u { 1773 shubreg_t ii_iprte0a_regval; 1774 struct { 1775 shubreg_t i_rsvd_1 : 54; 1776 shubreg_t i_widget : 4; 1777 shubreg_t i_to_cnt : 5; 1778 shubreg_t i_vld : 1; 1779 } ii_iprte0a_fld_s; 1780 } ii_iprte0a_u_t; 1781 1782 1783 /************************************************************************ 1784 * * 1785 * There are 8 instances of this register. This register contains * 1786 * the information that the II has to remember once it has launched a * 1787 * PIO Read operation. The contents are used to form the correct * 1788 * Router Network packet and direct the Crosstalk reply to the * 1789 * appropriate processor. * 1790 * * 1791 ************************************************************************/ 1792 1793 typedef union ii_iprte1a_u { 1794 shubreg_t ii_iprte1a_regval; 1795 struct { 1796 shubreg_t i_rsvd_1 : 54; 1797 shubreg_t i_widget : 4; 1798 shubreg_t i_to_cnt : 5; 1799 shubreg_t i_vld : 1; 1800 } ii_iprte1a_fld_s; 1801 } ii_iprte1a_u_t; 1802 1803 1804 /************************************************************************ 1805 * * 1806 * There are 8 instances of this register. This register contains * 1807 * the information that the II has to remember once it has launched a * 1808 * PIO Read operation. The contents are used to form the correct * 1809 * Router Network packet and direct the Crosstalk reply to the * 1810 * appropriate processor. * 1811 * * 1812 ************************************************************************/ 1813 1814 typedef union ii_iprte2a_u { 1815 shubreg_t ii_iprte2a_regval; 1816 struct { 1817 shubreg_t i_rsvd_1 : 54; 1818 shubreg_t i_widget : 4; 1819 shubreg_t i_to_cnt : 5; 1820 shubreg_t i_vld : 1; 1821 } ii_iprte2a_fld_s; 1822 } ii_iprte2a_u_t; 1823 1824 1825 /************************************************************************ 1826 * * 1827 * There are 8 instances of this register. This register contains * 1828 * the information that the II has to remember once it has launched a * 1829 * PIO Read operation. The contents are used to form the correct * 1830 * Router Network packet and direct the Crosstalk reply to the * 1831 * appropriate processor. * 1832 * * 1833 ************************************************************************/ 1834 1835 typedef union ii_iprte3a_u { 1836 shubreg_t ii_iprte3a_regval; 1837 struct { 1838 shubreg_t i_rsvd_1 : 54; 1839 shubreg_t i_widget : 4; 1840 shubreg_t i_to_cnt : 5; 1841 shubreg_t i_vld : 1; 1842 } ii_iprte3a_fld_s; 1843 } ii_iprte3a_u_t; 1844 1845 1846 /************************************************************************ 1847 * * 1848 * There are 8 instances of this register. This register contains * 1849 * the information that the II has to remember once it has launched a * 1850 * PIO Read operation. The contents are used to form the correct * 1851 * Router Network packet and direct the Crosstalk reply to the * 1852 * appropriate processor. * 1853 * * 1854 ************************************************************************/ 1855 1856 typedef union ii_iprte4a_u { 1857 shubreg_t ii_iprte4a_regval; 1858 struct { 1859 shubreg_t i_rsvd_1 : 54; 1860 shubreg_t i_widget : 4; 1861 shubreg_t i_to_cnt : 5; 1862 shubreg_t i_vld : 1; 1863 } ii_iprte4a_fld_s; 1864 } ii_iprte4a_u_t; 1865 1866 1867 /************************************************************************ 1868 * * 1869 * There are 8 instances of this register. This register contains * 1870 * the information that the II has to remember once it has launched a * 1871 * PIO Read operation. The contents are used to form the correct * 1872 * Router Network packet and direct the Crosstalk reply to the * 1873 * appropriate processor. * 1874 * * 1875 ************************************************************************/ 1876 1877 typedef union ii_iprte5a_u { 1878 shubreg_t ii_iprte5a_regval; 1879 struct { 1880 shubreg_t i_rsvd_1 : 54; 1881 shubreg_t i_widget : 4; 1882 shubreg_t i_to_cnt : 5; 1883 shubreg_t i_vld : 1; 1884 } ii_iprte5a_fld_s; 1885 } ii_iprte5a_u_t; 1886 1887 1888 /************************************************************************ 1889 * * 1890 * There are 8 instances of this register. This register contains * 1891 * the information that the II has to remember once it has launched a * 1892 * PIO Read operation. The contents are used to form the correct * 1893 * Router Network packet and direct the Crosstalk reply to the * 1894 * appropriate processor. * 1895 * * 1896 ************************************************************************/ 1897 1898 typedef union ii_iprte6a_u { 1899 shubreg_t ii_iprte6a_regval; 1900 struct { 1901 shubreg_t i_rsvd_1 : 54; 1902 shubreg_t i_widget : 4; 1903 shubreg_t i_to_cnt : 5; 1904 shubreg_t i_vld : 1; 1905 } ii_iprte6a_fld_s; 1906 } ii_iprte6a_u_t; 1907 1908 1909 /************************************************************************ 1910 * * 1911 * There are 8 instances of this register. This register contains * 1912 * the information that the II has to remember once it has launched a * 1913 * PIO Read operation. The contents are used to form the correct * 1914 * Router Network packet and direct the Crosstalk reply to the * 1915 * appropriate processor. * 1916 * * 1917 ************************************************************************/ 1918 1919 typedef union ii_iprte7a_u { 1920 shubreg_t ii_iprte7a_regval; 1921 struct { 1922 shubreg_t i_rsvd_1 : 54; 1923 shubreg_t i_widget : 4; 1924 shubreg_t i_to_cnt : 5; 1925 shubreg_t i_vld : 1; 1926 } ii_iprtea7_fld_s; 1927 } ii_iprte7a_u_t; 1928 1929 1930 1931 /************************************************************************ 1932 * * 1933 * There are 8 instances of this register. This register contains * 1934 * the information that the II has to remember once it has launched a * 1935 * PIO Read operation. The contents are used to form the correct * 1936 * Router Network packet and direct the Crosstalk reply to the * 1937 * appropriate processor. * 1938 * * 1939 ************************************************************************/ 1940 1941 1942 typedef union ii_iprte0b_u { 1943 shubreg_t ii_iprte0b_regval; 1944 struct { 1945 shubreg_t i_rsvd_1 : 3; 1946 shubreg_t i_address : 47; 1947 shubreg_t i_init : 3; 1948 shubreg_t i_source : 11; 1949 } ii_iprte0b_fld_s; 1950 } ii_iprte0b_u_t; 1951 1952 1953 /************************************************************************ 1954 * * 1955 * There are 8 instances of this register. This register contains * 1956 * the information that the II has to remember once it has launched a * 1957 * PIO Read operation. The contents are used to form the correct * 1958 * Router Network packet and direct the Crosstalk reply to the * 1959 * appropriate processor. * 1960 * * 1961 ************************************************************************/ 1962 1963 typedef union ii_iprte1b_u { 1964 shubreg_t ii_iprte1b_regval; 1965 struct { 1966 shubreg_t i_rsvd_1 : 3; 1967 shubreg_t i_address : 47; 1968 shubreg_t i_init : 3; 1969 shubreg_t i_source : 11; 1970 } ii_iprte1b_fld_s; 1971 } ii_iprte1b_u_t; 1972 1973 1974 /************************************************************************ 1975 * * 1976 * There are 8 instances of this register. This register contains * 1977 * the information that the II has to remember once it has launched a * 1978 * PIO Read operation. The contents are used to form the correct * 1979 * Router Network packet and direct the Crosstalk reply to the * 1980 * appropriate processor. * 1981 * * 1982 ************************************************************************/ 1983 1984 typedef union ii_iprte2b_u { 1985 shubreg_t ii_iprte2b_regval; 1986 struct { 1987 shubreg_t i_rsvd_1 : 3; 1988 shubreg_t i_address : 47; 1989 shubreg_t i_init : 3; 1990 shubreg_t i_source : 11; 1991 } ii_iprte2b_fld_s; 1992 } ii_iprte2b_u_t; 1993 1994 1995 /************************************************************************ 1996 * * 1997 * There are 8 instances of this register. This register contains * 1998 * the information that the II has to remember once it has launched a * 1999 * PIO Read operation. The contents are used to form the correct * 2000 * Router Network packet and direct the Crosstalk reply to the * 2001 * appropriate processor. * 2002 * * 2003 ************************************************************************/ 2004 2005 typedef union ii_iprte3b_u { 2006 shubreg_t ii_iprte3b_regval; 2007 struct { 2008 shubreg_t i_rsvd_1 : 3; 2009 shubreg_t i_address : 47; 2010 shubreg_t i_init : 3; 2011 shubreg_t i_source : 11; 2012 } ii_iprte3b_fld_s; 2013 } ii_iprte3b_u_t; 2014 2015 2016 /************************************************************************ 2017 * * 2018 * There are 8 instances of this register. This register contains * 2019 * the information that the II has to remember once it has launched a * 2020 * PIO Read operation. The contents are used to form the correct * 2021 * Router Network packet and direct the Crosstalk reply to the * 2022 * appropriate processor. * 2023 * * 2024 ************************************************************************/ 2025 2026 typedef union ii_iprte4b_u { 2027 shubreg_t ii_iprte4b_regval; 2028 struct { 2029 shubreg_t i_rsvd_1 : 3; 2030 shubreg_t i_address : 47; 2031 shubreg_t i_init : 3; 2032 shubreg_t i_source : 11; 2033 } ii_iprte4b_fld_s; 2034 } ii_iprte4b_u_t; 2035 2036 2037 /************************************************************************ 2038 * * 2039 * There are 8 instances of this register. This register contains * 2040 * the information that the II has to remember once it has launched a * 2041 * PIO Read operation. The contents are used to form the correct * 2042 * Router Network packet and direct the Crosstalk reply to the * 2043 * appropriate processor. * 2044 * * 2045 ************************************************************************/ 2046 2047 typedef union ii_iprte5b_u { 2048 shubreg_t ii_iprte5b_regval; 2049 struct { 2050 shubreg_t i_rsvd_1 : 3; 2051 shubreg_t i_address : 47; 2052 shubreg_t i_init : 3; 2053 shubreg_t i_source : 11; 2054 } ii_iprte5b_fld_s; 2055 } ii_iprte5b_u_t; 2056 2057 2058 /************************************************************************ 2059 * * 2060 * There are 8 instances of this register. This register contains * 2061 * the information that the II has to remember once it has launched a * 2062 * PIO Read operation. The contents are used to form the correct * 2063 * Router Network packet and direct the Crosstalk reply to the * 2064 * appropriate processor. * 2065 * * 2066 ************************************************************************/ 2067 2068 typedef union ii_iprte6b_u { 2069 shubreg_t ii_iprte6b_regval; 2070 struct { 2071 shubreg_t i_rsvd_1 : 3; 2072 shubreg_t i_address : 47; 2073 shubreg_t i_init : 3; 2074 shubreg_t i_source : 11; 2075 2076 } ii_iprte6b_fld_s; 2077 } ii_iprte6b_u_t; 2078 2079 2080 /************************************************************************ 2081 * * 2082 * There are 8 instances of this register. This register contains * 2083 * the information that the II has to remember once it has launched a * 2084 * PIO Read operation. The contents are used to form the correct * 2085 * Router Network packet and direct the Crosstalk reply to the * 2086 * appropriate processor. * 2087 * * 2088 ************************************************************************/ 2089 2090 typedef union ii_iprte7b_u { 2091 shubreg_t ii_iprte7b_regval; 2092 struct { 2093 shubreg_t i_rsvd_1 : 3; 2094 shubreg_t i_address : 47; 2095 shubreg_t i_init : 3; 2096 shubreg_t i_source : 11; 2097 } ii_iprte7b_fld_s; 2098 } ii_iprte7b_u_t; 2099 2100 2101 /************************************************************************ 2102 * * 2103 * Description: SHub II contains a feature which did not exist in * 2104 * the Hub which automatically cleans up after a Read Response * 2105 * timeout, including deallocation of the IPRTE and recovery of IBuf * 2106 * space. The inclusion of this register in SHub is for backward * 2107 * compatibility * 2108 * A write to this register causes an entry from the table of * 2109 * outstanding PIO Read Requests to be freed and returned to the * 2110 * stack of free entries. This register is used in handling the * 2111 * timeout errors that result in a PIO Reply never returning from * 2112 * Crosstalk. * 2113 * Note that this register does not affect the contents of the IPRTE * 2114 * registers. The Valid bits in those registers have to be * 2115 * specifically turned off by software. * 2116 * * 2117 ************************************************************************/ 2118 2119 typedef union ii_ipdr_u { 2120 shubreg_t ii_ipdr_regval; 2121 struct { 2122 shubreg_t i_te : 3; 2123 shubreg_t i_rsvd_1 : 1; 2124 shubreg_t i_pnd : 1; 2125 shubreg_t i_init_rpcnt : 1; 2126 shubreg_t i_rsvd : 58; 2127 } ii_ipdr_fld_s; 2128 } ii_ipdr_u_t; 2129 2130 2131 /************************************************************************ 2132 * * 2133 * A write to this register causes a CRB entry to be returned to the * 2134 * queue of free CRBs. The entry should have previously been cleared * 2135 * (mark bit) via backdoor access to the pertinent CRB entry. This * 2136 * register is used in the last step of handling the errors that are * 2137 * captured and marked in CRB entries. Briefly: 1) first error for * 2138 * DMA write from a particular device, and first error for a * 2139 * particular BTE stream, lead to a marked CRB entry, and processor * 2140 * interrupt, 2) software reads the error information captured in the * 2141 * CRB entry, and presumably takes some corrective action, 3) * 2142 * software clears the mark bit, and finally 4) software writes to * 2143 * the ICDR register to return the CRB entry to the list of free CRB * 2144 * entries. * 2145 * * 2146 ************************************************************************/ 2147 2148 typedef union ii_icdr_u { 2149 shubreg_t ii_icdr_regval; 2150 struct { 2151 shubreg_t i_crb_num : 4; 2152 shubreg_t i_pnd : 1; 2153 shubreg_t i_rsvd : 59; 2154 } ii_icdr_fld_s; 2155 } ii_icdr_u_t; 2156 2157 2158 /************************************************************************ 2159 * * 2160 * This register provides debug access to two FIFOs inside of II. * 2161 * Both IOQ_MAX* fields of this register contain the instantaneous * 2162 * depth (in units of the number of available entries) of the * 2163 * associated IOQ FIFO. A read of this register will return the * 2164 * number of free entries on each FIFO at the time of the read. So * 2165 * when a FIFO is idle, the associated field contains the maximum * 2166 * depth of the FIFO. This register is writable for debug reasons * 2167 * and is intended to be written with the maximum desired FIFO depth * 2168 * while the FIFO is idle. Software must assure that II is idle when * 2169 * this register is written. If there are any active entries in any * 2170 * of these FIFOs when this register is written, the results are * 2171 * undefined. * 2172 * * 2173 ************************************************************************/ 2174 2175 typedef union ii_ifdr_u { 2176 shubreg_t ii_ifdr_regval; 2177 struct { 2178 shubreg_t i_ioq_max_rq : 7; 2179 shubreg_t i_set_ioq_rq : 1; 2180 shubreg_t i_ioq_max_rp : 7; 2181 shubreg_t i_set_ioq_rp : 1; 2182 shubreg_t i_rsvd : 48; 2183 } ii_ifdr_fld_s; 2184 } ii_ifdr_u_t; 2185 2186 2187 /************************************************************************ 2188 * * 2189 * This register allows the II to become sluggish in removing * 2190 * messages from its inbound queue (IIQ). This will cause messages to * 2191 * back up in either virtual channel. Disabling the "molasses" mode * 2192 * subsequently allows the II to be tested under stress. In the * 2193 * sluggish ("Molasses") mode, the localized effects of congestion * 2194 * can be observed. * 2195 * * 2196 ************************************************************************/ 2197 2198 typedef union ii_iiap_u { 2199 shubreg_t ii_iiap_regval; 2200 struct { 2201 shubreg_t i_rq_mls : 6; 2202 shubreg_t i_rsvd_1 : 2; 2203 shubreg_t i_rp_mls : 6; 2204 shubreg_t i_rsvd : 50; 2205 } ii_iiap_fld_s; 2206 } ii_iiap_u_t; 2207 2208 2209 /************************************************************************ 2210 * * 2211 * This register allows several parameters of CRB operation to be * 2212 * set. Note that writing to this register can have catastrophic side * 2213 * effects, if the CRB is not quiescent, i.e. if the CRB is * 2214 * processing protocol messages when the write occurs. * 2215 * * 2216 ************************************************************************/ 2217 2218 typedef union ii_icmr_u { 2219 shubreg_t ii_icmr_regval; 2220 struct { 2221 shubreg_t i_sp_msg : 1; 2222 shubreg_t i_rd_hdr : 1; 2223 shubreg_t i_rsvd_4 : 2; 2224 shubreg_t i_c_cnt : 4; 2225 shubreg_t i_rsvd_3 : 4; 2226 shubreg_t i_clr_rqpd : 1; 2227 shubreg_t i_clr_rppd : 1; 2228 shubreg_t i_rsvd_2 : 2; 2229 shubreg_t i_fc_cnt : 4; 2230 shubreg_t i_crb_vld : 15; 2231 shubreg_t i_crb_mark : 15; 2232 shubreg_t i_rsvd_1 : 2; 2233 shubreg_t i_precise : 1; 2234 shubreg_t i_rsvd : 11; 2235 } ii_icmr_fld_s; 2236 } ii_icmr_u_t; 2237 2238 2239 /************************************************************************ 2240 * * 2241 * This register allows control of the table portion of the CRB * 2242 * logic via software. Control operations from this register have * 2243 * priority over all incoming Crosstalk or BTE requests. * 2244 * * 2245 ************************************************************************/ 2246 2247 typedef union ii_iccr_u { 2248 shubreg_t ii_iccr_regval; 2249 struct { 2250 shubreg_t i_crb_num : 4; 2251 shubreg_t i_rsvd_1 : 4; 2252 shubreg_t i_cmd : 8; 2253 shubreg_t i_pending : 1; 2254 shubreg_t i_rsvd : 47; 2255 } ii_iccr_fld_s; 2256 } ii_iccr_u_t; 2257 2258 2259 /************************************************************************ 2260 * * 2261 * This register allows the maximum timeout value to be programmed. * 2262 * * 2263 ************************************************************************/ 2264 2265 typedef union ii_icto_u { 2266 shubreg_t ii_icto_regval; 2267 struct { 2268 shubreg_t i_timeout : 8; 2269 shubreg_t i_rsvd : 56; 2270 } ii_icto_fld_s; 2271 } ii_icto_u_t; 2272 2273 2274 /************************************************************************ 2275 * * 2276 * This register allows the timeout prescalar to be programmed. An * 2277 * internal counter is associated with this register. When the * 2278 * internal counter reaches the value of the PRESCALE field, the * 2279 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * 2280 * field). The internal counter resets to zero, and then continues * 2281 * counting. * 2282 * * 2283 ************************************************************************/ 2284 2285 typedef union ii_ictp_u { 2286 shubreg_t ii_ictp_regval; 2287 struct { 2288 shubreg_t i_prescale : 24; 2289 shubreg_t i_rsvd : 40; 2290 } ii_ictp_fld_s; 2291 } ii_ictp_u_t; 2292 2293 2294 /************************************************************************ 2295 * * 2296 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2297 * used for Crosstalk operations (both cacheline and partial * 2298 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2299 * registers (_A to _E) are required to read and write each entry. * 2300 * The CRB Entry registers can be conceptualized as rows and columns * 2301 * (illustrated in the table above). Each row contains the 4 * 2302 * registers required for a single CRB Entry. The first doubleword * 2303 * (column) for each entry is labeled A, and the second doubleword * 2304 * (higher address) is labeled B, the third doubleword is labeled C, * 2305 * the fourth doubleword is labeled D and the fifth doubleword is * 2306 * labeled E. All CRB entries have their addresses on a quarter * 2307 * cacheline aligned boundary. * 2308 * Upon reset, only the following fields are initialized: valid * 2309 * (VLD), priority count, timeout, timeout valid, and context valid. * 2310 * All other bits should be cleared by software before use (after * 2311 * recovering any potential error state from before the reset). * 2312 * The following four tables summarize the format for the four * 2313 * registers that are used for each ICRB# Entry. * 2314 * * 2315 ************************************************************************/ 2316 2317 typedef union ii_icrb0_a_u { 2318 shubreg_t ii_icrb0_a_regval; 2319 struct { 2320 shubreg_t ia_iow : 1; 2321 shubreg_t ia_vld : 1; 2322 shubreg_t ia_addr : 47; 2323 shubreg_t ia_tnum : 5; 2324 shubreg_t ia_sidn : 4; 2325 shubreg_t ia_rsvd : 6; 2326 } ii_icrb0_a_fld_s; 2327 } ii_icrb0_a_u_t; 2328 2329 2330 /************************************************************************ 2331 * * 2332 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2333 * used for Crosstalk operations (both cacheline and partial * 2334 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2335 * registers (_A to _E) are required to read and write each entry. * 2336 * * 2337 ************************************************************************/ 2338 2339 typedef union ii_icrb0_b_u { 2340 shubreg_t ii_icrb0_b_regval; 2341 struct { 2342 shubreg_t ib_xt_err : 1; 2343 shubreg_t ib_mark : 1; 2344 shubreg_t ib_ln_uce : 1; 2345 shubreg_t ib_errcode : 3; 2346 shubreg_t ib_error : 1; 2347 shubreg_t ib_stall__bte_1 : 1; 2348 shubreg_t ib_stall__bte_0 : 1; 2349 shubreg_t ib_stall__intr : 1; 2350 shubreg_t ib_stall_ib : 1; 2351 shubreg_t ib_intvn : 1; 2352 shubreg_t ib_wb : 1; 2353 shubreg_t ib_hold : 1; 2354 shubreg_t ib_ack : 1; 2355 shubreg_t ib_resp : 1; 2356 shubreg_t ib_ack_cnt : 11; 2357 shubreg_t ib_rsvd : 7; 2358 shubreg_t ib_exc : 5; 2359 shubreg_t ib_init : 3; 2360 shubreg_t ib_imsg : 8; 2361 shubreg_t ib_imsgtype : 2; 2362 shubreg_t ib_use_old : 1; 2363 shubreg_t ib_rsvd_1 : 11; 2364 } ii_icrb0_b_fld_s; 2365 } ii_icrb0_b_u_t; 2366 2367 2368 /************************************************************************ 2369 * * 2370 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2371 * used for Crosstalk operations (both cacheline and partial * 2372 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2373 * registers (_A to _E) are required to read and write each entry. * 2374 * * 2375 ************************************************************************/ 2376 2377 typedef union ii_icrb0_c_u { 2378 shubreg_t ii_icrb0_c_regval; 2379 struct { 2380 shubreg_t ic_source : 15; 2381 shubreg_t ic_size : 2; 2382 shubreg_t ic_ct : 1; 2383 shubreg_t ic_bte_num : 1; 2384 shubreg_t ic_gbr : 1; 2385 shubreg_t ic_resprqd : 1; 2386 shubreg_t ic_bo : 1; 2387 shubreg_t ic_suppl : 15; 2388 shubreg_t ic_rsvd : 27; 2389 } ii_icrb0_c_fld_s; 2390 } ii_icrb0_c_u_t; 2391 2392 2393 /************************************************************************ 2394 * * 2395 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2396 * used for Crosstalk operations (both cacheline and partial * 2397 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2398 * registers (_A to _E) are required to read and write each entry. * 2399 * * 2400 ************************************************************************/ 2401 2402 typedef union ii_icrb0_d_u { 2403 shubreg_t ii_icrb0_d_regval; 2404 struct { 2405 shubreg_t id_pa_be : 43; 2406 shubreg_t id_bte_op : 1; 2407 shubreg_t id_pr_psc : 4; 2408 shubreg_t id_pr_cnt : 4; 2409 shubreg_t id_sleep : 1; 2410 shubreg_t id_rsvd : 11; 2411 } ii_icrb0_d_fld_s; 2412 } ii_icrb0_d_u_t; 2413 2414 2415 /************************************************************************ 2416 * * 2417 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * 2418 * used for Crosstalk operations (both cacheline and partial * 2419 * operations) or BTE/IO. Because the CRB entries are very wide, five * 2420 * registers (_A to _E) are required to read and write each entry. * 2421 * * 2422 ************************************************************************/ 2423 2424 typedef union ii_icrb0_e_u { 2425 shubreg_t ii_icrb0_e_regval; 2426 struct { 2427 shubreg_t ie_timeout : 8; 2428 shubreg_t ie_context : 15; 2429 shubreg_t ie_rsvd : 1; 2430 shubreg_t ie_tvld : 1; 2431 shubreg_t ie_cvld : 1; 2432 shubreg_t ie_rsvd_0 : 38; 2433 } ii_icrb0_e_fld_s; 2434 } ii_icrb0_e_u_t; 2435 2436 2437 /************************************************************************ 2438 * * 2439 * This register contains the lower 64 bits of the header of the * 2440 * spurious message captured by II. Valid when the SP_MSG bit in ICMR * 2441 * register is set. * 2442 * * 2443 ************************************************************************/ 2444 2445 typedef union ii_icsml_u { 2446 shubreg_t ii_icsml_regval; 2447 struct { 2448 shubreg_t i_tt_addr : 47; 2449 shubreg_t i_newsuppl_ex : 14; 2450 shubreg_t i_reserved : 2; 2451 shubreg_t i_overflow : 1; 2452 } ii_icsml_fld_s; 2453 } ii_icsml_u_t; 2454 2455 2456 /************************************************************************ 2457 * * 2458 * This register contains the middle 64 bits of the header of the * 2459 * spurious message captured by II. Valid when the SP_MSG bit in ICMR * 2460 * register is set. * 2461 * * 2462 ************************************************************************/ 2463 2464 typedef union ii_icsmm_u { 2465 shubreg_t ii_icsmm_regval; 2466 struct { 2467 shubreg_t i_tt_ack_cnt : 11; 2468 shubreg_t i_reserved : 53; 2469 } ii_icsmm_fld_s; 2470 } ii_icsmm_u_t; 2471 2472 2473 /************************************************************************ 2474 * * 2475 * This register contains the microscopic state, all the inputs to * 2476 * the protocol table, captured with the spurious message. Valid when * 2477 * the SP_MSG bit in the ICMR register is set. * 2478 * * 2479 ************************************************************************/ 2480 2481 typedef union ii_icsmh_u { 2482 shubreg_t ii_icsmh_regval; 2483 struct { 2484 shubreg_t i_tt_vld : 1; 2485 shubreg_t i_xerr : 1; 2486 shubreg_t i_ft_cwact_o : 1; 2487 shubreg_t i_ft_wact_o : 1; 2488 shubreg_t i_ft_active_o : 1; 2489 shubreg_t i_sync : 1; 2490 shubreg_t i_mnusg : 1; 2491 shubreg_t i_mnusz : 1; 2492 shubreg_t i_plusz : 1; 2493 shubreg_t i_plusg : 1; 2494 shubreg_t i_tt_exc : 5; 2495 shubreg_t i_tt_wb : 1; 2496 shubreg_t i_tt_hold : 1; 2497 shubreg_t i_tt_ack : 1; 2498 shubreg_t i_tt_resp : 1; 2499 shubreg_t i_tt_intvn : 1; 2500 shubreg_t i_g_stall_bte1 : 1; 2501 shubreg_t i_g_stall_bte0 : 1; 2502 shubreg_t i_g_stall_il : 1; 2503 shubreg_t i_g_stall_ib : 1; 2504 shubreg_t i_tt_imsg : 8; 2505 shubreg_t i_tt_imsgtype : 2; 2506 shubreg_t i_tt_use_old : 1; 2507 shubreg_t i_tt_respreqd : 1; 2508 shubreg_t i_tt_bte_num : 1; 2509 shubreg_t i_cbn : 1; 2510 shubreg_t i_match : 1; 2511 shubreg_t i_rpcnt_lt_34 : 1; 2512 shubreg_t i_rpcnt_ge_34 : 1; 2513 shubreg_t i_rpcnt_lt_18 : 1; 2514 shubreg_t i_rpcnt_ge_18 : 1; 2515 shubreg_t i_rpcnt_lt_2 : 1; 2516 shubreg_t i_rpcnt_ge_2 : 1; 2517 shubreg_t i_rqcnt_lt_18 : 1; 2518 shubreg_t i_rqcnt_ge_18 : 1; 2519 shubreg_t i_rqcnt_lt_2 : 1; 2520 shubreg_t i_rqcnt_ge_2 : 1; 2521 shubreg_t i_tt_device : 7; 2522 shubreg_t i_tt_init : 3; 2523 shubreg_t i_reserved : 5; 2524 } ii_icsmh_fld_s; 2525 } ii_icsmh_u_t; 2526 2527 2528 /************************************************************************ 2529 * * 2530 * The Shub DEBUG unit provides a 3-bit selection signal to the * 2531 * II core and a 3-bit selection signal to the fsbclk domain in the II * 2532 * wrapper. * 2533 * * 2534 ************************************************************************/ 2535 2536 typedef union ii_idbss_u { 2537 shubreg_t ii_idbss_regval; 2538 struct { 2539 shubreg_t i_iioclk_core_submenu : 3; 2540 shubreg_t i_rsvd : 5; 2541 shubreg_t i_fsbclk_wrapper_submenu : 3; 2542 shubreg_t i_rsvd_1 : 5; 2543 shubreg_t i_iioclk_menu : 5; 2544 shubreg_t i_rsvd_2 : 43; 2545 } ii_idbss_fld_s; 2546 } ii_idbss_u_t; 2547 2548 2549 /************************************************************************ 2550 * * 2551 * Description: This register is used to set up the length for a * 2552 * transfer and then to monitor the progress of that transfer. This * 2553 * register needs to be initialized before a transfer is started. A * 2554 * legitimate write to this register will set the Busy bit, clear the * 2555 * Error bit, and initialize the length to the value desired. * 2556 * While the transfer is in progress, hardware will decrement the * 2557 * length field with each successful block that is copied. Once the * 2558 * transfer completes, hardware will clear the Busy bit. The length * 2559 * field will also contain the number of cache lines left to be * 2560 * transferred. * 2561 * * 2562 ************************************************************************/ 2563 2564 typedef union ii_ibls0_u { 2565 shubreg_t ii_ibls0_regval; 2566 struct { 2567 shubreg_t i_length : 16; 2568 shubreg_t i_error : 1; 2569 shubreg_t i_rsvd_1 : 3; 2570 shubreg_t i_busy : 1; 2571 shubreg_t i_rsvd : 43; 2572 } ii_ibls0_fld_s; 2573 } ii_ibls0_u_t; 2574 2575 2576 /************************************************************************ 2577 * * 2578 * This register should be loaded before a transfer is started. The * 2579 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2580 * address as described in Section 1.3, Figure2 and Figure3. Since * 2581 * the bottom 7 bits of the address are always taken to be zero, BTE * 2582 * transfers are always cacheline-aligned. * 2583 * * 2584 ************************************************************************/ 2585 2586 typedef union ii_ibsa0_u { 2587 shubreg_t ii_ibsa0_regval; 2588 struct { 2589 shubreg_t i_rsvd_1 : 7; 2590 shubreg_t i_addr : 42; 2591 shubreg_t i_rsvd : 15; 2592 } ii_ibsa0_fld_s; 2593 } ii_ibsa0_u_t; 2594 2595 2596 /************************************************************************ 2597 * * 2598 * This register should be loaded before a transfer is started. The * 2599 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2600 * address as described in Section 1.3, Figure2 and Figure3. Since * 2601 * the bottom 7 bits of the address are always taken to be zero, BTE * 2602 * transfers are always cacheline-aligned. * 2603 * * 2604 ************************************************************************/ 2605 2606 typedef union ii_ibda0_u { 2607 shubreg_t ii_ibda0_regval; 2608 struct { 2609 shubreg_t i_rsvd_1 : 7; 2610 shubreg_t i_addr : 42; 2611 shubreg_t i_rsvd : 15; 2612 } ii_ibda0_fld_s; 2613 } ii_ibda0_u_t; 2614 2615 2616 /************************************************************************ 2617 * * 2618 * Writing to this register sets up the attributes of the transfer * 2619 * and initiates the transfer operation. Reading this register has * 2620 * the side effect of terminating any transfer in progress. Note: * 2621 * stopping a transfer midstream could have an adverse impact on the * 2622 * other BTE. If a BTE stream has to be stopped (due to error * 2623 * handling for example), both BTE streams should be stopped and * 2624 * their transfers discarded. * 2625 * * 2626 ************************************************************************/ 2627 2628 typedef union ii_ibct0_u { 2629 shubreg_t ii_ibct0_regval; 2630 struct { 2631 shubreg_t i_zerofill : 1; 2632 shubreg_t i_rsvd_2 : 3; 2633 shubreg_t i_notify : 1; 2634 shubreg_t i_rsvd_1 : 3; 2635 shubreg_t i_poison : 1; 2636 shubreg_t i_rsvd : 55; 2637 } ii_ibct0_fld_s; 2638 } ii_ibct0_u_t; 2639 2640 2641 /************************************************************************ 2642 * * 2643 * This register contains the address to which the WINV is sent. * 2644 * This address has to be cache line aligned. * 2645 * * 2646 ************************************************************************/ 2647 2648 typedef union ii_ibna0_u { 2649 shubreg_t ii_ibna0_regval; 2650 struct { 2651 shubreg_t i_rsvd_1 : 7; 2652 shubreg_t i_addr : 42; 2653 shubreg_t i_rsvd : 15; 2654 } ii_ibna0_fld_s; 2655 } ii_ibna0_u_t; 2656 2657 2658 /************************************************************************ 2659 * * 2660 * This register contains the programmable level as well as the node * 2661 * ID and PI unit of the processor to which the interrupt will be * 2662 * sent. * 2663 * * 2664 ************************************************************************/ 2665 2666 typedef union ii_ibia0_u { 2667 shubreg_t ii_ibia0_regval; 2668 struct { 2669 shubreg_t i_rsvd_2 : 1; 2670 shubreg_t i_node_id : 11; 2671 shubreg_t i_rsvd_1 : 4; 2672 shubreg_t i_level : 7; 2673 shubreg_t i_rsvd : 41; 2674 } ii_ibia0_fld_s; 2675 } ii_ibia0_u_t; 2676 2677 2678 /************************************************************************ 2679 * * 2680 * Description: This register is used to set up the length for a * 2681 * transfer and then to monitor the progress of that transfer. This * 2682 * register needs to be initialized before a transfer is started. A * 2683 * legitimate write to this register will set the Busy bit, clear the * 2684 * Error bit, and initialize the length to the value desired. * 2685 * While the transfer is in progress, hardware will decrement the * 2686 * length field with each successful block that is copied. Once the * 2687 * transfer completes, hardware will clear the Busy bit. The length * 2688 * field will also contain the number of cache lines left to be * 2689 * transferred. * 2690 * * 2691 ************************************************************************/ 2692 2693 typedef union ii_ibls1_u { 2694 shubreg_t ii_ibls1_regval; 2695 struct { 2696 shubreg_t i_length : 16; 2697 shubreg_t i_error : 1; 2698 shubreg_t i_rsvd_1 : 3; 2699 shubreg_t i_busy : 1; 2700 shubreg_t i_rsvd : 43; 2701 } ii_ibls1_fld_s; 2702 } ii_ibls1_u_t; 2703 2704 2705 /************************************************************************ 2706 * * 2707 * This register should be loaded before a transfer is started. The * 2708 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2709 * address as described in Section 1.3, Figure2 and Figure3. Since * 2710 * the bottom 7 bits of the address are always taken to be zero, BTE * 2711 * transfers are always cacheline-aligned. * 2712 * * 2713 ************************************************************************/ 2714 2715 typedef union ii_ibsa1_u { 2716 shubreg_t ii_ibsa1_regval; 2717 struct { 2718 shubreg_t i_rsvd_1 : 7; 2719 shubreg_t i_addr : 33; 2720 shubreg_t i_rsvd : 24; 2721 } ii_ibsa1_fld_s; 2722 } ii_ibsa1_u_t; 2723 2724 2725 /************************************************************************ 2726 * * 2727 * This register should be loaded before a transfer is started. The * 2728 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * 2729 * address as described in Section 1.3, Figure2 and Figure3. Since * 2730 * the bottom 7 bits of the address are always taken to be zero, BTE * 2731 * transfers are always cacheline-aligned. * 2732 * * 2733 ************************************************************************/ 2734 2735 typedef union ii_ibda1_u { 2736 shubreg_t ii_ibda1_regval; 2737 struct { 2738 shubreg_t i_rsvd_1 : 7; 2739 shubreg_t i_addr : 33; 2740 shubreg_t i_rsvd : 24; 2741 } ii_ibda1_fld_s; 2742 } ii_ibda1_u_t; 2743 2744 2745 /************************************************************************ 2746 * * 2747 * Writing to this register sets up the attributes of the transfer * 2748 * and initiates the transfer operation. Reading this register has * 2749 * the side effect of terminating any transfer in progress. Note: * 2750 * stopping a transfer midstream could have an adverse impact on the * 2751 * other BTE. If a BTE stream has to be stopped (due to error * 2752 * handling for example), both BTE streams should be stopped and * 2753 * their transfers discarded. * 2754 * * 2755 ************************************************************************/ 2756 2757 typedef union ii_ibct1_u { 2758 shubreg_t ii_ibct1_regval; 2759 struct { 2760 shubreg_t i_zerofill : 1; 2761 shubreg_t i_rsvd_2 : 3; 2762 shubreg_t i_notify : 1; 2763 shubreg_t i_rsvd_1 : 3; 2764 shubreg_t i_poison : 1; 2765 shubreg_t i_rsvd : 55; 2766 } ii_ibct1_fld_s; 2767 } ii_ibct1_u_t; 2768 2769 2770 /************************************************************************ 2771 * * 2772 * This register contains the address to which the WINV is sent. * 2773 * This address has to be cache line aligned. * 2774 * * 2775 ************************************************************************/ 2776 2777 typedef union ii_ibna1_u { 2778 shubreg_t ii_ibna1_regval; 2779 struct { 2780 shubreg_t i_rsvd_1 : 7; 2781 shubreg_t i_addr : 33; 2782 shubreg_t i_rsvd : 24; 2783 } ii_ibna1_fld_s; 2784 } ii_ibna1_u_t; 2785 2786 2787 /************************************************************************ 2788 * * 2789 * This register contains the programmable level as well as the node * 2790 * ID and PI unit of the processor to which the interrupt will be * 2791 * sent. * 2792 * * 2793 ************************************************************************/ 2794 2795 typedef union ii_ibia1_u { 2796 shubreg_t ii_ibia1_regval; 2797 struct { 2798 shubreg_t i_pi_id : 1; 2799 shubreg_t i_node_id : 8; 2800 shubreg_t i_rsvd_1 : 7; 2801 shubreg_t i_level : 7; 2802 shubreg_t i_rsvd : 41; 2803 } ii_ibia1_fld_s; 2804 } ii_ibia1_u_t; 2805 2806 2807 /************************************************************************ 2808 * * 2809 * This register defines the resources that feed information into * 2810 * the two performance counters located in the IO Performance * 2811 * Profiling Register. There are 17 different quantities that can be * 2812 * measured. Given these 17 different options, the two performance * 2813 * counters have 15 of them in common; menu selections 0 through 0xE * 2814 * are identical for each performance counter. As for the other two * 2815 * options, one is available from one performance counter and the * 2816 * other is available from the other performance counter. Hence, the * 2817 * II supports all 17*16=272 possible combinations of quantities to * 2818 * measure. * 2819 * * 2820 ************************************************************************/ 2821 2822 typedef union ii_ipcr_u { 2823 shubreg_t ii_ipcr_regval; 2824 struct { 2825 shubreg_t i_ippr0_c : 4; 2826 shubreg_t i_ippr1_c : 4; 2827 shubreg_t i_icct : 8; 2828 shubreg_t i_rsvd : 48; 2829 } ii_ipcr_fld_s; 2830 } ii_ipcr_u_t; 2831 2832 2833 /************************************************************************ 2834 * * 2835 * * 2836 * * 2837 ************************************************************************/ 2838 2839 typedef union ii_ippr_u { 2840 shubreg_t ii_ippr_regval; 2841 struct { 2842 shubreg_t i_ippr0 : 32; 2843 shubreg_t i_ippr1 : 32; 2844 } ii_ippr_fld_s; 2845 } ii_ippr_u_t; 2846 2847 2848 #endif /* __ASSEMBLY__ */ 2849 2850 /************************************************************************** 2851 * * 2852 * The following defines which were not formed into structures are * 2853 * probably indentical to another register, and the name of the * 2854 * register is provided against each of these registers. This * 2855 * information needs to be checked carefully * 2856 * * 2857 * IIO_ICRB1_A IIO_ICRB0_A * 2858 * IIO_ICRB1_B IIO_ICRB0_B * 2859 * IIO_ICRB1_C IIO_ICRB0_C * 2860 * IIO_ICRB1_D IIO_ICRB0_D * 2861 * IIO_ICRB1_E IIO_ICRB0_E * 2862 * IIO_ICRB2_A IIO_ICRB0_A * 2863 * IIO_ICRB2_B IIO_ICRB0_B * 2864 * IIO_ICRB2_C IIO_ICRB0_C * 2865 * IIO_ICRB2_D IIO_ICRB0_D * 2866 * IIO_ICRB2_E IIO_ICRB0_E * 2867 * IIO_ICRB3_A IIO_ICRB0_A * 2868 * IIO_ICRB3_B IIO_ICRB0_B * 2869 * IIO_ICRB3_C IIO_ICRB0_C * 2870 * IIO_ICRB3_D IIO_ICRB0_D * 2871 * IIO_ICRB3_E IIO_ICRB0_E * 2872 * IIO_ICRB4_A IIO_ICRB0_A * 2873 * IIO_ICRB4_B IIO_ICRB0_B * 2874 * IIO_ICRB4_C IIO_ICRB0_C * 2875 * IIO_ICRB4_D IIO_ICRB0_D * 2876 * IIO_ICRB4_E IIO_ICRB0_E * 2877 * IIO_ICRB5_A IIO_ICRB0_A * 2878 * IIO_ICRB5_B IIO_ICRB0_B * 2879 * IIO_ICRB5_C IIO_ICRB0_C * 2880 * IIO_ICRB5_D IIO_ICRB0_D * 2881 * IIO_ICRB5_E IIO_ICRB0_E * 2882 * IIO_ICRB6_A IIO_ICRB0_A * 2883 * IIO_ICRB6_B IIO_ICRB0_B * 2884 * IIO_ICRB6_C IIO_ICRB0_C * 2885 * IIO_ICRB6_D IIO_ICRB0_D * 2886 * IIO_ICRB6_E IIO_ICRB0_E * 2887 * IIO_ICRB7_A IIO_ICRB0_A * 2888 * IIO_ICRB7_B IIO_ICRB0_B * 2889 * IIO_ICRB7_C IIO_ICRB0_C * 2890 * IIO_ICRB7_D IIO_ICRB0_D * 2891 * IIO_ICRB7_E IIO_ICRB0_E * 2892 * IIO_ICRB8_A IIO_ICRB0_A * 2893 * IIO_ICRB8_B IIO_ICRB0_B * 2894 * IIO_ICRB8_C IIO_ICRB0_C * 2895 * IIO_ICRB8_D IIO_ICRB0_D * 2896 * IIO_ICRB8_E IIO_ICRB0_E * 2897 * IIO_ICRB9_A IIO_ICRB0_A * 2898 * IIO_ICRB9_B IIO_ICRB0_B * 2899 * IIO_ICRB9_C IIO_ICRB0_C * 2900 * IIO_ICRB9_D IIO_ICRB0_D * 2901 * IIO_ICRB9_E IIO_ICRB0_E * 2902 * IIO_ICRBA_A IIO_ICRB0_A * 2903 * IIO_ICRBA_B IIO_ICRB0_B * 2904 * IIO_ICRBA_C IIO_ICRB0_C * 2905 * IIO_ICRBA_D IIO_ICRB0_D * 2906 * IIO_ICRBA_E IIO_ICRB0_E * 2907 * IIO_ICRBB_A IIO_ICRB0_A * 2908 * IIO_ICRBB_B IIO_ICRB0_B * 2909 * IIO_ICRBB_C IIO_ICRB0_C * 2910 * IIO_ICRBB_D IIO_ICRB0_D * 2911 * IIO_ICRBB_E IIO_ICRB0_E * 2912 * IIO_ICRBC_A IIO_ICRB0_A * 2913 * IIO_ICRBC_B IIO_ICRB0_B * 2914 * IIO_ICRBC_C IIO_ICRB0_C * 2915 * IIO_ICRBC_D IIO_ICRB0_D * 2916 * IIO_ICRBC_E IIO_ICRB0_E * 2917 * IIO_ICRBD_A IIO_ICRB0_A * 2918 * IIO_ICRBD_B IIO_ICRB0_B * 2919 * IIO_ICRBD_C IIO_ICRB0_C * 2920 * IIO_ICRBD_D IIO_ICRB0_D * 2921 * IIO_ICRBD_E IIO_ICRB0_E * 2922 * IIO_ICRBE_A IIO_ICRB0_A * 2923 * IIO_ICRBE_B IIO_ICRB0_B * 2924 * IIO_ICRBE_C IIO_ICRB0_C * 2925 * IIO_ICRBE_D IIO_ICRB0_D * 2926 * IIO_ICRBE_E IIO_ICRB0_E * 2927 * * 2928 **************************************************************************/ 2929 2930 2931 /* 2932 * Slightly friendlier names for some common registers. 2933 */ 2934 #define IIO_WIDGET IIO_WID /* Widget identification */ 2935 #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ 2936 #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ 2937 #define IIO_PROTECT IIO_ILAPR /* IO interface protection */ 2938 #define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ 2939 #define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ 2940 #define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ 2941 #define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ 2942 #define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ 2943 #define IIO_LLP_LOG IIO_ILLR /* LLP log */ 2944 #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ 2945 #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ 2946 #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ 2947 #define IIO_IGFX_0 IIO_IGFX0 2948 #define IIO_IGFX_1 IIO_IGFX1 2949 #define IIO_IBCT_0 IIO_IBCT0 2950 #define IIO_IBCT_1 IIO_IBCT1 2951 #define IIO_IBLS_0 IIO_IBLS0 2952 #define IIO_IBLS_1 IIO_IBLS1 2953 #define IIO_IBSA_0 IIO_IBSA0 2954 #define IIO_IBSA_1 IIO_IBSA1 2955 #define IIO_IBDA_0 IIO_IBDA0 2956 #define IIO_IBDA_1 IIO_IBDA1 2957 #define IIO_IBNA_0 IIO_IBNA0 2958 #define IIO_IBNA_1 IIO_IBNA1 2959 #define IIO_IBIA_0 IIO_IBIA0 2960 #define IIO_IBIA_1 IIO_IBIA1 2961 #define IIO_IOPRB_0 IIO_IPRB0 2962 2963 #define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x))) 2964 #define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x))) 2965 #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ 2966 #define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ 2967 #define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ 2968 2969 #define IIO_NUM_IPRBS (9) 2970 2971 #define IIO_LLP_CSR_IS_UP 0x00002000 2972 #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 2973 #define IIO_LLP_CSR_LLP_STAT_SHFT 12 2974 2975 #define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */ 2976 #define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ 2977 2978 /* key to IIO_PROTECT_OVRRD */ 2979 #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ 2980 2981 /* BTE register names */ 2982 #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ 2983 #define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ 2984 #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ 2985 #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ 2986 #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ 2987 #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ 2988 #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ 2989 #define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ 2990 2991 /* BTE register offsets from base */ 2992 #define BTEOFF_STAT 0 2993 #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) 2994 #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) 2995 #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) 2996 #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) 2997 #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) 2998 2999 3000 /* names used in shub diags */ 3001 #define IIO_BASE_BTE0 IIO_IBLS_0 3002 #define IIO_BASE_BTE1 IIO_IBLS_1 3003 3004 /* 3005 * Macro which takes the widget number, and returns the 3006 * IO PRB address of that widget. 3007 * value _x is expected to be a widget number in the range 3008 * 0, 8 - 0xF 3009 */ 3010 #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ 3011 (_x) : \ 3012 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) 3013 3014 3015 /* GFX Flow Control Node/Widget Register */ 3016 #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ 3017 #define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1) 3018 #define IIO_IGFX_W_NUM_SHIFT 0 3019 #define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */ 3020 #define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1) 3021 #define IIO_IGFX_PI_NUM_SHIFT 4 3022 #define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */ 3023 #define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1) 3024 #define IIO_IGFX_N_NUM_SHIFT 5 3025 #define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */ 3026 #define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1) 3027 #define IIO_IGFX_P_NUM_SHIFT 16 3028 #define IIO_IGFX_INIT(widget, pi, node, cpu) (\ 3029 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ 3030 (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \ 3031 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ 3032 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) 3033 3034 3035 /* Scratch registers (all bits available) */ 3036 #define IIO_SCRATCH_REG0 IIO_ISCR0 3037 #define IIO_SCRATCH_REG1 IIO_ISCR1 3038 #define IIO_SCRATCH_MASK 0xffffffffffffffffUL 3039 3040 #define IIO_SCRATCH_BIT0_0 0x0000000000000001UL 3041 #define IIO_SCRATCH_BIT0_1 0x0000000000000002UL 3042 #define IIO_SCRATCH_BIT0_2 0x0000000000000004UL 3043 #define IIO_SCRATCH_BIT0_3 0x0000000000000008UL 3044 #define IIO_SCRATCH_BIT0_4 0x0000000000000010UL 3045 #define IIO_SCRATCH_BIT0_5 0x0000000000000020UL 3046 #define IIO_SCRATCH_BIT0_6 0x0000000000000040UL 3047 #define IIO_SCRATCH_BIT0_7 0x0000000000000080UL 3048 #define IIO_SCRATCH_BIT0_8 0x0000000000000100UL 3049 #define IIO_SCRATCH_BIT0_9 0x0000000000000200UL 3050 #define IIO_SCRATCH_BIT0_A 0x0000000000000400UL 3051 3052 #define IIO_SCRATCH_BIT1_0 0x0000000000000001UL 3053 #define IIO_SCRATCH_BIT1_1 0x0000000000000002UL 3054 /* IO Translation Table Entries */ 3055 #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ 3056 /* Hw manuals number them 1..7! */ 3057 /* 3058 * IIO_IMEM Register fields. 3059 */ 3060 #define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ 3061 #define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ 3062 #define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ 3063 3064 /* 3065 * As a permanent workaround for a bug in the PI side of the shub, we've 3066 * redefined big window 7 as small window 0. 3067 XXX does this still apply for SN1?? 3068 */ 3069 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) 3070 3071 /* 3072 * Use the top big window as a surrogate for the first small window 3073 */ 3074 #define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW 3075 3076 #define ILCSR_WARM_RESET 0x100 3077 3078 /* 3079 * CRB manipulation macros 3080 * The CRB macros are slightly complicated, since there are up to 3081 * four registers associated with each CRB entry. 3082 */ 3083 #define IIO_NUM_CRBS 15 /* Number of CRBs */ 3084 #define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ 3085 #define IIO_ICRB_OFFSET 8 3086 #define IIO_ICRB_0 IIO_ICRB0_A 3087 #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ 3088 /* XXX - This is now tuneable: 3089 #define IIO_FIRST_PC_ENTRY 12 3090 */ 3091 3092 #define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) 3093 #define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) 3094 #define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) 3095 #define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) 3096 #define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) 3097 3098 #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) 3099 3100 /* 3101 * values for "ecode" field 3102 */ 3103 #define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ 3104 #define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ 3105 #define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access 3106 * e.g. WINV to a Read only line. */ 3107 #define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ 3108 #define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ 3109 #define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ 3110 #define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ 3111 #define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ 3112 3113 /* 3114 * Values for field imsgtype 3115 */ 3116 #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ 3117 #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ 3118 #define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ 3119 #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ 3120 3121 /* 3122 * values for field initiator. 3123 */ 3124 #define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ 3125 #define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ 3126 #define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ 3127 #define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ 3128 #define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ 3129 3130 /* 3131 * Number of credits Hub widget has while sending req/response to 3132 * xbow. 3133 * Value of 3 is required by Xbow 1.1 3134 * We may be able to increase this to 4 with Xbow 1.2. 3135 */ 3136 #define HUBII_XBOW_CREDIT 3 3137 #define HUBII_XBOW_REV2_CREDIT 4 3138 3139 /* 3140 * Number of credits that xtalk devices should use when communicating 3141 * with a SHub (depth of SHub's queue). 3142 */ 3143 #define HUB_CREDIT 4 3144 3145 /* 3146 * Some IIO_PRB fields 3147 */ 3148 #define IIO_PRB_MULTI_ERR (1LL << 63) 3149 #define IIO_PRB_SPUR_RD (1LL << 51) 3150 #define IIO_PRB_SPUR_WR (1LL << 50) 3151 #define IIO_PRB_RD_TO (1LL << 49) 3152 #define IIO_PRB_ERROR (1LL << 48) 3153 3154 /************************************************************************* 3155 3156 Some of the IIO field masks and shifts are defined here. 3157 This is in order to maintain compatibility in SN0 and SN1 code 3158 3159 **************************************************************************/ 3160 3161 /* 3162 * ICMR register fields 3163 * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not 3164 * present in SHub) 3165 */ 3166 3167 #define IIO_ICMR_CRB_VLD_SHFT 20 3168 #define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) 3169 3170 #define IIO_ICMR_FC_CNT_SHFT 16 3171 #define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) 3172 3173 #define IIO_ICMR_C_CNT_SHFT 4 3174 #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) 3175 3176 #define IIO_ICMR_PRECISE (1UL << 52) 3177 #define IIO_ICMR_CLR_RPPD (1UL << 13) 3178 #define IIO_ICMR_CLR_RQPD (1UL << 12) 3179 3180 /* 3181 * IIO PIO Deallocation register field masks : (IIO_IPDR) 3182 XXX present but not needed in bedrock? See the manual. 3183 */ 3184 #define IIO_IPDR_PND (1 << 4) 3185 3186 /* 3187 * IIO CRB deallocation register field masks: (IIO_ICDR) 3188 */ 3189 #define IIO_ICDR_PND (1 << 4) 3190 3191 /* 3192 * IO BTE Length/Status (IIO_IBLS) register bit field definitions 3193 */ 3194 #define IBLS_BUSY (0x1UL << 20) 3195 #define IBLS_ERROR_SHFT 16 3196 #define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT) 3197 #define IBLS_LENGTH_MASK 0xffff 3198 3199 /* 3200 * IO BTE Control/Terminate register (IBCT) register bit field definitions 3201 */ 3202 #define IBCT_POISON (0x1UL << 8) 3203 #define IBCT_NOTIFY (0x1UL << 4) 3204 #define IBCT_ZFIL_MODE (0x1UL << 0) 3205 3206 /* 3207 * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2) 3208 */ 3209 #define IIEPH1_VALID (1UL << 44) 3210 #define IIEPH1_OVERRUN (1UL << 40) 3211 #define IIEPH1_ERR_TYPE_SHFT 32 3212 #define IIEPH1_ERR_TYPE_MASK 0xf 3213 #define IIEPH1_SOURCE_SHFT 20 3214 #define IIEPH1_SOURCE_MASK 11 3215 #define IIEPH1_SUPPL_SHFT 8 3216 #define IIEPH1_SUPPL_MASK 11 3217 #define IIEPH1_CMD_SHFT 0 3218 #define IIEPH1_CMD_MASK 7 3219 3220 #define IIEPH2_TAIL (1UL << 40) 3221 #define IIEPH2_ADDRESS_SHFT 0 3222 #define IIEPH2_ADDRESS_MASK 38 3223 3224 #define IIEPH1_ERR_SHORT_REQ 2 3225 #define IIEPH1_ERR_SHORT_REPLY 3 3226 #define IIEPH1_ERR_LONG_REQ 4 3227 #define IIEPH1_ERR_LONG_REPLY 5 3228 3229 /* 3230 * IO Error Clear register bit field definitions 3231 */ 3232 #define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ 3233 #define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ 3234 #define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ 3235 #define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ 3236 #define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ 3237 #define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ 3238 #define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ 3239 #define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ 3240 #define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ 3241 #define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ 3242 #define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ 3243 #define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ 3244 #define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ 3245 #define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ 3246 #define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ 3247 3248 /* 3249 * IIO CRB control register Fields: IIO_ICCR 3250 */ 3251 #define IIO_ICCR_PENDING (0x10000) 3252 #define IIO_ICCR_CMD_MASK (0xFF) 3253 #define IIO_ICCR_CMD_SHFT (7) 3254 #define IIO_ICCR_CMD_NOP (0x0) /* No Op */ 3255 #define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ 3256 #define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ 3257 #define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory 3258 * via a WB 3259 */ 3260 #define IIO_ICCR_CMD_FLUSH (0x800) 3261 3262 /* 3263 * 3264 * CRB Register description. 3265 * 3266 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3267 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3268 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3269 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3270 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING 3271 * 3272 * Many of the fields in CRB are status bits used by hardware 3273 * for implementation of the protocol. It's very dangerous to 3274 * mess around with the CRB registers. 3275 * 3276 * It's OK to read the CRB registers and try to make sense out of the 3277 * fields in CRB. 3278 * 3279 * Updating CRB requires all activities in Hub IIO to be quiesced. 3280 * otherwise, a write to CRB could corrupt other CRB entries. 3281 * CRBs are here only as a back door peek to shub IIO's status. 3282 * Quiescing implies no dmas no PIOs 3283 * either directly from the cpu or from sn0net. 3284 * this is not something that can be done easily. So, AVOID updating 3285 * CRBs. 3286 */ 3287 3288 #ifndef __ASSEMBLY__ 3289 3290 /* 3291 * Easy access macros for CRBs, all 5 registers (A-E) 3292 */ 3293 typedef ii_icrb0_a_u_t icrba_t; 3294 #define a_sidn ii_icrb0_a_fld_s.ia_sidn 3295 #define a_tnum ii_icrb0_a_fld_s.ia_tnum 3296 #define a_addr ii_icrb0_a_fld_s.ia_addr 3297 #define a_valid ii_icrb0_a_fld_s.ia_vld 3298 #define a_iow ii_icrb0_a_fld_s.ia_iow 3299 #define a_regvalue ii_icrb0_a_regval 3300 3301 typedef ii_icrb0_b_u_t icrbb_t; 3302 #define b_use_old ii_icrb0_b_fld_s.ib_use_old 3303 #define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype 3304 #define b_imsg ii_icrb0_b_fld_s.ib_imsg 3305 #define b_initiator ii_icrb0_b_fld_s.ib_init 3306 #define b_exc ii_icrb0_b_fld_s.ib_exc 3307 #define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt 3308 #define b_resp ii_icrb0_b_fld_s.ib_resp 3309 #define b_ack ii_icrb0_b_fld_s.ib_ack 3310 #define b_hold ii_icrb0_b_fld_s.ib_hold 3311 #define b_wb ii_icrb0_b_fld_s.ib_wb 3312 #define b_intvn ii_icrb0_b_fld_s.ib_intvn 3313 #define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib 3314 #define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr 3315 #define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0 3316 #define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1 3317 #define b_error ii_icrb0_b_fld_s.ib_error 3318 #define b_ecode ii_icrb0_b_fld_s.ib_errcode 3319 #define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce 3320 #define b_mark ii_icrb0_b_fld_s.ib_mark 3321 #define b_xerr ii_icrb0_b_fld_s.ib_xt_err 3322 #define b_regvalue ii_icrb0_b_regval 3323 3324 typedef ii_icrb0_c_u_t icrbc_t; 3325 #define c_suppl ii_icrb0_c_fld_s.ic_suppl 3326 #define c_barrop ii_icrb0_c_fld_s.ic_bo 3327 #define c_doresp ii_icrb0_c_fld_s.ic_resprqd 3328 #define c_gbr ii_icrb0_c_fld_s.ic_gbr 3329 #define c_btenum ii_icrb0_c_fld_s.ic_bte_num 3330 #define c_cohtrans ii_icrb0_c_fld_s.ic_ct 3331 #define c_xtsize ii_icrb0_c_fld_s.ic_size 3332 #define c_source ii_icrb0_c_fld_s.ic_source 3333 #define c_regvalue ii_icrb0_c_regval 3334 3335 3336 typedef ii_icrb0_d_u_t icrbd_t; 3337 #define d_sleep ii_icrb0_d_fld_s.id_sleep 3338 #define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt 3339 #define d_pripsc ii_icrb0_d_fld_s.id_pr_psc 3340 #define d_bteop ii_icrb0_d_fld_s.id_bte_op 3341 #define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ 3342 #define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ 3343 #define d_regvalue ii_icrb0_d_regval 3344 3345 typedef ii_icrb0_e_u_t icrbe_t; 3346 #define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld 3347 #define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld 3348 #define icrbe_context ii_icrb0_e_fld_s.ie_context 3349 #define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout 3350 #define e_regvalue ii_icrb0_e_regval 3351 3352 #endif /* __ASSEMBLY__ */ 3353 3354 /* Number of widgets supported by shub */ 3355 #define HUB_NUM_WIDGET 9 3356 #define HUB_WIDGET_ID_MIN 0x8 3357 #define HUB_WIDGET_ID_MAX 0xf 3358 3359 #define HUB_WIDGET_PART_NUM 0xc120 3360 #define MAX_HUBS_PER_XBOW 2 3361 3362 #ifndef __ASSEMBLY__ 3363 /* A few more #defines for backwards compatibility */ 3364 #define iprb_t ii_iprb0_u_t 3365 #define iprb_regval ii_iprb0_regval 3366 #define iprb_mult_err ii_iprb0_fld_s.i_mult_err 3367 #define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd 3368 #define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr 3369 #define iprb_rd_to ii_iprb0_fld_s.i_rd_to 3370 #define iprb_ovflow ii_iprb0_fld_s.i_of_cnt 3371 #define iprb_error ii_iprb0_fld_s.i_error 3372 #define iprb_ff ii_iprb0_fld_s.i_f 3373 #define iprb_mode ii_iprb0_fld_s.i_m 3374 #define iprb_bnakctr ii_iprb0_fld_s.i_nb 3375 #define iprb_anakctr ii_iprb0_fld_s.i_na 3376 #define iprb_xtalkctr ii_iprb0_fld_s.i_c 3377 #endif 3378 3379 #define LNK_STAT_WORKING 0x2 /* LLP is working */ 3380 3381 #define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ 3382 #define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ 3383 #define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */ 3384 #define IIO_WSTAT_TXRETRY_SHFT (16) 3385 #define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ 3386 IIO_WSTAT_TXRETRY_MASK) 3387 3388 /* Number of II perf. counters we can multiplex at once */ 3389 3390 #define IO_PERF_SETS 32 3391 3392 #if __KERNEL__ 3393 #ifndef __ASSEMBLY__ 3394 #include <asm/sn/alenlist.h> 3395 #include <asm/sn/dmamap.h> 3396 #include <asm/sn/driver.h> 3397 #include <asm/sn/xtalk/xtalk.h> 3398 3399 /* Bit for the widget in inbound access register */ 3400 #define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) 3401 /* Bit for the widget in outbound access register */ 3402 #define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) 3403 3404 /* NOTE: The following define assumes that we are going to get 3405 * widget numbers from 8 thru F and the device numbers within 3406 * widget from 0 thru 7. 3407 */ 3408 #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) 3409 3410 /* IO Interrupt Destination Register */ 3411 #define IIO_IIDSR_SENT_SHIFT 28 3412 #define IIO_IIDSR_SENT_MASK 0x30000000 3413 #define IIO_IIDSR_ENB_SHIFT 24 3414 #define IIO_IIDSR_ENB_MASK 0x01000000 3415 #define IIO_IIDSR_NODE_SHIFT 9 3416 #define IIO_IIDSR_NODE_MASK 0x000ff700 3417 #define IIO_IIDSR_PI_ID_SHIFT 8 3418 #define IIO_IIDSR_PI_ID_MASK 0x00000100 3419 #define IIO_IIDSR_LVL_SHIFT 0 3420 #define IIO_IIDSR_LVL_MASK 0x000000ff 3421 3422 /* Xtalk timeout threshhold register (IIO_IXTT) */ 3423 #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ 3424 #define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) 3425 #define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ 3426 #define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) 3427 #define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ 3428 #define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) 3429 3430 /* 3431 * The IO LLP control status register and widget control register 3432 */ 3433 3434 typedef union hubii_wcr_u { 3435 uint64_t wcr_reg_value; 3436 struct { 3437 uint64_t wcr_widget_id: 4, /* LLP crossbar credit */ 3438 wcr_tag_mode: 1, /* Tag mode */ 3439 wcr_rsvd1: 8, /* Reserved */ 3440 wcr_xbar_crd: 3, /* LLP crossbar credit */ 3441 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ 3442 wcr_dir_con: 1, /* widget direct connect */ 3443 wcr_e_thresh: 5, /* elasticity threshold */ 3444 wcr_rsvd: 41; /* unused */ 3445 } wcr_fields_s; 3446 } hubii_wcr_t; 3447 3448 #define iwcr_dir_con wcr_fields_s.wcr_dir_con 3449 3450 /* The structures below are defined to extract and modify the ii 3451 performance registers */ 3452 3453 /* io_perf_sel allows the caller to specify what tests will be 3454 performed */ 3455 3456 typedef union io_perf_sel { 3457 uint64_t perf_sel_reg; 3458 struct { 3459 uint64_t perf_ippr0 : 4, 3460 perf_ippr1 : 4, 3461 perf_icct : 8, 3462 perf_rsvd : 48; 3463 } perf_sel_bits; 3464 } io_perf_sel_t; 3465 3466 /* io_perf_cnt is to extract the count from the shub registers. Due to 3467 hardware problems there is only one counter, not two. */ 3468 3469 typedef union io_perf_cnt { 3470 uint64_t perf_cnt; 3471 struct { 3472 uint64_t perf_cnt : 20, 3473 perf_rsvd2 : 12, 3474 perf_rsvd1 : 32; 3475 } perf_cnt_bits; 3476 3477 } io_perf_cnt_t; 3478 3479 typedef union iprte_a { 3480 shubreg_t entry; 3481 struct { 3482 shubreg_t i_rsvd_1 : 3; 3483 shubreg_t i_addr : 38; 3484 shubreg_t i_init : 3; 3485 shubreg_t i_source : 8; 3486 shubreg_t i_rsvd : 2; 3487 shubreg_t i_widget : 4; 3488 shubreg_t i_to_cnt : 5; 3489 shubreg_t i_vld : 1; 3490 } iprte_fields; 3491 } iprte_a_t; 3492 3493 3494 /* PIO MANAGEMENT */ 3495 typedef struct hub_piomap_s *hub_piomap_t; 3496 3497 extern hub_piomap_t 3498 hub_piomap_alloc(vertex_hdl_t dev, /* set up mapping for this device */ 3499 device_desc_t dev_desc, /* device descriptor */ 3500 iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ 3501 size_t byte_count, 3502 size_t byte_count_max, /* maximum size of a mapping */ 3503 unsigned flags); /* defined in sys/pio.h */ 3504 3505 extern void hub_piomap_free(hub_piomap_t hub_piomap); 3506 3507 extern caddr_t 3508 hub_piomap_addr(hub_piomap_t hub_piomap, /* mapping resources */ 3509 iopaddr_t xtalk_addr, /* map for this xtalk addr */ 3510 size_t byte_count); /* map this many bytes */ 3511 3512 extern void 3513 hub_piomap_done(hub_piomap_t hub_piomap); 3514 3515 extern caddr_t 3516 hub_piotrans_addr( vertex_hdl_t dev, /* translate to this device */ 3517 device_desc_t dev_desc, /* device descriptor */ 3518 iopaddr_t xtalk_addr, /* Crosstalk address */ 3519 size_t byte_count, /* map this many bytes */ 3520 unsigned flags); /* (currently unused) */ 3521 3522 /* DMA MANAGEMENT */ 3523 typedef struct hub_dmamap_s *hub_dmamap_t; 3524 3525 extern hub_dmamap_t 3526 hub_dmamap_alloc( vertex_hdl_t dev, /* set up mappings for dev */ 3527 device_desc_t dev_desc, /* device descriptor */ 3528 size_t byte_count_max, /* max size of a mapping */ 3529 unsigned flags); /* defined in dma.h */ 3530 3531 extern void 3532 hub_dmamap_free(hub_dmamap_t dmamap); 3533 3534 extern iopaddr_t 3535 hub_dmamap_addr( hub_dmamap_t dmamap, /* use mapping resources */ 3536 paddr_t paddr, /* map for this address */ 3537 size_t byte_count); /* map this many bytes */ 3538 3539 extern alenlist_t 3540 hub_dmamap_list( hub_dmamap_t dmamap, /* use mapping resources */ 3541 alenlist_t alenlist, /* map this Addr/Length List */ 3542 unsigned flags); 3543 3544 extern void 3545 hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */ 3546 3547 extern iopaddr_t 3548 hub_dmatrans_addr( vertex_hdl_t dev, /* translate for this device */ 3549 device_desc_t dev_desc, /* device descriptor */ 3550 paddr_t paddr, /* system physical address */ 3551 size_t byte_count, /* length */ 3552 unsigned flags); /* defined in dma.h */ 3553 3554 extern alenlist_t 3555 hub_dmatrans_list( vertex_hdl_t dev, /* translate for this device */ 3556 device_desc_t dev_desc, /* device descriptor */ 3557 alenlist_t palenlist, /* system addr/length list */ 3558 unsigned flags); /* defined in dma.h */ 3559 3560 extern void 3561 hub_dmamap_drain( hub_dmamap_t map); 3562 3563 extern void 3564 hub_dmaaddr_drain( vertex_hdl_t vhdl, 3565 paddr_t addr, 3566 size_t bytes); 3567 3568 extern void 3569 hub_dmalist_drain( vertex_hdl_t vhdl, 3570 alenlist_t list); 3571 3572 3573 /* INTERRUPT MANAGEMENT */ 3574 typedef struct hub_intr_s *hub_intr_t; 3575 3576 extern hub_intr_t 3577 hub_intr_alloc( vertex_hdl_t dev, /* which device */ 3578 device_desc_t dev_desc, /* device descriptor */ 3579 vertex_hdl_t owner_dev); /* owner of this interrupt */ 3580 3581 extern hub_intr_t 3582 hub_intr_alloc_nothd(vertex_hdl_t dev, /* which device */ 3583 device_desc_t dev_desc, /* device descriptor */ 3584 vertex_hdl_t owner_dev); /* owner of this interrupt */ 3585 3586 extern void 3587 hub_intr_free(hub_intr_t intr_hdl); 3588 3589 extern int 3590 hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ 3591 intr_func_t intr_func, /* xtalk intr handler */ 3592 void *intr_arg, /* arg to intr handler */ 3593 xtalk_intr_setfunc_t setfunc, /* func to set intr hw */ 3594 void *setfunc_arg); /* arg to setfunc */ 3595 3596 extern void 3597 hub_intr_disconnect(hub_intr_t intr_hdl); 3598 3599 3600 /* CONFIGURATION MANAGEMENT */ 3601 3602 extern void 3603 hub_provider_startup(vertex_hdl_t hub); 3604 3605 extern void 3606 hub_provider_shutdown(vertex_hdl_t hub); 3607 3608 #define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */ 3609 #define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */ 3610 3611 /* Flags that make sense to hub_widget_flags_set */ 3612 #define HUB_WIDGET_FLAGS ( \ 3613 HUB_PIO_CONVEYOR | \ 3614 HUB_PIO_FIRE_N_FORGET \ 3615 ) 3616 3617 3618 typedef int hub_widget_flags_t; 3619 3620 /* Set the PIO mode for a widget. */ 3621 extern int hub_widget_flags_set(nasid_t nasid, 3622 xwidgetnum_t widget_num, 3623 hub_widget_flags_t flags); 3624 3625 /* Error Handling. */ 3626 extern int hub_ioerror_handler(vertex_hdl_t, int, int, struct io_error_s *); 3627 extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t, 3628 int, paddr_t, caddr_t, ioerror_mode_t); 3629 extern int hub_error_devenable(vertex_hdl_t, int, int); 3630 extern int hub_dma_enabled(vertex_hdl_t); 3631 3632 extern caddr_t hubdev_prombase_get(vertex_hdl_t hub); 3633 3634 extern cnodeid_t hubdev_cnodeid_get(vertex_hdl_t hub); 3635 3636 #endif /* __ASSEMBLY__ */ 3637 #endif /* _KERNEL */ 3638 #endif /* _ASM_IA64_SN_SN2_SHUBIO_H */ 3639 3640