1 /* $Id: avmcard.h,v 1.1.4.1 2001/11/20 14:19:34 kai Exp $
2 *
3 * Copyright 1999 by Carsten Paeth <calle@calle.de>
4 *
5 * This software may be used and distributed according to the terms
6 * of the GNU General Public License, incorporated herein by reference.
7 *
8 */
9
10 #ifndef _AVMCARD_H_
11 #define _AVMCARD_H_
12
13 #define AVMB1_PORTLEN 0x1f
14 #define AVM_MAXVERSION 8
15 #define AVM_NCCI_PER_CHANNEL 4
16
17 /*
18 * Versions
19 */
20
21 #define VER_DRIVER 0
22 #define VER_CARDTYPE 1
23 #define VER_HWID 2
24 #define VER_SERIAL 3
25 #define VER_OPTION 4
26 #define VER_PROTO 5
27 #define VER_PROFILE 6
28 #define VER_CAPI 7
29
30 enum avmcardtype {
31 avm_b1isa,
32 avm_b1pci,
33 avm_b1pcmcia,
34 avm_m1,
35 avm_m2,
36 avm_t1isa,
37 avm_t1pci,
38 avm_c4,
39 avm_c2
40 };
41
42 typedef struct avmcard_dmainfo {
43 __u32 recvlen;
44 __u8 recvbuf[128+2048];
45 struct sk_buff_head send_queue;
46 __u8 sendbuf[128+2048];
47 } avmcard_dmainfo;
48
49
50 typedef struct avmcard {
51 char name[32];
52 unsigned int port;
53 unsigned irq;
54 unsigned long membase;
55 enum avmcardtype cardtype;
56 unsigned char revision;
57 unsigned char class;
58 int cardnr; /* for t1isa */
59
60 char msgbuf[128]; /* capimsg msg part */
61 char databuf[2048]; /* capimsg data part */
62
63 int interrupt;
64
65 void *mbase;
66 volatile __u32 csr;
67 avmcard_dmainfo *dma;
68
69 struct avmctrl_info {
70 char cardname[32];
71
72 int versionlen;
73 char versionbuf[1024];
74 char *version[AVM_MAXVERSION];
75
76 char infobuf[128]; /* for function procinfo */
77
78 struct avmcard *card;
79 struct capi_ctr *capi_ctrl;
80
81 } *ctrlinfo;
82
83 int nlogcontr;
84 } avmcard;
85
86 typedef struct avmctrl_info avmctrl_info;
87
88 extern int b1_irq_table[16];
89
90 /*
91 * LLI Messages to the ISDN-ControllerISDN Controller
92 */
93
94 #define SEND_POLL 0x72 /*
95 * after load <- RECEIVE_POLL
96 */
97 #define SEND_INIT 0x11 /*
98 * first message <- RECEIVE_INIT
99 * int32 NumApplications int32
100 * NumNCCIs int32 BoardNumber
101 */
102 #define SEND_REGISTER 0x12 /*
103 * register an application int32
104 * ApplIDId int32 NumMessages
105 * int32 NumB3Connections int32
106 * NumB3Blocks int32 B3Size
107 *
108 * AnzB3Connection != 0 &&
109 * AnzB3Blocks >= 1 && B3Size >= 1
110 */
111 #define SEND_RELEASE 0x14 /*
112 * deregister an application int32
113 * ApplID
114 */
115 #define SEND_MESSAGE 0x15 /*
116 * send capi-message int32 length
117 * capi-data ...
118 */
119 #define SEND_DATA_B3_REQ 0x13 /*
120 * send capi-data-message int32
121 * MsgLength capi-data ... int32
122 * B3Length data ....
123 */
124
125 #define SEND_CONFIG 0x21 /*
126 */
127
128 #define SEND_POLLACK 0x73 /* T1 Watchdog */
129
130 /*
131 * LLI Messages from the ISDN-ControllerISDN Controller
132 */
133
134 #define RECEIVE_POLL 0x32 /*
135 * <- after SEND_POLL
136 */
137 #define RECEIVE_INIT 0x27 /*
138 * <- after SEND_INIT int32 length
139 * byte total length b1struct board
140 * driver revision b1struct card
141 * type b1struct reserved b1struct
142 * serial number b1struct driver
143 * capability b1struct d-channel
144 * protocol b1struct CAPI-2.0
145 * profile b1struct capi version
146 */
147 #define RECEIVE_MESSAGE 0x21 /*
148 * <- after SEND_MESSAGE int32
149 * AppllID int32 Length capi-data
150 * ....
151 */
152 #define RECEIVE_DATA_B3_IND 0x22 /*
153 * received data int32 AppllID
154 * int32 Length capi-data ...
155 * int32 B3Length data ...
156 */
157 #define RECEIVE_START 0x23 /*
158 * Handshake
159 */
160 #define RECEIVE_STOP 0x24 /*
161 * Handshake
162 */
163 #define RECEIVE_NEW_NCCI 0x25 /*
164 * int32 AppllID int32 NCCI int32
165 * WindowSize
166 */
167 #define RECEIVE_FREE_NCCI 0x26 /*
168 * int32 AppllID int32 NCCI
169 */
170 #define RECEIVE_RELEASE 0x26 /*
171 * int32 AppllID int32 0xffffffff
172 */
173 #define RECEIVE_TASK_READY 0x31 /*
174 * int32 tasknr
175 * int32 Length Taskname ...
176 */
177 #define RECEIVE_DEBUGMSG 0x71 /*
178 * int32 Length message
179 *
180 */
181 #define RECEIVE_POLLDWORD 0x75 /* t1pci in dword mode */
182
183 #define WRITE_REGISTER 0x00
184 #define READ_REGISTER 0x01
185
186 /*
187 * port offsets
188 */
189
190 #define B1_READ 0x00
191 #define B1_WRITE 0x01
192 #define B1_INSTAT 0x02
193 #define B1_OUTSTAT 0x03
194 #define B1_ANALYSE 0x04
195 #define B1_REVISION 0x05
196 #define B1_RESET 0x10
197
198
199 #define B1_STAT0(cardtype) ((cardtype) == avm_m1 ? 0x81200000l : 0x80A00000l)
200 #define B1_STAT1(cardtype) (0x80E00000l)
201
202 /* ---------------------------------------------------------------- */
203
b1outp(unsigned int base,unsigned short offset,unsigned char value)204 static inline unsigned char b1outp(unsigned int base,
205 unsigned short offset,
206 unsigned char value)
207 {
208 outb(value, base + offset);
209 return inb(base + B1_ANALYSE);
210 }
211
212
b1_rx_full(unsigned int base)213 static inline int b1_rx_full(unsigned int base)
214 {
215 return inb(base + B1_INSTAT) & 0x1;
216 }
217
b1_get_byte(unsigned int base)218 static inline unsigned char b1_get_byte(unsigned int base)
219 {
220 unsigned long stop = jiffies + 1 * HZ; /* maximum wait time 1 sec */
221 while (!b1_rx_full(base) && time_before(jiffies, stop));
222 if (b1_rx_full(base))
223 return inb(base + B1_READ);
224 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base);
225 return 0;
226 }
227
b1_get_word(unsigned int base)228 static inline unsigned int b1_get_word(unsigned int base)
229 {
230 unsigned int val = 0;
231 val |= b1_get_byte(base);
232 val |= (b1_get_byte(base) << 8);
233 val |= (b1_get_byte(base) << 16);
234 val |= (b1_get_byte(base) << 24);
235 return val;
236 }
237
b1_tx_empty(unsigned int base)238 static inline int b1_tx_empty(unsigned int base)
239 {
240 return inb(base + B1_OUTSTAT) & 0x1;
241 }
242
b1_put_byte(unsigned int base,unsigned char val)243 static inline void b1_put_byte(unsigned int base, unsigned char val)
244 {
245 while (!b1_tx_empty(base));
246 b1outp(base, B1_WRITE, val);
247 }
248
b1_save_put_byte(unsigned int base,unsigned char val)249 static inline int b1_save_put_byte(unsigned int base, unsigned char val)
250 {
251 unsigned long stop = jiffies + 2 * HZ;
252 while (!b1_tx_empty(base) && time_before(jiffies,stop));
253 if (!b1_tx_empty(base)) return -1;
254 b1outp(base, B1_WRITE, val);
255 return 0;
256 }
257
b1_put_word(unsigned int base,unsigned int val)258 static inline void b1_put_word(unsigned int base, unsigned int val)
259 {
260 b1_put_byte(base, val & 0xff);
261 b1_put_byte(base, (val >> 8) & 0xff);
262 b1_put_byte(base, (val >> 16) & 0xff);
263 b1_put_byte(base, (val >> 24) & 0xff);
264 }
265
b1_get_slice(unsigned int base,unsigned char * dp)266 static inline unsigned int b1_get_slice(unsigned int base,
267 unsigned char *dp)
268 {
269 unsigned int len, i;
270
271 len = i = b1_get_word(base);
272 while (i-- > 0) *dp++ = b1_get_byte(base);
273 return len;
274 }
275
b1_put_slice(unsigned int base,unsigned char * dp,unsigned int len)276 static inline void b1_put_slice(unsigned int base,
277 unsigned char *dp, unsigned int len)
278 {
279 unsigned i = len;
280 b1_put_word(base, i);
281 while (i-- > 0)
282 b1_put_byte(base, *dp++);
283 }
284
b1_wr_reg(unsigned int base,unsigned int reg,unsigned int value)285 static void b1_wr_reg(unsigned int base,
286 unsigned int reg,
287 unsigned int value)
288 {
289 b1_put_byte(base, WRITE_REGISTER);
290 b1_put_word(base, reg);
291 b1_put_word(base, value);
292 }
293
b1_rd_reg(unsigned int base,unsigned int reg)294 static inline unsigned int b1_rd_reg(unsigned int base,
295 unsigned int reg)
296 {
297 b1_put_byte(base, READ_REGISTER);
298 b1_put_word(base, reg);
299 return b1_get_word(base);
300
301 }
302
b1_reset(unsigned int base)303 static inline void b1_reset(unsigned int base)
304 {
305 b1outp(base, B1_RESET, 0);
306 mdelay(55 * 2); /* 2 TIC's */
307
308 b1outp(base, B1_RESET, 1);
309 mdelay(55 * 2); /* 2 TIC's */
310
311 b1outp(base, B1_RESET, 0);
312 mdelay(55 * 2); /* 2 TIC's */
313 }
314
b1_disable_irq(unsigned int base)315 static inline unsigned char b1_disable_irq(unsigned int base)
316 {
317 return b1outp(base, B1_INSTAT, 0x00);
318 }
319
320 /* ---------------------------------------------------------------- */
321
b1_set_test_bit(unsigned int base,enum avmcardtype cardtype,int onoff)322 static inline void b1_set_test_bit(unsigned int base,
323 enum avmcardtype cardtype,
324 int onoff)
325 {
326 b1_wr_reg(base, B1_STAT0(cardtype), onoff ? 0x21 : 0x20);
327 }
328
b1_get_test_bit(unsigned int base,enum avmcardtype cardtype)329 static inline int b1_get_test_bit(unsigned int base,
330 enum avmcardtype cardtype)
331 {
332 return (b1_rd_reg(base, B1_STAT0(cardtype)) & 0x01) != 0;
333 }
334
335 /* ---------------------------------------------------------------- */
336
337 #define T1_FASTLINK 0x00
338 #define T1_SLOWLINK 0x08
339
340 #define T1_READ B1_READ
341 #define T1_WRITE B1_WRITE
342 #define T1_INSTAT B1_INSTAT
343 #define T1_OUTSTAT B1_OUTSTAT
344 #define T1_IRQENABLE 0x05
345 #define T1_FIFOSTAT 0x06
346 #define T1_RESETLINK 0x10
347 #define T1_ANALYSE 0x11
348 #define T1_IRQMASTER 0x12
349 #define T1_IDENT 0x17
350 #define T1_RESETBOARD 0x1f
351
352 #define T1F_IREADY 0x01
353 #define T1F_IHALF 0x02
354 #define T1F_IFULL 0x04
355 #define T1F_IEMPTY 0x08
356 #define T1F_IFLAGS 0xF0
357
358 #define T1F_OREADY 0x10
359 #define T1F_OHALF 0x20
360 #define T1F_OEMPTY 0x40
361 #define T1F_OFULL 0x80
362 #define T1F_OFLAGS 0xF0
363
364 /* there are HEMA cards with 1k and 4k FIFO out */
365 #define FIFO_OUTBSIZE 256
366 #define FIFO_INPBSIZE 512
367
368 #define HEMA_VERSION_ID 0
369 #define HEMA_PAL_ID 0
370
t1outp(unsigned int base,unsigned short offset,unsigned char value)371 static inline void t1outp(unsigned int base,
372 unsigned short offset,
373 unsigned char value)
374 {
375 outb(value, base + offset);
376 }
377
t1inp(unsigned int base,unsigned short offset)378 static inline unsigned char t1inp(unsigned int base,
379 unsigned short offset)
380 {
381 return inb(base + offset);
382 }
383
t1_isfastlink(unsigned int base)384 static inline int t1_isfastlink(unsigned int base)
385 {
386 return (inb(base + T1_IDENT) & ~0x82) == 1;
387 }
388
t1_fifostatus(unsigned int base)389 static inline unsigned char t1_fifostatus(unsigned int base)
390 {
391 return inb(base + T1_FIFOSTAT);
392 }
393
t1_get_slice(unsigned int base,unsigned char * dp)394 static inline unsigned int t1_get_slice(unsigned int base,
395 unsigned char *dp)
396 {
397 unsigned int len, i;
398 #ifdef FASTLINK_DEBUG
399 unsigned wcnt = 0, bcnt = 0;
400 #endif
401
402 len = i = b1_get_word(base);
403 if (t1_isfastlink(base)) {
404 int status;
405 while (i > 0) {
406 status = t1_fifostatus(base) & (T1F_IREADY|T1F_IHALF);
407 if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
408
409 switch (status) {
410 case T1F_IREADY|T1F_IHALF|T1F_IFULL:
411 insb(base+B1_READ, dp, FIFO_INPBSIZE);
412 dp += FIFO_INPBSIZE;
413 i -= FIFO_INPBSIZE;
414 #ifdef FASTLINK_DEBUG
415 wcnt += FIFO_INPBSIZE;
416 #endif
417 break;
418 case T1F_IREADY|T1F_IHALF:
419 insb(base+B1_READ,dp, i);
420 #ifdef FASTLINK_DEBUG
421 wcnt += i;
422 #endif
423 dp += i;
424 i = 0;
425 if (i == 0)
426 break;
427 /* fall through */
428 default:
429 *dp++ = b1_get_byte(base);
430 i--;
431 #ifdef FASTLINK_DEBUG
432 bcnt++;
433 #endif
434 break;
435 }
436 }
437 #ifdef FASTLINK_DEBUG
438 if (wcnt)
439 printk(KERN_DEBUG "b1lli(0x%x): get_slice l=%d w=%d b=%d\n",
440 base, len, wcnt, bcnt);
441 #endif
442 } else {
443 while (i-- > 0)
444 *dp++ = b1_get_byte(base);
445 }
446 return len;
447 }
448
t1_put_slice(unsigned int base,unsigned char * dp,unsigned int len)449 static inline void t1_put_slice(unsigned int base,
450 unsigned char *dp, unsigned int len)
451 {
452 unsigned i = len;
453 b1_put_word(base, i);
454 if (t1_isfastlink(base)) {
455 int status;
456 while (i > 0) {
457 status = t1_fifostatus(base) & (T1F_OREADY|T1F_OHALF);
458 if (i >= FIFO_OUTBSIZE) status |= T1F_OEMPTY;
459 switch (status) {
460 case T1F_OREADY|T1F_OHALF|T1F_OEMPTY:
461 outsb(base+B1_WRITE, dp, FIFO_OUTBSIZE);
462 dp += FIFO_OUTBSIZE;
463 i -= FIFO_OUTBSIZE;
464 break;
465 case T1F_OREADY|T1F_OHALF:
466 outsb(base+B1_WRITE, dp, i);
467 dp += i;
468 i = 0;
469 break;
470 default:
471 b1_put_byte(base, *dp++);
472 i--;
473 break;
474 }
475 }
476 } else {
477 while (i-- > 0)
478 b1_put_byte(base, *dp++);
479 }
480 }
481
t1_disable_irq(unsigned int base)482 static inline void t1_disable_irq(unsigned int base)
483 {
484 t1outp(base, T1_IRQMASTER, 0x00);
485 }
486
t1_reset(unsigned int base)487 static inline void t1_reset(unsigned int base)
488 {
489 /* reset T1 Controller */
490 b1_reset(base);
491 /* disable irq on HEMA */
492 t1outp(base, B1_INSTAT, 0x00);
493 t1outp(base, B1_OUTSTAT, 0x00);
494 t1outp(base, T1_IRQMASTER, 0x00);
495 /* reset HEMA board configuration */
496 t1outp(base, T1_RESETBOARD, 0xf);
497 }
498
b1_setinterrupt(unsigned int base,unsigned irq,enum avmcardtype cardtype)499 static inline void b1_setinterrupt(unsigned int base, unsigned irq,
500 enum avmcardtype cardtype)
501 {
502 switch (cardtype) {
503 case avm_t1isa:
504 t1outp(base, B1_INSTAT, 0x00);
505 t1outp(base, B1_INSTAT, 0x02);
506 t1outp(base, T1_IRQMASTER, 0x08);
507 break;
508 case avm_b1isa:
509 b1outp(base, B1_INSTAT, 0x00);
510 b1outp(base, B1_RESET, b1_irq_table[irq]);
511 b1outp(base, B1_INSTAT, 0x02);
512 break;
513 default:
514 case avm_m1:
515 case avm_m2:
516 case avm_b1pci:
517 b1outp(base, B1_INSTAT, 0x00);
518 b1outp(base, B1_RESET, 0xf0);
519 b1outp(base, B1_INSTAT, 0x02);
520 break;
521 case avm_c4:
522 case avm_t1pci:
523 b1outp(base, B1_RESET, 0xf0);
524 break;
525 }
526 }
527
528 /* b1.c */
529 int b1_detect(unsigned int base, enum avmcardtype cardtype);
530 void b1_getrevision(avmcard *card);
531 int b1_load_t4file(avmcard *card, capiloaddatapart * t4file);
532 int b1_load_config(avmcard *card, capiloaddatapart * config);
533 int b1_loaded(avmcard *card);
534
535 int b1_load_firmware(struct capi_ctr *ctrl, capiloaddata *data);
536 void b1_reset_ctr(struct capi_ctr *ctrl);
537 void b1_register_appl(struct capi_ctr *ctrl, __u16 appl,
538 capi_register_params *rp);
539 void b1_release_appl(struct capi_ctr *ctrl, __u16 appl);
540 void b1_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
541 void b1_parse_version(avmctrl_info *card);
542 void b1_handle_interrupt(avmcard * card);
543
544 int b1ctl_read_proc(char *page, char **start, off_t off,
545 int count, int *eof, struct capi_ctr *ctrl);
546
547 /* b1dma.c */
548 int b1pciv4_detect(avmcard *card);
549 int t1pci_detect(avmcard *card);
550 void b1dma_reset(avmcard *card);
551 void b1dma_interrupt(int interrupt, void *devptr, struct pt_regs *regs);
552
553 int b1dma_load_firmware(struct capi_ctr *ctrl, capiloaddata *data);
554 void b1dma_reset_ctr(struct capi_ctr *ctrl);
555 void b1dma_remove_ctr(struct capi_ctr *ctrl);
556 void b1dma_register_appl(struct capi_ctr *ctrl,
557 __u16 appl,
558 capi_register_params *rp);
559 void b1dma_release_appl(struct capi_ctr *ctrl, __u16 appl);
560 void b1dma_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
561 int b1dmactl_read_proc(char *page, char **start, off_t off,
562 int count, int *eof, struct capi_ctr *ctrl);
563
564 #endif /* _AVMCARD_H_ */
565