1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4  * Copyright (c) 2006, 2007 Cisco Systems.  All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 
35 #ifndef MLX4_FW_H
36 #define MLX4_FW_H
37 
38 #include "mlx4.h"
39 #include "icm.h"
40 
41 struct mlx4_mod_stat_cfg {
42 	u8 log_pg_sz;
43 	u8 log_pg_sz_m;
44 };
45 
46 struct mlx4_dev_cap {
47 	int max_srq_sz;
48 	int max_qp_sz;
49 	int reserved_qps;
50 	int max_qps;
51 	int reserved_srqs;
52 	int max_srqs;
53 	int max_cq_sz;
54 	int reserved_cqs;
55 	int max_cqs;
56 	int max_mpts;
57 	int reserved_eqs;
58 	int max_eqs;
59 	int reserved_mtts;
60 	int max_mrw_sz;
61 	int reserved_mrws;
62 	int max_mtt_seg;
63 	int max_requester_per_qp;
64 	int max_responder_per_qp;
65 	int max_rdma_global;
66 	int local_ca_ack_delay;
67 	int num_ports;
68 	u32 max_msg_sz;
69 	int ib_mtu[MLX4_MAX_PORTS + 1];
70 	int max_port_width[MLX4_MAX_PORTS + 1];
71 	int max_vl[MLX4_MAX_PORTS + 1];
72 	int max_gids[MLX4_MAX_PORTS + 1];
73 	int max_pkeys[MLX4_MAX_PORTS + 1];
74 	u64 def_mac[MLX4_MAX_PORTS + 1];
75 	u16 eth_mtu[MLX4_MAX_PORTS + 1];
76 	int trans_type[MLX4_MAX_PORTS + 1];
77 	int vendor_oui[MLX4_MAX_PORTS + 1];
78 	u16 wavelength[MLX4_MAX_PORTS + 1];
79 	u64 trans_code[MLX4_MAX_PORTS + 1];
80 	u16 stat_rate_support;
81 	int udp_rss;
82 	int loopback_support;
83 	int vep_uc_steering;
84 	int vep_mc_steering;
85 	int wol;
86 	u32 flags;
87 	int reserved_uars;
88 	int uar_size;
89 	int min_page_sz;
90 	int bf_reg_size;
91 	int bf_regs_per_page;
92 	int max_sq_sg;
93 	int max_sq_desc_sz;
94 	int max_rq_sg;
95 	int max_rq_desc_sz;
96 	int max_qp_per_mcg;
97 	int reserved_mgms;
98 	int max_mcgs;
99 	int reserved_pds;
100 	int max_pds;
101 	int qpc_entry_sz;
102 	int rdmarc_entry_sz;
103 	int altc_entry_sz;
104 	int aux_entry_sz;
105 	int srq_entry_sz;
106 	int cqc_entry_sz;
107 	int eqc_entry_sz;
108 	int dmpt_entry_sz;
109 	int cmpt_entry_sz;
110 	int mtt_entry_sz;
111 	int resize_srq;
112 	u32 bmme_flags;
113 	u32 reserved_lkey;
114 	u64 max_icm_sz;
115 	int max_gso_sz;
116 	u8  supported_port_types[MLX4_MAX_PORTS + 1];
117 	u8  log_max_macs[MLX4_MAX_PORTS + 1];
118 	u8  log_max_vlans[MLX4_MAX_PORTS + 1];
119 };
120 
121 struct mlx4_adapter {
122 	char board_id[MLX4_BOARD_ID_LEN];
123 	u8   inta_pin;
124 };
125 
126 struct mlx4_init_hca_param {
127 	u64 qpc_base;
128 	u64 rdmarc_base;
129 	u64 auxc_base;
130 	u64 altc_base;
131 	u64 srqc_base;
132 	u64 cqc_base;
133 	u64 eqc_base;
134 	u64 mc_base;
135 	u64 dmpt_base;
136 	u64 cmpt_base;
137 	u64 mtt_base;
138 	u16 log_mc_entry_sz;
139 	u16 log_mc_hash_sz;
140 	u8  log_num_qps;
141 	u8  log_num_srqs;
142 	u8  log_num_cqs;
143 	u8  log_num_eqs;
144 	u8  log_rd_per_qp;
145 	u8  log_mc_table_sz;
146 	u8  log_mpt_sz;
147 	u8  log_uar_sz;
148 };
149 
150 struct mlx4_init_ib_param {
151 	int port_width;
152 	int vl_cap;
153 	int mtu_cap;
154 	u16 gid_cap;
155 	u16 pkey_cap;
156 	int set_guid0;
157 	u64 guid0;
158 	int set_node_guid;
159 	u64 node_guid;
160 	int set_si_guid;
161 	u64 si_guid;
162 };
163 
164 struct mlx4_set_ib_param {
165 	int set_si_guid;
166 	int reset_qkey_viol;
167 	u64 si_guid;
168 	u32 cap_mask;
169 };
170 
171 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
172 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
173 int mlx4_UNMAP_FA(struct mlx4_dev *dev);
174 int mlx4_RUN_FW(struct mlx4_dev *dev);
175 int mlx4_QUERY_FW(struct mlx4_dev *dev);
176 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
177 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
178 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
179 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
180 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
181 int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
182 int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
183 int mlx4_NOP(struct mlx4_dev *dev);
184 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
185 
186 #endif /* MLX4_FW_H */
187