1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/spinlock.h>
38 #include <linux/string.h>
39 #include <linux/delay.h>
40 #include <asm/au1000.h>
41 #include <asm/au1xxx_dbdma.h>
42 #include <asm/system.h>
43
44 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
45
46 /*
47 * The Descriptor Based DMA supports up to 16 channels.
48 *
49 * There are 32 devices defined. We keep an internal structure
50 * of devices using these channels, along with additional
51 * information.
52 *
53 * We allocate the descriptors and allow access to them through various
54 * functions. The drivers allocate the data buffers and assign them
55 * to the descriptors.
56 */
57 static spinlock_t au1xxx_dbdma_spin_lock = SPIN_LOCK_UNLOCKED;
58
59 /* I couldn't find a macro that did this......
60 */
61 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
62
63 static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
64 static int dbdma_initialized;
65 static void au1xxx_dbdma_init(void);
66
67 typedef struct dbdma_device_table {
68 u32 dev_id;
69 u32 dev_flags;
70 u32 dev_tsize;
71 u32 dev_devwidth;
72 u32 dev_physaddr; /* If FIFO */
73 u32 dev_intlevel;
74 u32 dev_intpolarity;
75 } dbdev_tab_t;
76
77 typedef struct dbdma_chan_config {
78 u32 chan_flags;
79 u32 chan_index;
80 dbdev_tab_t *chan_src;
81 dbdev_tab_t *chan_dest;
82 au1x_dma_chan_t *chan_ptr;
83 au1x_ddma_desc_t *chan_desc_base;
84 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
85 void *chan_callparam;
86 void (*chan_callback)(int, void *, struct pt_regs *);
87 } chan_tab_t;
88
89 #define DEV_FLAGS_INUSE (1 << 0)
90 #define DEV_FLAGS_ANYUSE (1 << 1)
91 #define DEV_FLAGS_OUT (1 << 2)
92 #define DEV_FLAGS_IN (1 << 3)
93
94 static dbdev_tab_t dbdev_tab[] = {
95 #ifdef CONFIG_SOC_AU1550
96 /* UARTS */
97 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
98 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
99 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
100 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
101
102 /* EXT DMA */
103 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
104 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
105 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
106 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
107
108 /* USB DEV */
109 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
110 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
111 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
112 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
113 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
114 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
115
116 /* PSC 0 */
117 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
118 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
119
120 /* PSC 1 */
121 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
122 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
123
124 /* PSC 2 */
125 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
126 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
127
128 /* PSC 3 */
129 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
130 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
131
132 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
133 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
134
135 /* MAC 0 */
136 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
137 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
138
139 /* MAC 1 */
140 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
141 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
142
143 #endif /* CONFIG_SOC_AU1550 */
144
145 #ifdef CONFIG_SOC_AU1200
146 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
147 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
148 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
149 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
150
151 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
152 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
153
154 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
155 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
156 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
157 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
158
159 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
160 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
161 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
162 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
163
164 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
165 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
166
167 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
168 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
169 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
170
171 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
172 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
173 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
174
175 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
176 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
177 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
178 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
179
180 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
181
182 #endif // CONFIG_SOC_AU1200
183
184 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
185 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
186 };
187
188 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
189
190 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
191
192 static dbdev_tab_t *
find_dbdev_id(u32 id)193 find_dbdev_id (u32 id)
194 {
195 int i;
196 dbdev_tab_t *p;
197 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
198 p = &dbdev_tab[i];
199 if (p->dev_id == id)
200 return p;
201 }
202 return NULL;
203 }
204
205 /* Allocate a channel and return a non-zero descriptor if successful.
206 */
207 u32
au1xxx_dbdma_chan_alloc(u32 srcid,u32 destid,void (* callback)(int,void *,struct pt_regs *),void * callparam)208 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
209 void (*callback)(int, void *, struct pt_regs *), void *callparam)
210 {
211 unsigned long flags;
212 u32 used, chan, rv;
213 u32 dcp;
214 int i;
215 dbdev_tab_t *stp, *dtp;
216 chan_tab_t *ctp;
217 volatile au1x_dma_chan_t *cp;
218
219 /* We do the intialization on the first channel allocation.
220 * We have to wait because of the interrupt handler initialization
221 * which can't be done successfully during board set up.
222 */
223 if (!dbdma_initialized)
224 au1xxx_dbdma_init();
225 dbdma_initialized = 1;
226
227 if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
228 return 0;
229
230 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
231 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
232
233 used = 0;
234 rv = 0;
235
236 /* Check to see if we can get both channels.
237 */
238 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
239 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
240 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
241 /* Got source */
242 stp->dev_flags |= DEV_FLAGS_INUSE;
243 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
244 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
245 /* Got destination */
246 dtp->dev_flags |= DEV_FLAGS_INUSE;
247 }
248 else {
249 /* Can't get dest. Release src.
250 */
251 stp->dev_flags &= ~DEV_FLAGS_INUSE;
252 used++;
253 }
254 }
255 else {
256 used++;
257 }
258 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
259
260 if (!used) {
261 /* Let's see if we can allocate a channel for it.
262 */
263 ctp = NULL;
264 chan = 0;
265 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
266 for (i=0; i<NUM_DBDMA_CHANS; i++) {
267 if (chan_tab_ptr[i] == NULL) {
268 /* If kmalloc fails, it is caught below same
269 * as a channel not available.
270 */
271 ctp = (chan_tab_t *)kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
272 chan_tab_ptr[i] = ctp;
273 ctp->chan_index = chan = i;
274 break;
275 }
276 }
277 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
278
279 if (ctp != NULL) {
280 memset(ctp, 0, sizeof(chan_tab_t));
281 dcp = DDMA_CHANNEL_BASE;
282 dcp += (0x0100 * chan);
283 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
284 cp = (volatile au1x_dma_chan_t *)dcp;
285 ctp->chan_src = stp;
286 ctp->chan_dest = dtp;
287 ctp->chan_callback = callback;
288 ctp->chan_callparam = callparam;
289
290 /* Initialize channel configuration.
291 */
292 i = 0;
293 if (stp->dev_intlevel)
294 i |= DDMA_CFG_SED;
295 if (stp->dev_intpolarity)
296 i |= DDMA_CFG_SP;
297 if (dtp->dev_intlevel)
298 i |= DDMA_CFG_DED;
299 if (dtp->dev_intpolarity)
300 i |= DDMA_CFG_DP;
301 cp->ddma_cfg = i;
302 au_sync();
303
304 /* Return a non-zero value that can be used to
305 * find the channel information in subsequent
306 * operations.
307 */
308 rv = (u32)(&chan_tab_ptr[chan]);
309 }
310 else {
311 /* Release devices.
312 */
313 stp->dev_flags &= ~DEV_FLAGS_INUSE;
314 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
315 }
316 }
317 return rv;
318 }
319
320 /* Set the device width if source or destination is a FIFO.
321 * Should be 8, 16, or 32 bits.
322 */
323 u32
au1xxx_dbdma_set_devwidth(u32 chanid,int bits)324 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
325 {
326 u32 rv;
327 chan_tab_t *ctp;
328 dbdev_tab_t *stp, *dtp;
329
330 ctp = *((chan_tab_t **)chanid);
331 stp = ctp->chan_src;
332 dtp = ctp->chan_dest;
333 rv = 0;
334
335 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
336 rv = stp->dev_devwidth;
337 stp->dev_devwidth = bits;
338 }
339 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
340 rv = dtp->dev_devwidth;
341 dtp->dev_devwidth = bits;
342 }
343
344 return rv;
345 }
346
347 /* Allocate a descriptor ring, initializing as much as possible.
348 */
349 u32
au1xxx_dbdma_ring_alloc(u32 chanid,int entries)350 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
351 {
352 int i;
353 u32 desc_base, srcid, destid;
354 u32 cmd0, cmd1, src1, dest1;
355 u32 src0, dest0;
356 chan_tab_t *ctp;
357 dbdev_tab_t *stp, *dtp;
358 au1x_ddma_desc_t *dp;
359
360 /* I guess we could check this to be within the
361 * range of the table......
362 */
363 ctp = *((chan_tab_t **)chanid);
364 stp = ctp->chan_src;
365 dtp = ctp->chan_dest;
366
367 /* The descriptors must be 32-byte aligned. There is a
368 * possibility the allocation will give us such an address,
369 * and if we try that first we are likely to not waste larger
370 * slabs of memory.
371 */
372 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL);
373 if (desc_base == 0)
374 return 0;
375
376 if (desc_base & 0x1f) {
377 /* Lost....do it again, allocate extra, and round
378 * the address base.
379 */
380 kfree((const void *)desc_base);
381 i = entries * sizeof(au1x_ddma_desc_t);
382 i += (sizeof(au1x_ddma_desc_t) - 1);
383 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
384 return 0;
385
386 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
387 }
388 dp = (au1x_ddma_desc_t *)desc_base;
389
390 /* Keep track of the base descriptor.
391 */
392 ctp->chan_desc_base = dp;
393
394 /* Initialize the rings with as much information as we know.
395 */
396 srcid = stp->dev_id;
397 destid = dtp->dev_id;
398
399 cmd0 = cmd1 = src1 = dest1 = 0;
400 src0 = dest0 = 0;
401
402 cmd0 |= DSCR_CMD0_SID(srcid);
403 cmd0 |= DSCR_CMD0_DID(destid);
404 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
405 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT);
406
407 switch (stp->dev_devwidth) {
408 case 8:
409 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
410 break;
411 case 16:
412 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
413 break;
414 case 32:
415 default:
416 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
417 break;
418 }
419
420 switch (dtp->dev_devwidth) {
421 case 8:
422 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
423 break;
424 case 16:
425 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
426 break;
427 case 32:
428 default:
429 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
430 break;
431 }
432
433 /* If the device is marked as an in/out FIFO, ensure it is
434 * set non-coherent.
435 */
436 if (stp->dev_flags & DEV_FLAGS_IN)
437 cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
438 if (dtp->dev_flags & DEV_FLAGS_OUT)
439 cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
440
441 /* Set up source1. For now, assume no stride and increment.
442 * A channel attribute update can change this later.
443 */
444 switch (stp->dev_tsize) {
445 case 1:
446 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
447 break;
448 case 2:
449 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
450 break;
451 case 4:
452 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
453 break;
454 case 8:
455 default:
456 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
457 break;
458 }
459
460 /* If source input is fifo, set static address.
461 */
462 if (stp->dev_flags & DEV_FLAGS_IN) {
463 src0 = stp->dev_physaddr;
464 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
465 }
466
467 /* Set up dest1. For now, assume no stride and increment.
468 * A channel attribute update can change this later.
469 */
470 switch (dtp->dev_tsize) {
471 case 1:
472 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
473 break;
474 case 2:
475 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
476 break;
477 case 4:
478 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
479 break;
480 case 8:
481 default:
482 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
483 break;
484 }
485
486 /* If destination output is fifo, set static address.
487 */
488 if (dtp->dev_flags & DEV_FLAGS_OUT) {
489 dest0 = dtp->dev_physaddr;
490 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
491 }
492
493 for (i=0; i<entries; i++) {
494 dp->dscr_cmd0 = cmd0;
495 dp->dscr_cmd1 = cmd1;
496 dp->dscr_source0 = src0;
497 dp->dscr_source1 = src1;
498 dp->dscr_dest0 = dest0;
499 dp->dscr_dest1 = dest1;
500 dp->dscr_stat = 0;
501 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
502 dp++;
503 }
504
505 /* Make last descrptor point to the first.
506 */
507 dp--;
508 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
509 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
510
511 return (u32)(ctp->chan_desc_base);
512 }
513
514 /* Put a source buffer into the DMA ring.
515 * This updates the source pointer and byte count. Normally used
516 * for memory to fifo transfers.
517 */
518 u32
au1xxx_dbdma_put_source(u32 chanid,void * buf,int nbytes)519 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
520 {
521 chan_tab_t *ctp;
522 au1x_ddma_desc_t *dp;
523
524 /* I guess we could check this to be within the
525 * range of the table......
526 */
527 ctp = *((chan_tab_t **)chanid);
528
529 /* We should have multiple callers for a particular channel,
530 * an interrupt doesn't affect this pointer nor the descriptor,
531 * so no locking should be needed.
532 */
533 dp = ctp->put_ptr;
534
535 /* If the descriptor is valid, we are way ahead of the DMA
536 * engine, so just return an error condition.
537 */
538 if (dp->dscr_cmd0 & DSCR_CMD0_V) {
539 return 0;
540 }
541
542 /* Load up buffer address and byte count.
543 */
544 dp->dscr_source0 = virt_to_phys(buf);
545 dp->dscr_cmd1 = nbytes;
546 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
547 ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
548
549 /* Get next descriptor pointer.
550 */
551 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
552
553 /* return something not zero.
554 */
555 return nbytes;
556 }
557
558 /* Put a destination buffer into the DMA ring.
559 * This updates the destination pointer and byte count. Normally used
560 * to place an empty buffer into the ring for fifo to memory transfers.
561 */
562 u32
au1xxx_dbdma_put_dest(u32 chanid,void * buf,int nbytes)563 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
564 {
565 chan_tab_t *ctp;
566 au1x_ddma_desc_t *dp;
567
568 /* I guess we could check this to be within the
569 * range of the table......
570 */
571 ctp = *((chan_tab_t **)chanid);
572
573 /* We should have multiple callers for a particular channel,
574 * an interrupt doesn't affect this pointer nor the descriptor,
575 * so no locking should be needed.
576 */
577 dp = ctp->put_ptr;
578
579 /* If the descriptor is valid, we are way ahead of the DMA
580 * engine, so just return an error condition.
581 */
582 if (dp->dscr_cmd0 & DSCR_CMD0_V)
583 return 0;
584
585 /* Load up buffer address and byte count.
586 */
587 dp->dscr_dest0 = virt_to_phys(buf);
588 dp->dscr_cmd1 = nbytes;
589 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
590
591 /* Get next descriptor pointer.
592 */
593 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
594
595 /* return something not zero.
596 */
597 return nbytes;
598 }
599
600 /* Get a destination buffer into the DMA ring.
601 * Normally used to get a full buffer from the ring during fifo
602 * to memory transfers. This does not set the valid bit, you will
603 * have to put another destination buffer to keep the DMA going.
604 */
605 u32
au1xxx_dbdma_get_dest(u32 chanid,void ** buf,int * nbytes)606 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
607 {
608 chan_tab_t *ctp;
609 au1x_ddma_desc_t *dp;
610 u32 rv;
611
612 /* I guess we could check this to be within the
613 * range of the table......
614 */
615 ctp = *((chan_tab_t **)chanid);
616
617 /* We should have multiple callers for a particular channel,
618 * an interrupt doesn't affect this pointer nor the descriptor,
619 * so no locking should be needed.
620 */
621 dp = ctp->get_ptr;
622
623 /* If the descriptor is valid, we are way ahead of the DMA
624 * engine, so just return an error condition.
625 */
626 if (dp->dscr_cmd0 & DSCR_CMD0_V)
627 return 0;
628
629 /* Return buffer address and byte count.
630 */
631 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
632 *nbytes = dp->dscr_cmd1;
633 rv = dp->dscr_stat;
634
635 /* Get next descriptor pointer.
636 */
637 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
638
639 /* return something not zero.
640 */
641 return rv;
642 }
643
644 void
au1xxx_dbdma_stop(u32 chanid)645 au1xxx_dbdma_stop(u32 chanid)
646 {
647 chan_tab_t *ctp;
648 volatile au1x_dma_chan_t *cp;
649 int halt_timeout = 0;
650
651 ctp = *((chan_tab_t **)chanid);
652
653 cp = ctp->chan_ptr;
654 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
655 au_sync();
656 while (!(cp->ddma_stat & DDMA_STAT_H)) {
657 udelay(1);
658 halt_timeout++;
659 if (halt_timeout > 100) {
660 printk("warning: DMA channel won't halt\n");
661 break;
662 }
663 }
664 /* clear current desc valid and doorbell */
665 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
666 au_sync();
667 }
668
669 /* Start using the current descriptor pointer. If the dbdma encounters
670 * a not valid descriptor, it will stop. In this case, we can just
671 * continue by adding a buffer to the list and starting again.
672 */
673 void
au1xxx_dbdma_start(u32 chanid)674 au1xxx_dbdma_start(u32 chanid)
675 {
676 chan_tab_t *ctp;
677 volatile au1x_dma_chan_t *cp;
678
679 ctp = *((chan_tab_t **)chanid);
680
681 cp = ctp->chan_ptr;
682 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
683 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
684 au_sync();
685 cp->ddma_dbell = 0xffffffff; /* Make it go */
686 au_sync();
687 }
688
689 void
au1xxx_dbdma_reset(u32 chanid)690 au1xxx_dbdma_reset(u32 chanid)
691 {
692 chan_tab_t *ctp;
693 au1x_ddma_desc_t *dp;
694
695 au1xxx_dbdma_stop(chanid);
696
697 ctp = *((chan_tab_t **)chanid);
698 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
699
700 /* Run through the descriptors and reset the valid indicator.
701 */
702 dp = ctp->chan_desc_base;
703
704 do {
705 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
706 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
707 } while (dp != ctp->chan_desc_base);
708 }
709
710 u32
au1xxx_get_dma_residue(u32 chanid)711 au1xxx_get_dma_residue(u32 chanid)
712 {
713 chan_tab_t *ctp;
714 volatile au1x_dma_chan_t *cp;
715 u32 rv;
716
717 ctp = *((chan_tab_t **)chanid);
718 cp = ctp->chan_ptr;
719
720 /* This is only valid if the channel is stopped.
721 */
722 rv = cp->ddma_bytecnt;
723 au_sync();
724
725 return rv;
726 }
727
728 void
au1xxx_dbdma_chan_free(u32 chanid)729 au1xxx_dbdma_chan_free(u32 chanid)
730 {
731 chan_tab_t *ctp;
732 dbdev_tab_t *stp, *dtp;
733
734 ctp = *((chan_tab_t **)chanid);
735 stp = ctp->chan_src;
736 dtp = ctp->chan_dest;
737
738 au1xxx_dbdma_stop(chanid);
739
740 if (ctp->chan_desc_base != NULL)
741 kfree(ctp->chan_desc_base);
742
743 stp->dev_flags &= ~DEV_FLAGS_INUSE;
744 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
745 chan_tab_ptr[ctp->chan_index] = NULL;
746
747 kfree(ctp);
748 }
749
750 static void
dbdma_interrupt(int irq,void * dev_id,struct pt_regs * regs)751 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
752 {
753 u32 intstat;
754 u32 chan_index;
755 chan_tab_t *ctp;
756 au1x_ddma_desc_t *dp;
757 volatile au1x_dma_chan_t *cp;
758
759 intstat = dbdma_gptr->ddma_intstat;
760 au_sync();
761 chan_index = au_ffs(intstat) - 1;
762
763 ctp = chan_tab_ptr[chan_index];
764 cp = ctp->chan_ptr;
765 dp = ctp->cur_ptr;
766
767 /* Reset interrupt.
768 */
769 cp->ddma_irq = 0;
770 au_sync();
771
772 if (ctp->chan_callback)
773 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
774
775 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
776
777 }
778
779 static void
au1xxx_dbdma_init(void)780 au1xxx_dbdma_init(void)
781 {
782 dbdma_gptr->ddma_config = 0;
783 dbdma_gptr->ddma_throttle = 0;
784 dbdma_gptr->ddma_inten = 0xffff;
785 au_sync();
786
787 if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
788 "Au1xxx dbdma", (void *)dbdma_gptr))
789 printk("Can't get 1550 dbdma irq");
790 }
791
792 void
au1xxx_dbdma_dump(u32 chanid)793 au1xxx_dbdma_dump(u32 chanid)
794 {
795 chan_tab_t *ctp;
796 au1x_ddma_desc_t *dp;
797 dbdev_tab_t *stp, *dtp;
798 volatile au1x_dma_chan_t *cp;
799
800 ctp = *((chan_tab_t **)chanid);
801 stp = ctp->chan_src;
802 dtp = ctp->chan_dest;
803 cp = ctp->chan_ptr;
804
805 printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
806 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
807 printk("desc base %x, get %x, put %x, cur %x\n",
808 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
809 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
810
811 printk("dbdma chan %x\n", (u32)cp);
812 printk("cfg %08x, desptr %08x, statptr %08x\n",
813 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
814 printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
815 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
816
817
818 /* Run through the descriptors
819 */
820 dp = ctp->chan_desc_base;
821
822 do {
823 printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
824 (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
825 printk("src0 %08x, src1 %08x, dest0 %08x\n",
826 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
827 printk("dest1 %08x, stat %08x, nxtptr %08x\n",
828 dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
829 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
830 } while (dp != ctp->chan_desc_base);
831 }
832
833 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
834
835