1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/init.h>
34 #include <linux/kernel.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/interrupt.h>
38 #include <linux/module.h>
39 #include <linux/sysdev.h>
40 #include <asm/mach-au1x00/au1000.h>
41 #include <asm/mach-au1x00/au1xxx_dbdma.h>
42
43 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
44
45 /*
46 * The Descriptor Based DMA supports up to 16 channels.
47 *
48 * There are 32 devices defined. We keep an internal structure
49 * of devices using these channels, along with additional
50 * information.
51 *
52 * We allocate the descriptors and allow access to them through various
53 * functions. The drivers allocate the data buffers and assign them
54 * to the descriptors.
55 */
56 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
57
58 /* I couldn't find a macro that did this... */
59 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
60
61 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
62 static int dbdma_initialized;
63
64 static dbdev_tab_t dbdev_tab[] = {
65 #ifdef CONFIG_SOC_AU1550
66 /* UARTS */
67 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
68 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
69 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
70 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
71
72 /* EXT DMA */
73 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
74 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
75 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
76 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
77
78 /* USB DEV */
79 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
80 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
81 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
82 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
83 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
84 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
85
86 /* PSC 0 */
87 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
88 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
89
90 /* PSC 1 */
91 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
92 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
93
94 /* PSC 2 */
95 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
96 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
97
98 /* PSC 3 */
99 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
100 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
101
102 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
103 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
104
105 /* MAC 0 */
106 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
107 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
108
109 /* MAC 1 */
110 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
111 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
112
113 #endif /* CONFIG_SOC_AU1550 */
114
115 #ifdef CONFIG_SOC_AU1200
116 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
117 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
118 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
119 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
120
121 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
122 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
123
124 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
125 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
126 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
127 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
128
129 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
130 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
131 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
132 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
133
134 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
135 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
136
137 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
138 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
139 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
140
141 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
142 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
143 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
144
145 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
146 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
147 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
148 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149
150 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
151
152 #endif /* CONFIG_SOC_AU1200 */
153
154 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
155 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
156
157 /* Provide 16 user definable device types */
158 { ~0, 0, 0, 0, 0, 0, 0 },
159 { ~0, 0, 0, 0, 0, 0, 0 },
160 { ~0, 0, 0, 0, 0, 0, 0 },
161 { ~0, 0, 0, 0, 0, 0, 0 },
162 { ~0, 0, 0, 0, 0, 0, 0 },
163 { ~0, 0, 0, 0, 0, 0, 0 },
164 { ~0, 0, 0, 0, 0, 0, 0 },
165 { ~0, 0, 0, 0, 0, 0, 0 },
166 { ~0, 0, 0, 0, 0, 0, 0 },
167 { ~0, 0, 0, 0, 0, 0, 0 },
168 { ~0, 0, 0, 0, 0, 0, 0 },
169 { ~0, 0, 0, 0, 0, 0, 0 },
170 { ~0, 0, 0, 0, 0, 0, 0 },
171 { ~0, 0, 0, 0, 0, 0, 0 },
172 { ~0, 0, 0, 0, 0, 0, 0 },
173 { ~0, 0, 0, 0, 0, 0, 0 },
174 };
175
176 #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
177
178
179 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
180
find_dbdev_id(u32 id)181 static dbdev_tab_t *find_dbdev_id(u32 id)
182 {
183 int i;
184 dbdev_tab_t *p;
185 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
186 p = &dbdev_tab[i];
187 if (p->dev_id == id)
188 return p;
189 }
190 return NULL;
191 }
192
au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t * dp)193 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
194 {
195 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
196 }
197 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
198
au1xxx_ddma_add_device(dbdev_tab_t * dev)199 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
200 {
201 u32 ret = 0;
202 dbdev_tab_t *p;
203 static u16 new_id = 0x1000;
204
205 p = find_dbdev_id(~0);
206 if (NULL != p) {
207 memcpy(p, dev, sizeof(dbdev_tab_t));
208 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
209 ret = p->dev_id;
210 new_id++;
211 #if 0
212 printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
213 p->dev_id, p->dev_flags, p->dev_physaddr);
214 #endif
215 }
216
217 return ret;
218 }
219 EXPORT_SYMBOL(au1xxx_ddma_add_device);
220
au1xxx_ddma_del_device(u32 devid)221 void au1xxx_ddma_del_device(u32 devid)
222 {
223 dbdev_tab_t *p = find_dbdev_id(devid);
224
225 if (p != NULL) {
226 memset(p, 0, sizeof(dbdev_tab_t));
227 p->dev_id = ~0;
228 }
229 }
230 EXPORT_SYMBOL(au1xxx_ddma_del_device);
231
232 /* Allocate a channel and return a non-zero descriptor if successful. */
au1xxx_dbdma_chan_alloc(u32 srcid,u32 destid,void (* callback)(int,void *),void * callparam)233 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
234 void (*callback)(int, void *), void *callparam)
235 {
236 unsigned long flags;
237 u32 used, chan;
238 u32 dcp;
239 int i;
240 dbdev_tab_t *stp, *dtp;
241 chan_tab_t *ctp;
242 au1x_dma_chan_t *cp;
243
244 /*
245 * We do the intialization on the first channel allocation.
246 * We have to wait because of the interrupt handler initialization
247 * which can't be done successfully during board set up.
248 */
249 if (!dbdma_initialized)
250 return 0;
251
252 stp = find_dbdev_id(srcid);
253 if (stp == NULL)
254 return 0;
255 dtp = find_dbdev_id(destid);
256 if (dtp == NULL)
257 return 0;
258
259 used = 0;
260
261 /* Check to see if we can get both channels. */
262 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
263 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
264 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
265 /* Got source */
266 stp->dev_flags |= DEV_FLAGS_INUSE;
267 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
268 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
269 /* Got destination */
270 dtp->dev_flags |= DEV_FLAGS_INUSE;
271 } else {
272 /* Can't get dest. Release src. */
273 stp->dev_flags &= ~DEV_FLAGS_INUSE;
274 used++;
275 }
276 } else
277 used++;
278 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
279
280 if (used)
281 return 0;
282
283 /* Let's see if we can allocate a channel for it. */
284 ctp = NULL;
285 chan = 0;
286 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
287 for (i = 0; i < NUM_DBDMA_CHANS; i++)
288 if (chan_tab_ptr[i] == NULL) {
289 /*
290 * If kmalloc fails, it is caught below same
291 * as a channel not available.
292 */
293 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
294 chan_tab_ptr[i] = ctp;
295 break;
296 }
297 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
298
299 if (ctp != NULL) {
300 memset(ctp, 0, sizeof(chan_tab_t));
301 ctp->chan_index = chan = i;
302 dcp = DDMA_CHANNEL_BASE;
303 dcp += (0x0100 * chan);
304 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
305 cp = (au1x_dma_chan_t *)dcp;
306 ctp->chan_src = stp;
307 ctp->chan_dest = dtp;
308 ctp->chan_callback = callback;
309 ctp->chan_callparam = callparam;
310
311 /* Initialize channel configuration. */
312 i = 0;
313 if (stp->dev_intlevel)
314 i |= DDMA_CFG_SED;
315 if (stp->dev_intpolarity)
316 i |= DDMA_CFG_SP;
317 if (dtp->dev_intlevel)
318 i |= DDMA_CFG_DED;
319 if (dtp->dev_intpolarity)
320 i |= DDMA_CFG_DP;
321 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
322 (dtp->dev_flags & DEV_FLAGS_SYNC))
323 i |= DDMA_CFG_SYNC;
324 cp->ddma_cfg = i;
325 au_sync();
326
327 /*
328 * Return a non-zero value that can be used to find the channel
329 * information in subsequent operations.
330 */
331 return (u32)(&chan_tab_ptr[chan]);
332 }
333
334 /* Release devices */
335 stp->dev_flags &= ~DEV_FLAGS_INUSE;
336 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
337
338 return 0;
339 }
340 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
341
342 /*
343 * Set the device width if source or destination is a FIFO.
344 * Should be 8, 16, or 32 bits.
345 */
au1xxx_dbdma_set_devwidth(u32 chanid,int bits)346 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
347 {
348 u32 rv;
349 chan_tab_t *ctp;
350 dbdev_tab_t *stp, *dtp;
351
352 ctp = *((chan_tab_t **)chanid);
353 stp = ctp->chan_src;
354 dtp = ctp->chan_dest;
355 rv = 0;
356
357 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
358 rv = stp->dev_devwidth;
359 stp->dev_devwidth = bits;
360 }
361 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
362 rv = dtp->dev_devwidth;
363 dtp->dev_devwidth = bits;
364 }
365
366 return rv;
367 }
368 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
369
370 /* Allocate a descriptor ring, initializing as much as possible. */
au1xxx_dbdma_ring_alloc(u32 chanid,int entries)371 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
372 {
373 int i;
374 u32 desc_base, srcid, destid;
375 u32 cmd0, cmd1, src1, dest1;
376 u32 src0, dest0;
377 chan_tab_t *ctp;
378 dbdev_tab_t *stp, *dtp;
379 au1x_ddma_desc_t *dp;
380
381 /*
382 * I guess we could check this to be within the
383 * range of the table......
384 */
385 ctp = *((chan_tab_t **)chanid);
386 stp = ctp->chan_src;
387 dtp = ctp->chan_dest;
388
389 /*
390 * The descriptors must be 32-byte aligned. There is a
391 * possibility the allocation will give us such an address,
392 * and if we try that first we are likely to not waste larger
393 * slabs of memory.
394 */
395 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
396 GFP_KERNEL|GFP_DMA);
397 if (desc_base == 0)
398 return 0;
399
400 if (desc_base & 0x1f) {
401 /*
402 * Lost....do it again, allocate extra, and round
403 * the address base.
404 */
405 kfree((const void *)desc_base);
406 i = entries * sizeof(au1x_ddma_desc_t);
407 i += (sizeof(au1x_ddma_desc_t) - 1);
408 desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
409 if (desc_base == 0)
410 return 0;
411
412 ctp->cdb_membase = desc_base;
413 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
414 } else
415 ctp->cdb_membase = desc_base;
416
417 dp = (au1x_ddma_desc_t *)desc_base;
418
419 /* Keep track of the base descriptor. */
420 ctp->chan_desc_base = dp;
421
422 /* Initialize the rings with as much information as we know. */
423 srcid = stp->dev_id;
424 destid = dtp->dev_id;
425
426 cmd0 = cmd1 = src1 = dest1 = 0;
427 src0 = dest0 = 0;
428
429 cmd0 |= DSCR_CMD0_SID(srcid);
430 cmd0 |= DSCR_CMD0_DID(destid);
431 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
432 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
433
434 /* Is it mem to mem transfer? */
435 if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
436 (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
437 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
438 (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
439 cmd0 |= DSCR_CMD0_MEM;
440
441 switch (stp->dev_devwidth) {
442 case 8:
443 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
444 break;
445 case 16:
446 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
447 break;
448 case 32:
449 default:
450 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
451 break;
452 }
453
454 switch (dtp->dev_devwidth) {
455 case 8:
456 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
457 break;
458 case 16:
459 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
460 break;
461 case 32:
462 default:
463 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
464 break;
465 }
466
467 /*
468 * If the device is marked as an in/out FIFO, ensure it is
469 * set non-coherent.
470 */
471 if (stp->dev_flags & DEV_FLAGS_IN)
472 cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
473 if (dtp->dev_flags & DEV_FLAGS_OUT)
474 cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
475
476 /*
477 * Set up source1. For now, assume no stride and increment.
478 * A channel attribute update can change this later.
479 */
480 switch (stp->dev_tsize) {
481 case 1:
482 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
483 break;
484 case 2:
485 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
486 break;
487 case 4:
488 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
489 break;
490 case 8:
491 default:
492 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
493 break;
494 }
495
496 /* If source input is FIFO, set static address. */
497 if (stp->dev_flags & DEV_FLAGS_IN) {
498 if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
499 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
500 else
501 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
502 }
503
504 if (stp->dev_physaddr)
505 src0 = stp->dev_physaddr;
506
507 /*
508 * Set up dest1. For now, assume no stride and increment.
509 * A channel attribute update can change this later.
510 */
511 switch (dtp->dev_tsize) {
512 case 1:
513 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
514 break;
515 case 2:
516 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
517 break;
518 case 4:
519 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
520 break;
521 case 8:
522 default:
523 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
524 break;
525 }
526
527 /* If destination output is FIFO, set static address. */
528 if (dtp->dev_flags & DEV_FLAGS_OUT) {
529 if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
530 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
531 else
532 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
533 }
534
535 if (dtp->dev_physaddr)
536 dest0 = dtp->dev_physaddr;
537
538 #if 0
539 printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
540 "source1:%x dest0:%x dest1:%x\n",
541 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
542 src1, dest0, dest1);
543 #endif
544 for (i = 0; i < entries; i++) {
545 dp->dscr_cmd0 = cmd0;
546 dp->dscr_cmd1 = cmd1;
547 dp->dscr_source0 = src0;
548 dp->dscr_source1 = src1;
549 dp->dscr_dest0 = dest0;
550 dp->dscr_dest1 = dest1;
551 dp->dscr_stat = 0;
552 dp->sw_context = 0;
553 dp->sw_status = 0;
554 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
555 dp++;
556 }
557
558 /* Make last descrptor point to the first. */
559 dp--;
560 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
561 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
562
563 return (u32)ctp->chan_desc_base;
564 }
565 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
566
567 /*
568 * Put a source buffer into the DMA ring.
569 * This updates the source pointer and byte count. Normally used
570 * for memory to fifo transfers.
571 */
au1xxx_dbdma_put_source(u32 chanid,dma_addr_t buf,int nbytes,u32 flags)572 u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
573 {
574 chan_tab_t *ctp;
575 au1x_ddma_desc_t *dp;
576
577 /*
578 * I guess we could check this to be within the
579 * range of the table......
580 */
581 ctp = *(chan_tab_t **)chanid;
582
583 /*
584 * We should have multiple callers for a particular channel,
585 * an interrupt doesn't affect this pointer nor the descriptor,
586 * so no locking should be needed.
587 */
588 dp = ctp->put_ptr;
589
590 /*
591 * If the descriptor is valid, we are way ahead of the DMA
592 * engine, so just return an error condition.
593 */
594 if (dp->dscr_cmd0 & DSCR_CMD0_V)
595 return 0;
596
597 /* Load up buffer address and byte count. */
598 dp->dscr_source0 = buf & ~0UL;
599 dp->dscr_cmd1 = nbytes;
600 /* Check flags */
601 if (flags & DDMA_FLAGS_IE)
602 dp->dscr_cmd0 |= DSCR_CMD0_IE;
603 if (flags & DDMA_FLAGS_NOIE)
604 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
605
606 /*
607 * There is an errata on the Au1200/Au1550 parts that could result
608 * in "stale" data being DMA'ed. It has to do with the snoop logic on
609 * the cache eviction buffer. DMA_NONCOHERENT is on by default for
610 * these parts. If it is fixed in the future, these dma_cache_inv will
611 * just be nothing more than empty macros. See io.h.
612 */
613 dma_cache_wback_inv((unsigned long)buf, nbytes);
614 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
615 au_sync();
616 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
617 ctp->chan_ptr->ddma_dbell = 0;
618
619 /* Get next descriptor pointer. */
620 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
621
622 /* Return something non-zero. */
623 return nbytes;
624 }
625 EXPORT_SYMBOL(au1xxx_dbdma_put_source);
626
627 /* Put a destination buffer into the DMA ring.
628 * This updates the destination pointer and byte count. Normally used
629 * to place an empty buffer into the ring for fifo to memory transfers.
630 */
au1xxx_dbdma_put_dest(u32 chanid,dma_addr_t buf,int nbytes,u32 flags)631 u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
632 {
633 chan_tab_t *ctp;
634 au1x_ddma_desc_t *dp;
635
636 /* I guess we could check this to be within the
637 * range of the table......
638 */
639 ctp = *((chan_tab_t **)chanid);
640
641 /* We should have multiple callers for a particular channel,
642 * an interrupt doesn't affect this pointer nor the descriptor,
643 * so no locking should be needed.
644 */
645 dp = ctp->put_ptr;
646
647 /* If the descriptor is valid, we are way ahead of the DMA
648 * engine, so just return an error condition.
649 */
650 if (dp->dscr_cmd0 & DSCR_CMD0_V)
651 return 0;
652
653 /* Load up buffer address and byte count */
654
655 /* Check flags */
656 if (flags & DDMA_FLAGS_IE)
657 dp->dscr_cmd0 |= DSCR_CMD0_IE;
658 if (flags & DDMA_FLAGS_NOIE)
659 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
660
661 dp->dscr_dest0 = buf & ~0UL;
662 dp->dscr_cmd1 = nbytes;
663 #if 0
664 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
665 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
666 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
667 #endif
668 /*
669 * There is an errata on the Au1200/Au1550 parts that could result in
670 * "stale" data being DMA'ed. It has to do with the snoop logic on the
671 * cache eviction buffer. DMA_NONCOHERENT is on by default for these
672 * parts. If it is fixed in the future, these dma_cache_inv will just
673 * be nothing more than empty macros. See io.h.
674 */
675 dma_cache_inv((unsigned long)buf, nbytes);
676 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
677 au_sync();
678 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
679 ctp->chan_ptr->ddma_dbell = 0;
680
681 /* Get next descriptor pointer. */
682 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
683
684 /* Return something non-zero. */
685 return nbytes;
686 }
687 EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
688
689 /*
690 * Get a destination buffer into the DMA ring.
691 * Normally used to get a full buffer from the ring during fifo
692 * to memory transfers. This does not set the valid bit, you will
693 * have to put another destination buffer to keep the DMA going.
694 */
au1xxx_dbdma_get_dest(u32 chanid,void ** buf,int * nbytes)695 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
696 {
697 chan_tab_t *ctp;
698 au1x_ddma_desc_t *dp;
699 u32 rv;
700
701 /*
702 * I guess we could check this to be within the
703 * range of the table......
704 */
705 ctp = *((chan_tab_t **)chanid);
706
707 /*
708 * We should have multiple callers for a particular channel,
709 * an interrupt doesn't affect this pointer nor the descriptor,
710 * so no locking should be needed.
711 */
712 dp = ctp->get_ptr;
713
714 /*
715 * If the descriptor is valid, we are way ahead of the DMA
716 * engine, so just return an error condition.
717 */
718 if (dp->dscr_cmd0 & DSCR_CMD0_V)
719 return 0;
720
721 /* Return buffer address and byte count. */
722 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
723 *nbytes = dp->dscr_cmd1;
724 rv = dp->dscr_stat;
725
726 /* Get next descriptor pointer. */
727 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
728
729 /* Return something non-zero. */
730 return rv;
731 }
732 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
733
au1xxx_dbdma_stop(u32 chanid)734 void au1xxx_dbdma_stop(u32 chanid)
735 {
736 chan_tab_t *ctp;
737 au1x_dma_chan_t *cp;
738 int halt_timeout = 0;
739
740 ctp = *((chan_tab_t **)chanid);
741
742 cp = ctp->chan_ptr;
743 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
744 au_sync();
745 while (!(cp->ddma_stat & DDMA_STAT_H)) {
746 udelay(1);
747 halt_timeout++;
748 if (halt_timeout > 100) {
749 printk(KERN_WARNING "warning: DMA channel won't halt\n");
750 break;
751 }
752 }
753 /* clear current desc valid and doorbell */
754 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
755 au_sync();
756 }
757 EXPORT_SYMBOL(au1xxx_dbdma_stop);
758
759 /*
760 * Start using the current descriptor pointer. If the DBDMA encounters
761 * a non-valid descriptor, it will stop. In this case, we can just
762 * continue by adding a buffer to the list and starting again.
763 */
au1xxx_dbdma_start(u32 chanid)764 void au1xxx_dbdma_start(u32 chanid)
765 {
766 chan_tab_t *ctp;
767 au1x_dma_chan_t *cp;
768
769 ctp = *((chan_tab_t **)chanid);
770 cp = ctp->chan_ptr;
771 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
772 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
773 au_sync();
774 cp->ddma_dbell = 0;
775 au_sync();
776 }
777 EXPORT_SYMBOL(au1xxx_dbdma_start);
778
au1xxx_dbdma_reset(u32 chanid)779 void au1xxx_dbdma_reset(u32 chanid)
780 {
781 chan_tab_t *ctp;
782 au1x_ddma_desc_t *dp;
783
784 au1xxx_dbdma_stop(chanid);
785
786 ctp = *((chan_tab_t **)chanid);
787 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
788
789 /* Run through the descriptors and reset the valid indicator. */
790 dp = ctp->chan_desc_base;
791
792 do {
793 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
794 /*
795 * Reset our software status -- this is used to determine
796 * if a descriptor is in use by upper level software. Since
797 * posting can reset 'V' bit.
798 */
799 dp->sw_status = 0;
800 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
801 } while (dp != ctp->chan_desc_base);
802 }
803 EXPORT_SYMBOL(au1xxx_dbdma_reset);
804
au1xxx_get_dma_residue(u32 chanid)805 u32 au1xxx_get_dma_residue(u32 chanid)
806 {
807 chan_tab_t *ctp;
808 au1x_dma_chan_t *cp;
809 u32 rv;
810
811 ctp = *((chan_tab_t **)chanid);
812 cp = ctp->chan_ptr;
813
814 /* This is only valid if the channel is stopped. */
815 rv = cp->ddma_bytecnt;
816 au_sync();
817
818 return rv;
819 }
820 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
821
au1xxx_dbdma_chan_free(u32 chanid)822 void au1xxx_dbdma_chan_free(u32 chanid)
823 {
824 chan_tab_t *ctp;
825 dbdev_tab_t *stp, *dtp;
826
827 ctp = *((chan_tab_t **)chanid);
828 stp = ctp->chan_src;
829 dtp = ctp->chan_dest;
830
831 au1xxx_dbdma_stop(chanid);
832
833 kfree((void *)ctp->cdb_membase);
834
835 stp->dev_flags &= ~DEV_FLAGS_INUSE;
836 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
837 chan_tab_ptr[ctp->chan_index] = NULL;
838
839 kfree(ctp);
840 }
841 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
842
dbdma_interrupt(int irq,void * dev_id)843 static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
844 {
845 u32 intstat;
846 u32 chan_index;
847 chan_tab_t *ctp;
848 au1x_ddma_desc_t *dp;
849 au1x_dma_chan_t *cp;
850
851 intstat = dbdma_gptr->ddma_intstat;
852 au_sync();
853 chan_index = __ffs(intstat);
854
855 ctp = chan_tab_ptr[chan_index];
856 cp = ctp->chan_ptr;
857 dp = ctp->cur_ptr;
858
859 /* Reset interrupt. */
860 cp->ddma_irq = 0;
861 au_sync();
862
863 if (ctp->chan_callback)
864 ctp->chan_callback(irq, ctp->chan_callparam);
865
866 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
867 return IRQ_RETVAL(1);
868 }
869
au1xxx_dbdma_dump(u32 chanid)870 void au1xxx_dbdma_dump(u32 chanid)
871 {
872 chan_tab_t *ctp;
873 au1x_ddma_desc_t *dp;
874 dbdev_tab_t *stp, *dtp;
875 au1x_dma_chan_t *cp;
876 u32 i = 0;
877
878 ctp = *((chan_tab_t **)chanid);
879 stp = ctp->chan_src;
880 dtp = ctp->chan_dest;
881 cp = ctp->chan_ptr;
882
883 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n",
884 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
885 dtp - dbdev_tab);
886 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
887 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
888 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
889
890 printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
891 printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
892 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
893 printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
894 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
895 cp->ddma_bytecnt);
896
897 /* Run through the descriptors */
898 dp = ctp->chan_desc_base;
899
900 do {
901 printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
902 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
903 printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
904 dp->dscr_source0, dp->dscr_source1,
905 dp->dscr_dest0, dp->dscr_dest1);
906 printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
907 dp->dscr_stat, dp->dscr_nxtptr);
908 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
909 } while (dp != ctp->chan_desc_base);
910 }
911
912 /* Put a descriptor into the DMA ring.
913 * This updates the source/destination pointers and byte count.
914 */
au1xxx_dbdma_put_dscr(u32 chanid,au1x_ddma_desc_t * dscr)915 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
916 {
917 chan_tab_t *ctp;
918 au1x_ddma_desc_t *dp;
919 u32 nbytes = 0;
920
921 /*
922 * I guess we could check this to be within the
923 * range of the table......
924 */
925 ctp = *((chan_tab_t **)chanid);
926
927 /*
928 * We should have multiple callers for a particular channel,
929 * an interrupt doesn't affect this pointer nor the descriptor,
930 * so no locking should be needed.
931 */
932 dp = ctp->put_ptr;
933
934 /*
935 * If the descriptor is valid, we are way ahead of the DMA
936 * engine, so just return an error condition.
937 */
938 if (dp->dscr_cmd0 & DSCR_CMD0_V)
939 return 0;
940
941 /* Load up buffer addresses and byte count. */
942 dp->dscr_dest0 = dscr->dscr_dest0;
943 dp->dscr_source0 = dscr->dscr_source0;
944 dp->dscr_dest1 = dscr->dscr_dest1;
945 dp->dscr_source1 = dscr->dscr_source1;
946 dp->dscr_cmd1 = dscr->dscr_cmd1;
947 nbytes = dscr->dscr_cmd1;
948 /* Allow the caller to specifiy if an interrupt is generated */
949 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
950 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
951 ctp->chan_ptr->ddma_dbell = 0;
952
953 /* Get next descriptor pointer. */
954 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
955
956 /* Return something non-zero. */
957 return nbytes;
958 }
959
960
961 struct alchemy_dbdma_sysdev {
962 struct sys_device sysdev;
963 u32 pm_regs[NUM_DBDMA_CHANS + 1][6];
964 };
965
alchemy_dbdma_suspend(struct sys_device * dev,pm_message_t state)966 static int alchemy_dbdma_suspend(struct sys_device *dev,
967 pm_message_t state)
968 {
969 struct alchemy_dbdma_sysdev *sdev =
970 container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
971 int i;
972 u32 addr;
973
974 addr = DDMA_GLOBAL_BASE;
975 sdev->pm_regs[0][0] = au_readl(addr + 0x00);
976 sdev->pm_regs[0][1] = au_readl(addr + 0x04);
977 sdev->pm_regs[0][2] = au_readl(addr + 0x08);
978 sdev->pm_regs[0][3] = au_readl(addr + 0x0c);
979
980 /* save channel configurations */
981 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
982 sdev->pm_regs[i][0] = au_readl(addr + 0x00);
983 sdev->pm_regs[i][1] = au_readl(addr + 0x04);
984 sdev->pm_regs[i][2] = au_readl(addr + 0x08);
985 sdev->pm_regs[i][3] = au_readl(addr + 0x0c);
986 sdev->pm_regs[i][4] = au_readl(addr + 0x10);
987 sdev->pm_regs[i][5] = au_readl(addr + 0x14);
988
989 /* halt channel */
990 au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00);
991 au_sync();
992 while (!(au_readl(addr + 0x14) & 1))
993 au_sync();
994
995 addr += 0x100; /* next channel base */
996 }
997 /* disable channel interrupts */
998 au_writel(0, DDMA_GLOBAL_BASE + 0x0c);
999 au_sync();
1000
1001 return 0;
1002 }
1003
alchemy_dbdma_resume(struct sys_device * dev)1004 static int alchemy_dbdma_resume(struct sys_device *dev)
1005 {
1006 struct alchemy_dbdma_sysdev *sdev =
1007 container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
1008 int i;
1009 u32 addr;
1010
1011 addr = DDMA_GLOBAL_BASE;
1012 au_writel(sdev->pm_regs[0][0], addr + 0x00);
1013 au_writel(sdev->pm_regs[0][1], addr + 0x04);
1014 au_writel(sdev->pm_regs[0][2], addr + 0x08);
1015 au_writel(sdev->pm_regs[0][3], addr + 0x0c);
1016
1017 /* restore channel configurations */
1018 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
1019 au_writel(sdev->pm_regs[i][0], addr + 0x00);
1020 au_writel(sdev->pm_regs[i][1], addr + 0x04);
1021 au_writel(sdev->pm_regs[i][2], addr + 0x08);
1022 au_writel(sdev->pm_regs[i][3], addr + 0x0c);
1023 au_writel(sdev->pm_regs[i][4], addr + 0x10);
1024 au_writel(sdev->pm_regs[i][5], addr + 0x14);
1025 au_sync();
1026 addr += 0x100; /* next channel base */
1027 }
1028
1029 return 0;
1030 }
1031
1032 static struct sysdev_class alchemy_dbdma_sysdev_class = {
1033 .name = "dbdma",
1034 .suspend = alchemy_dbdma_suspend,
1035 .resume = alchemy_dbdma_resume,
1036 };
1037
alchemy_dbdma_sysdev_init(void)1038 static int __init alchemy_dbdma_sysdev_init(void)
1039 {
1040 struct alchemy_dbdma_sysdev *sdev;
1041 int ret;
1042
1043 ret = sysdev_class_register(&alchemy_dbdma_sysdev_class);
1044 if (ret)
1045 return ret;
1046
1047 sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL);
1048 if (!sdev)
1049 return -ENOMEM;
1050
1051 sdev->sysdev.id = -1;
1052 sdev->sysdev.cls = &alchemy_dbdma_sysdev_class;
1053 ret = sysdev_register(&sdev->sysdev);
1054 if (ret)
1055 kfree(sdev);
1056
1057 return ret;
1058 }
1059
au1xxx_dbdma_init(void)1060 static int __init au1xxx_dbdma_init(void)
1061 {
1062 int irq_nr, ret;
1063
1064 dbdma_gptr->ddma_config = 0;
1065 dbdma_gptr->ddma_throttle = 0;
1066 dbdma_gptr->ddma_inten = 0xffff;
1067 au_sync();
1068
1069 switch (alchemy_get_cputype()) {
1070 case ALCHEMY_CPU_AU1550:
1071 irq_nr = AU1550_DDMA_INT;
1072 break;
1073 case ALCHEMY_CPU_AU1200:
1074 irq_nr = AU1200_DDMA_INT;
1075 break;
1076 default:
1077 return -ENODEV;
1078 }
1079
1080 ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
1081 "Au1xxx dbdma", (void *)dbdma_gptr);
1082 if (ret)
1083 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1084 else {
1085 dbdma_initialized = 1;
1086 printk(KERN_INFO "Alchemy DBDMA initialized\n");
1087 ret = alchemy_dbdma_sysdev_init();
1088 if (ret) {
1089 printk(KERN_ERR "DBDMA PM init failed\n");
1090 ret = 0;
1091 }
1092 }
1093
1094 return ret;
1095 }
1096 subsys_initcall(au1xxx_dbdma_init);
1097
1098 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
1099