1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "rv515_reg_safe.h"
36 
37 /* This files gather functions specifics to: rv515 */
38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42 
rv515_debugfs(struct radeon_device * rdev)43 void rv515_debugfs(struct radeon_device *rdev)
44 {
45 	if (r100_debugfs_rbbm_init(rdev)) {
46 		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
47 	}
48 	if (rv515_debugfs_pipes_info_init(rdev)) {
49 		DRM_ERROR("Failed to register debugfs file for pipes !\n");
50 	}
51 	if (rv515_debugfs_ga_info_init(rdev)) {
52 		DRM_ERROR("Failed to register debugfs file for pipes !\n");
53 	}
54 }
55 
rv515_ring_start(struct radeon_device * rdev,struct radeon_ring * ring)56 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
57 {
58 	int r;
59 
60 	r = radeon_ring_lock(rdev, ring, 64);
61 	if (r) {
62 		return;
63 	}
64 	radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
65 	radeon_ring_write(ring,
66 			  ISYNC_ANY2D_IDLE3D |
67 			  ISYNC_ANY3D_IDLE2D |
68 			  ISYNC_WAIT_IDLEGUI |
69 			  ISYNC_CPSCRATCH_IDLEGUI);
70 	radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
71 	radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
72 	radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
73 	radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
74 	radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
75 	radeon_ring_write(ring, 0);
76 	radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
77 	radeon_ring_write(ring, 0);
78 	radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
79 	radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
80 	radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
81 	radeon_ring_write(ring, 0);
82 	radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83 	radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
84 	radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85 	radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
86 	radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
87 	radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88 	radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
89 	radeon_ring_write(ring, 0);
90 	radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91 	radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
92 	radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93 	radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
94 	radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
95 	radeon_ring_write(ring,
96 			  ((6 << MS_X0_SHIFT) |
97 			   (6 << MS_Y0_SHIFT) |
98 			   (6 << MS_X1_SHIFT) |
99 			   (6 << MS_Y1_SHIFT) |
100 			   (6 << MS_X2_SHIFT) |
101 			   (6 << MS_Y2_SHIFT) |
102 			   (6 << MSBD0_Y_SHIFT) |
103 			   (6 << MSBD0_X_SHIFT)));
104 	radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
105 	radeon_ring_write(ring,
106 			  ((6 << MS_X3_SHIFT) |
107 			   (6 << MS_Y3_SHIFT) |
108 			   (6 << MS_X4_SHIFT) |
109 			   (6 << MS_Y4_SHIFT) |
110 			   (6 << MS_X5_SHIFT) |
111 			   (6 << MS_Y5_SHIFT) |
112 			   (6 << MSBD1_SHIFT)));
113 	radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
114 	radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
115 	radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
116 	radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
117 	radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
118 	radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
119 	radeon_ring_write(ring, PACKET0(0x20C8, 0));
120 	radeon_ring_write(ring, 0);
121 	radeon_ring_unlock_commit(rdev, ring);
122 }
123 
rv515_mc_wait_for_idle(struct radeon_device * rdev)124 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
125 {
126 	unsigned i;
127 	uint32_t tmp;
128 
129 	for (i = 0; i < rdev->usec_timeout; i++) {
130 		/* read MC_STATUS */
131 		tmp = RREG32_MC(MC_STATUS);
132 		if (tmp & MC_STATUS_IDLE) {
133 			return 0;
134 		}
135 		DRM_UDELAY(1);
136 	}
137 	return -1;
138 }
139 
rv515_vga_render_disable(struct radeon_device * rdev)140 void rv515_vga_render_disable(struct radeon_device *rdev)
141 {
142 	WREG32(R_000300_VGA_RENDER_CONTROL,
143 		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
144 }
145 
rv515_gpu_init(struct radeon_device * rdev)146 void rv515_gpu_init(struct radeon_device *rdev)
147 {
148 	unsigned pipe_select_current, gb_pipe_select, tmp;
149 
150 	if (r100_gui_wait_for_idle(rdev)) {
151 		printk(KERN_WARNING "Failed to wait GUI idle while "
152 		       "resetting GPU. Bad things might happen.\n");
153 	}
154 	rv515_vga_render_disable(rdev);
155 	r420_pipes_init(rdev);
156 	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
157 	tmp = RREG32(R300_DST_PIPE_CONFIG);
158 	pipe_select_current = (tmp >> 2) & 3;
159 	tmp = (1 << pipe_select_current) |
160 	      (((gb_pipe_select >> 8) & 0xF) << 4);
161 	WREG32_PLL(0x000D, tmp);
162 	if (r100_gui_wait_for_idle(rdev)) {
163 		printk(KERN_WARNING "Failed to wait GUI idle while "
164 		       "resetting GPU. Bad things might happen.\n");
165 	}
166 	if (rv515_mc_wait_for_idle(rdev)) {
167 		printk(KERN_WARNING "Failed to wait MC idle while "
168 		       "programming pipes. Bad things might happen.\n");
169 	}
170 }
171 
rv515_vram_get_type(struct radeon_device * rdev)172 static void rv515_vram_get_type(struct radeon_device *rdev)
173 {
174 	uint32_t tmp;
175 
176 	rdev->mc.vram_width = 128;
177 	rdev->mc.vram_is_ddr = true;
178 	tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
179 	switch (tmp) {
180 	case 0:
181 		rdev->mc.vram_width = 64;
182 		break;
183 	case 1:
184 		rdev->mc.vram_width = 128;
185 		break;
186 	default:
187 		rdev->mc.vram_width = 128;
188 		break;
189 	}
190 }
191 
rv515_mc_init(struct radeon_device * rdev)192 void rv515_mc_init(struct radeon_device *rdev)
193 {
194 
195 	rv515_vram_get_type(rdev);
196 	r100_vram_init_sizes(rdev);
197 	radeon_vram_location(rdev, &rdev->mc, 0);
198 	rdev->mc.gtt_base_align = 0;
199 	if (!(rdev->flags & RADEON_IS_AGP))
200 		radeon_gtt_location(rdev, &rdev->mc);
201 	radeon_update_bandwidth_info(rdev);
202 }
203 
rv515_mc_rreg(struct radeon_device * rdev,uint32_t reg)204 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
205 {
206 	uint32_t r;
207 
208 	WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
209 	r = RREG32(MC_IND_DATA);
210 	WREG32(MC_IND_INDEX, 0);
211 	return r;
212 }
213 
rv515_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)214 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
215 {
216 	WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
217 	WREG32(MC_IND_DATA, (v));
218 	WREG32(MC_IND_INDEX, 0);
219 }
220 
221 #if defined(CONFIG_DEBUG_FS)
rv515_debugfs_pipes_info(struct seq_file * m,void * data)222 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
223 {
224 	struct drm_info_node *node = (struct drm_info_node *) m->private;
225 	struct drm_device *dev = node->minor->dev;
226 	struct radeon_device *rdev = dev->dev_private;
227 	uint32_t tmp;
228 
229 	tmp = RREG32(GB_PIPE_SELECT);
230 	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
231 	tmp = RREG32(SU_REG_DEST);
232 	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
233 	tmp = RREG32(GB_TILE_CONFIG);
234 	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
235 	tmp = RREG32(DST_PIPE_CONFIG);
236 	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
237 	return 0;
238 }
239 
rv515_debugfs_ga_info(struct seq_file * m,void * data)240 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
241 {
242 	struct drm_info_node *node = (struct drm_info_node *) m->private;
243 	struct drm_device *dev = node->minor->dev;
244 	struct radeon_device *rdev = dev->dev_private;
245 	uint32_t tmp;
246 
247 	tmp = RREG32(0x2140);
248 	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
249 	radeon_asic_reset(rdev);
250 	tmp = RREG32(0x425C);
251 	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
252 	return 0;
253 }
254 
255 static struct drm_info_list rv515_pipes_info_list[] = {
256 	{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
257 };
258 
259 static struct drm_info_list rv515_ga_info_list[] = {
260 	{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
261 };
262 #endif
263 
rv515_debugfs_pipes_info_init(struct radeon_device * rdev)264 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
265 {
266 #if defined(CONFIG_DEBUG_FS)
267 	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
268 #else
269 	return 0;
270 #endif
271 }
272 
rv515_debugfs_ga_info_init(struct radeon_device * rdev)273 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
274 {
275 #if defined(CONFIG_DEBUG_FS)
276 	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
277 #else
278 	return 0;
279 #endif
280 }
281 
rv515_mc_stop(struct radeon_device * rdev,struct rv515_mc_save * save)282 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
283 {
284 	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
285 	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
286 
287 	/* Stop all video */
288 	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
289 	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
290 	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
291 	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
292 	WREG32(R_006080_D1CRTC_CONTROL, 0);
293 	WREG32(R_006880_D2CRTC_CONTROL, 0);
294 	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
295 	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
296 	WREG32(R_000330_D1VGA_CONTROL, 0);
297 	WREG32(R_000338_D2VGA_CONTROL, 0);
298 }
299 
rv515_mc_resume(struct radeon_device * rdev,struct rv515_mc_save * save)300 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
301 {
302 	WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
303 	WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
304 	WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
305 	WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
306 	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
307 	/* Unlock host access */
308 	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
309 	mdelay(1);
310 	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
311 }
312 
rv515_mc_program(struct radeon_device * rdev)313 void rv515_mc_program(struct radeon_device *rdev)
314 {
315 	struct rv515_mc_save save;
316 
317 	/* Stops all mc clients */
318 	rv515_mc_stop(rdev, &save);
319 
320 	/* Wait for mc idle */
321 	if (rv515_mc_wait_for_idle(rdev))
322 		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
323 	/* Write VRAM size in case we are limiting it */
324 	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
325 	/* Program MC, should be a 32bits limited address space */
326 	WREG32_MC(R_000001_MC_FB_LOCATION,
327 			S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
328 			S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
329 	WREG32(R_000134_HDP_FB_LOCATION,
330 		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
331 	if (rdev->flags & RADEON_IS_AGP) {
332 		WREG32_MC(R_000002_MC_AGP_LOCATION,
333 			S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
334 			S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
335 		WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
336 		WREG32_MC(R_000004_MC_AGP_BASE_2,
337 			S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
338 	} else {
339 		WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
340 		WREG32_MC(R_000003_MC_AGP_BASE, 0);
341 		WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
342 	}
343 
344 	rv515_mc_resume(rdev, &save);
345 }
346 
rv515_clock_startup(struct radeon_device * rdev)347 void rv515_clock_startup(struct radeon_device *rdev)
348 {
349 	if (radeon_dynclks != -1 && radeon_dynclks)
350 		radeon_atom_set_clock_gating(rdev, 1);
351 	/* We need to force on some of the block */
352 	WREG32_PLL(R_00000F_CP_DYN_CNTL,
353 		RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
354 	WREG32_PLL(R_000011_E2_DYN_CNTL,
355 		RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
356 	WREG32_PLL(R_000013_IDCT_DYN_CNTL,
357 		RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
358 }
359 
rv515_startup(struct radeon_device * rdev)360 static int rv515_startup(struct radeon_device *rdev)
361 {
362 	int r;
363 
364 	rv515_mc_program(rdev);
365 	/* Resume clock */
366 	rv515_clock_startup(rdev);
367 	/* Initialize GPU configuration (# pipes, ...) */
368 	rv515_gpu_init(rdev);
369 	/* Initialize GART (initialize after TTM so we can allocate
370 	 * memory through TTM but finalize after TTM) */
371 	if (rdev->flags & RADEON_IS_PCIE) {
372 		r = rv370_pcie_gart_enable(rdev);
373 		if (r)
374 			return r;
375 	}
376 
377 	/* allocate wb buffer */
378 	r = radeon_wb_init(rdev);
379 	if (r)
380 		return r;
381 
382 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
383 	if (r) {
384 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
385 		return r;
386 	}
387 
388 	/* Enable IRQ */
389 	if (!rdev->irq.installed) {
390 		r = radeon_irq_kms_init(rdev);
391 		if (r)
392 			return r;
393 	}
394 
395 	rs600_irq_set(rdev);
396 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
397 	/* 1M ring buffer */
398 	r = r100_cp_init(rdev, 1024 * 1024);
399 	if (r) {
400 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
401 		return r;
402 	}
403 
404 	r = radeon_ib_pool_start(rdev);
405 	if (r)
406 		return r;
407 
408 	r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
409 	if (r) {
410 		dev_err(rdev->dev, "failed testing IB (%d).\n", r);
411 		rdev->accel_working = false;
412 		return r;
413 	}
414 	return 0;
415 }
416 
rv515_resume(struct radeon_device * rdev)417 int rv515_resume(struct radeon_device *rdev)
418 {
419 	int r;
420 
421 	/* Make sur GART are not working */
422 	if (rdev->flags & RADEON_IS_PCIE)
423 		rv370_pcie_gart_disable(rdev);
424 	/* Resume clock before doing reset */
425 	rv515_clock_startup(rdev);
426 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
427 	if (radeon_asic_reset(rdev)) {
428 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
429 			RREG32(R_000E40_RBBM_STATUS),
430 			RREG32(R_0007C0_CP_STAT));
431 	}
432 	/* post */
433 	atom_asic_init(rdev->mode_info.atom_context);
434 	/* Resume clock after posting */
435 	rv515_clock_startup(rdev);
436 	/* Initialize surface registers */
437 	radeon_surface_init(rdev);
438 
439 	rdev->accel_working = true;
440 	r =  rv515_startup(rdev);
441 	if (r) {
442 		rdev->accel_working = false;
443 	}
444 	return r;
445 }
446 
rv515_suspend(struct radeon_device * rdev)447 int rv515_suspend(struct radeon_device *rdev)
448 {
449 	r100_cp_disable(rdev);
450 	radeon_wb_disable(rdev);
451 	rs600_irq_disable(rdev);
452 	if (rdev->flags & RADEON_IS_PCIE)
453 		rv370_pcie_gart_disable(rdev);
454 	return 0;
455 }
456 
rv515_set_safe_registers(struct radeon_device * rdev)457 void rv515_set_safe_registers(struct radeon_device *rdev)
458 {
459 	rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
460 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
461 }
462 
rv515_fini(struct radeon_device * rdev)463 void rv515_fini(struct radeon_device *rdev)
464 {
465 	r100_cp_fini(rdev);
466 	radeon_wb_fini(rdev);
467 	r100_ib_fini(rdev);
468 	radeon_gem_fini(rdev);
469 	rv370_pcie_gart_fini(rdev);
470 	radeon_agp_fini(rdev);
471 	radeon_irq_kms_fini(rdev);
472 	radeon_fence_driver_fini(rdev);
473 	radeon_bo_fini(rdev);
474 	radeon_atombios_fini(rdev);
475 	kfree(rdev->bios);
476 	rdev->bios = NULL;
477 }
478 
rv515_init(struct radeon_device * rdev)479 int rv515_init(struct radeon_device *rdev)
480 {
481 	int r;
482 
483 	/* Initialize scratch registers */
484 	radeon_scratch_init(rdev);
485 	/* Initialize surface registers */
486 	radeon_surface_init(rdev);
487 	/* TODO: disable VGA need to use VGA request */
488 	/* restore some register to sane defaults */
489 	r100_restore_sanity(rdev);
490 	/* BIOS*/
491 	if (!radeon_get_bios(rdev)) {
492 		if (ASIC_IS_AVIVO(rdev))
493 			return -EINVAL;
494 	}
495 	if (rdev->is_atom_bios) {
496 		r = radeon_atombios_init(rdev);
497 		if (r)
498 			return r;
499 	} else {
500 		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
501 		return -EINVAL;
502 	}
503 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
504 	if (radeon_asic_reset(rdev)) {
505 		dev_warn(rdev->dev,
506 			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
507 			RREG32(R_000E40_RBBM_STATUS),
508 			RREG32(R_0007C0_CP_STAT));
509 	}
510 	/* check if cards are posted or not */
511 	if (radeon_boot_test_post_card(rdev) == false)
512 		return -EINVAL;
513 	/* Initialize clocks */
514 	radeon_get_clock_info(rdev->ddev);
515 	/* initialize AGP */
516 	if (rdev->flags & RADEON_IS_AGP) {
517 		r = radeon_agp_init(rdev);
518 		if (r) {
519 			radeon_agp_disable(rdev);
520 		}
521 	}
522 	/* initialize memory controller */
523 	rv515_mc_init(rdev);
524 	rv515_debugfs(rdev);
525 	/* Fence driver */
526 	r = radeon_fence_driver_init(rdev);
527 	if (r)
528 		return r;
529 	/* Memory manager */
530 	r = radeon_bo_init(rdev);
531 	if (r)
532 		return r;
533 	r = rv370_pcie_gart_init(rdev);
534 	if (r)
535 		return r;
536 	rv515_set_safe_registers(rdev);
537 
538 	r = radeon_ib_pool_init(rdev);
539 	rdev->accel_working = true;
540 	if (r) {
541 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
542 		rdev->accel_working = false;
543 	}
544 
545 	r = rv515_startup(rdev);
546 	if (r) {
547 		/* Somethings want wront with the accel init stop accel */
548 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
549 		r100_cp_fini(rdev);
550 		radeon_wb_fini(rdev);
551 		r100_ib_fini(rdev);
552 		radeon_irq_kms_fini(rdev);
553 		rv370_pcie_gart_fini(rdev);
554 		radeon_agp_fini(rdev);
555 		rdev->accel_working = false;
556 	}
557 	return 0;
558 }
559 
atom_rv515_force_tv_scaler(struct radeon_device * rdev,struct radeon_crtc * crtc)560 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
561 {
562 	int index_reg = 0x6578 + crtc->crtc_offset;
563 	int data_reg = 0x657c + crtc->crtc_offset;
564 
565 	WREG32(0x659C + crtc->crtc_offset, 0x0);
566 	WREG32(0x6594 + crtc->crtc_offset, 0x705);
567 	WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
568 	WREG32(0x65D8 + crtc->crtc_offset, 0x0);
569 	WREG32(0x65B0 + crtc->crtc_offset, 0x0);
570 	WREG32(0x65C0 + crtc->crtc_offset, 0x0);
571 	WREG32(0x65D4 + crtc->crtc_offset, 0x0);
572 	WREG32(index_reg, 0x0);
573 	WREG32(data_reg, 0x841880A8);
574 	WREG32(index_reg, 0x1);
575 	WREG32(data_reg, 0x84208680);
576 	WREG32(index_reg, 0x2);
577 	WREG32(data_reg, 0xBFF880B0);
578 	WREG32(index_reg, 0x100);
579 	WREG32(data_reg, 0x83D88088);
580 	WREG32(index_reg, 0x101);
581 	WREG32(data_reg, 0x84608680);
582 	WREG32(index_reg, 0x102);
583 	WREG32(data_reg, 0xBFF080D0);
584 	WREG32(index_reg, 0x200);
585 	WREG32(data_reg, 0x83988068);
586 	WREG32(index_reg, 0x201);
587 	WREG32(data_reg, 0x84A08680);
588 	WREG32(index_reg, 0x202);
589 	WREG32(data_reg, 0xBFF080F8);
590 	WREG32(index_reg, 0x300);
591 	WREG32(data_reg, 0x83588058);
592 	WREG32(index_reg, 0x301);
593 	WREG32(data_reg, 0x84E08660);
594 	WREG32(index_reg, 0x302);
595 	WREG32(data_reg, 0xBFF88120);
596 	WREG32(index_reg, 0x400);
597 	WREG32(data_reg, 0x83188040);
598 	WREG32(index_reg, 0x401);
599 	WREG32(data_reg, 0x85008660);
600 	WREG32(index_reg, 0x402);
601 	WREG32(data_reg, 0xBFF88150);
602 	WREG32(index_reg, 0x500);
603 	WREG32(data_reg, 0x82D88030);
604 	WREG32(index_reg, 0x501);
605 	WREG32(data_reg, 0x85408640);
606 	WREG32(index_reg, 0x502);
607 	WREG32(data_reg, 0xBFF88180);
608 	WREG32(index_reg, 0x600);
609 	WREG32(data_reg, 0x82A08018);
610 	WREG32(index_reg, 0x601);
611 	WREG32(data_reg, 0x85808620);
612 	WREG32(index_reg, 0x602);
613 	WREG32(data_reg, 0xBFF081B8);
614 	WREG32(index_reg, 0x700);
615 	WREG32(data_reg, 0x82608010);
616 	WREG32(index_reg, 0x701);
617 	WREG32(data_reg, 0x85A08600);
618 	WREG32(index_reg, 0x702);
619 	WREG32(data_reg, 0x800081F0);
620 	WREG32(index_reg, 0x800);
621 	WREG32(data_reg, 0x8228BFF8);
622 	WREG32(index_reg, 0x801);
623 	WREG32(data_reg, 0x85E085E0);
624 	WREG32(index_reg, 0x802);
625 	WREG32(data_reg, 0xBFF88228);
626 	WREG32(index_reg, 0x10000);
627 	WREG32(data_reg, 0x82A8BF00);
628 	WREG32(index_reg, 0x10001);
629 	WREG32(data_reg, 0x82A08CC0);
630 	WREG32(index_reg, 0x10002);
631 	WREG32(data_reg, 0x8008BEF8);
632 	WREG32(index_reg, 0x10100);
633 	WREG32(data_reg, 0x81F0BF28);
634 	WREG32(index_reg, 0x10101);
635 	WREG32(data_reg, 0x83608CA0);
636 	WREG32(index_reg, 0x10102);
637 	WREG32(data_reg, 0x8018BED0);
638 	WREG32(index_reg, 0x10200);
639 	WREG32(data_reg, 0x8148BF38);
640 	WREG32(index_reg, 0x10201);
641 	WREG32(data_reg, 0x84408C80);
642 	WREG32(index_reg, 0x10202);
643 	WREG32(data_reg, 0x8008BEB8);
644 	WREG32(index_reg, 0x10300);
645 	WREG32(data_reg, 0x80B0BF78);
646 	WREG32(index_reg, 0x10301);
647 	WREG32(data_reg, 0x85008C20);
648 	WREG32(index_reg, 0x10302);
649 	WREG32(data_reg, 0x8020BEA0);
650 	WREG32(index_reg, 0x10400);
651 	WREG32(data_reg, 0x8028BF90);
652 	WREG32(index_reg, 0x10401);
653 	WREG32(data_reg, 0x85E08BC0);
654 	WREG32(index_reg, 0x10402);
655 	WREG32(data_reg, 0x8018BE90);
656 	WREG32(index_reg, 0x10500);
657 	WREG32(data_reg, 0xBFB8BFB0);
658 	WREG32(index_reg, 0x10501);
659 	WREG32(data_reg, 0x86C08B40);
660 	WREG32(index_reg, 0x10502);
661 	WREG32(data_reg, 0x8010BE90);
662 	WREG32(index_reg, 0x10600);
663 	WREG32(data_reg, 0xBF58BFC8);
664 	WREG32(index_reg, 0x10601);
665 	WREG32(data_reg, 0x87A08AA0);
666 	WREG32(index_reg, 0x10602);
667 	WREG32(data_reg, 0x8010BE98);
668 	WREG32(index_reg, 0x10700);
669 	WREG32(data_reg, 0xBF10BFF0);
670 	WREG32(index_reg, 0x10701);
671 	WREG32(data_reg, 0x886089E0);
672 	WREG32(index_reg, 0x10702);
673 	WREG32(data_reg, 0x8018BEB0);
674 	WREG32(index_reg, 0x10800);
675 	WREG32(data_reg, 0xBED8BFE8);
676 	WREG32(index_reg, 0x10801);
677 	WREG32(data_reg, 0x89408940);
678 	WREG32(index_reg, 0x10802);
679 	WREG32(data_reg, 0xBFE8BED8);
680 	WREG32(index_reg, 0x20000);
681 	WREG32(data_reg, 0x80008000);
682 	WREG32(index_reg, 0x20001);
683 	WREG32(data_reg, 0x90008000);
684 	WREG32(index_reg, 0x20002);
685 	WREG32(data_reg, 0x80008000);
686 	WREG32(index_reg, 0x20003);
687 	WREG32(data_reg, 0x80008000);
688 	WREG32(index_reg, 0x20100);
689 	WREG32(data_reg, 0x80108000);
690 	WREG32(index_reg, 0x20101);
691 	WREG32(data_reg, 0x8FE0BF70);
692 	WREG32(index_reg, 0x20102);
693 	WREG32(data_reg, 0xBFE880C0);
694 	WREG32(index_reg, 0x20103);
695 	WREG32(data_reg, 0x80008000);
696 	WREG32(index_reg, 0x20200);
697 	WREG32(data_reg, 0x8018BFF8);
698 	WREG32(index_reg, 0x20201);
699 	WREG32(data_reg, 0x8F80BF08);
700 	WREG32(index_reg, 0x20202);
701 	WREG32(data_reg, 0xBFD081A0);
702 	WREG32(index_reg, 0x20203);
703 	WREG32(data_reg, 0xBFF88000);
704 	WREG32(index_reg, 0x20300);
705 	WREG32(data_reg, 0x80188000);
706 	WREG32(index_reg, 0x20301);
707 	WREG32(data_reg, 0x8EE0BEC0);
708 	WREG32(index_reg, 0x20302);
709 	WREG32(data_reg, 0xBFB082A0);
710 	WREG32(index_reg, 0x20303);
711 	WREG32(data_reg, 0x80008000);
712 	WREG32(index_reg, 0x20400);
713 	WREG32(data_reg, 0x80188000);
714 	WREG32(index_reg, 0x20401);
715 	WREG32(data_reg, 0x8E00BEA0);
716 	WREG32(index_reg, 0x20402);
717 	WREG32(data_reg, 0xBF8883C0);
718 	WREG32(index_reg, 0x20403);
719 	WREG32(data_reg, 0x80008000);
720 	WREG32(index_reg, 0x20500);
721 	WREG32(data_reg, 0x80188000);
722 	WREG32(index_reg, 0x20501);
723 	WREG32(data_reg, 0x8D00BE90);
724 	WREG32(index_reg, 0x20502);
725 	WREG32(data_reg, 0xBF588500);
726 	WREG32(index_reg, 0x20503);
727 	WREG32(data_reg, 0x80008008);
728 	WREG32(index_reg, 0x20600);
729 	WREG32(data_reg, 0x80188000);
730 	WREG32(index_reg, 0x20601);
731 	WREG32(data_reg, 0x8BC0BE98);
732 	WREG32(index_reg, 0x20602);
733 	WREG32(data_reg, 0xBF308660);
734 	WREG32(index_reg, 0x20603);
735 	WREG32(data_reg, 0x80008008);
736 	WREG32(index_reg, 0x20700);
737 	WREG32(data_reg, 0x80108000);
738 	WREG32(index_reg, 0x20701);
739 	WREG32(data_reg, 0x8A80BEB0);
740 	WREG32(index_reg, 0x20702);
741 	WREG32(data_reg, 0xBF0087C0);
742 	WREG32(index_reg, 0x20703);
743 	WREG32(data_reg, 0x80008008);
744 	WREG32(index_reg, 0x20800);
745 	WREG32(data_reg, 0x80108000);
746 	WREG32(index_reg, 0x20801);
747 	WREG32(data_reg, 0x8920BED0);
748 	WREG32(index_reg, 0x20802);
749 	WREG32(data_reg, 0xBED08920);
750 	WREG32(index_reg, 0x20803);
751 	WREG32(data_reg, 0x80008010);
752 	WREG32(index_reg, 0x30000);
753 	WREG32(data_reg, 0x90008000);
754 	WREG32(index_reg, 0x30001);
755 	WREG32(data_reg, 0x80008000);
756 	WREG32(index_reg, 0x30100);
757 	WREG32(data_reg, 0x8FE0BF90);
758 	WREG32(index_reg, 0x30101);
759 	WREG32(data_reg, 0xBFF880A0);
760 	WREG32(index_reg, 0x30200);
761 	WREG32(data_reg, 0x8F60BF40);
762 	WREG32(index_reg, 0x30201);
763 	WREG32(data_reg, 0xBFE88180);
764 	WREG32(index_reg, 0x30300);
765 	WREG32(data_reg, 0x8EC0BF00);
766 	WREG32(index_reg, 0x30301);
767 	WREG32(data_reg, 0xBFC88280);
768 	WREG32(index_reg, 0x30400);
769 	WREG32(data_reg, 0x8DE0BEE0);
770 	WREG32(index_reg, 0x30401);
771 	WREG32(data_reg, 0xBFA083A0);
772 	WREG32(index_reg, 0x30500);
773 	WREG32(data_reg, 0x8CE0BED0);
774 	WREG32(index_reg, 0x30501);
775 	WREG32(data_reg, 0xBF7884E0);
776 	WREG32(index_reg, 0x30600);
777 	WREG32(data_reg, 0x8BA0BED8);
778 	WREG32(index_reg, 0x30601);
779 	WREG32(data_reg, 0xBF508640);
780 	WREG32(index_reg, 0x30700);
781 	WREG32(data_reg, 0x8A60BEE8);
782 	WREG32(index_reg, 0x30701);
783 	WREG32(data_reg, 0xBF2087A0);
784 	WREG32(index_reg, 0x30800);
785 	WREG32(data_reg, 0x8900BF00);
786 	WREG32(index_reg, 0x30801);
787 	WREG32(data_reg, 0xBF008900);
788 }
789 
790 struct rv515_watermark {
791 	u32        lb_request_fifo_depth;
792 	fixed20_12 num_line_pair;
793 	fixed20_12 estimated_width;
794 	fixed20_12 worst_case_latency;
795 	fixed20_12 consumption_rate;
796 	fixed20_12 active_time;
797 	fixed20_12 dbpp;
798 	fixed20_12 priority_mark_max;
799 	fixed20_12 priority_mark;
800 	fixed20_12 sclk;
801 };
802 
rv515_crtc_bandwidth_compute(struct radeon_device * rdev,struct radeon_crtc * crtc,struct rv515_watermark * wm)803 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
804 				  struct radeon_crtc *crtc,
805 				  struct rv515_watermark *wm)
806 {
807 	struct drm_display_mode *mode = &crtc->base.mode;
808 	fixed20_12 a, b, c;
809 	fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
810 	fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
811 
812 	if (!crtc->base.enabled) {
813 		/* FIXME: wouldn't it better to set priority mark to maximum */
814 		wm->lb_request_fifo_depth = 4;
815 		return;
816 	}
817 
818 	if (crtc->vsc.full > dfixed_const(2))
819 		wm->num_line_pair.full = dfixed_const(2);
820 	else
821 		wm->num_line_pair.full = dfixed_const(1);
822 
823 	b.full = dfixed_const(mode->crtc_hdisplay);
824 	c.full = dfixed_const(256);
825 	a.full = dfixed_div(b, c);
826 	request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
827 	request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
828 	if (a.full < dfixed_const(4)) {
829 		wm->lb_request_fifo_depth = 4;
830 	} else {
831 		wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
832 	}
833 
834 	/* Determine consumption rate
835 	 *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
836 	 *  vtaps = number of vertical taps,
837 	 *  vsc = vertical scaling ratio, defined as source/destination
838 	 *  hsc = horizontal scaling ration, defined as source/destination
839 	 */
840 	a.full = dfixed_const(mode->clock);
841 	b.full = dfixed_const(1000);
842 	a.full = dfixed_div(a, b);
843 	pclk.full = dfixed_div(b, a);
844 	if (crtc->rmx_type != RMX_OFF) {
845 		b.full = dfixed_const(2);
846 		if (crtc->vsc.full > b.full)
847 			b.full = crtc->vsc.full;
848 		b.full = dfixed_mul(b, crtc->hsc);
849 		c.full = dfixed_const(2);
850 		b.full = dfixed_div(b, c);
851 		consumption_time.full = dfixed_div(pclk, b);
852 	} else {
853 		consumption_time.full = pclk.full;
854 	}
855 	a.full = dfixed_const(1);
856 	wm->consumption_rate.full = dfixed_div(a, consumption_time);
857 
858 
859 	/* Determine line time
860 	 *  LineTime = total time for one line of displayhtotal
861 	 *  LineTime = total number of horizontal pixels
862 	 *  pclk = pixel clock period(ns)
863 	 */
864 	a.full = dfixed_const(crtc->base.mode.crtc_htotal);
865 	line_time.full = dfixed_mul(a, pclk);
866 
867 	/* Determine active time
868 	 *  ActiveTime = time of active region of display within one line,
869 	 *  hactive = total number of horizontal active pixels
870 	 *  htotal = total number of horizontal pixels
871 	 */
872 	a.full = dfixed_const(crtc->base.mode.crtc_htotal);
873 	b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
874 	wm->active_time.full = dfixed_mul(line_time, b);
875 	wm->active_time.full = dfixed_div(wm->active_time, a);
876 
877 	/* Determine chunk time
878 	 * ChunkTime = the time it takes the DCP to send one chunk of data
879 	 * to the LB which consists of pipeline delay and inter chunk gap
880 	 * sclk = system clock(Mhz)
881 	 */
882 	a.full = dfixed_const(600 * 1000);
883 	chunk_time.full = dfixed_div(a, rdev->pm.sclk);
884 	read_delay_latency.full = dfixed_const(1000);
885 
886 	/* Determine the worst case latency
887 	 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
888 	 * WorstCaseLatency = worst case time from urgent to when the MC starts
889 	 *                    to return data
890 	 * READ_DELAY_IDLE_MAX = constant of 1us
891 	 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
892 	 *             which consists of pipeline delay and inter chunk gap
893 	 */
894 	if (dfixed_trunc(wm->num_line_pair) > 1) {
895 		a.full = dfixed_const(3);
896 		wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
897 		wm->worst_case_latency.full += read_delay_latency.full;
898 	} else {
899 		wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
900 	}
901 
902 	/* Determine the tolerable latency
903 	 * TolerableLatency = Any given request has only 1 line time
904 	 *                    for the data to be returned
905 	 * LBRequestFifoDepth = Number of chunk requests the LB can
906 	 *                      put into the request FIFO for a display
907 	 *  LineTime = total time for one line of display
908 	 *  ChunkTime = the time it takes the DCP to send one chunk
909 	 *              of data to the LB which consists of
910 	 *  pipeline delay and inter chunk gap
911 	 */
912 	if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
913 		tolerable_latency.full = line_time.full;
914 	} else {
915 		tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
916 		tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
917 		tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
918 		tolerable_latency.full = line_time.full - tolerable_latency.full;
919 	}
920 	/* We assume worst case 32bits (4 bytes) */
921 	wm->dbpp.full = dfixed_const(2 * 16);
922 
923 	/* Determine the maximum priority mark
924 	 *  width = viewport width in pixels
925 	 */
926 	a.full = dfixed_const(16);
927 	wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
928 	wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
929 	wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
930 
931 	/* Determine estimated width */
932 	estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
933 	estimated_width.full = dfixed_div(estimated_width, consumption_time);
934 	if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
935 		wm->priority_mark.full = wm->priority_mark_max.full;
936 	} else {
937 		a.full = dfixed_const(16);
938 		wm->priority_mark.full = dfixed_div(estimated_width, a);
939 		wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
940 		wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
941 	}
942 }
943 
rv515_bandwidth_avivo_update(struct radeon_device * rdev)944 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
945 {
946 	struct drm_display_mode *mode0 = NULL;
947 	struct drm_display_mode *mode1 = NULL;
948 	struct rv515_watermark wm0;
949 	struct rv515_watermark wm1;
950 	u32 tmp;
951 	u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
952 	u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
953 	fixed20_12 priority_mark02, priority_mark12, fill_rate;
954 	fixed20_12 a, b;
955 
956 	if (rdev->mode_info.crtcs[0]->base.enabled)
957 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
958 	if (rdev->mode_info.crtcs[1]->base.enabled)
959 		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
960 	rs690_line_buffer_adjust(rdev, mode0, mode1);
961 
962 	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
963 	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
964 
965 	tmp = wm0.lb_request_fifo_depth;
966 	tmp |= wm1.lb_request_fifo_depth << 16;
967 	WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
968 
969 	if (mode0 && mode1) {
970 		if (dfixed_trunc(wm0.dbpp) > 64)
971 			a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
972 		else
973 			a.full = wm0.num_line_pair.full;
974 		if (dfixed_trunc(wm1.dbpp) > 64)
975 			b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
976 		else
977 			b.full = wm1.num_line_pair.full;
978 		a.full += b.full;
979 		fill_rate.full = dfixed_div(wm0.sclk, a);
980 		if (wm0.consumption_rate.full > fill_rate.full) {
981 			b.full = wm0.consumption_rate.full - fill_rate.full;
982 			b.full = dfixed_mul(b, wm0.active_time);
983 			a.full = dfixed_const(16);
984 			b.full = dfixed_div(b, a);
985 			a.full = dfixed_mul(wm0.worst_case_latency,
986 						wm0.consumption_rate);
987 			priority_mark02.full = a.full + b.full;
988 		} else {
989 			a.full = dfixed_mul(wm0.worst_case_latency,
990 						wm0.consumption_rate);
991 			b.full = dfixed_const(16 * 1000);
992 			priority_mark02.full = dfixed_div(a, b);
993 		}
994 		if (wm1.consumption_rate.full > fill_rate.full) {
995 			b.full = wm1.consumption_rate.full - fill_rate.full;
996 			b.full = dfixed_mul(b, wm1.active_time);
997 			a.full = dfixed_const(16);
998 			b.full = dfixed_div(b, a);
999 			a.full = dfixed_mul(wm1.worst_case_latency,
1000 						wm1.consumption_rate);
1001 			priority_mark12.full = a.full + b.full;
1002 		} else {
1003 			a.full = dfixed_mul(wm1.worst_case_latency,
1004 						wm1.consumption_rate);
1005 			b.full = dfixed_const(16 * 1000);
1006 			priority_mark12.full = dfixed_div(a, b);
1007 		}
1008 		if (wm0.priority_mark.full > priority_mark02.full)
1009 			priority_mark02.full = wm0.priority_mark.full;
1010 		if (dfixed_trunc(priority_mark02) < 0)
1011 			priority_mark02.full = 0;
1012 		if (wm0.priority_mark_max.full > priority_mark02.full)
1013 			priority_mark02.full = wm0.priority_mark_max.full;
1014 		if (wm1.priority_mark.full > priority_mark12.full)
1015 			priority_mark12.full = wm1.priority_mark.full;
1016 		if (dfixed_trunc(priority_mark12) < 0)
1017 			priority_mark12.full = 0;
1018 		if (wm1.priority_mark_max.full > priority_mark12.full)
1019 			priority_mark12.full = wm1.priority_mark_max.full;
1020 		d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1021 		d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1022 		if (rdev->disp_priority == 2) {
1023 			d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1024 			d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1025 		}
1026 	} else if (mode0) {
1027 		if (dfixed_trunc(wm0.dbpp) > 64)
1028 			a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1029 		else
1030 			a.full = wm0.num_line_pair.full;
1031 		fill_rate.full = dfixed_div(wm0.sclk, a);
1032 		if (wm0.consumption_rate.full > fill_rate.full) {
1033 			b.full = wm0.consumption_rate.full - fill_rate.full;
1034 			b.full = dfixed_mul(b, wm0.active_time);
1035 			a.full = dfixed_const(16);
1036 			b.full = dfixed_div(b, a);
1037 			a.full = dfixed_mul(wm0.worst_case_latency,
1038 						wm0.consumption_rate);
1039 			priority_mark02.full = a.full + b.full;
1040 		} else {
1041 			a.full = dfixed_mul(wm0.worst_case_latency,
1042 						wm0.consumption_rate);
1043 			b.full = dfixed_const(16);
1044 			priority_mark02.full = dfixed_div(a, b);
1045 		}
1046 		if (wm0.priority_mark.full > priority_mark02.full)
1047 			priority_mark02.full = wm0.priority_mark.full;
1048 		if (dfixed_trunc(priority_mark02) < 0)
1049 			priority_mark02.full = 0;
1050 		if (wm0.priority_mark_max.full > priority_mark02.full)
1051 			priority_mark02.full = wm0.priority_mark_max.full;
1052 		d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1053 		if (rdev->disp_priority == 2)
1054 			d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1055 	} else if (mode1) {
1056 		if (dfixed_trunc(wm1.dbpp) > 64)
1057 			a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1058 		else
1059 			a.full = wm1.num_line_pair.full;
1060 		fill_rate.full = dfixed_div(wm1.sclk, a);
1061 		if (wm1.consumption_rate.full > fill_rate.full) {
1062 			b.full = wm1.consumption_rate.full - fill_rate.full;
1063 			b.full = dfixed_mul(b, wm1.active_time);
1064 			a.full = dfixed_const(16);
1065 			b.full = dfixed_div(b, a);
1066 			a.full = dfixed_mul(wm1.worst_case_latency,
1067 						wm1.consumption_rate);
1068 			priority_mark12.full = a.full + b.full;
1069 		} else {
1070 			a.full = dfixed_mul(wm1.worst_case_latency,
1071 						wm1.consumption_rate);
1072 			b.full = dfixed_const(16 * 1000);
1073 			priority_mark12.full = dfixed_div(a, b);
1074 		}
1075 		if (wm1.priority_mark.full > priority_mark12.full)
1076 			priority_mark12.full = wm1.priority_mark.full;
1077 		if (dfixed_trunc(priority_mark12) < 0)
1078 			priority_mark12.full = 0;
1079 		if (wm1.priority_mark_max.full > priority_mark12.full)
1080 			priority_mark12.full = wm1.priority_mark_max.full;
1081 		d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1082 		if (rdev->disp_priority == 2)
1083 			d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1084 	}
1085 
1086 	WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1087 	WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1088 	WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1089 	WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1090 }
1091 
rv515_bandwidth_update(struct radeon_device * rdev)1092 void rv515_bandwidth_update(struct radeon_device *rdev)
1093 {
1094 	uint32_t tmp;
1095 	struct drm_display_mode *mode0 = NULL;
1096 	struct drm_display_mode *mode1 = NULL;
1097 
1098 	radeon_update_display_priority(rdev);
1099 
1100 	if (rdev->mode_info.crtcs[0]->base.enabled)
1101 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1102 	if (rdev->mode_info.crtcs[1]->base.enabled)
1103 		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1104 	/*
1105 	 * Set display0/1 priority up in the memory controller for
1106 	 * modes if the user specifies HIGH for displaypriority
1107 	 * option.
1108 	 */
1109 	if ((rdev->disp_priority == 2) &&
1110 	    (rdev->family == CHIP_RV515)) {
1111 		tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1112 		tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1113 		tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1114 		if (mode1)
1115 			tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1116 		if (mode0)
1117 			tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1118 		WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1119 	}
1120 	rv515_bandwidth_avivo_update(rdev);
1121 }
1122