1 /*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/mii.h>
24 #include <linux/crc32.h>
25
26 #include "atl1c.h"
27
28 /*
29 * check_eeprom_exist
30 * return 1 if eeprom exist
31 */
atl1c_check_eeprom_exist(struct atl1c_hw * hw)32 int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
33 {
34 u32 data;
35
36 AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
37 if (data & TWSI_DEBUG_DEV_EXIST)
38 return 1;
39
40 AT_READ_REG(hw, REG_MASTER_CTRL, &data);
41 if (data & MASTER_CTRL_OTP_SEL)
42 return 1;
43 return 0;
44 }
45
atl1c_hw_set_mac_addr(struct atl1c_hw * hw)46 void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
47 {
48 u32 value;
49 /*
50 * 00-0B-6A-F6-00-DC
51 * 0: 6AF600DC 1: 000B
52 * low dword
53 */
54 value = (((u32)hw->mac_addr[2]) << 24) |
55 (((u32)hw->mac_addr[3]) << 16) |
56 (((u32)hw->mac_addr[4]) << 8) |
57 (((u32)hw->mac_addr[5])) ;
58 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
59 /* hight dword */
60 value = (((u32)hw->mac_addr[0]) << 8) |
61 (((u32)hw->mac_addr[1])) ;
62 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
63 }
64
65 /*
66 * atl1c_get_permanent_address
67 * return 0 if get valid mac address,
68 */
atl1c_get_permanent_address(struct atl1c_hw * hw)69 static int atl1c_get_permanent_address(struct atl1c_hw *hw)
70 {
71 u32 addr[2];
72 u32 i;
73 u32 otp_ctrl_data;
74 u32 twsi_ctrl_data;
75 u32 ltssm_ctrl_data;
76 u32 wol_data;
77 u8 eth_addr[ETH_ALEN];
78 u16 phy_data;
79 bool raise_vol = false;
80
81 /* init */
82 addr[0] = addr[1] = 0;
83 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
84 if (atl1c_check_eeprom_exist(hw)) {
85 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
86 /* Enable OTP CLK */
87 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
88 otp_ctrl_data |= OTP_CTRL_CLK_EN;
89 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
90 AT_WRITE_FLUSH(hw);
91 msleep(1);
92 }
93 }
94
95 if (hw->nic_type == athr_l2c_b ||
96 hw->nic_type == athr_l2c_b2 ||
97 hw->nic_type == athr_l1d) {
98 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
99 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
100 goto out;
101 phy_data &= 0xFF7F;
102 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
103
104 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
105 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
106 goto out;
107 phy_data |= 0x8;
108 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
109 udelay(20);
110 raise_vol = true;
111 }
112 /* close open bit of ReadOnly*/
113 AT_READ_REG(hw, REG_LTSSM_ID_CTRL, <ssm_ctrl_data);
114 ltssm_ctrl_data &= ~LTSSM_ID_EN_WRO;
115 AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, ltssm_ctrl_data);
116
117 /* clear any WOL settings */
118 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
119 AT_READ_REG(hw, REG_WOL_CTRL, &wol_data);
120
121
122 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
123 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
124 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
125 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
126 msleep(10);
127 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
128 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
129 break;
130 }
131 if (i >= AT_TWSI_EEPROM_TIMEOUT)
132 return -1;
133 }
134 /* Disable OTP_CLK */
135 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) {
136 otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
137 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
138 msleep(1);
139 }
140 if (raise_vol) {
141 if (hw->nic_type == athr_l2c_b ||
142 hw->nic_type == athr_l2c_b2 ||
143 hw->nic_type == athr_l1d ||
144 hw->nic_type == athr_l1d_2) {
145 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
146 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
147 goto out;
148 phy_data |= 0x80;
149 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
150
151 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
152 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
153 goto out;
154 phy_data &= 0xFFF7;
155 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
156 udelay(20);
157 }
158 }
159
160 /* maybe MAC-address is from BIOS */
161 AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
162 AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
163 *(u32 *) ð_addr[2] = swab32(addr[0]);
164 *(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]);
165
166 if (is_valid_ether_addr(eth_addr)) {
167 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
168 return 0;
169 }
170
171 out:
172 return -1;
173 }
174
atl1c_read_eeprom(struct atl1c_hw * hw,u32 offset,u32 * p_value)175 bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value)
176 {
177 int i;
178 int ret = false;
179 u32 otp_ctrl_data;
180 u32 control;
181 u32 data;
182
183 if (offset & 3)
184 return ret; /* address do not align */
185
186 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
187 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
188 AT_WRITE_REG(hw, REG_OTP_CTRL,
189 (otp_ctrl_data | OTP_CTRL_CLK_EN));
190
191 AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
192 control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT;
193 AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
194
195 for (i = 0; i < 10; i++) {
196 udelay(100);
197 AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
198 if (control & EEPROM_CTRL_RW)
199 break;
200 }
201 if (control & EEPROM_CTRL_RW) {
202 AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
203 AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
204 data = data & 0xFFFF;
205 *p_value = swab32((data << 16) | (*p_value >> 16));
206 ret = true;
207 }
208 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
209 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
210
211 return ret;
212 }
213 /*
214 * Reads the adapter's MAC address from the EEPROM
215 *
216 * hw - Struct containing variables accessed by shared code
217 */
atl1c_read_mac_addr(struct atl1c_hw * hw)218 int atl1c_read_mac_addr(struct atl1c_hw *hw)
219 {
220 int err = 0;
221
222 err = atl1c_get_permanent_address(hw);
223 if (err)
224 random_ether_addr(hw->perm_mac_addr);
225
226 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
227 return err;
228 }
229
230 /*
231 * atl1c_hash_mc_addr
232 * purpose
233 * set hash value for a multicast address
234 * hash calcu processing :
235 * 1. calcu 32bit CRC for multicast address
236 * 2. reverse crc with MSB to LSB
237 */
atl1c_hash_mc_addr(struct atl1c_hw * hw,u8 * mc_addr)238 u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr)
239 {
240 u32 crc32;
241 u32 value = 0;
242 int i;
243
244 crc32 = ether_crc_le(6, mc_addr);
245 for (i = 0; i < 32; i++)
246 value |= (((crc32 >> i) & 1) << (31 - i));
247
248 return value;
249 }
250
251 /*
252 * Sets the bit in the multicast table corresponding to the hash value.
253 * hw - Struct containing variables accessed by shared code
254 * hash_value - Multicast address hash value
255 */
atl1c_hash_set(struct atl1c_hw * hw,u32 hash_value)256 void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
257 {
258 u32 hash_bit, hash_reg;
259 u32 mta;
260
261 /*
262 * The HASH Table is a register array of 2 32-bit registers.
263 * It is treated like an array of 64 bits. We want to set
264 * bit BitArray[hash_value]. So we figure out what register
265 * the bit is in, read it, OR in the new bit, then write
266 * back the new value. The register is determined by the
267 * upper bit of the hash value and the bit within that
268 * register are determined by the lower 5 bits of the value.
269 */
270 hash_reg = (hash_value >> 31) & 0x1;
271 hash_bit = (hash_value >> 26) & 0x1F;
272
273 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
274
275 mta |= (1 << hash_bit);
276
277 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
278 }
279
280 /*
281 * Reads the value from a PHY register
282 * hw - Struct containing variables accessed by shared code
283 * reg_addr - address of the PHY register to read
284 */
atl1c_read_phy_reg(struct atl1c_hw * hw,u16 reg_addr,u16 * phy_data)285 int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
286 {
287 u32 val;
288 int i;
289
290 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
291 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
292 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
293
294 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
295
296 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
297 udelay(2);
298 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
299 if (!(val & (MDIO_START | MDIO_BUSY)))
300 break;
301 }
302 if (!(val & (MDIO_START | MDIO_BUSY))) {
303 *phy_data = (u16)val;
304 return 0;
305 }
306
307 return -1;
308 }
309
310 /*
311 * Writes a value to a PHY register
312 * hw - Struct containing variables accessed by shared code
313 * reg_addr - address of the PHY register to write
314 * data - data to write to the PHY
315 */
atl1c_write_phy_reg(struct atl1c_hw * hw,u32 reg_addr,u16 phy_data)316 int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
317 {
318 int i;
319 u32 val;
320
321 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
322 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
323 MDIO_SUP_PREAMBLE | MDIO_START |
324 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
325
326 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
327
328 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
329 udelay(2);
330 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
331 if (!(val & (MDIO_START | MDIO_BUSY)))
332 break;
333 }
334
335 if (!(val & (MDIO_START | MDIO_BUSY)))
336 return 0;
337
338 return -1;
339 }
340
341 /*
342 * Configures PHY autoneg and flow control advertisement settings
343 *
344 * hw - Struct containing variables accessed by shared code
345 */
atl1c_phy_setup_adv(struct atl1c_hw * hw)346 static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
347 {
348 u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_ALL;
349 u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP &
350 ~GIGA_CR_1000T_SPEED_MASK;
351
352 if (hw->autoneg_advertised & ADVERTISED_10baseT_Half)
353 mii_adv_data |= ADVERTISE_10HALF;
354 if (hw->autoneg_advertised & ADVERTISED_10baseT_Full)
355 mii_adv_data |= ADVERTISE_10FULL;
356 if (hw->autoneg_advertised & ADVERTISED_100baseT_Half)
357 mii_adv_data |= ADVERTISE_100HALF;
358 if (hw->autoneg_advertised & ADVERTISED_100baseT_Full)
359 mii_adv_data |= ADVERTISE_100FULL;
360
361 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
362 mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
363 ADVERTISE_100HALF | ADVERTISE_100FULL;
364
365 if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M) {
366 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
367 mii_giga_ctrl_data |= ADVERTISE_1000HALF;
368 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
369 mii_giga_ctrl_data |= ADVERTISE_1000FULL;
370 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
371 mii_giga_ctrl_data |= ADVERTISE_1000HALF |
372 ADVERTISE_1000FULL;
373 }
374
375 if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 ||
376 atl1c_write_phy_reg(hw, MII_CTRL1000, mii_giga_ctrl_data) != 0)
377 return -1;
378 return 0;
379 }
380
atl1c_phy_disable(struct atl1c_hw * hw)381 void atl1c_phy_disable(struct atl1c_hw *hw)
382 {
383 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
384 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
385 }
386
atl1c_phy_magic_data(struct atl1c_hw * hw)387 static void atl1c_phy_magic_data(struct atl1c_hw *hw)
388 {
389 u16 data;
390
391 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
392 ((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
393 ANA_INTERVAL_SEL_TIMER_SHIFT);
394
395 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
396 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
397
398 data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
399 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
400 ANA_SERDES_EN_LCKDT;
401
402 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
403 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
404
405 data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
406 ((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
407 ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
408 ANA_BP_SMALL_BW;
409
410 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
411 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
412
413 data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
414 ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
415 ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
416 ANA_IECHO_ADJ_0_SHIFT);
417
418 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
419 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
420
421 data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
422 ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
423 ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
424
425 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
426 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
427
428 if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
429 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
430 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
431 return;
432 data &= ~ANA_TOP_PS_EN;
433 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
434
435 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
436 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
437 return;
438 data &= ~ANA_PS_HIB_EN;
439 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
440 }
441 }
442
atl1c_phy_reset(struct atl1c_hw * hw)443 int atl1c_phy_reset(struct atl1c_hw *hw)
444 {
445 struct atl1c_adapter *adapter = hw->adapter;
446 struct pci_dev *pdev = adapter->pdev;
447 u16 phy_data;
448 u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
449 u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
450 int err;
451
452 if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
453 phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
454
455 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
456 AT_WRITE_FLUSH(hw);
457 msleep(40);
458 phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
459 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
460 AT_WRITE_FLUSH(hw);
461 msleep(10);
462
463 if (hw->nic_type == athr_l2c_b) {
464 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x0A);
465 atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
466 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xDFFF);
467 }
468
469 if (hw->nic_type == athr_l2c_b ||
470 hw->nic_type == athr_l2c_b2 ||
471 hw->nic_type == athr_l1d ||
472 hw->nic_type == athr_l1d_2) {
473 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
474 atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
475 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xFFF7);
476 msleep(20);
477 }
478 if (hw->nic_type == athr_l1d) {
479 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
480 atl1c_write_phy_reg(hw, MII_DBG_DATA, 0x929D);
481 }
482 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b2
483 || hw->nic_type == athr_l2c) {
484 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
485 atl1c_write_phy_reg(hw, MII_DBG_DATA, 0xB6DD);
486 }
487 err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
488 if (err) {
489 if (netif_msg_hw(adapter))
490 dev_err(&pdev->dev,
491 "Error enable PHY linkChange Interrupt\n");
492 return err;
493 }
494 if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
495 atl1c_phy_magic_data(hw);
496 return 0;
497 }
498
atl1c_phy_init(struct atl1c_hw * hw)499 int atl1c_phy_init(struct atl1c_hw *hw)
500 {
501 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
502 struct pci_dev *pdev = adapter->pdev;
503 int ret_val;
504 u16 mii_bmcr_data = BMCR_RESET;
505
506 if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id1) != 0) ||
507 (atl1c_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id2) != 0)) {
508 dev_err(&pdev->dev, "Error get phy ID\n");
509 return -1;
510 }
511 switch (hw->media_type) {
512 case MEDIA_TYPE_AUTO_SENSOR:
513 ret_val = atl1c_phy_setup_adv(hw);
514 if (ret_val) {
515 if (netif_msg_link(adapter))
516 dev_err(&pdev->dev,
517 "Error Setting up Auto-Negotiation\n");
518 return ret_val;
519 }
520 mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART;
521 break;
522 case MEDIA_TYPE_100M_FULL:
523 mii_bmcr_data |= BMCR_SPEED100 | BMCR_FULLDPLX;
524 break;
525 case MEDIA_TYPE_100M_HALF:
526 mii_bmcr_data |= BMCR_SPEED100;
527 break;
528 case MEDIA_TYPE_10M_FULL:
529 mii_bmcr_data |= BMCR_FULLDPLX;
530 break;
531 case MEDIA_TYPE_10M_HALF:
532 break;
533 default:
534 if (netif_msg_link(adapter))
535 dev_err(&pdev->dev, "Wrong Media type %d\n",
536 hw->media_type);
537 return -1;
538 break;
539 }
540
541 ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
542 if (ret_val)
543 return ret_val;
544 hw->phy_configured = true;
545
546 return 0;
547 }
548
549 /*
550 * Detects the current speed and duplex settings of the hardware.
551 *
552 * hw - Struct containing variables accessed by shared code
553 * speed - Speed of the connection
554 * duplex - Duplex setting of the connection
555 */
atl1c_get_speed_and_duplex(struct atl1c_hw * hw,u16 * speed,u16 * duplex)556 int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
557 {
558 int err;
559 u16 phy_data;
560
561 /* Read PHY Specific Status Register (17) */
562 err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
563 if (err)
564 return err;
565
566 if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED))
567 return -1;
568
569 switch (phy_data & GIGA_PSSR_SPEED) {
570 case GIGA_PSSR_1000MBS:
571 *speed = SPEED_1000;
572 break;
573 case GIGA_PSSR_100MBS:
574 *speed = SPEED_100;
575 break;
576 case GIGA_PSSR_10MBS:
577 *speed = SPEED_10;
578 break;
579 default:
580 return -1;
581 break;
582 }
583
584 if (phy_data & GIGA_PSSR_DPLX)
585 *duplex = FULL_DUPLEX;
586 else
587 *duplex = HALF_DUPLEX;
588
589 return 0;
590 }
591
atl1c_phy_power_saving(struct atl1c_hw * hw)592 int atl1c_phy_power_saving(struct atl1c_hw *hw)
593 {
594 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
595 struct pci_dev *pdev = adapter->pdev;
596 int ret = 0;
597 u16 autoneg_advertised = ADVERTISED_10baseT_Half;
598 u16 save_autoneg_advertised;
599 u16 phy_data;
600 u16 mii_lpa_data;
601 u16 speed = SPEED_0;
602 u16 duplex = FULL_DUPLEX;
603 int i;
604
605 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
606 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
607 if (phy_data & BMSR_LSTATUS) {
608 atl1c_read_phy_reg(hw, MII_LPA, &mii_lpa_data);
609 if (mii_lpa_data & LPA_10FULL)
610 autoneg_advertised = ADVERTISED_10baseT_Full;
611 else if (mii_lpa_data & LPA_10HALF)
612 autoneg_advertised = ADVERTISED_10baseT_Half;
613 else if (mii_lpa_data & LPA_100HALF)
614 autoneg_advertised = ADVERTISED_100baseT_Half;
615 else if (mii_lpa_data & LPA_100FULL)
616 autoneg_advertised = ADVERTISED_100baseT_Full;
617
618 save_autoneg_advertised = hw->autoneg_advertised;
619 hw->phy_configured = false;
620 hw->autoneg_advertised = autoneg_advertised;
621 if (atl1c_restart_autoneg(hw) != 0) {
622 dev_dbg(&pdev->dev, "phy autoneg failed\n");
623 ret = -1;
624 }
625 hw->autoneg_advertised = save_autoneg_advertised;
626
627 if (mii_lpa_data) {
628 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
629 mdelay(100);
630 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
631 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
632 if (phy_data & BMSR_LSTATUS) {
633 if (atl1c_get_speed_and_duplex(hw, &speed,
634 &duplex) != 0)
635 dev_dbg(&pdev->dev,
636 "get speed and duplex failed\n");
637 break;
638 }
639 }
640 }
641 } else {
642 speed = SPEED_10;
643 duplex = HALF_DUPLEX;
644 }
645 adapter->link_speed = speed;
646 adapter->link_duplex = duplex;
647
648 return ret;
649 }
650
atl1c_restart_autoneg(struct atl1c_hw * hw)651 int atl1c_restart_autoneg(struct atl1c_hw *hw)
652 {
653 int err = 0;
654 u16 mii_bmcr_data = BMCR_RESET;
655
656 err = atl1c_phy_setup_adv(hw);
657 if (err)
658 return err;
659 mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART;
660
661 return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
662 }
663