1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20 
21 #define BITS_PER_BYTE           8
22 #define OFDM_PLCP_BITS          22
23 #define HT_RC_2_STREAMS(_rc)    ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF                   8
25 #define L_LTF                   8
26 #define L_SIG                   4
27 #define HT_SIG                  8
28 #define HT_STF                  4
29 #define HT_LTF(_ns)             (4 * (_ns))
30 #define SYMBOL_TIME(_ns)        ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)  /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t)         ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t)  (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 
37 
38 static u16 bits_per_symbol[][2] = {
39 	/* 20MHz 40MHz */
40 	{    26,   54 },     /*  0: BPSK */
41 	{    52,  108 },     /*  1: QPSK 1/2 */
42 	{    78,  162 },     /*  2: QPSK 3/4 */
43 	{   104,  216 },     /*  3: 16-QAM 1/2 */
44 	{   156,  324 },     /*  4: 16-QAM 3/4 */
45 	{   208,  432 },     /*  5: 64-QAM 2/3 */
46 	{   234,  486 },     /*  6: 64-QAM 3/4 */
47 	{   260,  540 },     /*  7: 64-QAM 5/6 */
48 };
49 
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 			       struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 			    int tx_flags, struct ath_txq *txq,
54 			    struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 				struct ath_txq *txq, struct list_head *bf_q,
57 				struct ieee80211_sta *sta,
58 				struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 			     struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 			     struct ath_tx_status *ts, int nframes, int nbad,
63 			     int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 			      struct ath_buf *bf);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 					   struct ath_txq *txq,
68 					   struct ath_atx_tid *tid,
69 					   struct sk_buff *skb);
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 			  struct ath_tx_control *txctl);
72 
73 enum {
74 	MCS_HT20,
75 	MCS_HT20_SGI,
76 	MCS_HT40,
77 	MCS_HT40_SGI,
78 };
79 
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
83 
ath_tx_status(struct ieee80211_hw * hw,struct sk_buff * skb)84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
85 {
86 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 	struct ieee80211_sta *sta = info->status.status_driver_data[0];
88 
89 	if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 			   IEEE80211_TX_STATUS_EOSP)) {
91 		ieee80211_tx_status(hw, skb);
92 		return;
93 	}
94 
95 	if (sta)
96 		ieee80211_tx_status_noskb(hw, sta, info);
97 
98 	dev_kfree_skb(skb);
99 }
100 
ath_txq_unlock_complete(struct ath_softc * sc,struct ath_txq * txq)101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 	__releases(&txq->axq_lock)
103 {
104 	struct ieee80211_hw *hw = sc->hw;
105 	struct sk_buff_head q;
106 	struct sk_buff *skb;
107 
108 	__skb_queue_head_init(&q);
109 	skb_queue_splice_init(&txq->complete_q, &q);
110 	spin_unlock_bh(&txq->axq_lock);
111 
112 	while ((skb = __skb_dequeue(&q)))
113 		ath_tx_status(hw, skb);
114 }
115 
ath_tx_queue_tid(struct ath_softc * sc,struct ath_atx_tid * tid)116 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
117 {
118 	struct ieee80211_txq *queue =
119 		container_of((void *)tid, struct ieee80211_txq, drv_priv);
120 
121 	ieee80211_schedule_txq(sc->hw, queue);
122 }
123 
ath9k_wake_tx_queue(struct ieee80211_hw * hw,struct ieee80211_txq * queue)124 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
125 {
126 	struct ath_softc *sc = hw->priv;
127 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
128 	struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
129 	struct ath_txq *txq = tid->txq;
130 
131 	ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
132 		queue->sta ? queue->sta->addr : queue->vif->addr,
133 		tid->tidno);
134 
135 	ath_txq_lock(sc, txq);
136 	ath_txq_schedule(sc, txq);
137 	ath_txq_unlock(sc, txq);
138 }
139 
get_frame_info(struct sk_buff * skb)140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
141 {
142 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 	BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 		     sizeof(tx_info->status.status_driver_data));
145 	return (struct ath_frame_info *) &tx_info->status.status_driver_data[0];
146 }
147 
ath_send_bar(struct ath_atx_tid * tid,u16 seqno)148 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
149 {
150 	if (!tid->an->sta)
151 		return;
152 
153 	ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
154 			   seqno << IEEE80211_SEQ_SEQ_SHIFT);
155 }
156 
ath_merge_ratetbl(struct ieee80211_sta * sta,struct ath_buf * bf,struct ieee80211_tx_info * tx_info)157 static bool ath_merge_ratetbl(struct ieee80211_sta *sta, struct ath_buf *bf,
158 			      struct ieee80211_tx_info *tx_info)
159 {
160 	struct ieee80211_sta_rates *ratetbl;
161 	u8 i;
162 
163 	if (!sta)
164 		return false;
165 
166 	ratetbl = rcu_dereference(sta->rates);
167 	if (!ratetbl)
168 		return false;
169 
170 	if (tx_info->control.rates[0].idx < 0 ||
171 	    tx_info->control.rates[0].count == 0)
172 	{
173 		i = 0;
174 	} else {
175 		bf->rates[0] = tx_info->control.rates[0];
176 		i = 1;
177 	}
178 
179 	for ( ; i < IEEE80211_TX_MAX_RATES; i++) {
180 		bf->rates[i].idx = ratetbl->rate[i].idx;
181 		bf->rates[i].flags = ratetbl->rate[i].flags;
182 		if (tx_info->control.use_rts)
183 			bf->rates[i].count = ratetbl->rate[i].count_rts;
184 		else if (tx_info->control.use_cts_prot)
185 			bf->rates[i].count = ratetbl->rate[i].count_cts;
186 		else
187 			bf->rates[i].count = ratetbl->rate[i].count;
188 	}
189 
190 	return true;
191 }
192 
ath_set_rates(struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ath_buf * bf)193 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
194 			  struct ath_buf *bf)
195 {
196 	struct ieee80211_tx_info *tx_info;
197 
198 	tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
199 
200 	if (!ath_merge_ratetbl(sta, bf, tx_info))
201 		ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
202 				       ARRAY_SIZE(bf->rates));
203 }
204 
ath_txq_skb_done(struct ath_softc * sc,struct ath_txq * txq,struct sk_buff * skb)205 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
206 			     struct sk_buff *skb)
207 {
208 	struct ath_frame_info *fi = get_frame_info(skb);
209 	int q = fi->txq;
210 
211 	if (q < 0)
212 		return;
213 
214 	txq = sc->tx.txq_map[q];
215 	if (WARN_ON(--txq->pending_frames < 0))
216 		txq->pending_frames = 0;
217 
218 }
219 
220 static struct ath_atx_tid *
ath_get_skb_tid(struct ath_softc * sc,struct ath_node * an,struct sk_buff * skb)221 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
222 {
223 	u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
224 	return ATH_AN_2_TID(an, tidno);
225 }
226 
227 static int
ath_tid_pull(struct ath_atx_tid * tid,struct sk_buff ** skbuf)228 ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf)
229 {
230 	struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
231 	struct ath_softc *sc = tid->an->sc;
232 	struct ieee80211_hw *hw = sc->hw;
233 	struct ath_tx_control txctl = {
234 		.txq = tid->txq,
235 		.sta = tid->an->sta,
236 	};
237 	struct sk_buff *skb;
238 	struct ath_frame_info *fi;
239 	int q, ret;
240 
241 	skb = ieee80211_tx_dequeue(hw, txq);
242 	if (!skb)
243 		return -ENOENT;
244 
245 	ret = ath_tx_prepare(hw, skb, &txctl);
246 	if (ret) {
247 		ieee80211_free_txskb(hw, skb);
248 		return ret;
249 	}
250 
251 	q = skb_get_queue_mapping(skb);
252 	if (tid->txq == sc->tx.txq_map[q]) {
253 		fi = get_frame_info(skb);
254 		fi->txq = q;
255 		++tid->txq->pending_frames;
256 	}
257 
258 	*skbuf = skb;
259 	return 0;
260 }
261 
ath_tid_dequeue(struct ath_atx_tid * tid,struct sk_buff ** skb)262 static int ath_tid_dequeue(struct ath_atx_tid *tid,
263 			   struct sk_buff **skb)
264 {
265 	int ret = 0;
266 	*skb = __skb_dequeue(&tid->retry_q);
267 	if (!*skb)
268 		ret = ath_tid_pull(tid, skb);
269 
270 	return ret;
271 }
272 
ath_tx_flush_tid(struct ath_softc * sc,struct ath_atx_tid * tid)273 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
274 {
275 	struct ath_txq *txq = tid->txq;
276 	struct sk_buff *skb;
277 	struct ath_buf *bf;
278 	struct list_head bf_head;
279 	struct ath_tx_status ts;
280 	struct ath_frame_info *fi;
281 	bool sendbar = false;
282 
283 	INIT_LIST_HEAD(&bf_head);
284 
285 	memset(&ts, 0, sizeof(ts));
286 
287 	while ((skb = __skb_dequeue(&tid->retry_q))) {
288 		fi = get_frame_info(skb);
289 		bf = fi->bf;
290 		if (!bf) {
291 			ath_txq_skb_done(sc, txq, skb);
292 			ieee80211_free_txskb(sc->hw, skb);
293 			continue;
294 		}
295 
296 		if (fi->baw_tracked) {
297 			ath_tx_update_baw(sc, tid, bf);
298 			sendbar = true;
299 		}
300 
301 		list_add_tail(&bf->list, &bf_head);
302 		ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
303 	}
304 
305 	if (sendbar) {
306 		ath_txq_unlock(sc, txq);
307 		ath_send_bar(tid, tid->seq_start);
308 		ath_txq_lock(sc, txq);
309 	}
310 }
311 
ath_tx_update_baw(struct ath_softc * sc,struct ath_atx_tid * tid,struct ath_buf * bf)312 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
313 			      struct ath_buf *bf)
314 {
315 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
316 	u16 seqno = bf->bf_state.seqno;
317 	int index, cindex;
318 
319 	if (!fi->baw_tracked)
320 		return;
321 
322 	index  = ATH_BA_INDEX(tid->seq_start, seqno);
323 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
324 
325 	__clear_bit(cindex, tid->tx_buf);
326 
327 	while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
328 		INCR(tid->seq_start, IEEE80211_SEQ_MAX);
329 		INCR(tid->baw_head, ATH_TID_MAX_BUFS);
330 		if (tid->bar_index >= 0)
331 			tid->bar_index--;
332 	}
333 }
334 
ath_tx_addto_baw(struct ath_softc * sc,struct ath_atx_tid * tid,struct ath_buf * bf)335 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
336 			     struct ath_buf *bf)
337 {
338 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
339 	u16 seqno = bf->bf_state.seqno;
340 	int index, cindex;
341 
342 	if (fi->baw_tracked)
343 		return;
344 
345 	index  = ATH_BA_INDEX(tid->seq_start, seqno);
346 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
347 	__set_bit(cindex, tid->tx_buf);
348 	fi->baw_tracked = 1;
349 
350 	if (index >= ((tid->baw_tail - tid->baw_head) &
351 		(ATH_TID_MAX_BUFS - 1))) {
352 		tid->baw_tail = cindex;
353 		INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
354 	}
355 }
356 
ath_tid_drain(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid)357 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
358 			  struct ath_atx_tid *tid)
359 
360 {
361 	struct sk_buff *skb;
362 	struct ath_buf *bf;
363 	struct list_head bf_head;
364 	struct ath_tx_status ts;
365 	struct ath_frame_info *fi;
366 	int ret;
367 
368 	memset(&ts, 0, sizeof(ts));
369 	INIT_LIST_HEAD(&bf_head);
370 
371 	while ((ret = ath_tid_dequeue(tid, &skb)) == 0) {
372 		fi = get_frame_info(skb);
373 		bf = fi->bf;
374 
375 		if (!bf) {
376 			ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
377 			continue;
378 		}
379 
380 		list_add_tail(&bf->list, &bf_head);
381 		ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
382 	}
383 }
384 
ath_tx_set_retry(struct ath_softc * sc,struct ath_txq * txq,struct sk_buff * skb,int count)385 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
386 			     struct sk_buff *skb, int count)
387 {
388 	struct ath_frame_info *fi = get_frame_info(skb);
389 	struct ath_buf *bf = fi->bf;
390 	struct ieee80211_hdr *hdr;
391 	int prev = fi->retries;
392 
393 	TX_STAT_INC(sc, txq->axq_qnum, a_retries);
394 	fi->retries += count;
395 
396 	if (prev > 0)
397 		return;
398 
399 	hdr = (struct ieee80211_hdr *)skb->data;
400 	hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
401 	dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
402 		sizeof(*hdr), DMA_TO_DEVICE);
403 }
404 
ath_tx_get_buffer(struct ath_softc * sc)405 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
406 {
407 	struct ath_buf *bf = NULL;
408 
409 	spin_lock_bh(&sc->tx.txbuflock);
410 
411 	if (unlikely(list_empty(&sc->tx.txbuf))) {
412 		spin_unlock_bh(&sc->tx.txbuflock);
413 		return NULL;
414 	}
415 
416 	bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
417 	list_del(&bf->list);
418 
419 	spin_unlock_bh(&sc->tx.txbuflock);
420 
421 	return bf;
422 }
423 
ath_tx_return_buffer(struct ath_softc * sc,struct ath_buf * bf)424 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
425 {
426 	spin_lock_bh(&sc->tx.txbuflock);
427 	list_add_tail(&bf->list, &sc->tx.txbuf);
428 	spin_unlock_bh(&sc->tx.txbuflock);
429 }
430 
ath_clone_txbuf(struct ath_softc * sc,struct ath_buf * bf)431 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
432 {
433 	struct ath_buf *tbf;
434 
435 	tbf = ath_tx_get_buffer(sc);
436 	if (WARN_ON(!tbf))
437 		return NULL;
438 
439 	ATH_TXBUF_RESET(tbf);
440 
441 	tbf->bf_mpdu = bf->bf_mpdu;
442 	tbf->bf_buf_addr = bf->bf_buf_addr;
443 	memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
444 	tbf->bf_state = bf->bf_state;
445 	tbf->bf_state.stale = false;
446 
447 	return tbf;
448 }
449 
ath_tx_count_frames(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,int txok,int * nframes,int * nbad)450 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
451 			        struct ath_tx_status *ts, int txok,
452 			        int *nframes, int *nbad)
453 {
454 	u16 seq_st = 0;
455 	u32 ba[WME_BA_BMP_SIZE >> 5];
456 	int ba_index;
457 	int isaggr = 0;
458 
459 	*nbad = 0;
460 	*nframes = 0;
461 
462 	isaggr = bf_isaggr(bf);
463 	if (isaggr) {
464 		seq_st = ts->ts_seqnum;
465 		memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
466 	}
467 
468 	while (bf) {
469 		ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
470 
471 		(*nframes)++;
472 		if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
473 			(*nbad)++;
474 
475 		bf = bf->bf_next;
476 	}
477 }
478 
479 
ath_tx_complete_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_buf * bf,struct list_head * bf_q,struct ieee80211_sta * sta,struct ath_atx_tid * tid,struct ath_tx_status * ts,int txok)480 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
481 				 struct ath_buf *bf, struct list_head *bf_q,
482 				 struct ieee80211_sta *sta,
483 				 struct ath_atx_tid *tid,
484 				 struct ath_tx_status *ts, int txok)
485 {
486 	struct ath_node *an = NULL;
487 	struct sk_buff *skb;
488 	struct ieee80211_tx_info *tx_info;
489 	struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
490 	struct list_head bf_head;
491 	struct sk_buff_head bf_pending;
492 	u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
493 	u32 ba[WME_BA_BMP_SIZE >> 5];
494 	int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
495 	bool rc_update = true, isba;
496 	struct ieee80211_tx_rate rates[4];
497 	struct ath_frame_info *fi;
498 	int nframes;
499 	bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
500 	int i, retries;
501 	int bar_index = -1;
502 
503 	skb = bf->bf_mpdu;
504 	tx_info = IEEE80211_SKB_CB(skb);
505 
506 	memcpy(rates, bf->rates, sizeof(rates));
507 
508 	retries = ts->ts_longretry + 1;
509 	for (i = 0; i < ts->ts_rateindex; i++)
510 		retries += rates[i].count;
511 
512 	if (!sta) {
513 		INIT_LIST_HEAD(&bf_head);
514 		while (bf) {
515 			bf_next = bf->bf_next;
516 
517 			if (!bf->bf_state.stale || bf_next != NULL)
518 				list_move_tail(&bf->list, &bf_head);
519 
520 			ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
521 
522 			bf = bf_next;
523 		}
524 		return;
525 	}
526 
527 	an = (struct ath_node *)sta->drv_priv;
528 	seq_first = tid->seq_start;
529 	isba = ts->ts_flags & ATH9K_TX_BA;
530 
531 	/*
532 	 * The hardware occasionally sends a tx status for the wrong TID.
533 	 * In this case, the BA status cannot be considered valid and all
534 	 * subframes need to be retransmitted
535 	 *
536 	 * Only BlockAcks have a TID and therefore normal Acks cannot be
537 	 * checked
538 	 */
539 	if (isba && tid->tidno != ts->tid)
540 		txok = false;
541 
542 	isaggr = bf_isaggr(bf);
543 	memset(ba, 0, WME_BA_BMP_SIZE >> 3);
544 
545 	if (isaggr && txok) {
546 		if (ts->ts_flags & ATH9K_TX_BA) {
547 			seq_st = ts->ts_seqnum;
548 			memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
549 		} else {
550 			/*
551 			 * AR5416 can become deaf/mute when BA
552 			 * issue happens. Chip needs to be reset.
553 			 * But AP code may have sychronization issues
554 			 * when perform internal reset in this routine.
555 			 * Only enable reset in STA mode for now.
556 			 */
557 			if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
558 				needreset = 1;
559 		}
560 	}
561 
562 	__skb_queue_head_init(&bf_pending);
563 
564 	ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
565 	while (bf) {
566 		u16 seqno = bf->bf_state.seqno;
567 
568 		txfail = txpending = sendbar = 0;
569 		bf_next = bf->bf_next;
570 
571 		skb = bf->bf_mpdu;
572 		tx_info = IEEE80211_SKB_CB(skb);
573 		fi = get_frame_info(skb);
574 
575 		if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
576 		    !tid->active) {
577 			/*
578 			 * Outside of the current BlockAck window,
579 			 * maybe part of a previous session
580 			 */
581 			txfail = 1;
582 		} else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
583 			/* transmit completion, subframe is
584 			 * acked by block ack */
585 			acked_cnt++;
586 		} else if (!isaggr && txok) {
587 			/* transmit completion */
588 			acked_cnt++;
589 		} else if (flush) {
590 			txpending = 1;
591 		} else if (fi->retries < ATH_MAX_SW_RETRIES) {
592 			if (txok || !an->sleeping)
593 				ath_tx_set_retry(sc, txq, bf->bf_mpdu,
594 						 retries);
595 
596 			txpending = 1;
597 		} else {
598 			txfail = 1;
599 			txfail_cnt++;
600 			bar_index = max_t(int, bar_index,
601 				ATH_BA_INDEX(seq_first, seqno));
602 		}
603 
604 		/*
605 		 * Make sure the last desc is reclaimed if it
606 		 * not a holding desc.
607 		 */
608 		INIT_LIST_HEAD(&bf_head);
609 		if (bf_next != NULL || !bf_last->bf_state.stale)
610 			list_move_tail(&bf->list, &bf_head);
611 
612 		if (!txpending) {
613 			/*
614 			 * complete the acked-ones/xretried ones; update
615 			 * block-ack window
616 			 */
617 			ath_tx_update_baw(sc, tid, bf);
618 
619 			if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
620 				memcpy(tx_info->control.rates, rates, sizeof(rates));
621 				ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
622 				rc_update = false;
623 				if (bf == bf->bf_lastbf)
624 					ath_dynack_sample_tx_ts(sc->sc_ah,
625 								bf->bf_mpdu,
626 								ts, sta);
627 			}
628 
629 			ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
630 				!txfail);
631 		} else {
632 			if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
633 				tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
634 				ieee80211_sta_eosp(sta);
635 			}
636 			/* retry the un-acked ones */
637 			if (bf->bf_next == NULL && bf_last->bf_state.stale) {
638 				struct ath_buf *tbf;
639 
640 				tbf = ath_clone_txbuf(sc, bf_last);
641 				/*
642 				 * Update tx baw and complete the
643 				 * frame with failed status if we
644 				 * run out of tx buf.
645 				 */
646 				if (!tbf) {
647 					ath_tx_update_baw(sc, tid, bf);
648 
649 					ath_tx_complete_buf(sc, bf, txq,
650 							    &bf_head, NULL, ts,
651 							    0);
652 					bar_index = max_t(int, bar_index,
653 						ATH_BA_INDEX(seq_first, seqno));
654 					break;
655 				}
656 
657 				fi->bf = tbf;
658 			}
659 
660 			/*
661 			 * Put this buffer to the temporary pending
662 			 * queue to retain ordering
663 			 */
664 			__skb_queue_tail(&bf_pending, skb);
665 		}
666 
667 		bf = bf_next;
668 	}
669 
670 	/* prepend un-acked frames to the beginning of the pending frame queue */
671 	if (!skb_queue_empty(&bf_pending)) {
672 		if (an->sleeping)
673 			ieee80211_sta_set_buffered(sta, tid->tidno, true);
674 
675 		skb_queue_splice_tail(&bf_pending, &tid->retry_q);
676 		if (!an->sleeping) {
677 			ath_tx_queue_tid(sc, tid);
678 			if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
679 				tid->clear_ps_filter = true;
680 		}
681 	}
682 
683 	if (bar_index >= 0) {
684 		u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
685 
686 		if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
687 			tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
688 
689 		ath_txq_unlock(sc, txq);
690 		ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
691 		ath_txq_lock(sc, txq);
692 	}
693 
694 	if (needreset)
695 		ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
696 }
697 
bf_is_ampdu_not_probing(struct ath_buf * bf)698 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
699 {
700     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
701     return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
702 }
703 
ath_tx_count_airtime(struct ath_softc * sc,struct ieee80211_sta * sta,struct ath_buf * bf,struct ath_tx_status * ts,u8 tid)704 static void ath_tx_count_airtime(struct ath_softc *sc,
705 				 struct ieee80211_sta *sta,
706 				 struct ath_buf *bf,
707 				 struct ath_tx_status *ts,
708 				 u8 tid)
709 {
710 	u32 airtime = 0;
711 	int i;
712 
713 	airtime += ts->duration * (ts->ts_longretry + 1);
714 	for(i = 0; i < ts->ts_rateindex; i++) {
715 		int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
716 		airtime += rate_dur * bf->rates[i].count;
717 	}
718 
719 	ieee80211_sta_register_airtime(sta, tid, airtime, 0);
720 }
721 
ath_tx_process_buffer(struct ath_softc * sc,struct ath_txq * txq,struct ath_tx_status * ts,struct ath_buf * bf,struct list_head * bf_head)722 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
723 				  struct ath_tx_status *ts, struct ath_buf *bf,
724 				  struct list_head *bf_head)
725 {
726 	struct ieee80211_hw *hw = sc->hw;
727 	struct ieee80211_tx_info *info;
728 	struct ieee80211_sta *sta;
729 	struct ieee80211_hdr *hdr;
730 	struct ath_atx_tid *tid = NULL;
731 	bool txok, flush;
732 
733 	txok = !(ts->ts_status & ATH9K_TXERR_MASK);
734 	flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
735 	txq->axq_tx_inprogress = false;
736 
737 	txq->axq_depth--;
738 	if (bf_is_ampdu_not_probing(bf))
739 		txq->axq_ampdu_depth--;
740 
741 	ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
742 					     ts->ts_rateindex);
743 
744 	hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
745 	sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
746 	if (sta) {
747 		struct ath_node *an = (struct ath_node *)sta->drv_priv;
748 		tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
749 		ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno);
750 		if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
751 			tid->clear_ps_filter = true;
752 	}
753 
754 	if (!bf_isampdu(bf)) {
755 		if (!flush) {
756 			info = IEEE80211_SKB_CB(bf->bf_mpdu);
757 			memcpy(info->control.rates, bf->rates,
758 			       sizeof(info->control.rates));
759 			ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
760 			ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
761 						sta);
762 		}
763 		ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
764 	} else
765 		ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
766 
767 	if (!flush)
768 		ath_txq_schedule(sc, txq);
769 }
770 
ath_lookup_legacy(struct ath_buf * bf)771 static bool ath_lookup_legacy(struct ath_buf *bf)
772 {
773 	struct sk_buff *skb;
774 	struct ieee80211_tx_info *tx_info;
775 	struct ieee80211_tx_rate *rates;
776 	int i;
777 
778 	skb = bf->bf_mpdu;
779 	tx_info = IEEE80211_SKB_CB(skb);
780 	rates = tx_info->control.rates;
781 
782 	for (i = 0; i < 4; i++) {
783 		if (!rates[i].count || rates[i].idx < 0)
784 			break;
785 
786 		if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
787 			return true;
788 	}
789 
790 	return false;
791 }
792 
ath_lookup_rate(struct ath_softc * sc,struct ath_buf * bf,struct ath_atx_tid * tid)793 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
794 			   struct ath_atx_tid *tid)
795 {
796 	struct sk_buff *skb;
797 	struct ieee80211_tx_info *tx_info;
798 	struct ieee80211_tx_rate *rates;
799 	u32 max_4ms_framelen, frmlen;
800 	u16 aggr_limit, bt_aggr_limit, legacy = 0;
801 	int q = tid->txq->mac80211_qnum;
802 	int i;
803 
804 	skb = bf->bf_mpdu;
805 	tx_info = IEEE80211_SKB_CB(skb);
806 	rates = bf->rates;
807 
808 	/*
809 	 * Find the lowest frame length among the rate series that will have a
810 	 * 4ms (or TXOP limited) transmit duration.
811 	 */
812 	max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
813 
814 	for (i = 0; i < 4; i++) {
815 		int modeidx;
816 
817 		if (!rates[i].count)
818 			continue;
819 
820 		if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
821 			legacy = 1;
822 			break;
823 		}
824 
825 		if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
826 			modeidx = MCS_HT40;
827 		else
828 			modeidx = MCS_HT20;
829 
830 		if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
831 			modeidx++;
832 
833 		frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
834 		max_4ms_framelen = min(max_4ms_framelen, frmlen);
835 	}
836 
837 	/*
838 	 * limit aggregate size by the minimum rate if rate selected is
839 	 * not a probe rate, if rate selected is a probe rate then
840 	 * avoid aggregation of this packet.
841 	 */
842 	if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
843 		return 0;
844 
845 	aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
846 
847 	/*
848 	 * Override the default aggregation limit for BTCOEX.
849 	 */
850 	bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
851 	if (bt_aggr_limit)
852 		aggr_limit = bt_aggr_limit;
853 
854 	if (tid->an->maxampdu)
855 		aggr_limit = min(aggr_limit, tid->an->maxampdu);
856 
857 	return aggr_limit;
858 }
859 
860 /*
861  * Returns the number of delimiters to be added to
862  * meet the minimum required mpdudensity.
863  */
ath_compute_num_delims(struct ath_softc * sc,struct ath_atx_tid * tid,struct ath_buf * bf,u16 frmlen,bool first_subfrm)864 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
865 				  struct ath_buf *bf, u16 frmlen,
866 				  bool first_subfrm)
867 {
868 #define FIRST_DESC_NDELIMS 60
869 	u32 nsymbits, nsymbols;
870 	u16 minlen;
871 	u8 flags, rix;
872 	int width, streams, half_gi, ndelim, mindelim;
873 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
874 
875 	/* Select standard number of delimiters based on frame length alone */
876 	ndelim = ATH_AGGR_GET_NDELIM(frmlen);
877 
878 	/*
879 	 * If encryption enabled, hardware requires some more padding between
880 	 * subframes.
881 	 * TODO - this could be improved to be dependent on the rate.
882 	 *      The hardware can keep up at lower rates, but not higher rates
883 	 */
884 	if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
885 	    !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
886 		ndelim += ATH_AGGR_ENCRYPTDELIM;
887 
888 	/*
889 	 * Add delimiter when using RTS/CTS with aggregation
890 	 * and non enterprise AR9003 card
891 	 */
892 	if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
893 	    (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
894 		ndelim = max(ndelim, FIRST_DESC_NDELIMS);
895 
896 	/*
897 	 * Convert desired mpdu density from microeconds to bytes based
898 	 * on highest rate in rate series (i.e. first rate) to determine
899 	 * required minimum length for subframe. Take into account
900 	 * whether high rate is 20 or 40Mhz and half or full GI.
901 	 *
902 	 * If there is no mpdu density restriction, no further calculation
903 	 * is needed.
904 	 */
905 
906 	if (tid->an->mpdudensity == 0)
907 		return ndelim;
908 
909 	rix = bf->rates[0].idx;
910 	flags = bf->rates[0].flags;
911 	width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
912 	half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
913 
914 	if (half_gi)
915 		nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
916 	else
917 		nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
918 
919 	if (nsymbols == 0)
920 		nsymbols = 1;
921 
922 	streams = HT_RC_2_STREAMS(rix);
923 	nsymbits = bits_per_symbol[rix % 8][width] * streams;
924 	minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
925 
926 	if (frmlen < minlen) {
927 		mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
928 		ndelim = max(mindelim, ndelim);
929 	}
930 
931 	return ndelim;
932 }
933 
934 static int
ath_tx_get_tid_subframe(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct ath_buf ** buf)935 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
936 			struct ath_atx_tid *tid, struct ath_buf **buf)
937 {
938 	struct ieee80211_tx_info *tx_info;
939 	struct ath_frame_info *fi;
940 	struct ath_buf *bf;
941 	struct sk_buff *skb, *first_skb = NULL;
942 	u16 seqno;
943 	int ret;
944 
945 	while (1) {
946 		ret = ath_tid_dequeue(tid, &skb);
947 		if (ret < 0)
948 			return ret;
949 
950 		fi = get_frame_info(skb);
951 		bf = fi->bf;
952 		if (!fi->bf)
953 			bf = ath_tx_setup_buffer(sc, txq, tid, skb);
954 		else
955 			bf->bf_state.stale = false;
956 
957 		if (!bf) {
958 			ath_txq_skb_done(sc, txq, skb);
959 			ieee80211_free_txskb(sc->hw, skb);
960 			continue;
961 		}
962 
963 		bf->bf_next = NULL;
964 		bf->bf_lastbf = bf;
965 
966 		tx_info = IEEE80211_SKB_CB(skb);
967 		tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
968 				    IEEE80211_TX_STATUS_EOSP);
969 
970 		/*
971 		 * No aggregation session is running, but there may be frames
972 		 * from a previous session or a failed attempt in the queue.
973 		 * Send them out as normal data frames
974 		 */
975 		if (!tid->active)
976 			tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
977 
978 		if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
979 			bf->bf_state.bf_type = 0;
980 			break;
981 		}
982 
983 		bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
984 		seqno = bf->bf_state.seqno;
985 
986 		/* do not step over block-ack window */
987 		if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
988 			__skb_queue_tail(&tid->retry_q, skb);
989 
990 			/* If there are other skbs in the retry q, they are
991 			 * probably within the BAW, so loop immediately to get
992 			 * one of them. Otherwise the queue can get stuck. */
993 			if (!skb_queue_is_first(&tid->retry_q, skb) &&
994 			    !WARN_ON(skb == first_skb)) {
995 				if(!first_skb) /* infinite loop prevention */
996 					first_skb = skb;
997 				continue;
998 			}
999 			return -EINPROGRESS;
1000 		}
1001 
1002 		if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
1003 			struct ath_tx_status ts = {};
1004 			struct list_head bf_head;
1005 
1006 			INIT_LIST_HEAD(&bf_head);
1007 			list_add(&bf->list, &bf_head);
1008 			ath_tx_update_baw(sc, tid, bf);
1009 			ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
1010 			continue;
1011 		}
1012 
1013 		if (bf_isampdu(bf))
1014 			ath_tx_addto_baw(sc, tid, bf);
1015 
1016 		break;
1017 	}
1018 
1019 	*buf = bf;
1020 	return 0;
1021 }
1022 
1023 static int
ath_tx_form_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct list_head * bf_q,struct ath_buf * bf_first)1024 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
1025 		 struct ath_atx_tid *tid, struct list_head *bf_q,
1026 		 struct ath_buf *bf_first)
1027 {
1028 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1029 	struct ath_buf *bf = bf_first, *bf_prev = NULL;
1030 	int nframes = 0, ndelim, ret;
1031 	u16 aggr_limit = 0, al = 0, bpad = 0,
1032 	    al_delta, h_baw = tid->baw_size / 2;
1033 	struct ieee80211_tx_info *tx_info;
1034 	struct ath_frame_info *fi;
1035 	struct sk_buff *skb;
1036 
1037 
1038 	bf = bf_first;
1039 	aggr_limit = ath_lookup_rate(sc, bf, tid);
1040 
1041 	while (bf)
1042 	{
1043 		skb = bf->bf_mpdu;
1044 		fi = get_frame_info(skb);
1045 
1046 		/* do not exceed aggregation limit */
1047 		al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1048 		if (nframes) {
1049 			if (aggr_limit < al + bpad + al_delta ||
1050 			    ath_lookup_legacy(bf) || nframes >= h_baw)
1051 				goto stop;
1052 
1053 			tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1054 			if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1055 			    !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1056 				goto stop;
1057 		}
1058 
1059 		/* add padding for previous frame to aggregation length */
1060 		al += bpad + al_delta;
1061 
1062 		/*
1063 		 * Get the delimiters needed to meet the MPDU
1064 		 * density for this node.
1065 		 */
1066 		ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1067 						!nframes);
1068 		bpad = PADBYTES(al_delta) + (ndelim << 2);
1069 
1070 		nframes++;
1071 		bf->bf_next = NULL;
1072 
1073 		/* link buffers of this frame to the aggregate */
1074 		bf->bf_state.ndelim = ndelim;
1075 
1076 		list_add_tail(&bf->list, bf_q);
1077 		if (bf_prev)
1078 			bf_prev->bf_next = bf;
1079 
1080 		bf_prev = bf;
1081 
1082 		ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1083 		if (ret < 0)
1084 			break;
1085 	}
1086 	goto finish;
1087 stop:
1088 	__skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1089 finish:
1090 	bf = bf_first;
1091 	bf->bf_lastbf = bf_prev;
1092 
1093 	if (bf == bf_prev) {
1094 		al = get_frame_info(bf->bf_mpdu)->framelen;
1095 		bf->bf_state.bf_type = BUF_AMPDU;
1096 	} else {
1097 		TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1098 	}
1099 
1100 	return al;
1101 #undef PADBYTES
1102 }
1103 
1104 /*
1105  * rix - rate index
1106  * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1107  * width  - 0 for 20 MHz, 1 for 40 MHz
1108  * half_gi - to use 4us v/s 3.6 us for symbol time
1109  */
ath_pkt_duration(struct ath_softc * sc,u8 rix,int pktlen,int width,int half_gi,bool shortPreamble)1110 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1111 		     int width, int half_gi, bool shortPreamble)
1112 {
1113 	u32 nbits, nsymbits, duration, nsymbols;
1114 	int streams;
1115 
1116 	/* find number of symbols: PLCP + data */
1117 	streams = HT_RC_2_STREAMS(rix);
1118 	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1119 	nsymbits = bits_per_symbol[rix % 8][width] * streams;
1120 	nsymbols = (nbits + nsymbits - 1) / nsymbits;
1121 
1122 	if (!half_gi)
1123 		duration = SYMBOL_TIME(nsymbols);
1124 	else
1125 		duration = SYMBOL_TIME_HALFGI(nsymbols);
1126 
1127 	/* addup duration for legacy/ht training and signal fields */
1128 	duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1129 
1130 	return duration;
1131 }
1132 
ath_max_framelen(int usec,int mcs,bool ht40,bool sgi)1133 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1134 {
1135 	int streams = HT_RC_2_STREAMS(mcs);
1136 	int symbols, bits;
1137 	int bytes = 0;
1138 
1139 	usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1140 	symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1141 	bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1142 	bits -= OFDM_PLCP_BITS;
1143 	bytes = bits / 8;
1144 	if (bytes > 65532)
1145 		bytes = 65532;
1146 
1147 	return bytes;
1148 }
1149 
ath_update_max_aggr_framelen(struct ath_softc * sc,int queue,int txop)1150 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1151 {
1152 	u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1153 	int mcs;
1154 
1155 	/* 4ms is the default (and maximum) duration */
1156 	if (!txop || txop > 4096)
1157 		txop = 4096;
1158 
1159 	cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1160 	cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1161 	cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1162 	cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1163 	for (mcs = 0; mcs < 32; mcs++) {
1164 		cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1165 		cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1166 		cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1167 		cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1168 	}
1169 }
1170 
ath_get_rate_txpower(struct ath_softc * sc,struct ath_buf * bf,u8 rateidx,bool is_40,bool is_cck)1171 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1172 			       u8 rateidx, bool is_40, bool is_cck)
1173 {
1174 	u8 max_power;
1175 	struct sk_buff *skb;
1176 	struct ath_frame_info *fi;
1177 	struct ieee80211_tx_info *info;
1178 	struct ath_hw *ah = sc->sc_ah;
1179 
1180 	if (sc->tx99_state || !ah->tpc_enabled)
1181 		return MAX_RATE_POWER;
1182 
1183 	skb = bf->bf_mpdu;
1184 	fi = get_frame_info(skb);
1185 	info = IEEE80211_SKB_CB(skb);
1186 
1187 	if (!AR_SREV_9300_20_OR_LATER(ah)) {
1188 		int txpower = fi->tx_power;
1189 
1190 		if (is_40) {
1191 			u8 power_ht40delta;
1192 			struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1193 			u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1194 
1195 			if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1196 				bool is_2ghz;
1197 				struct modal_eep_header *pmodal;
1198 
1199 				is_2ghz = info->band == NL80211_BAND_2GHZ;
1200 				pmodal = &eep->modalHeader[is_2ghz];
1201 				power_ht40delta = pmodal->ht40PowerIncForPdadc;
1202 			} else {
1203 				power_ht40delta = 2;
1204 			}
1205 			txpower += power_ht40delta;
1206 		}
1207 
1208 		if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1209 		    AR_SREV_9271(ah)) {
1210 			txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1211 		} else if (AR_SREV_9280_20_OR_LATER(ah)) {
1212 			s8 power_offset;
1213 
1214 			power_offset = ah->eep_ops->get_eeprom(ah,
1215 							EEP_PWR_TABLE_OFFSET);
1216 			txpower -= 2 * power_offset;
1217 		}
1218 
1219 		if (OLC_FOR_AR9280_20_LATER && is_cck)
1220 			txpower -= 2;
1221 
1222 		txpower = max(txpower, 0);
1223 		max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1224 
1225 		/* XXX: clamp minimum TX power at 1 for AR9160 since if
1226 		 * max_power is set to 0, frames are transmitted at max
1227 		 * TX power
1228 		 */
1229 		if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1230 			max_power = 1;
1231 	} else if (!bf->bf_state.bfs_paprd) {
1232 		if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1233 			max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1234 					  fi->tx_power);
1235 		else
1236 			max_power = min_t(u8, ah->tx_power[rateidx],
1237 					  fi->tx_power);
1238 	} else {
1239 		max_power = ah->paprd_training_power;
1240 	}
1241 
1242 	return max_power;
1243 }
1244 
ath_buf_set_rate(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_info * info,int len,bool rts)1245 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1246 			     struct ath_tx_info *info, int len, bool rts)
1247 {
1248 	struct ath_hw *ah = sc->sc_ah;
1249 	struct ath_common *common = ath9k_hw_common(ah);
1250 	struct sk_buff *skb;
1251 	struct ieee80211_tx_info *tx_info;
1252 	struct ieee80211_tx_rate *rates;
1253 	const struct ieee80211_rate *rate;
1254 	struct ieee80211_hdr *hdr;
1255 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1256 	u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1257 	int i;
1258 	u8 rix = 0;
1259 
1260 	skb = bf->bf_mpdu;
1261 	tx_info = IEEE80211_SKB_CB(skb);
1262 	rates = bf->rates;
1263 	hdr = (struct ieee80211_hdr *)skb->data;
1264 
1265 	/* set dur_update_en for l-sig computation except for PS-Poll frames */
1266 	info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1267 	info->rtscts_rate = fi->rtscts_rate;
1268 
1269 	for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1270 		bool is_40, is_sgi, is_sp, is_cck;
1271 		int phy;
1272 
1273 		if (!rates[i].count || (rates[i].idx < 0))
1274 			break;
1275 
1276 		rix = rates[i].idx;
1277 		info->rates[i].Tries = rates[i].count;
1278 
1279 		/*
1280 		 * Handle RTS threshold for unaggregated HT frames.
1281 		 */
1282 		if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1283 		    (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1284 		    unlikely(rts_thresh != (u32) -1)) {
1285 			if (!rts_thresh || (len > rts_thresh))
1286 				rts = true;
1287 		}
1288 
1289 		if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1290 			info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1291 			info->flags |= ATH9K_TXDESC_RTSENA;
1292 		} else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1293 			info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1294 			info->flags |= ATH9K_TXDESC_CTSENA;
1295 		}
1296 
1297 		if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1298 			info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1299 		if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1300 			info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1301 
1302 		is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1303 		is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1304 		is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1305 
1306 		if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1307 			/* MCS rates */
1308 			info->rates[i].Rate = rix | 0x80;
1309 			info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1310 					ah->txchainmask, info->rates[i].Rate);
1311 			info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1312 				 is_40, is_sgi, is_sp);
1313 			if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1314 				info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1315 			if (rix >= 8 && fi->dyn_smps) {
1316 				info->rates[i].RateFlags |=
1317 					ATH9K_RATESERIES_RTS_CTS;
1318 				info->flags |= ATH9K_TXDESC_CTSENA;
1319 			}
1320 
1321 			info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1322 								is_40, false);
1323 			continue;
1324 		}
1325 
1326 		/* legacy rates */
1327 		rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1328 		if ((tx_info->band == NL80211_BAND_2GHZ) &&
1329 		    !(rate->flags & IEEE80211_RATE_ERP_G))
1330 			phy = WLAN_RC_PHY_CCK;
1331 		else
1332 			phy = WLAN_RC_PHY_OFDM;
1333 
1334 		info->rates[i].Rate = rate->hw_value;
1335 		if (rate->hw_value_short) {
1336 			if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1337 				info->rates[i].Rate |= rate->hw_value_short;
1338 		} else {
1339 			is_sp = false;
1340 		}
1341 
1342 		if (bf->bf_state.bfs_paprd)
1343 			info->rates[i].ChSel = ah->txchainmask;
1344 		else
1345 			info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1346 					ah->txchainmask, info->rates[i].Rate);
1347 
1348 		info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1349 			phy, rate->bitrate * 100, len, rix, is_sp);
1350 
1351 		is_cck = IS_CCK_RATE(info->rates[i].Rate);
1352 		info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1353 							is_cck);
1354 	}
1355 
1356 	/* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1357 	if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1358 		info->flags &= ~ATH9K_TXDESC_RTSENA;
1359 
1360 	/* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1361 	if (info->flags & ATH9K_TXDESC_RTSENA)
1362 		info->flags &= ~ATH9K_TXDESC_CTSENA;
1363 }
1364 
get_hw_packet_type(struct sk_buff * skb)1365 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1366 {
1367 	struct ieee80211_hdr *hdr;
1368 	enum ath9k_pkt_type htype;
1369 	__le16 fc;
1370 
1371 	hdr = (struct ieee80211_hdr *)skb->data;
1372 	fc = hdr->frame_control;
1373 
1374 	if (ieee80211_is_beacon(fc))
1375 		htype = ATH9K_PKT_TYPE_BEACON;
1376 	else if (ieee80211_is_probe_resp(fc))
1377 		htype = ATH9K_PKT_TYPE_PROBE_RESP;
1378 	else if (ieee80211_is_atim(fc))
1379 		htype = ATH9K_PKT_TYPE_ATIM;
1380 	else if (ieee80211_is_pspoll(fc))
1381 		htype = ATH9K_PKT_TYPE_PSPOLL;
1382 	else
1383 		htype = ATH9K_PKT_TYPE_NORMAL;
1384 
1385 	return htype;
1386 }
1387 
ath_tx_fill_desc(struct ath_softc * sc,struct ath_buf * bf,struct ath_txq * txq,int len)1388 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1389 			     struct ath_txq *txq, int len)
1390 {
1391 	struct ath_hw *ah = sc->sc_ah;
1392 	struct ath_buf *bf_first = NULL;
1393 	struct ath_tx_info info;
1394 	u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1395 	bool rts = false;
1396 
1397 	memset(&info, 0, sizeof(info));
1398 	info.is_first = true;
1399 	info.is_last = true;
1400 	info.qcu = txq->axq_qnum;
1401 
1402 	while (bf) {
1403 		struct sk_buff *skb = bf->bf_mpdu;
1404 		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1405 		struct ath_frame_info *fi = get_frame_info(skb);
1406 		bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1407 
1408 		info.type = get_hw_packet_type(skb);
1409 		if (bf->bf_next)
1410 			info.link = bf->bf_next->bf_daddr;
1411 		else
1412 			info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1413 
1414 		if (!bf_first) {
1415 			bf_first = bf;
1416 
1417 			if (!sc->tx99_state)
1418 				info.flags = ATH9K_TXDESC_INTREQ;
1419 			if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1420 			    txq == sc->tx.uapsdq)
1421 				info.flags |= ATH9K_TXDESC_CLRDMASK;
1422 
1423 			if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1424 				info.flags |= ATH9K_TXDESC_NOACK;
1425 			if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1426 				info.flags |= ATH9K_TXDESC_LDPC;
1427 
1428 			if (bf->bf_state.bfs_paprd)
1429 				info.flags |= (u32) bf->bf_state.bfs_paprd <<
1430 					      ATH9K_TXDESC_PAPRD_S;
1431 
1432 			/*
1433 			 * mac80211 doesn't handle RTS threshold for HT because
1434 			 * the decision has to be taken based on AMPDU length
1435 			 * and aggregation is done entirely inside ath9k.
1436 			 * Set the RTS/CTS flag for the first subframe based
1437 			 * on the threshold.
1438 			 */
1439 			if (aggr && (bf == bf_first) &&
1440 			    unlikely(rts_thresh != (u32) -1)) {
1441 				/*
1442 				 * "len" is the size of the entire AMPDU.
1443 				 */
1444 				if (!rts_thresh || (len > rts_thresh))
1445 					rts = true;
1446 			}
1447 
1448 			if (!aggr)
1449 				len = fi->framelen;
1450 
1451 			ath_buf_set_rate(sc, bf, &info, len, rts);
1452 		}
1453 
1454 		info.buf_addr[0] = bf->bf_buf_addr;
1455 		info.buf_len[0] = skb->len;
1456 		info.pkt_len = fi->framelen;
1457 		info.keyix = fi->keyix;
1458 		info.keytype = fi->keytype;
1459 
1460 		if (aggr) {
1461 			if (bf == bf_first)
1462 				info.aggr = AGGR_BUF_FIRST;
1463 			else if (bf == bf_first->bf_lastbf)
1464 				info.aggr = AGGR_BUF_LAST;
1465 			else
1466 				info.aggr = AGGR_BUF_MIDDLE;
1467 
1468 			info.ndelim = bf->bf_state.ndelim;
1469 			info.aggr_len = len;
1470 		}
1471 
1472 		if (bf == bf_first->bf_lastbf)
1473 			bf_first = NULL;
1474 
1475 		ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1476 		bf = bf->bf_next;
1477 	}
1478 }
1479 
1480 static void
ath_tx_form_burst(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct list_head * bf_q,struct ath_buf * bf_first)1481 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1482 		  struct ath_atx_tid *tid, struct list_head *bf_q,
1483 		  struct ath_buf *bf_first)
1484 {
1485 	struct ath_buf *bf = bf_first, *bf_prev = NULL;
1486 	int nframes = 0, ret;
1487 
1488 	do {
1489 		struct ieee80211_tx_info *tx_info;
1490 
1491 		nframes++;
1492 		list_add_tail(&bf->list, bf_q);
1493 		if (bf_prev)
1494 			bf_prev->bf_next = bf;
1495 		bf_prev = bf;
1496 
1497 		if (nframes >= 2)
1498 			break;
1499 
1500 		ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1501 		if (ret < 0)
1502 			break;
1503 
1504 		tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1505 		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1506 			__skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1507 			break;
1508 		}
1509 
1510 		ath_set_rates(tid->an->vif, tid->an->sta, bf);
1511 	} while (1);
1512 }
1513 
ath_tx_sched_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid)1514 static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1515 			     struct ath_atx_tid *tid)
1516 {
1517 	struct ath_buf *bf = NULL;
1518 	struct ieee80211_tx_info *tx_info;
1519 	struct list_head bf_q;
1520 	int aggr_len = 0, ret;
1521 	bool aggr;
1522 
1523 	INIT_LIST_HEAD(&bf_q);
1524 
1525 	ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1526 	if (ret < 0)
1527 		return ret;
1528 
1529 	tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1530 	aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1531 	if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1532 	    (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1533 		__skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1534 		return -EBUSY;
1535 	}
1536 
1537 	ath_set_rates(tid->an->vif, tid->an->sta, bf);
1538 	if (aggr)
1539 		aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1540 	else
1541 		ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1542 
1543 	if (list_empty(&bf_q))
1544 		return -EAGAIN;
1545 
1546 	if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1547 		tid->clear_ps_filter = false;
1548 		tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1549 	}
1550 
1551 	ath_tx_fill_desc(sc, bf, txq, aggr_len);
1552 	ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1553 	return 0;
1554 }
1555 
ath_tx_aggr_start(struct ath_softc * sc,struct ieee80211_sta * sta,u16 tid,u16 * ssn)1556 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1557 		      u16 tid, u16 *ssn)
1558 {
1559 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1560 	struct ath_atx_tid *txtid;
1561 	struct ath_txq *txq;
1562 	struct ath_node *an;
1563 	u8 density;
1564 
1565 	ath_dbg(common, XMIT, "%s called\n", __func__);
1566 
1567 	an = (struct ath_node *)sta->drv_priv;
1568 	txtid = ATH_AN_2_TID(an, tid);
1569 	txq = txtid->txq;
1570 
1571 	ath_txq_lock(sc, txq);
1572 
1573 	/* update ampdu factor/density, they may have changed. This may happen
1574 	 * in HT IBSS when a beacon with HT-info is received after the station
1575 	 * has already been added.
1576 	 */
1577 	if (sta->deflink.ht_cap.ht_supported) {
1578 		an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1579 				      sta->deflink.ht_cap.ampdu_factor)) - 1;
1580 		density = ath9k_parse_mpdudensity(sta->deflink.ht_cap.ampdu_density);
1581 		an->mpdudensity = density;
1582 	}
1583 
1584 	txtid->active = true;
1585 	*ssn = txtid->seq_start = txtid->seq_next;
1586 	txtid->bar_index = -1;
1587 
1588 	memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1589 	txtid->baw_head = txtid->baw_tail = 0;
1590 
1591 	ath_txq_unlock_complete(sc, txq);
1592 
1593 	return 0;
1594 }
1595 
ath_tx_aggr_stop(struct ath_softc * sc,struct ieee80211_sta * sta,u16 tid)1596 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1597 {
1598 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1599 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
1600 	struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1601 	struct ath_txq *txq = txtid->txq;
1602 
1603 	ath_dbg(common, XMIT, "%s called\n", __func__);
1604 
1605 	ath_txq_lock(sc, txq);
1606 	txtid->active = false;
1607 	ath_tx_flush_tid(sc, txtid);
1608 	ath_txq_unlock_complete(sc, txq);
1609 }
1610 
ath_tx_aggr_sleep(struct ieee80211_sta * sta,struct ath_softc * sc,struct ath_node * an)1611 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1612 		       struct ath_node *an)
1613 {
1614 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1615 	struct ath_atx_tid *tid;
1616 	int tidno;
1617 
1618 	ath_dbg(common, XMIT, "%s called\n", __func__);
1619 
1620 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1621 		tid = ath_node_to_tid(an, tidno);
1622 
1623 		if (!skb_queue_empty(&tid->retry_q))
1624 			ieee80211_sta_set_buffered(sta, tid->tidno, true);
1625 
1626 	}
1627 }
1628 
ath_tx_aggr_wakeup(struct ath_softc * sc,struct ath_node * an)1629 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1630 {
1631 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1632 	struct ath_atx_tid *tid;
1633 	struct ath_txq *txq;
1634 	int tidno;
1635 
1636 	ath_dbg(common, XMIT, "%s called\n", __func__);
1637 
1638 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1639 		tid = ath_node_to_tid(an, tidno);
1640 		txq = tid->txq;
1641 
1642 		ath_txq_lock(sc, txq);
1643 		tid->clear_ps_filter = true;
1644 		if (!skb_queue_empty(&tid->retry_q)) {
1645 			ath_tx_queue_tid(sc, tid);
1646 			ath_txq_schedule(sc, txq);
1647 		}
1648 		ath_txq_unlock_complete(sc, txq);
1649 
1650 	}
1651 }
1652 
1653 
1654 static void
ath9k_set_moredata(struct ath_softc * sc,struct ath_buf * bf,bool val)1655 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1656 {
1657 	struct ieee80211_hdr *hdr;
1658 	u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1659 	u16 mask_val = mask * val;
1660 
1661 	hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1662 	if ((hdr->frame_control & mask) != mask_val) {
1663 		hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1664 		dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1665 			sizeof(*hdr), DMA_TO_DEVICE);
1666 	}
1667 }
1668 
ath9k_release_buffered_frames(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u16 tids,int nframes,enum ieee80211_frame_release_type reason,bool more_data)1669 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1670 				   struct ieee80211_sta *sta,
1671 				   u16 tids, int nframes,
1672 				   enum ieee80211_frame_release_type reason,
1673 				   bool more_data)
1674 {
1675 	struct ath_softc *sc = hw->priv;
1676 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
1677 	struct ath_txq *txq = sc->tx.uapsdq;
1678 	struct ieee80211_tx_info *info;
1679 	struct list_head bf_q;
1680 	struct ath_buf *bf_tail = NULL, *bf = NULL;
1681 	int sent = 0;
1682 	int i, ret;
1683 
1684 	INIT_LIST_HEAD(&bf_q);
1685 	for (i = 0; tids && nframes; i++, tids >>= 1) {
1686 		struct ath_atx_tid *tid;
1687 
1688 		if (!(tids & 1))
1689 			continue;
1690 
1691 		tid = ATH_AN_2_TID(an, i);
1692 
1693 		ath_txq_lock(sc, tid->txq);
1694 		while (nframes > 0) {
1695 			ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq,
1696 						      tid, &bf);
1697 			if (ret < 0)
1698 				break;
1699 
1700 			ath9k_set_moredata(sc, bf, true);
1701 			list_add_tail(&bf->list, &bf_q);
1702 			ath_set_rates(tid->an->vif, tid->an->sta, bf);
1703 			if (bf_isampdu(bf))
1704 				bf->bf_state.bf_type &= ~BUF_AGGR;
1705 			if (bf_tail)
1706 				bf_tail->bf_next = bf;
1707 
1708 			bf_tail = bf;
1709 			nframes--;
1710 			sent++;
1711 			TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1712 
1713 			if (an->sta && skb_queue_empty(&tid->retry_q))
1714 				ieee80211_sta_set_buffered(an->sta, i, false);
1715 		}
1716 		ath_txq_unlock_complete(sc, tid->txq);
1717 	}
1718 
1719 	if (list_empty(&bf_q))
1720 		return;
1721 
1722 	if (!more_data)
1723 		ath9k_set_moredata(sc, bf_tail, false);
1724 
1725 	info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1726 	info->flags |= IEEE80211_TX_STATUS_EOSP;
1727 
1728 	bf = list_first_entry(&bf_q, struct ath_buf, list);
1729 	ath_txq_lock(sc, txq);
1730 	ath_tx_fill_desc(sc, bf, txq, 0);
1731 	ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1732 	ath_txq_unlock(sc, txq);
1733 }
1734 
1735 /********************/
1736 /* Queue Management */
1737 /********************/
1738 
ath_txq_setup(struct ath_softc * sc,int qtype,int subtype)1739 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1740 {
1741 	struct ath_hw *ah = sc->sc_ah;
1742 	struct ath9k_tx_queue_info qi;
1743 	static const int subtype_txq_to_hwq[] = {
1744 		[IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1745 		[IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1746 		[IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1747 		[IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1748 	};
1749 	int axq_qnum, i;
1750 
1751 	memset(&qi, 0, sizeof(qi));
1752 	qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1753 	qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1754 	qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1755 	qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1756 	qi.tqi_physCompBuf = 0;
1757 
1758 	/*
1759 	 * Enable interrupts only for EOL and DESC conditions.
1760 	 * We mark tx descriptors to receive a DESC interrupt
1761 	 * when a tx queue gets deep; otherwise waiting for the
1762 	 * EOL to reap descriptors.  Note that this is done to
1763 	 * reduce interrupt load and this only defers reaping
1764 	 * descriptors, never transmitting frames.  Aside from
1765 	 * reducing interrupts this also permits more concurrency.
1766 	 * The only potential downside is if the tx queue backs
1767 	 * up in which case the top half of the kernel may backup
1768 	 * due to a lack of tx descriptors.
1769 	 *
1770 	 * The UAPSD queue is an exception, since we take a desc-
1771 	 * based intr on the EOSP frames.
1772 	 */
1773 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1774 		qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1775 	} else {
1776 		if (qtype == ATH9K_TX_QUEUE_UAPSD)
1777 			qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1778 		else
1779 			qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1780 					TXQ_FLAG_TXDESCINT_ENABLE;
1781 	}
1782 	axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1783 	if (axq_qnum == -1) {
1784 		/*
1785 		 * NB: don't print a message, this happens
1786 		 * normally on parts with too few tx queues
1787 		 */
1788 		return NULL;
1789 	}
1790 	if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1791 		struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1792 
1793 		txq->axq_qnum = axq_qnum;
1794 		txq->mac80211_qnum = -1;
1795 		txq->axq_link = NULL;
1796 		__skb_queue_head_init(&txq->complete_q);
1797 		INIT_LIST_HEAD(&txq->axq_q);
1798 		spin_lock_init(&txq->axq_lock);
1799 		txq->axq_depth = 0;
1800 		txq->axq_ampdu_depth = 0;
1801 		txq->axq_tx_inprogress = false;
1802 		sc->tx.txqsetup |= 1<<axq_qnum;
1803 
1804 		txq->txq_headidx = txq->txq_tailidx = 0;
1805 		for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1806 			INIT_LIST_HEAD(&txq->txq_fifo[i]);
1807 	}
1808 	return &sc->tx.txq[axq_qnum];
1809 }
1810 
ath_txq_update(struct ath_softc * sc,int qnum,struct ath9k_tx_queue_info * qinfo)1811 int ath_txq_update(struct ath_softc *sc, int qnum,
1812 		   struct ath9k_tx_queue_info *qinfo)
1813 {
1814 	struct ath_hw *ah = sc->sc_ah;
1815 	int error = 0;
1816 	struct ath9k_tx_queue_info qi;
1817 
1818 	BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1819 
1820 	ath9k_hw_get_txq_props(ah, qnum, &qi);
1821 	qi.tqi_aifs = qinfo->tqi_aifs;
1822 	qi.tqi_cwmin = qinfo->tqi_cwmin;
1823 	qi.tqi_cwmax = qinfo->tqi_cwmax;
1824 	qi.tqi_burstTime = qinfo->tqi_burstTime;
1825 	qi.tqi_readyTime = qinfo->tqi_readyTime;
1826 
1827 	if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1828 		ath_err(ath9k_hw_common(sc->sc_ah),
1829 			"Unable to update hardware queue %u!\n", qnum);
1830 		error = -EIO;
1831 	} else {
1832 		ath9k_hw_resettxqueue(ah, qnum);
1833 	}
1834 
1835 	return error;
1836 }
1837 
ath_cabq_update(struct ath_softc * sc)1838 int ath_cabq_update(struct ath_softc *sc)
1839 {
1840 	struct ath9k_tx_queue_info qi;
1841 	struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1842 	int qnum = sc->beacon.cabq->axq_qnum;
1843 
1844 	ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1845 
1846 	qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1847 			    ATH_CABQ_READY_TIME) / 100;
1848 	ath_txq_update(sc, qnum, &qi);
1849 
1850 	return 0;
1851 }
1852 
ath_drain_txq_list(struct ath_softc * sc,struct ath_txq * txq,struct list_head * list)1853 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1854 			       struct list_head *list)
1855 {
1856 	struct ath_buf *bf, *lastbf;
1857 	struct list_head bf_head;
1858 	struct ath_tx_status ts;
1859 
1860 	memset(&ts, 0, sizeof(ts));
1861 	ts.ts_status = ATH9K_TX_FLUSH;
1862 	INIT_LIST_HEAD(&bf_head);
1863 
1864 	while (!list_empty(list)) {
1865 		bf = list_first_entry(list, struct ath_buf, list);
1866 
1867 		if (bf->bf_state.stale) {
1868 			list_del(&bf->list);
1869 
1870 			ath_tx_return_buffer(sc, bf);
1871 			continue;
1872 		}
1873 
1874 		lastbf = bf->bf_lastbf;
1875 		list_cut_position(&bf_head, list, &lastbf->list);
1876 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1877 	}
1878 }
1879 
1880 /*
1881  * Drain a given TX queue (could be Beacon or Data)
1882  *
1883  * This assumes output has been stopped and
1884  * we do not need to block ath_tx_tasklet.
1885  */
ath_draintxq(struct ath_softc * sc,struct ath_txq * txq)1886 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1887 {
1888 	rcu_read_lock();
1889 	ath_txq_lock(sc, txq);
1890 
1891 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1892 		int idx = txq->txq_tailidx;
1893 
1894 		while (!list_empty(&txq->txq_fifo[idx])) {
1895 			ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1896 
1897 			INCR(idx, ATH_TXFIFO_DEPTH);
1898 		}
1899 		txq->txq_tailidx = idx;
1900 	}
1901 
1902 	txq->axq_link = NULL;
1903 	txq->axq_tx_inprogress = false;
1904 	ath_drain_txq_list(sc, txq, &txq->axq_q);
1905 
1906 	ath_txq_unlock_complete(sc, txq);
1907 	rcu_read_unlock();
1908 }
1909 
ath_drain_all_txq(struct ath_softc * sc)1910 bool ath_drain_all_txq(struct ath_softc *sc)
1911 {
1912 	struct ath_hw *ah = sc->sc_ah;
1913 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1914 	struct ath_txq *txq;
1915 	int i;
1916 	u32 npend = 0;
1917 
1918 	if (test_bit(ATH_OP_INVALID, &common->op_flags))
1919 		return true;
1920 
1921 	ath9k_hw_abort_tx_dma(ah);
1922 
1923 	/* Check if any queue remains active */
1924 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1925 		if (!ATH_TXQ_SETUP(sc, i))
1926 			continue;
1927 
1928 		if (!sc->tx.txq[i].axq_depth)
1929 			continue;
1930 
1931 		if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1932 			npend |= BIT(i);
1933 	}
1934 
1935 	if (npend) {
1936 		RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1937 		ath_dbg(common, RESET,
1938 			"Failed to stop TX DMA, queues=0x%03x!\n", npend);
1939 	}
1940 
1941 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1942 		if (!ATH_TXQ_SETUP(sc, i))
1943 			continue;
1944 
1945 		txq = &sc->tx.txq[i];
1946 		ath_draintxq(sc, txq);
1947 	}
1948 
1949 	return !npend;
1950 }
1951 
ath_tx_cleanupq(struct ath_softc * sc,struct ath_txq * txq)1952 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1953 {
1954 	ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1955 	sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1956 }
1957 
1958 /* For each acq entry, for each tid, try to schedule packets
1959  * for transmit until ampdu_depth has reached min Q depth.
1960  */
ath_txq_schedule(struct ath_softc * sc,struct ath_txq * txq)1961 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1962 {
1963 	struct ieee80211_hw *hw = sc->hw;
1964 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1965 	struct ieee80211_txq *queue;
1966 	struct ath_atx_tid *tid;
1967 	int ret;
1968 
1969 	if (txq->mac80211_qnum < 0)
1970 		return;
1971 
1972 	if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1973 		return;
1974 
1975 	ieee80211_txq_schedule_start(hw, txq->mac80211_qnum);
1976 	spin_lock_bh(&sc->chan_lock);
1977 	rcu_read_lock();
1978 
1979 	if (sc->cur_chan->stopped)
1980 		goto out;
1981 
1982 	while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) {
1983 		bool force;
1984 
1985 		tid = (struct ath_atx_tid *)queue->drv_priv;
1986 
1987 		ret = ath_tx_sched_aggr(sc, txq, tid);
1988 		ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret);
1989 
1990 		force = !skb_queue_empty(&tid->retry_q);
1991 		ieee80211_return_txq(hw, queue, force);
1992 	}
1993 
1994 out:
1995 	rcu_read_unlock();
1996 	spin_unlock_bh(&sc->chan_lock);
1997 	ieee80211_txq_schedule_end(hw, txq->mac80211_qnum);
1998 }
1999 
ath_txq_schedule_all(struct ath_softc * sc)2000 void ath_txq_schedule_all(struct ath_softc *sc)
2001 {
2002 	struct ath_txq *txq;
2003 	int i;
2004 
2005 	for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2006 		txq = sc->tx.txq_map[i];
2007 
2008 		spin_lock_bh(&txq->axq_lock);
2009 		ath_txq_schedule(sc, txq);
2010 		spin_unlock_bh(&txq->axq_lock);
2011 	}
2012 }
2013 
2014 /***********/
2015 /* TX, DMA */
2016 /***********/
2017 
2018 /*
2019  * Insert a chain of ath_buf (descriptors) on a txq and
2020  * assume the descriptors are already chained together by caller.
2021  */
ath_tx_txqaddbuf(struct ath_softc * sc,struct ath_txq * txq,struct list_head * head,bool internal)2022 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2023 			     struct list_head *head, bool internal)
2024 {
2025 	struct ath_hw *ah = sc->sc_ah;
2026 	struct ath_common *common = ath9k_hw_common(ah);
2027 	struct ath_buf *bf, *bf_last;
2028 	bool puttxbuf = false;
2029 	bool edma;
2030 
2031 	/*
2032 	 * Insert the frame on the outbound list and
2033 	 * pass it on to the hardware.
2034 	 */
2035 
2036 	if (list_empty(head))
2037 		return;
2038 
2039 	edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2040 	bf = list_first_entry(head, struct ath_buf, list);
2041 	bf_last = list_entry(head->prev, struct ath_buf, list);
2042 
2043 	ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2044 		txq->axq_qnum, txq->axq_depth);
2045 
2046 	if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2047 		list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2048 		INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2049 		puttxbuf = true;
2050 	} else {
2051 		list_splice_tail_init(head, &txq->axq_q);
2052 
2053 		if (txq->axq_link) {
2054 			ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2055 			ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2056 				txq->axq_qnum, txq->axq_link,
2057 				ito64(bf->bf_daddr), bf->bf_desc);
2058 		} else if (!edma)
2059 			puttxbuf = true;
2060 
2061 		txq->axq_link = bf_last->bf_desc;
2062 	}
2063 
2064 	if (puttxbuf) {
2065 		TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2066 		ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2067 		ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2068 			txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2069 	}
2070 
2071 	if (!edma || sc->tx99_state) {
2072 		TX_STAT_INC(sc, txq->axq_qnum, txstart);
2073 		ath9k_hw_txstart(ah, txq->axq_qnum);
2074 	}
2075 
2076 	if (!internal) {
2077 		while (bf) {
2078 			txq->axq_depth++;
2079 			if (bf_is_ampdu_not_probing(bf))
2080 				txq->axq_ampdu_depth++;
2081 
2082 			bf_last = bf->bf_lastbf;
2083 			bf = bf_last->bf_next;
2084 			bf_last->bf_next = NULL;
2085 		}
2086 	}
2087 }
2088 
ath_tx_send_normal(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct sk_buff * skb)2089 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2090 			       struct ath_atx_tid *tid, struct sk_buff *skb)
2091 {
2092 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2093 	struct ath_frame_info *fi = get_frame_info(skb);
2094 	struct list_head bf_head;
2095 	struct ath_buf *bf = fi->bf;
2096 
2097 	INIT_LIST_HEAD(&bf_head);
2098 	list_add_tail(&bf->list, &bf_head);
2099 	bf->bf_state.bf_type = 0;
2100 	if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2101 		bf->bf_state.bf_type = BUF_AMPDU;
2102 		ath_tx_addto_baw(sc, tid, bf);
2103 	}
2104 
2105 	bf->bf_next = NULL;
2106 	bf->bf_lastbf = bf;
2107 	ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2108 	ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2109 	TX_STAT_INC(sc, txq->axq_qnum, queued);
2110 }
2111 
setup_frame_info(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,int framelen)2112 static void setup_frame_info(struct ieee80211_hw *hw,
2113 			     struct ieee80211_sta *sta,
2114 			     struct sk_buff *skb,
2115 			     int framelen)
2116 {
2117 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2118 	struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2119 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2120 	const struct ieee80211_rate *rate;
2121 	struct ath_frame_info *fi = get_frame_info(skb);
2122 	struct ath_node *an = NULL;
2123 	enum ath9k_key_type keytype;
2124 	bool short_preamble = false;
2125 	u8 txpower;
2126 
2127 	/*
2128 	 * We check if Short Preamble is needed for the CTS rate by
2129 	 * checking the BSS's global flag.
2130 	 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2131 	 */
2132 	if (tx_info->control.vif &&
2133 	    tx_info->control.vif->bss_conf.use_short_preamble)
2134 		short_preamble = true;
2135 
2136 	rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2137 	keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2138 
2139 	if (sta)
2140 		an = (struct ath_node *) sta->drv_priv;
2141 
2142 	if (tx_info->control.vif) {
2143 		struct ieee80211_vif *vif = tx_info->control.vif;
2144 		if (vif->bss_conf.txpower == INT_MIN)
2145 			goto nonvifpower;
2146 		txpower = 2 * vif->bss_conf.txpower;
2147 	} else {
2148 		struct ath_softc *sc;
2149 	nonvifpower:
2150 		sc = hw->priv;
2151 
2152 		txpower = sc->cur_chan->cur_txpower;
2153 	}
2154 
2155 	memset(fi, 0, sizeof(*fi));
2156 	fi->txq = -1;
2157 	if (hw_key)
2158 		fi->keyix = hw_key->hw_key_idx;
2159 	else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2160 		fi->keyix = an->ps_key;
2161 	else
2162 		fi->keyix = ATH9K_TXKEYIX_INVALID;
2163 	fi->dyn_smps = sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC;
2164 	fi->keytype = keytype;
2165 	fi->framelen = framelen;
2166 	fi->tx_power = txpower;
2167 
2168 	if (!rate)
2169 		return;
2170 	fi->rtscts_rate = rate->hw_value;
2171 	if (short_preamble)
2172 		fi->rtscts_rate |= rate->hw_value_short;
2173 }
2174 
ath_txchainmask_reduction(struct ath_softc * sc,u8 chainmask,u32 rate)2175 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2176 {
2177 	struct ath_hw *ah = sc->sc_ah;
2178 	struct ath9k_channel *curchan = ah->curchan;
2179 
2180 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2181 	    (chainmask == 0x7) && (rate < 0x90))
2182 		return 0x3;
2183 	else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2184 		 IS_CCK_RATE(rate))
2185 		return 0x2;
2186 	else
2187 		return chainmask;
2188 }
2189 
2190 /*
2191  * Assign a descriptor (and sequence number if necessary,
2192  * and map buffer for DMA. Frees skb on error
2193  */
ath_tx_setup_buffer(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct sk_buff * skb)2194 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2195 					   struct ath_txq *txq,
2196 					   struct ath_atx_tid *tid,
2197 					   struct sk_buff *skb)
2198 {
2199 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2200 	struct ath_frame_info *fi = get_frame_info(skb);
2201 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2202 	struct ath_buf *bf;
2203 	int fragno;
2204 	u16 seqno;
2205 
2206 	bf = ath_tx_get_buffer(sc);
2207 	if (!bf) {
2208 		ath_dbg(common, XMIT, "TX buffers are full\n");
2209 		return NULL;
2210 	}
2211 
2212 	ATH_TXBUF_RESET(bf);
2213 
2214 	if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2215 		fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2216 		seqno = tid->seq_next;
2217 		hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2218 
2219 		if (fragno)
2220 			hdr->seq_ctrl |= cpu_to_le16(fragno);
2221 
2222 		if (!ieee80211_has_morefrags(hdr->frame_control))
2223 			INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2224 
2225 		bf->bf_state.seqno = seqno;
2226 	}
2227 
2228 	bf->bf_mpdu = skb;
2229 
2230 	bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2231 					 skb->len, DMA_TO_DEVICE);
2232 	if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2233 		bf->bf_mpdu = NULL;
2234 		bf->bf_buf_addr = 0;
2235 		ath_err(ath9k_hw_common(sc->sc_ah),
2236 			"dma_mapping_error() on TX\n");
2237 		ath_tx_return_buffer(sc, bf);
2238 		return NULL;
2239 	}
2240 
2241 	fi->bf = bf;
2242 
2243 	return bf;
2244 }
2245 
ath_assign_seq(struct ath_common * common,struct sk_buff * skb)2246 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2247 {
2248 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2249 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2250 	struct ieee80211_vif *vif = info->control.vif;
2251 	struct ath_vif *avp;
2252 
2253 	if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2254 		return;
2255 
2256 	if (!vif)
2257 		return;
2258 
2259 	avp = (struct ath_vif *)vif->drv_priv;
2260 
2261 	if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2262 		avp->seq_no += 0x10;
2263 
2264 	hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2265 	hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2266 }
2267 
ath_tx_prepare(struct ieee80211_hw * hw,struct sk_buff * skb,struct ath_tx_control * txctl)2268 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2269 			  struct ath_tx_control *txctl)
2270 {
2271 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2272 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2273 	struct ieee80211_sta *sta = txctl->sta;
2274 	struct ieee80211_vif *vif = info->control.vif;
2275 	struct ath_vif *avp;
2276 	struct ath_softc *sc = hw->priv;
2277 	int frmlen = skb->len + FCS_LEN;
2278 	int padpos, padsize;
2279 
2280 	/* NOTE:  sta can be NULL according to net/mac80211.h */
2281 	if (sta)
2282 		txctl->an = (struct ath_node *)sta->drv_priv;
2283 	else if (vif && ieee80211_is_data(hdr->frame_control)) {
2284 		avp = (void *)vif->drv_priv;
2285 		txctl->an = &avp->mcast_node;
2286 	}
2287 
2288 	if (info->control.hw_key)
2289 		frmlen += info->control.hw_key->icv_len;
2290 
2291 	ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2292 
2293 	if ((vif && vif->type != NL80211_IFTYPE_AP &&
2294 	            vif->type != NL80211_IFTYPE_AP_VLAN) ||
2295 	    !ieee80211_is_data(hdr->frame_control))
2296 		info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2297 
2298 	/* Add the padding after the header if this is not already done */
2299 	padpos = ieee80211_hdrlen(hdr->frame_control);
2300 	padsize = padpos & 3;
2301 	if (padsize && skb->len > padpos) {
2302 		if (skb_headroom(skb) < padsize)
2303 			return -ENOMEM;
2304 
2305 		skb_push(skb, padsize);
2306 		memmove(skb->data, skb->data + padsize, padpos);
2307 	}
2308 
2309 	setup_frame_info(hw, sta, skb, frmlen);
2310 	return 0;
2311 }
2312 
2313 
2314 /* Upon failure caller should free skb */
ath_tx_start(struct ieee80211_hw * hw,struct sk_buff * skb,struct ath_tx_control * txctl)2315 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2316 		 struct ath_tx_control *txctl)
2317 {
2318 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2319 	struct ieee80211_sta *sta = txctl->sta;
2320 	struct ieee80211_vif *vif = info->control.vif;
2321 	struct ath_frame_info *fi = get_frame_info(skb);
2322 	struct ath_softc *sc = hw->priv;
2323 	struct ath_txq *txq = txctl->txq;
2324 	struct ath_atx_tid *tid = NULL;
2325 	struct ath_node *an = NULL;
2326 	struct ath_buf *bf;
2327 	bool ps_resp;
2328 	int q, ret;
2329 
2330 	ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2331 
2332 	ret = ath_tx_prepare(hw, skb, txctl);
2333 	if (ret)
2334 	    return ret;
2335 
2336 	/*
2337 	 * At this point, the vif, hw_key and sta pointers in the tx control
2338 	 * info are no longer valid (overwritten by the ath_frame_info data.
2339 	 */
2340 
2341 	q = skb_get_queue_mapping(skb);
2342 
2343 	if (ps_resp)
2344 		txq = sc->tx.uapsdq;
2345 
2346 	if (txctl->sta) {
2347 		an = (struct ath_node *) sta->drv_priv;
2348 		tid = ath_get_skb_tid(sc, an, skb);
2349 	}
2350 
2351 	ath_txq_lock(sc, txq);
2352 	if (txq == sc->tx.txq_map[q]) {
2353 		fi->txq = q;
2354 		++txq->pending_frames;
2355 	}
2356 
2357 	bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2358 	if (!bf) {
2359 		ath_txq_skb_done(sc, txq, skb);
2360 		if (txctl->paprd)
2361 			dev_kfree_skb_any(skb);
2362 		else
2363 			ieee80211_free_txskb(sc->hw, skb);
2364 		goto out;
2365 	}
2366 
2367 	bf->bf_state.bfs_paprd = txctl->paprd;
2368 
2369 	if (txctl->paprd)
2370 		bf->bf_state.bfs_paprd_timestamp = jiffies;
2371 
2372 	ath_set_rates(vif, sta, bf);
2373 	ath_tx_send_normal(sc, txq, tid, skb);
2374 
2375 out:
2376 	ath_txq_unlock(sc, txq);
2377 
2378 	return 0;
2379 }
2380 
ath_tx_cabq(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct sk_buff * skb)2381 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2382 		 struct sk_buff *skb)
2383 {
2384 	struct ath_softc *sc = hw->priv;
2385 	struct ath_tx_control txctl = {
2386 		.txq = sc->beacon.cabq
2387 	};
2388 	struct ath_tx_info info = {};
2389 	struct ath_buf *bf_tail = NULL;
2390 	struct ath_buf *bf;
2391 	LIST_HEAD(bf_q);
2392 	int duration = 0;
2393 	int max_duration;
2394 
2395 	max_duration =
2396 		sc->cur_chan->beacon.beacon_interval * 1000 *
2397 		sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2398 
2399 	do {
2400 		struct ath_frame_info *fi = get_frame_info(skb);
2401 
2402 		if (ath_tx_prepare(hw, skb, &txctl))
2403 			break;
2404 
2405 		bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2406 		if (!bf)
2407 			break;
2408 
2409 		bf->bf_lastbf = bf;
2410 		ath_set_rates(vif, NULL, bf);
2411 		ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2412 		duration += info.rates[0].PktDuration;
2413 		if (bf_tail)
2414 			bf_tail->bf_next = bf;
2415 
2416 		list_add_tail(&bf->list, &bf_q);
2417 		bf_tail = bf;
2418 		skb = NULL;
2419 
2420 		if (duration > max_duration)
2421 			break;
2422 
2423 		skb = ieee80211_get_buffered_bc(hw, vif);
2424 	} while(skb);
2425 
2426 	if (skb)
2427 		ieee80211_free_txskb(hw, skb);
2428 
2429 	if (list_empty(&bf_q))
2430 		return;
2431 
2432 	bf = list_last_entry(&bf_q, struct ath_buf, list);
2433 	ath9k_set_moredata(sc, bf, false);
2434 
2435 	bf = list_first_entry(&bf_q, struct ath_buf, list);
2436 	ath_txq_lock(sc, txctl.txq);
2437 	ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2438 	ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2439 	TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2440 	ath_txq_unlock(sc, txctl.txq);
2441 }
2442 
2443 /*****************/
2444 /* TX Completion */
2445 /*****************/
2446 
ath_tx_complete(struct ath_softc * sc,struct sk_buff * skb,int tx_flags,struct ath_txq * txq,struct ieee80211_sta * sta)2447 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2448 			    int tx_flags, struct ath_txq *txq,
2449 			    struct ieee80211_sta *sta)
2450 {
2451 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2452 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2453 	struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2454 	int padpos, padsize;
2455 	unsigned long flags;
2456 
2457 	ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2458 
2459 	if (sc->sc_ah->caldata)
2460 		set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2461 
2462 	if (!(tx_flags & ATH_TX_ERROR)) {
2463 		if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2464 			tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2465 		else
2466 			tx_info->flags |= IEEE80211_TX_STAT_ACK;
2467 	}
2468 
2469 	if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2470 		padpos = ieee80211_hdrlen(hdr->frame_control);
2471 		padsize = padpos & 3;
2472 		if (padsize && skb->len>padpos+padsize) {
2473 			/*
2474 			 * Remove MAC header padding before giving the frame back to
2475 			 * mac80211.
2476 			 */
2477 			memmove(skb->data + padsize, skb->data, padpos);
2478 			skb_pull(skb, padsize);
2479 		}
2480 	}
2481 
2482 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
2483 	if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2484 		sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2485 		ath_dbg(common, PS,
2486 			"Going back to sleep after having received TX status (0x%lx)\n",
2487 			sc->ps_flags & (PS_WAIT_FOR_BEACON |
2488 					PS_WAIT_FOR_CAB |
2489 					PS_WAIT_FOR_PSPOLL_DATA |
2490 					PS_WAIT_FOR_TX_ACK));
2491 	}
2492 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2493 
2494 	ath_txq_skb_done(sc, txq, skb);
2495 	tx_info->status.status_driver_data[0] = sta;
2496 	__skb_queue_tail(&txq->complete_q, skb);
2497 }
2498 
ath_tx_complete_buf(struct ath_softc * sc,struct ath_buf * bf,struct ath_txq * txq,struct list_head * bf_q,struct ieee80211_sta * sta,struct ath_tx_status * ts,int txok)2499 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2500 				struct ath_txq *txq, struct list_head *bf_q,
2501 				struct ieee80211_sta *sta,
2502 				struct ath_tx_status *ts, int txok)
2503 {
2504 	struct sk_buff *skb = bf->bf_mpdu;
2505 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2506 	unsigned long flags;
2507 	int tx_flags = 0;
2508 
2509 	if (!txok)
2510 		tx_flags |= ATH_TX_ERROR;
2511 
2512 	if (ts->ts_status & ATH9K_TXERR_FILT)
2513 		tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2514 
2515 	dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2516 	bf->bf_buf_addr = 0;
2517 	if (sc->tx99_state)
2518 		goto skip_tx_complete;
2519 
2520 	if (bf->bf_state.bfs_paprd) {
2521 		if (time_after(jiffies,
2522 				bf->bf_state.bfs_paprd_timestamp +
2523 				msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2524 			dev_kfree_skb_any(skb);
2525 		else
2526 			complete(&sc->paprd_complete);
2527 	} else {
2528 		ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2529 		ath_tx_complete(sc, skb, tx_flags, txq, sta);
2530 	}
2531 skip_tx_complete:
2532 	/* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2533 	 * accidentally reference it later.
2534 	 */
2535 	bf->bf_mpdu = NULL;
2536 
2537 	/*
2538 	 * Return the list of ath_buf of this mpdu to free queue
2539 	 */
2540 	spin_lock_irqsave(&sc->tx.txbuflock, flags);
2541 	list_splice_tail_init(bf_q, &sc->tx.txbuf);
2542 	spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2543 }
2544 
ath_clear_tx_status(struct ieee80211_tx_info * tx_info)2545 static void ath_clear_tx_status(struct ieee80211_tx_info *tx_info)
2546 {
2547 	void *ptr = &tx_info->status;
2548 
2549 	memset(ptr + sizeof(tx_info->status.rates), 0,
2550 	       sizeof(tx_info->status) -
2551 	       sizeof(tx_info->status.rates) -
2552 	       sizeof(tx_info->status.status_driver_data));
2553 }
2554 
ath_tx_rc_status(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,int nframes,int nbad,int txok)2555 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2556 			     struct ath_tx_status *ts, int nframes, int nbad,
2557 			     int txok)
2558 {
2559 	struct sk_buff *skb = bf->bf_mpdu;
2560 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2561 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2562 	struct ieee80211_hw *hw = sc->hw;
2563 	struct ath_hw *ah = sc->sc_ah;
2564 	u8 i, tx_rateindex;
2565 
2566 	ath_clear_tx_status(tx_info);
2567 
2568 	if (txok)
2569 		tx_info->status.ack_signal = ts->ts_rssi;
2570 
2571 	tx_rateindex = ts->ts_rateindex;
2572 	WARN_ON(tx_rateindex >= hw->max_rates);
2573 
2574 	if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2575 		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2576 
2577 		BUG_ON(nbad > nframes);
2578 	}
2579 	tx_info->status.ampdu_len = nframes;
2580 	tx_info->status.ampdu_ack_len = nframes - nbad;
2581 
2582 	tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2583 
2584 	for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2585 		tx_info->status.rates[i].count = 0;
2586 		tx_info->status.rates[i].idx = -1;
2587 	}
2588 
2589 	if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2590 	    (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2591 		/*
2592 		 * If an underrun error is seen assume it as an excessive
2593 		 * retry only if max frame trigger level has been reached
2594 		 * (2 KB for single stream, and 4 KB for dual stream).
2595 		 * Adjust the long retry as if the frame was tried
2596 		 * hw->max_rate_tries times to affect how rate control updates
2597 		 * PER for the failed rate.
2598 		 * In case of congestion on the bus penalizing this type of
2599 		 * underruns should help hardware actually transmit new frames
2600 		 * successfully by eventually preferring slower rates.
2601 		 * This itself should also alleviate congestion on the bus.
2602 		 */
2603 		if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2604 		                             ATH9K_TX_DELIM_UNDERRUN)) &&
2605 		    ieee80211_is_data(hdr->frame_control) &&
2606 		    ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2607 			tx_info->status.rates[tx_rateindex].count =
2608 				hw->max_rate_tries;
2609 	}
2610 }
2611 
ath_tx_processq(struct ath_softc * sc,struct ath_txq * txq)2612 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2613 {
2614 	struct ath_hw *ah = sc->sc_ah;
2615 	struct ath_common *common = ath9k_hw_common(ah);
2616 	struct ath_buf *bf, *lastbf, *bf_held = NULL;
2617 	struct list_head bf_head;
2618 	struct ath_desc *ds;
2619 	struct ath_tx_status ts;
2620 	int status;
2621 
2622 	ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2623 		txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2624 		txq->axq_link);
2625 
2626 	ath_txq_lock(sc, txq);
2627 	for (;;) {
2628 		if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2629 			break;
2630 
2631 		if (list_empty(&txq->axq_q)) {
2632 			txq->axq_link = NULL;
2633 			ath_txq_schedule(sc, txq);
2634 			break;
2635 		}
2636 		bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2637 
2638 		/*
2639 		 * There is a race condition that a BH gets scheduled
2640 		 * after sw writes TxE and before hw re-load the last
2641 		 * descriptor to get the newly chained one.
2642 		 * Software must keep the last DONE descriptor as a
2643 		 * holding descriptor - software does so by marking
2644 		 * it with the STALE flag.
2645 		 */
2646 		bf_held = NULL;
2647 		if (bf->bf_state.stale) {
2648 			bf_held = bf;
2649 			if (list_is_last(&bf_held->list, &txq->axq_q))
2650 				break;
2651 
2652 			bf = list_entry(bf_held->list.next, struct ath_buf,
2653 					list);
2654 		}
2655 
2656 		lastbf = bf->bf_lastbf;
2657 		ds = lastbf->bf_desc;
2658 
2659 		memset(&ts, 0, sizeof(ts));
2660 		status = ath9k_hw_txprocdesc(ah, ds, &ts);
2661 		if (status == -EINPROGRESS)
2662 			break;
2663 
2664 		TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2665 
2666 		/*
2667 		 * Remove ath_buf's of the same transmit unit from txq,
2668 		 * however leave the last descriptor back as the holding
2669 		 * descriptor for hw.
2670 		 */
2671 		lastbf->bf_state.stale = true;
2672 		INIT_LIST_HEAD(&bf_head);
2673 		if (!list_is_singular(&lastbf->list))
2674 			list_cut_position(&bf_head,
2675 				&txq->axq_q, lastbf->list.prev);
2676 
2677 		if (bf_held) {
2678 			list_del(&bf_held->list);
2679 			ath_tx_return_buffer(sc, bf_held);
2680 		}
2681 
2682 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2683 	}
2684 	ath_txq_unlock_complete(sc, txq);
2685 }
2686 
ath_tx_tasklet(struct ath_softc * sc)2687 void ath_tx_tasklet(struct ath_softc *sc)
2688 {
2689 	struct ath_hw *ah = sc->sc_ah;
2690 	u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2691 	int i;
2692 
2693 	rcu_read_lock();
2694 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2695 		if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2696 			ath_tx_processq(sc, &sc->tx.txq[i]);
2697 	}
2698 	rcu_read_unlock();
2699 }
2700 
ath_tx_edma_tasklet(struct ath_softc * sc)2701 void ath_tx_edma_tasklet(struct ath_softc *sc)
2702 {
2703 	struct ath_tx_status ts;
2704 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2705 	struct ath_hw *ah = sc->sc_ah;
2706 	struct ath_txq *txq;
2707 	struct ath_buf *bf, *lastbf;
2708 	struct list_head bf_head;
2709 	struct list_head *fifo_list;
2710 	int status;
2711 
2712 	rcu_read_lock();
2713 	for (;;) {
2714 		if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2715 			break;
2716 
2717 		status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2718 		if (status == -EINPROGRESS)
2719 			break;
2720 		if (status == -EIO) {
2721 			ath_dbg(common, XMIT, "Error processing tx status\n");
2722 			break;
2723 		}
2724 
2725 		/* Process beacon completions separately */
2726 		if (ts.qid == sc->beacon.beaconq) {
2727 			sc->beacon.tx_processed = true;
2728 			sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2729 
2730 			if (ath9k_is_chanctx_enabled()) {
2731 				ath_chanctx_event(sc, NULL,
2732 						  ATH_CHANCTX_EVENT_BEACON_SENT);
2733 			}
2734 
2735 			ath9k_csa_update(sc);
2736 			continue;
2737 		}
2738 
2739 		txq = &sc->tx.txq[ts.qid];
2740 
2741 		ath_txq_lock(sc, txq);
2742 
2743 		TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2744 
2745 		fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2746 		if (list_empty(fifo_list)) {
2747 			ath_txq_unlock(sc, txq);
2748 			break;
2749 		}
2750 
2751 		bf = list_first_entry(fifo_list, struct ath_buf, list);
2752 		if (bf->bf_state.stale) {
2753 			list_del(&bf->list);
2754 			ath_tx_return_buffer(sc, bf);
2755 			bf = list_first_entry(fifo_list, struct ath_buf, list);
2756 		}
2757 
2758 		lastbf = bf->bf_lastbf;
2759 
2760 		INIT_LIST_HEAD(&bf_head);
2761 		if (list_is_last(&lastbf->list, fifo_list)) {
2762 			list_splice_tail_init(fifo_list, &bf_head);
2763 			INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2764 
2765 			if (!list_empty(&txq->axq_q)) {
2766 				struct list_head bf_q;
2767 
2768 				INIT_LIST_HEAD(&bf_q);
2769 				txq->axq_link = NULL;
2770 				list_splice_tail_init(&txq->axq_q, &bf_q);
2771 				ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2772 			}
2773 		} else {
2774 			lastbf->bf_state.stale = true;
2775 			if (bf != lastbf)
2776 				list_cut_position(&bf_head, fifo_list,
2777 						  lastbf->list.prev);
2778 		}
2779 
2780 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2781 		ath_txq_unlock_complete(sc, txq);
2782 	}
2783 	rcu_read_unlock();
2784 }
2785 
2786 /*****************/
2787 /* Init, Cleanup */
2788 /*****************/
2789 
ath_txstatus_setup(struct ath_softc * sc,int size)2790 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2791 {
2792 	struct ath_descdma *dd = &sc->txsdma;
2793 	u8 txs_len = sc->sc_ah->caps.txs_len;
2794 
2795 	dd->dd_desc_len = size * txs_len;
2796 	dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2797 					  &dd->dd_desc_paddr, GFP_KERNEL);
2798 	if (!dd->dd_desc)
2799 		return -ENOMEM;
2800 
2801 	return 0;
2802 }
2803 
ath_tx_edma_init(struct ath_softc * sc)2804 static int ath_tx_edma_init(struct ath_softc *sc)
2805 {
2806 	int err;
2807 
2808 	err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2809 	if (!err)
2810 		ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2811 					  sc->txsdma.dd_desc_paddr,
2812 					  ATH_TXSTATUS_RING_SIZE);
2813 
2814 	return err;
2815 }
2816 
ath_tx_init(struct ath_softc * sc,int nbufs)2817 int ath_tx_init(struct ath_softc *sc, int nbufs)
2818 {
2819 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2820 	int error = 0;
2821 
2822 	spin_lock_init(&sc->tx.txbuflock);
2823 
2824 	error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2825 				  "tx", nbufs, 1, 1);
2826 	if (error != 0) {
2827 		ath_err(common,
2828 			"Failed to allocate tx descriptors: %d\n", error);
2829 		return error;
2830 	}
2831 
2832 	error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2833 				  "beacon", ATH_BCBUF, 1, 1);
2834 	if (error != 0) {
2835 		ath_err(common,
2836 			"Failed to allocate beacon descriptors: %d\n", error);
2837 		return error;
2838 	}
2839 
2840 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2841 		error = ath_tx_edma_init(sc);
2842 
2843 	return error;
2844 }
2845 
ath_tx_node_init(struct ath_softc * sc,struct ath_node * an)2846 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2847 {
2848 	struct ath_atx_tid *tid;
2849 	int tidno, acno;
2850 
2851 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2852 		tid = ath_node_to_tid(an, tidno);
2853 		tid->an        = an;
2854 		tid->tidno     = tidno;
2855 		tid->seq_start = tid->seq_next = 0;
2856 		tid->baw_size  = WME_MAX_BA;
2857 		tid->baw_head  = tid->baw_tail = 0;
2858 		tid->active	   = false;
2859 		tid->clear_ps_filter = true;
2860 		__skb_queue_head_init(&tid->retry_q);
2861 		INIT_LIST_HEAD(&tid->list);
2862 		acno = TID_TO_WME_AC(tidno);
2863 		tid->txq = sc->tx.txq_map[acno];
2864 
2865 		if (!an->sta)
2866 			break; /* just one multicast ath_atx_tid */
2867 	}
2868 }
2869 
ath_tx_node_cleanup(struct ath_softc * sc,struct ath_node * an)2870 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2871 {
2872 	struct ath_atx_tid *tid;
2873 	struct ath_txq *txq;
2874 	int tidno;
2875 
2876 	rcu_read_lock();
2877 
2878 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2879 		tid = ath_node_to_tid(an, tidno);
2880 		txq = tid->txq;
2881 
2882 		ath_txq_lock(sc, txq);
2883 
2884 		if (!list_empty(&tid->list))
2885 			list_del_init(&tid->list);
2886 
2887 		ath_tid_drain(sc, txq, tid);
2888 		tid->active = false;
2889 
2890 		ath_txq_unlock(sc, txq);
2891 
2892 		if (!an->sta)
2893 			break; /* just one multicast ath_atx_tid */
2894 	}
2895 
2896 	rcu_read_unlock();
2897 }
2898 
2899 #ifdef CONFIG_ATH9K_TX99
2900 
ath9k_tx99_send(struct ath_softc * sc,struct sk_buff * skb,struct ath_tx_control * txctl)2901 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2902 		    struct ath_tx_control *txctl)
2903 {
2904 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2905 	struct ath_frame_info *fi = get_frame_info(skb);
2906 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2907 	struct ath_buf *bf;
2908 	int padpos, padsize;
2909 
2910 	padpos = ieee80211_hdrlen(hdr->frame_control);
2911 	padsize = padpos & 3;
2912 
2913 	if (padsize && skb->len > padpos) {
2914 		if (skb_headroom(skb) < padsize) {
2915 			ath_dbg(common, XMIT,
2916 				"tx99 padding failed\n");
2917 			return -EINVAL;
2918 		}
2919 
2920 		skb_push(skb, padsize);
2921 		memmove(skb->data, skb->data + padsize, padpos);
2922 	}
2923 
2924 	fi->keyix = ATH9K_TXKEYIX_INVALID;
2925 	fi->framelen = skb->len + FCS_LEN;
2926 	fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2927 
2928 	bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2929 	if (!bf) {
2930 		ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2931 		return -EINVAL;
2932 	}
2933 
2934 	ath_set_rates(sc->tx99_vif, NULL, bf);
2935 
2936 	ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2937 	ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2938 
2939 	ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2940 
2941 	return 0;
2942 }
2943 
2944 #endif /* CONFIG_ATH9K_TX99 */
2945