1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22
ath_is_alt_ant_ratio_better(int alt_ratio,int maxdelta,int mindelta,int main_rssi_avg,int alt_rssi_avg,int pkt_count)23 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26 {
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30 }
31
ath_ant_div_comb_alt_check(u8 div_group,int alt_ratio,int curr_main_set,int curr_alt_set,int alt_rssi_avg,int main_rssi_avg)32 static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35 {
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
43 case 2:
44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58 }
59
ath9k_check_auto_sleep(struct ath_softc * sc)60 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61 {
62 return sc->ps_enabled &&
63 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
64 }
65
66 /*
67 * Setup and link descriptors.
68 *
69 * 11N: we can no longer afford to self link the last descriptor.
70 * MAC acknowledges BA status as long as it copies frames to host
71 * buffer (or rx fifo). This can incorrectly acknowledge packets
72 * to a sender if last desc is self-linked.
73 */
ath_rx_buf_link(struct ath_softc * sc,struct ath_buf * bf)74 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
75 {
76 struct ath_hw *ah = sc->sc_ah;
77 struct ath_common *common = ath9k_hw_common(ah);
78 struct ath_desc *ds;
79 struct sk_buff *skb;
80
81 ds = bf->bf_desc;
82 ds->ds_link = 0; /* link to null */
83 ds->ds_data = bf->bf_buf_addr;
84
85 /* virtual addr of the beginning of the buffer. */
86 skb = bf->bf_mpdu;
87 BUG_ON(skb == NULL);
88 ds->ds_vdata = skb->data;
89
90 /*
91 * setup rx descriptors. The rx_bufsize here tells the hardware
92 * how much data it can DMA to us and that we are prepared
93 * to process
94 */
95 ath9k_hw_setuprxdesc(ah, ds,
96 common->rx_bufsize,
97 0);
98
99 if (sc->rx.rxlink == NULL)
100 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
101 else
102 *sc->rx.rxlink = bf->bf_daddr;
103
104 sc->rx.rxlink = &ds->ds_link;
105 }
106
ath_rx_buf_relink(struct ath_softc * sc,struct ath_buf * bf)107 static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_buf *bf)
108 {
109 if (sc->rx.buf_hold)
110 ath_rx_buf_link(sc, sc->rx.buf_hold);
111
112 sc->rx.buf_hold = bf;
113 }
114
ath_setdefantenna(struct ath_softc * sc,u32 antenna)115 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
116 {
117 /* XXX block beacon interrupts */
118 ath9k_hw_setantenna(sc->sc_ah, antenna);
119 sc->rx.defant = antenna;
120 sc->rx.rxotherant = 0;
121 }
122
ath_opmode_init(struct ath_softc * sc)123 static void ath_opmode_init(struct ath_softc *sc)
124 {
125 struct ath_hw *ah = sc->sc_ah;
126 struct ath_common *common = ath9k_hw_common(ah);
127
128 u32 rfilt, mfilt[2];
129
130 /* configure rx filter */
131 rfilt = ath_calcrxfilter(sc);
132 ath9k_hw_setrxfilter(ah, rfilt);
133
134 /* configure bssid mask */
135 ath_hw_setbssidmask(common);
136
137 /* configure operational mode */
138 ath9k_hw_setopmode(ah);
139
140 /* calculate and install multicast filter */
141 mfilt[0] = mfilt[1] = ~0;
142 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
143 }
144
ath_rx_edma_buf_link(struct ath_softc * sc,enum ath9k_rx_qtype qtype)145 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
146 enum ath9k_rx_qtype qtype)
147 {
148 struct ath_hw *ah = sc->sc_ah;
149 struct ath_rx_edma *rx_edma;
150 struct sk_buff *skb;
151 struct ath_buf *bf;
152
153 rx_edma = &sc->rx.rx_edma[qtype];
154 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
155 return false;
156
157 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
158 list_del_init(&bf->list);
159
160 skb = bf->bf_mpdu;
161
162 memset(skb->data, 0, ah->caps.rx_status_len);
163 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
164 ah->caps.rx_status_len, DMA_TO_DEVICE);
165
166 SKB_CB_ATHBUF(skb) = bf;
167 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
168 skb_queue_tail(&rx_edma->rx_fifo, skb);
169
170 return true;
171 }
172
ath_rx_addbuffer_edma(struct ath_softc * sc,enum ath9k_rx_qtype qtype,int size)173 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
174 enum ath9k_rx_qtype qtype, int size)
175 {
176 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
177 struct ath_buf *bf, *tbf;
178
179 if (list_empty(&sc->rx.rxbuf)) {
180 ath_dbg(common, QUEUE, "No free rx buf available\n");
181 return;
182 }
183
184 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
185 if (!ath_rx_edma_buf_link(sc, qtype))
186 break;
187
188 }
189
ath_rx_remove_buffer(struct ath_softc * sc,enum ath9k_rx_qtype qtype)190 static void ath_rx_remove_buffer(struct ath_softc *sc,
191 enum ath9k_rx_qtype qtype)
192 {
193 struct ath_buf *bf;
194 struct ath_rx_edma *rx_edma;
195 struct sk_buff *skb;
196
197 rx_edma = &sc->rx.rx_edma[qtype];
198
199 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
200 bf = SKB_CB_ATHBUF(skb);
201 BUG_ON(!bf);
202 list_add_tail(&bf->list, &sc->rx.rxbuf);
203 }
204 }
205
ath_rx_edma_cleanup(struct ath_softc * sc)206 static void ath_rx_edma_cleanup(struct ath_softc *sc)
207 {
208 struct ath_hw *ah = sc->sc_ah;
209 struct ath_common *common = ath9k_hw_common(ah);
210 struct ath_buf *bf;
211
212 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
213 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
214
215 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
216 if (bf->bf_mpdu) {
217 dma_unmap_single(sc->dev, bf->bf_buf_addr,
218 common->rx_bufsize,
219 DMA_BIDIRECTIONAL);
220 dev_kfree_skb_any(bf->bf_mpdu);
221 bf->bf_buf_addr = 0;
222 bf->bf_mpdu = NULL;
223 }
224 }
225
226 INIT_LIST_HEAD(&sc->rx.rxbuf);
227
228 kfree(sc->rx.rx_bufptr);
229 sc->rx.rx_bufptr = NULL;
230 }
231
ath_rx_edma_init_queue(struct ath_rx_edma * rx_edma,int size)232 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
233 {
234 skb_queue_head_init(&rx_edma->rx_fifo);
235 rx_edma->rx_fifo_hwsize = size;
236 }
237
ath_rx_edma_init(struct ath_softc * sc,int nbufs)238 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
239 {
240 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
241 struct ath_hw *ah = sc->sc_ah;
242 struct sk_buff *skb;
243 struct ath_buf *bf;
244 int error = 0, i;
245 u32 size;
246
247 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
248 ah->caps.rx_status_len);
249
250 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
251 ah->caps.rx_lp_qdepth);
252 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
253 ah->caps.rx_hp_qdepth);
254
255 size = sizeof(struct ath_buf) * nbufs;
256 bf = kzalloc(size, GFP_KERNEL);
257 if (!bf)
258 return -ENOMEM;
259
260 INIT_LIST_HEAD(&sc->rx.rxbuf);
261 sc->rx.rx_bufptr = bf;
262
263 for (i = 0; i < nbufs; i++, bf++) {
264 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
265 if (!skb) {
266 error = -ENOMEM;
267 goto rx_init_fail;
268 }
269
270 memset(skb->data, 0, common->rx_bufsize);
271 bf->bf_mpdu = skb;
272
273 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
274 common->rx_bufsize,
275 DMA_BIDIRECTIONAL);
276 if (unlikely(dma_mapping_error(sc->dev,
277 bf->bf_buf_addr))) {
278 dev_kfree_skb_any(skb);
279 bf->bf_mpdu = NULL;
280 bf->bf_buf_addr = 0;
281 ath_err(common,
282 "dma_mapping_error() on RX init\n");
283 error = -ENOMEM;
284 goto rx_init_fail;
285 }
286
287 list_add_tail(&bf->list, &sc->rx.rxbuf);
288 }
289
290 return 0;
291
292 rx_init_fail:
293 ath_rx_edma_cleanup(sc);
294 return error;
295 }
296
ath_edma_start_recv(struct ath_softc * sc)297 static void ath_edma_start_recv(struct ath_softc *sc)
298 {
299 spin_lock_bh(&sc->rx.rxbuflock);
300
301 ath9k_hw_rxena(sc->sc_ah);
302
303 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
304 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
305
306 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
307 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
308
309 ath_opmode_init(sc);
310
311 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
312
313 spin_unlock_bh(&sc->rx.rxbuflock);
314 }
315
ath_edma_stop_recv(struct ath_softc * sc)316 static void ath_edma_stop_recv(struct ath_softc *sc)
317 {
318 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
319 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
320 }
321
ath_rx_init(struct ath_softc * sc,int nbufs)322 int ath_rx_init(struct ath_softc *sc, int nbufs)
323 {
324 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
325 struct sk_buff *skb;
326 struct ath_buf *bf;
327 int error = 0;
328
329 spin_lock_init(&sc->sc_pcu_lock);
330 sc->sc_flags &= ~SC_OP_RXFLUSH;
331 spin_lock_init(&sc->rx.rxbuflock);
332
333 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
334 sc->sc_ah->caps.rx_status_len;
335
336 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
337 return ath_rx_edma_init(sc, nbufs);
338 } else {
339 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
340 common->cachelsz, common->rx_bufsize);
341
342 /* Initialize rx descriptors */
343
344 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
345 "rx", nbufs, 1, 0);
346 if (error != 0) {
347 ath_err(common,
348 "failed to allocate rx descriptors: %d\n",
349 error);
350 goto err;
351 }
352
353 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
354 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
355 GFP_KERNEL);
356 if (skb == NULL) {
357 error = -ENOMEM;
358 goto err;
359 }
360
361 bf->bf_mpdu = skb;
362 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
363 common->rx_bufsize,
364 DMA_FROM_DEVICE);
365 if (unlikely(dma_mapping_error(sc->dev,
366 bf->bf_buf_addr))) {
367 dev_kfree_skb_any(skb);
368 bf->bf_mpdu = NULL;
369 bf->bf_buf_addr = 0;
370 ath_err(common,
371 "dma_mapping_error() on RX init\n");
372 error = -ENOMEM;
373 goto err;
374 }
375 }
376 sc->rx.rxlink = NULL;
377 }
378
379 err:
380 if (error)
381 ath_rx_cleanup(sc);
382
383 return error;
384 }
385
ath_rx_cleanup(struct ath_softc * sc)386 void ath_rx_cleanup(struct ath_softc *sc)
387 {
388 struct ath_hw *ah = sc->sc_ah;
389 struct ath_common *common = ath9k_hw_common(ah);
390 struct sk_buff *skb;
391 struct ath_buf *bf;
392
393 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
394 ath_rx_edma_cleanup(sc);
395 return;
396 } else {
397 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
398 skb = bf->bf_mpdu;
399 if (skb) {
400 dma_unmap_single(sc->dev, bf->bf_buf_addr,
401 common->rx_bufsize,
402 DMA_FROM_DEVICE);
403 dev_kfree_skb(skb);
404 bf->bf_buf_addr = 0;
405 bf->bf_mpdu = NULL;
406 }
407 }
408
409 if (sc->rx.rxdma.dd_desc_len != 0)
410 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
411 }
412 }
413
414 /*
415 * Calculate the receive filter according to the
416 * operating mode and state:
417 *
418 * o always accept unicast, broadcast, and multicast traffic
419 * o maintain current state of phy error reception (the hal
420 * may enable phy error frames for noise immunity work)
421 * o probe request frames are accepted only when operating in
422 * hostap, adhoc, or monitor modes
423 * o enable promiscuous mode according to the interface state
424 * o accept beacons:
425 * - when operating in adhoc mode so the 802.11 layer creates
426 * node table entries for peers,
427 * - when operating in station mode for collecting rssi data when
428 * the station is otherwise quiet, or
429 * - when operating as a repeater so we see repeater-sta beacons
430 * - when scanning
431 */
432
ath_calcrxfilter(struct ath_softc * sc)433 u32 ath_calcrxfilter(struct ath_softc *sc)
434 {
435 u32 rfilt;
436
437 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
438 | ATH9K_RX_FILTER_MCAST;
439
440 if (sc->rx.rxfilter & FIF_PROBE_REQ)
441 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
442
443 /*
444 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
445 * mode interface or when in monitor mode. AP mode does not need this
446 * since it receives all in-BSS frames anyway.
447 */
448 if (sc->sc_ah->is_monitoring)
449 rfilt |= ATH9K_RX_FILTER_PROM;
450
451 if (sc->rx.rxfilter & FIF_CONTROL)
452 rfilt |= ATH9K_RX_FILTER_CONTROL;
453
454 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
455 (sc->nvifs <= 1) &&
456 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
457 rfilt |= ATH9K_RX_FILTER_MYBEACON;
458 else
459 rfilt |= ATH9K_RX_FILTER_BEACON;
460
461 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
462 (sc->rx.rxfilter & FIF_PSPOLL))
463 rfilt |= ATH9K_RX_FILTER_PSPOLL;
464
465 if (conf_is_ht(&sc->hw->conf))
466 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
467
468 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
469 /* The following may also be needed for other older chips */
470 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
471 rfilt |= ATH9K_RX_FILTER_PROM;
472 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
473 }
474
475 return rfilt;
476
477 }
478
ath_startrecv(struct ath_softc * sc)479 int ath_startrecv(struct ath_softc *sc)
480 {
481 struct ath_hw *ah = sc->sc_ah;
482 struct ath_buf *bf, *tbf;
483
484 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
485 ath_edma_start_recv(sc);
486 return 0;
487 }
488
489 spin_lock_bh(&sc->rx.rxbuflock);
490 if (list_empty(&sc->rx.rxbuf))
491 goto start_recv;
492
493 sc->rx.buf_hold = NULL;
494 sc->rx.rxlink = NULL;
495 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
496 ath_rx_buf_link(sc, bf);
497 }
498
499 /* We could have deleted elements so the list may be empty now */
500 if (list_empty(&sc->rx.rxbuf))
501 goto start_recv;
502
503 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
504 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
505 ath9k_hw_rxena(ah);
506
507 start_recv:
508 ath_opmode_init(sc);
509 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
510
511 spin_unlock_bh(&sc->rx.rxbuflock);
512
513 return 0;
514 }
515
ath_stoprecv(struct ath_softc * sc)516 bool ath_stoprecv(struct ath_softc *sc)
517 {
518 struct ath_hw *ah = sc->sc_ah;
519 bool stopped, reset = false;
520
521 spin_lock_bh(&sc->rx.rxbuflock);
522 ath9k_hw_abortpcurecv(ah);
523 ath9k_hw_setrxfilter(ah, 0);
524 stopped = ath9k_hw_stopdmarecv(ah, &reset);
525
526 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
527 ath_edma_stop_recv(sc);
528 else
529 sc->rx.rxlink = NULL;
530 spin_unlock_bh(&sc->rx.rxbuflock);
531
532 if (!(ah->ah_flags & AH_UNPLUGGED) &&
533 unlikely(!stopped)) {
534 ath_err(ath9k_hw_common(sc->sc_ah),
535 "Could not stop RX, we could be "
536 "confusing the DMA engine when we start RX up\n");
537 ATH_DBG_WARN_ON_ONCE(!stopped);
538 }
539 return stopped && !reset;
540 }
541
ath_flushrecv(struct ath_softc * sc)542 void ath_flushrecv(struct ath_softc *sc)
543 {
544 sc->sc_flags |= SC_OP_RXFLUSH;
545 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
546 ath_rx_tasklet(sc, 1, true);
547 ath_rx_tasklet(sc, 1, false);
548 sc->sc_flags &= ~SC_OP_RXFLUSH;
549 }
550
ath_beacon_dtim_pending_cab(struct sk_buff * skb)551 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
552 {
553 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
554 struct ieee80211_mgmt *mgmt;
555 u8 *pos, *end, id, elen;
556 struct ieee80211_tim_ie *tim;
557
558 mgmt = (struct ieee80211_mgmt *)skb->data;
559 pos = mgmt->u.beacon.variable;
560 end = skb->data + skb->len;
561
562 while (pos + 2 < end) {
563 id = *pos++;
564 elen = *pos++;
565 if (pos + elen > end)
566 break;
567
568 if (id == WLAN_EID_TIM) {
569 if (elen < sizeof(*tim))
570 break;
571 tim = (struct ieee80211_tim_ie *) pos;
572 if (tim->dtim_count != 0)
573 break;
574 return tim->bitmap_ctrl & 0x01;
575 }
576
577 pos += elen;
578 }
579
580 return false;
581 }
582
ath_rx_ps_beacon(struct ath_softc * sc,struct sk_buff * skb)583 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
584 {
585 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
586
587 if (skb->len < 24 + 8 + 2 + 2)
588 return;
589
590 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
591
592 if (sc->ps_flags & PS_BEACON_SYNC) {
593 sc->ps_flags &= ~PS_BEACON_SYNC;
594 ath_dbg(common, PS,
595 "Reconfigure Beacon timers based on timestamp from the AP\n");
596 ath_set_beacon(sc);
597 }
598
599 if (ath_beacon_dtim_pending_cab(skb)) {
600 /*
601 * Remain awake waiting for buffered broadcast/multicast
602 * frames. If the last broadcast/multicast frame is not
603 * received properly, the next beacon frame will work as
604 * a backup trigger for returning into NETWORK SLEEP state,
605 * so we are waiting for it as well.
606 */
607 ath_dbg(common, PS,
608 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
609 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
610 return;
611 }
612
613 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
614 /*
615 * This can happen if a broadcast frame is dropped or the AP
616 * fails to send a frame indicating that all CAB frames have
617 * been delivered.
618 */
619 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
620 ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
621 }
622 }
623
ath_rx_ps(struct ath_softc * sc,struct sk_buff * skb,bool mybeacon)624 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
625 {
626 struct ieee80211_hdr *hdr;
627 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
628
629 hdr = (struct ieee80211_hdr *)skb->data;
630
631 /* Process Beacon and CAB receive in PS state */
632 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
633 && mybeacon)
634 ath_rx_ps_beacon(sc, skb);
635 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
636 (ieee80211_is_data(hdr->frame_control) ||
637 ieee80211_is_action(hdr->frame_control)) &&
638 is_multicast_ether_addr(hdr->addr1) &&
639 !ieee80211_has_moredata(hdr->frame_control)) {
640 /*
641 * No more broadcast/multicast frames to be received at this
642 * point.
643 */
644 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
645 ath_dbg(common, PS,
646 "All PS CAB frames received, back to sleep\n");
647 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
648 !is_multicast_ether_addr(hdr->addr1) &&
649 !ieee80211_has_morefrags(hdr->frame_control)) {
650 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
651 ath_dbg(common, PS,
652 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
653 sc->ps_flags & (PS_WAIT_FOR_BEACON |
654 PS_WAIT_FOR_CAB |
655 PS_WAIT_FOR_PSPOLL_DATA |
656 PS_WAIT_FOR_TX_ACK));
657 }
658 }
659
ath_edma_get_buffers(struct ath_softc * sc,enum ath9k_rx_qtype qtype,struct ath_rx_status * rs,struct ath_buf ** dest)660 static bool ath_edma_get_buffers(struct ath_softc *sc,
661 enum ath9k_rx_qtype qtype,
662 struct ath_rx_status *rs,
663 struct ath_buf **dest)
664 {
665 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
666 struct ath_hw *ah = sc->sc_ah;
667 struct ath_common *common = ath9k_hw_common(ah);
668 struct sk_buff *skb;
669 struct ath_buf *bf;
670 int ret;
671
672 skb = skb_peek(&rx_edma->rx_fifo);
673 if (!skb)
674 return false;
675
676 bf = SKB_CB_ATHBUF(skb);
677 BUG_ON(!bf);
678
679 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
680 common->rx_bufsize, DMA_FROM_DEVICE);
681
682 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
683 if (ret == -EINPROGRESS) {
684 /*let device gain the buffer again*/
685 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
686 common->rx_bufsize, DMA_FROM_DEVICE);
687 return false;
688 }
689
690 __skb_unlink(skb, &rx_edma->rx_fifo);
691 if (ret == -EINVAL) {
692 /* corrupt descriptor, skip this one and the following one */
693 list_add_tail(&bf->list, &sc->rx.rxbuf);
694 ath_rx_edma_buf_link(sc, qtype);
695
696 skb = skb_peek(&rx_edma->rx_fifo);
697 if (skb) {
698 bf = SKB_CB_ATHBUF(skb);
699 BUG_ON(!bf);
700
701 __skb_unlink(skb, &rx_edma->rx_fifo);
702 list_add_tail(&bf->list, &sc->rx.rxbuf);
703 ath_rx_edma_buf_link(sc, qtype);
704 }
705
706 bf = NULL;
707 }
708
709 *dest = bf;
710 return true;
711 }
712
ath_edma_get_next_rx_buf(struct ath_softc * sc,struct ath_rx_status * rs,enum ath9k_rx_qtype qtype)713 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
714 struct ath_rx_status *rs,
715 enum ath9k_rx_qtype qtype)
716 {
717 struct ath_buf *bf = NULL;
718
719 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
720 if (!bf)
721 continue;
722
723 return bf;
724 }
725 return NULL;
726 }
727
ath_get_next_rx_buf(struct ath_softc * sc,struct ath_rx_status * rs)728 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
729 struct ath_rx_status *rs)
730 {
731 struct ath_hw *ah = sc->sc_ah;
732 struct ath_common *common = ath9k_hw_common(ah);
733 struct ath_desc *ds;
734 struct ath_buf *bf;
735 int ret;
736
737 if (list_empty(&sc->rx.rxbuf)) {
738 sc->rx.rxlink = NULL;
739 return NULL;
740 }
741
742 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
743 if (bf == sc->rx.buf_hold)
744 return NULL;
745
746 ds = bf->bf_desc;
747
748 /*
749 * Must provide the virtual address of the current
750 * descriptor, the physical address, and the virtual
751 * address of the next descriptor in the h/w chain.
752 * This allows the HAL to look ahead to see if the
753 * hardware is done with a descriptor by checking the
754 * done bit in the following descriptor and the address
755 * of the current descriptor the DMA engine is working
756 * on. All this is necessary because of our use of
757 * a self-linked list to avoid rx overruns.
758 */
759 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
760 if (ret == -EINPROGRESS) {
761 struct ath_rx_status trs;
762 struct ath_buf *tbf;
763 struct ath_desc *tds;
764
765 memset(&trs, 0, sizeof(trs));
766 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
767 sc->rx.rxlink = NULL;
768 return NULL;
769 }
770
771 tbf = list_entry(bf->list.next, struct ath_buf, list);
772
773 /*
774 * On some hardware the descriptor status words could
775 * get corrupted, including the done bit. Because of
776 * this, check if the next descriptor's done bit is
777 * set or not.
778 *
779 * If the next descriptor's done bit is set, the current
780 * descriptor has been corrupted. Force s/w to discard
781 * this descriptor and continue...
782 */
783
784 tds = tbf->bf_desc;
785 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
786 if (ret == -EINPROGRESS)
787 return NULL;
788 }
789
790 list_del(&bf->list);
791 if (!bf->bf_mpdu)
792 return bf;
793
794 /*
795 * Synchronize the DMA transfer with CPU before
796 * 1. accessing the frame
797 * 2. requeueing the same buffer to h/w
798 */
799 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
800 common->rx_bufsize,
801 DMA_FROM_DEVICE);
802
803 return bf;
804 }
805
806 /* Assumes you've already done the endian to CPU conversion */
ath9k_rx_accept(struct ath_common * common,struct ieee80211_hdr * hdr,struct ieee80211_rx_status * rxs,struct ath_rx_status * rx_stats,bool * decrypt_error)807 static bool ath9k_rx_accept(struct ath_common *common,
808 struct ieee80211_hdr *hdr,
809 struct ieee80211_rx_status *rxs,
810 struct ath_rx_status *rx_stats,
811 bool *decrypt_error)
812 {
813 struct ath_softc *sc = (struct ath_softc *) common->priv;
814 bool is_mc, is_valid_tkip, strip_mic, mic_error;
815 struct ath_hw *ah = common->ah;
816 __le16 fc;
817 u8 rx_status_len = ah->caps.rx_status_len;
818
819 fc = hdr->frame_control;
820
821 is_mc = !!is_multicast_ether_addr(hdr->addr1);
822 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
823 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
824 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
825 !(rx_stats->rs_status &
826 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
827 ATH9K_RXERR_KEYMISS));
828
829 /*
830 * Key miss events are only relevant for pairwise keys where the
831 * descriptor does contain a valid key index. This has been observed
832 * mostly with CCMP encryption.
833 */
834 if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID ||
835 !test_bit(rx_stats->rs_keyix, common->ccmp_keymap))
836 rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS;
837
838 if (!rx_stats->rs_datalen)
839 return false;
840 /*
841 * rs_status follows rs_datalen so if rs_datalen is too large
842 * we can take a hint that hardware corrupted it, so ignore
843 * those frames.
844 */
845 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
846 return false;
847
848 /* Only use error bits from the last fragment */
849 if (rx_stats->rs_more)
850 return true;
851
852 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
853 !ieee80211_has_morefrags(fc) &&
854 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
855 (rx_stats->rs_status & ATH9K_RXERR_MIC);
856
857 /*
858 * The rx_stats->rs_status will not be set until the end of the
859 * chained descriptors so it can be ignored if rs_more is set. The
860 * rs_more will be false at the last element of the chained
861 * descriptors.
862 */
863 if (rx_stats->rs_status != 0) {
864 u8 status_mask;
865
866 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
867 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
868 mic_error = false;
869 }
870 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
871 return false;
872
873 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
874 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
875 *decrypt_error = true;
876 mic_error = false;
877 }
878
879 /*
880 * Reject error frames with the exception of
881 * decryption and MIC failures. For monitor mode,
882 * we also ignore the CRC error.
883 */
884 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
885 ATH9K_RXERR_KEYMISS;
886
887 if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
888 status_mask |= ATH9K_RXERR_CRC;
889
890 if (rx_stats->rs_status & ~status_mask)
891 return false;
892 }
893
894 /*
895 * For unicast frames the MIC error bit can have false positives,
896 * so all MIC error reports need to be validated in software.
897 * False negatives are not common, so skip software verification
898 * if the hardware considers the MIC valid.
899 */
900 if (strip_mic)
901 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
902 else if (is_mc && mic_error)
903 rxs->flag |= RX_FLAG_MMIC_ERROR;
904
905 return true;
906 }
907
ath9k_process_rate(struct ath_common * common,struct ieee80211_hw * hw,struct ath_rx_status * rx_stats,struct ieee80211_rx_status * rxs)908 static int ath9k_process_rate(struct ath_common *common,
909 struct ieee80211_hw *hw,
910 struct ath_rx_status *rx_stats,
911 struct ieee80211_rx_status *rxs)
912 {
913 struct ieee80211_supported_band *sband;
914 enum ieee80211_band band;
915 unsigned int i = 0;
916
917 band = hw->conf.channel->band;
918 sband = hw->wiphy->bands[band];
919
920 if (rx_stats->rs_rate & 0x80) {
921 /* HT rate */
922 rxs->flag |= RX_FLAG_HT;
923 if (rx_stats->rs_flags & ATH9K_RX_2040)
924 rxs->flag |= RX_FLAG_40MHZ;
925 if (rx_stats->rs_flags & ATH9K_RX_GI)
926 rxs->flag |= RX_FLAG_SHORT_GI;
927 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
928 return 0;
929 }
930
931 for (i = 0; i < sband->n_bitrates; i++) {
932 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
933 rxs->rate_idx = i;
934 return 0;
935 }
936 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
937 rxs->flag |= RX_FLAG_SHORTPRE;
938 rxs->rate_idx = i;
939 return 0;
940 }
941 }
942
943 /*
944 * No valid hardware bitrate found -- we should not get here
945 * because hardware has already validated this frame as OK.
946 */
947 ath_dbg(common, ANY,
948 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
949 rx_stats->rs_rate);
950
951 return -EINVAL;
952 }
953
ath9k_process_rssi(struct ath_common * common,struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ath_rx_status * rx_stats)954 static void ath9k_process_rssi(struct ath_common *common,
955 struct ieee80211_hw *hw,
956 struct ieee80211_hdr *hdr,
957 struct ath_rx_status *rx_stats)
958 {
959 struct ath_softc *sc = hw->priv;
960 struct ath_hw *ah = common->ah;
961 int last_rssi;
962 int rssi = rx_stats->rs_rssi;
963
964 if (!rx_stats->is_mybeacon ||
965 ((ah->opmode != NL80211_IFTYPE_STATION) &&
966 (ah->opmode != NL80211_IFTYPE_ADHOC)))
967 return;
968
969 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
970 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
971
972 last_rssi = sc->last_rssi;
973 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
974 rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER);
975 if (rssi < 0)
976 rssi = 0;
977
978 /* Update Beacon RSSI, this is used by ANI. */
979 ah->stats.avgbrssi = rssi;
980 }
981
982 /*
983 * For Decrypt or Demic errors, we only mark packet status here and always push
984 * up the frame up to let mac80211 handle the actual error case, be it no
985 * decryption key or real decryption error. This let us keep statistics there.
986 */
ath9k_rx_skb_preprocess(struct ath_common * common,struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ath_rx_status * rx_stats,struct ieee80211_rx_status * rx_status,bool * decrypt_error)987 static int ath9k_rx_skb_preprocess(struct ath_common *common,
988 struct ieee80211_hw *hw,
989 struct ieee80211_hdr *hdr,
990 struct ath_rx_status *rx_stats,
991 struct ieee80211_rx_status *rx_status,
992 bool *decrypt_error)
993 {
994 struct ath_hw *ah = common->ah;
995
996 /*
997 * everything but the rate is checked here, the rate check is done
998 * separately to avoid doing two lookups for a rate for each frame.
999 */
1000 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1001 return -EINVAL;
1002
1003 /* Only use status info from the last fragment */
1004 if (rx_stats->rs_more)
1005 return 0;
1006
1007 ath9k_process_rssi(common, hw, hdr, rx_stats);
1008
1009 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1010 return -EINVAL;
1011
1012 rx_status->band = hw->conf.channel->band;
1013 rx_status->freq = hw->conf.channel->center_freq;
1014 rx_status->signal = ah->noise + rx_stats->rs_rssi;
1015 rx_status->antenna = rx_stats->rs_antenna;
1016 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
1017 if (rx_stats->rs_moreaggr)
1018 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
1019
1020 return 0;
1021 }
1022
ath9k_rx_skb_postprocess(struct ath_common * common,struct sk_buff * skb,struct ath_rx_status * rx_stats,struct ieee80211_rx_status * rxs,bool decrypt_error)1023 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1024 struct sk_buff *skb,
1025 struct ath_rx_status *rx_stats,
1026 struct ieee80211_rx_status *rxs,
1027 bool decrypt_error)
1028 {
1029 struct ath_hw *ah = common->ah;
1030 struct ieee80211_hdr *hdr;
1031 int hdrlen, padpos, padsize;
1032 u8 keyix;
1033 __le16 fc;
1034
1035 /* see if any padding is done by the hw and remove it */
1036 hdr = (struct ieee80211_hdr *) skb->data;
1037 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1038 fc = hdr->frame_control;
1039 padpos = ath9k_cmn_padpos(hdr->frame_control);
1040
1041 /* The MAC header is padded to have 32-bit boundary if the
1042 * packet payload is non-zero. The general calculation for
1043 * padsize would take into account odd header lengths:
1044 * padsize = (4 - padpos % 4) % 4; However, since only
1045 * even-length headers are used, padding can only be 0 or 2
1046 * bytes and we can optimize this a bit. In addition, we must
1047 * not try to remove padding from short control frames that do
1048 * not have payload. */
1049 padsize = padpos & 3;
1050 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1051 memmove(skb->data + padsize, skb->data, padpos);
1052 skb_pull(skb, padsize);
1053 }
1054
1055 keyix = rx_stats->rs_keyix;
1056
1057 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1058 ieee80211_has_protected(fc)) {
1059 rxs->flag |= RX_FLAG_DECRYPTED;
1060 } else if (ieee80211_has_protected(fc)
1061 && !decrypt_error && skb->len >= hdrlen + 4) {
1062 keyix = skb->data[hdrlen + 3] >> 6;
1063
1064 if (test_bit(keyix, common->keymap))
1065 rxs->flag |= RX_FLAG_DECRYPTED;
1066 }
1067 if (ah->sw_mgmt_crypto &&
1068 (rxs->flag & RX_FLAG_DECRYPTED) &&
1069 ieee80211_is_mgmt(fc))
1070 /* Use software decrypt for management frames. */
1071 rxs->flag &= ~RX_FLAG_DECRYPTED;
1072 }
1073
ath_lnaconf_alt_good_scan(struct ath_ant_comb * antcomb,struct ath_hw_antcomb_conf ant_conf,int main_rssi_avg)1074 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1075 struct ath_hw_antcomb_conf ant_conf,
1076 int main_rssi_avg)
1077 {
1078 antcomb->quick_scan_cnt = 0;
1079
1080 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1081 antcomb->rssi_lna2 = main_rssi_avg;
1082 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1083 antcomb->rssi_lna1 = main_rssi_avg;
1084
1085 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1086 case 0x10: /* LNA2 A-B */
1087 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1088 antcomb->first_quick_scan_conf =
1089 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1090 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1091 break;
1092 case 0x20: /* LNA1 A-B */
1093 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1094 antcomb->first_quick_scan_conf =
1095 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1096 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1097 break;
1098 case 0x21: /* LNA1 LNA2 */
1099 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1100 antcomb->first_quick_scan_conf =
1101 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1102 antcomb->second_quick_scan_conf =
1103 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1104 break;
1105 case 0x12: /* LNA2 LNA1 */
1106 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1107 antcomb->first_quick_scan_conf =
1108 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1109 antcomb->second_quick_scan_conf =
1110 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1111 break;
1112 case 0x13: /* LNA2 A+B */
1113 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1114 antcomb->first_quick_scan_conf =
1115 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1116 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1117 break;
1118 case 0x23: /* LNA1 A+B */
1119 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1120 antcomb->first_quick_scan_conf =
1121 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1122 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1123 break;
1124 default:
1125 break;
1126 }
1127 }
1128
ath_select_ant_div_from_quick_scan(struct ath_ant_comb * antcomb,struct ath_hw_antcomb_conf * div_ant_conf,int main_rssi_avg,int alt_rssi_avg,int alt_ratio)1129 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1130 struct ath_hw_antcomb_conf *div_ant_conf,
1131 int main_rssi_avg, int alt_rssi_avg,
1132 int alt_ratio)
1133 {
1134 /* alt_good */
1135 switch (antcomb->quick_scan_cnt) {
1136 case 0:
1137 /* set alt to main, and alt to first conf */
1138 div_ant_conf->main_lna_conf = antcomb->main_conf;
1139 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1140 break;
1141 case 1:
1142 /* set alt to main, and alt to first conf */
1143 div_ant_conf->main_lna_conf = antcomb->main_conf;
1144 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1145 antcomb->rssi_first = main_rssi_avg;
1146 antcomb->rssi_second = alt_rssi_avg;
1147
1148 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1149 /* main is LNA1 */
1150 if (ath_is_alt_ant_ratio_better(alt_ratio,
1151 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1152 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1153 main_rssi_avg, alt_rssi_avg,
1154 antcomb->total_pkt_count))
1155 antcomb->first_ratio = true;
1156 else
1157 antcomb->first_ratio = false;
1158 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1159 if (ath_is_alt_ant_ratio_better(alt_ratio,
1160 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1161 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1162 main_rssi_avg, alt_rssi_avg,
1163 antcomb->total_pkt_count))
1164 antcomb->first_ratio = true;
1165 else
1166 antcomb->first_ratio = false;
1167 } else {
1168 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1169 (alt_rssi_avg > main_rssi_avg +
1170 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1171 (alt_rssi_avg > main_rssi_avg)) &&
1172 (antcomb->total_pkt_count > 50))
1173 antcomb->first_ratio = true;
1174 else
1175 antcomb->first_ratio = false;
1176 }
1177 break;
1178 case 2:
1179 antcomb->alt_good = false;
1180 antcomb->scan_not_start = false;
1181 antcomb->scan = false;
1182 antcomb->rssi_first = main_rssi_avg;
1183 antcomb->rssi_third = alt_rssi_avg;
1184
1185 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1186 antcomb->rssi_lna1 = alt_rssi_avg;
1187 else if (antcomb->second_quick_scan_conf ==
1188 ATH_ANT_DIV_COMB_LNA2)
1189 antcomb->rssi_lna2 = alt_rssi_avg;
1190 else if (antcomb->second_quick_scan_conf ==
1191 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1192 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1193 antcomb->rssi_lna2 = main_rssi_avg;
1194 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1195 antcomb->rssi_lna1 = main_rssi_avg;
1196 }
1197
1198 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1199 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1200 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1201 else
1202 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1203
1204 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1205 if (ath_is_alt_ant_ratio_better(alt_ratio,
1206 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1207 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1208 main_rssi_avg, alt_rssi_avg,
1209 antcomb->total_pkt_count))
1210 antcomb->second_ratio = true;
1211 else
1212 antcomb->second_ratio = false;
1213 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1214 if (ath_is_alt_ant_ratio_better(alt_ratio,
1215 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1216 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1217 main_rssi_avg, alt_rssi_avg,
1218 antcomb->total_pkt_count))
1219 antcomb->second_ratio = true;
1220 else
1221 antcomb->second_ratio = false;
1222 } else {
1223 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1224 (alt_rssi_avg > main_rssi_avg +
1225 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1226 (alt_rssi_avg > main_rssi_avg)) &&
1227 (antcomb->total_pkt_count > 50))
1228 antcomb->second_ratio = true;
1229 else
1230 antcomb->second_ratio = false;
1231 }
1232
1233 /* set alt to the conf with maximun ratio */
1234 if (antcomb->first_ratio && antcomb->second_ratio) {
1235 if (antcomb->rssi_second > antcomb->rssi_third) {
1236 /* first alt*/
1237 if ((antcomb->first_quick_scan_conf ==
1238 ATH_ANT_DIV_COMB_LNA1) ||
1239 (antcomb->first_quick_scan_conf ==
1240 ATH_ANT_DIV_COMB_LNA2))
1241 /* Set alt LNA1 or LNA2*/
1242 if (div_ant_conf->main_lna_conf ==
1243 ATH_ANT_DIV_COMB_LNA2)
1244 div_ant_conf->alt_lna_conf =
1245 ATH_ANT_DIV_COMB_LNA1;
1246 else
1247 div_ant_conf->alt_lna_conf =
1248 ATH_ANT_DIV_COMB_LNA2;
1249 else
1250 /* Set alt to A+B or A-B */
1251 div_ant_conf->alt_lna_conf =
1252 antcomb->first_quick_scan_conf;
1253 } else if ((antcomb->second_quick_scan_conf ==
1254 ATH_ANT_DIV_COMB_LNA1) ||
1255 (antcomb->second_quick_scan_conf ==
1256 ATH_ANT_DIV_COMB_LNA2)) {
1257 /* Set alt LNA1 or LNA2 */
1258 if (div_ant_conf->main_lna_conf ==
1259 ATH_ANT_DIV_COMB_LNA2)
1260 div_ant_conf->alt_lna_conf =
1261 ATH_ANT_DIV_COMB_LNA1;
1262 else
1263 div_ant_conf->alt_lna_conf =
1264 ATH_ANT_DIV_COMB_LNA2;
1265 } else {
1266 /* Set alt to A+B or A-B */
1267 div_ant_conf->alt_lna_conf =
1268 antcomb->second_quick_scan_conf;
1269 }
1270 } else if (antcomb->first_ratio) {
1271 /* first alt */
1272 if ((antcomb->first_quick_scan_conf ==
1273 ATH_ANT_DIV_COMB_LNA1) ||
1274 (antcomb->first_quick_scan_conf ==
1275 ATH_ANT_DIV_COMB_LNA2))
1276 /* Set alt LNA1 or LNA2 */
1277 if (div_ant_conf->main_lna_conf ==
1278 ATH_ANT_DIV_COMB_LNA2)
1279 div_ant_conf->alt_lna_conf =
1280 ATH_ANT_DIV_COMB_LNA1;
1281 else
1282 div_ant_conf->alt_lna_conf =
1283 ATH_ANT_DIV_COMB_LNA2;
1284 else
1285 /* Set alt to A+B or A-B */
1286 div_ant_conf->alt_lna_conf =
1287 antcomb->first_quick_scan_conf;
1288 } else if (antcomb->second_ratio) {
1289 /* second alt */
1290 if ((antcomb->second_quick_scan_conf ==
1291 ATH_ANT_DIV_COMB_LNA1) ||
1292 (antcomb->second_quick_scan_conf ==
1293 ATH_ANT_DIV_COMB_LNA2))
1294 /* Set alt LNA1 or LNA2 */
1295 if (div_ant_conf->main_lna_conf ==
1296 ATH_ANT_DIV_COMB_LNA2)
1297 div_ant_conf->alt_lna_conf =
1298 ATH_ANT_DIV_COMB_LNA1;
1299 else
1300 div_ant_conf->alt_lna_conf =
1301 ATH_ANT_DIV_COMB_LNA2;
1302 else
1303 /* Set alt to A+B or A-B */
1304 div_ant_conf->alt_lna_conf =
1305 antcomb->second_quick_scan_conf;
1306 } else {
1307 /* main is largest */
1308 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1309 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1310 /* Set alt LNA1 or LNA2 */
1311 if (div_ant_conf->main_lna_conf ==
1312 ATH_ANT_DIV_COMB_LNA2)
1313 div_ant_conf->alt_lna_conf =
1314 ATH_ANT_DIV_COMB_LNA1;
1315 else
1316 div_ant_conf->alt_lna_conf =
1317 ATH_ANT_DIV_COMB_LNA2;
1318 else
1319 /* Set alt to A+B or A-B */
1320 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1321 }
1322 break;
1323 default:
1324 break;
1325 }
1326 }
1327
ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf * ant_conf,struct ath_ant_comb * antcomb,int alt_ratio)1328 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1329 struct ath_ant_comb *antcomb, int alt_ratio)
1330 {
1331 if (ant_conf->div_group == 0) {
1332 /* Adjust the fast_div_bias based on main and alt lna conf */
1333 switch ((ant_conf->main_lna_conf << 4) |
1334 ant_conf->alt_lna_conf) {
1335 case 0x01: /* A-B LNA2 */
1336 ant_conf->fast_div_bias = 0x3b;
1337 break;
1338 case 0x02: /* A-B LNA1 */
1339 ant_conf->fast_div_bias = 0x3d;
1340 break;
1341 case 0x03: /* A-B A+B */
1342 ant_conf->fast_div_bias = 0x1;
1343 break;
1344 case 0x10: /* LNA2 A-B */
1345 ant_conf->fast_div_bias = 0x7;
1346 break;
1347 case 0x12: /* LNA2 LNA1 */
1348 ant_conf->fast_div_bias = 0x2;
1349 break;
1350 case 0x13: /* LNA2 A+B */
1351 ant_conf->fast_div_bias = 0x7;
1352 break;
1353 case 0x20: /* LNA1 A-B */
1354 ant_conf->fast_div_bias = 0x6;
1355 break;
1356 case 0x21: /* LNA1 LNA2 */
1357 ant_conf->fast_div_bias = 0x0;
1358 break;
1359 case 0x23: /* LNA1 A+B */
1360 ant_conf->fast_div_bias = 0x6;
1361 break;
1362 case 0x30: /* A+B A-B */
1363 ant_conf->fast_div_bias = 0x1;
1364 break;
1365 case 0x31: /* A+B LNA2 */
1366 ant_conf->fast_div_bias = 0x3b;
1367 break;
1368 case 0x32: /* A+B LNA1 */
1369 ant_conf->fast_div_bias = 0x3d;
1370 break;
1371 default:
1372 break;
1373 }
1374 } else if (ant_conf->div_group == 1) {
1375 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1376 switch ((ant_conf->main_lna_conf << 4) |
1377 ant_conf->alt_lna_conf) {
1378 case 0x01: /* A-B LNA2 */
1379 ant_conf->fast_div_bias = 0x1;
1380 ant_conf->main_gaintb = 0;
1381 ant_conf->alt_gaintb = 0;
1382 break;
1383 case 0x02: /* A-B LNA1 */
1384 ant_conf->fast_div_bias = 0x1;
1385 ant_conf->main_gaintb = 0;
1386 ant_conf->alt_gaintb = 0;
1387 break;
1388 case 0x03: /* A-B A+B */
1389 ant_conf->fast_div_bias = 0x1;
1390 ant_conf->main_gaintb = 0;
1391 ant_conf->alt_gaintb = 0;
1392 break;
1393 case 0x10: /* LNA2 A-B */
1394 if (!(antcomb->scan) &&
1395 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1396 ant_conf->fast_div_bias = 0x3f;
1397 else
1398 ant_conf->fast_div_bias = 0x1;
1399 ant_conf->main_gaintb = 0;
1400 ant_conf->alt_gaintb = 0;
1401 break;
1402 case 0x12: /* LNA2 LNA1 */
1403 ant_conf->fast_div_bias = 0x1;
1404 ant_conf->main_gaintb = 0;
1405 ant_conf->alt_gaintb = 0;
1406 break;
1407 case 0x13: /* LNA2 A+B */
1408 if (!(antcomb->scan) &&
1409 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1410 ant_conf->fast_div_bias = 0x3f;
1411 else
1412 ant_conf->fast_div_bias = 0x1;
1413 ant_conf->main_gaintb = 0;
1414 ant_conf->alt_gaintb = 0;
1415 break;
1416 case 0x20: /* LNA1 A-B */
1417 if (!(antcomb->scan) &&
1418 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1419 ant_conf->fast_div_bias = 0x3f;
1420 else
1421 ant_conf->fast_div_bias = 0x1;
1422 ant_conf->main_gaintb = 0;
1423 ant_conf->alt_gaintb = 0;
1424 break;
1425 case 0x21: /* LNA1 LNA2 */
1426 ant_conf->fast_div_bias = 0x1;
1427 ant_conf->main_gaintb = 0;
1428 ant_conf->alt_gaintb = 0;
1429 break;
1430 case 0x23: /* LNA1 A+B */
1431 if (!(antcomb->scan) &&
1432 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1433 ant_conf->fast_div_bias = 0x3f;
1434 else
1435 ant_conf->fast_div_bias = 0x1;
1436 ant_conf->main_gaintb = 0;
1437 ant_conf->alt_gaintb = 0;
1438 break;
1439 case 0x30: /* A+B A-B */
1440 ant_conf->fast_div_bias = 0x1;
1441 ant_conf->main_gaintb = 0;
1442 ant_conf->alt_gaintb = 0;
1443 break;
1444 case 0x31: /* A+B LNA2 */
1445 ant_conf->fast_div_bias = 0x1;
1446 ant_conf->main_gaintb = 0;
1447 ant_conf->alt_gaintb = 0;
1448 break;
1449 case 0x32: /* A+B LNA1 */
1450 ant_conf->fast_div_bias = 0x1;
1451 ant_conf->main_gaintb = 0;
1452 ant_conf->alt_gaintb = 0;
1453 break;
1454 default:
1455 break;
1456 }
1457 } else if (ant_conf->div_group == 2) {
1458 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1459 switch ((ant_conf->main_lna_conf << 4) |
1460 ant_conf->alt_lna_conf) {
1461 case 0x01: /* A-B LNA2 */
1462 ant_conf->fast_div_bias = 0x1;
1463 ant_conf->main_gaintb = 0;
1464 ant_conf->alt_gaintb = 0;
1465 break;
1466 case 0x02: /* A-B LNA1 */
1467 ant_conf->fast_div_bias = 0x1;
1468 ant_conf->main_gaintb = 0;
1469 ant_conf->alt_gaintb = 0;
1470 break;
1471 case 0x03: /* A-B A+B */
1472 ant_conf->fast_div_bias = 0x1;
1473 ant_conf->main_gaintb = 0;
1474 ant_conf->alt_gaintb = 0;
1475 break;
1476 case 0x10: /* LNA2 A-B */
1477 if (!(antcomb->scan) &&
1478 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1479 ant_conf->fast_div_bias = 0x1;
1480 else
1481 ant_conf->fast_div_bias = 0x2;
1482 ant_conf->main_gaintb = 0;
1483 ant_conf->alt_gaintb = 0;
1484 break;
1485 case 0x12: /* LNA2 LNA1 */
1486 ant_conf->fast_div_bias = 0x1;
1487 ant_conf->main_gaintb = 0;
1488 ant_conf->alt_gaintb = 0;
1489 break;
1490 case 0x13: /* LNA2 A+B */
1491 if (!(antcomb->scan) &&
1492 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1493 ant_conf->fast_div_bias = 0x1;
1494 else
1495 ant_conf->fast_div_bias = 0x2;
1496 ant_conf->main_gaintb = 0;
1497 ant_conf->alt_gaintb = 0;
1498 break;
1499 case 0x20: /* LNA1 A-B */
1500 if (!(antcomb->scan) &&
1501 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1502 ant_conf->fast_div_bias = 0x1;
1503 else
1504 ant_conf->fast_div_bias = 0x2;
1505 ant_conf->main_gaintb = 0;
1506 ant_conf->alt_gaintb = 0;
1507 break;
1508 case 0x21: /* LNA1 LNA2 */
1509 ant_conf->fast_div_bias = 0x1;
1510 ant_conf->main_gaintb = 0;
1511 ant_conf->alt_gaintb = 0;
1512 break;
1513 case 0x23: /* LNA1 A+B */
1514 if (!(antcomb->scan) &&
1515 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1516 ant_conf->fast_div_bias = 0x1;
1517 else
1518 ant_conf->fast_div_bias = 0x2;
1519 ant_conf->main_gaintb = 0;
1520 ant_conf->alt_gaintb = 0;
1521 break;
1522 case 0x30: /* A+B A-B */
1523 ant_conf->fast_div_bias = 0x1;
1524 ant_conf->main_gaintb = 0;
1525 ant_conf->alt_gaintb = 0;
1526 break;
1527 case 0x31: /* A+B LNA2 */
1528 ant_conf->fast_div_bias = 0x1;
1529 ant_conf->main_gaintb = 0;
1530 ant_conf->alt_gaintb = 0;
1531 break;
1532 case 0x32: /* A+B LNA1 */
1533 ant_conf->fast_div_bias = 0x1;
1534 ant_conf->main_gaintb = 0;
1535 ant_conf->alt_gaintb = 0;
1536 break;
1537 default:
1538 break;
1539 }
1540 }
1541 }
1542
1543 /* Antenna diversity and combining */
ath_ant_comb_scan(struct ath_softc * sc,struct ath_rx_status * rs)1544 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1545 {
1546 struct ath_hw_antcomb_conf div_ant_conf;
1547 struct ath_ant_comb *antcomb = &sc->ant_comb;
1548 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1549 int curr_main_set;
1550 int main_rssi = rs->rs_rssi_ctl0;
1551 int alt_rssi = rs->rs_rssi_ctl1;
1552 int rx_ant_conf, main_ant_conf;
1553 bool short_scan = false;
1554
1555 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1556 ATH_ANT_RX_MASK;
1557 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1558 ATH_ANT_RX_MASK;
1559
1560 /* Record packet only when both main_rssi and alt_rssi is positive */
1561 if (main_rssi > 0 && alt_rssi > 0) {
1562 antcomb->total_pkt_count++;
1563 antcomb->main_total_rssi += main_rssi;
1564 antcomb->alt_total_rssi += alt_rssi;
1565 if (main_ant_conf == rx_ant_conf)
1566 antcomb->main_recv_cnt++;
1567 else
1568 antcomb->alt_recv_cnt++;
1569 }
1570
1571 /* Short scan check */
1572 if (antcomb->scan && antcomb->alt_good) {
1573 if (time_after(jiffies, antcomb->scan_start_time +
1574 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1575 short_scan = true;
1576 else
1577 if (antcomb->total_pkt_count ==
1578 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1579 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1580 antcomb->total_pkt_count);
1581 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1582 short_scan = true;
1583 }
1584 }
1585
1586 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1587 rs->rs_moreaggr) && !short_scan)
1588 return;
1589
1590 if (antcomb->total_pkt_count) {
1591 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1592 antcomb->total_pkt_count);
1593 main_rssi_avg = (antcomb->main_total_rssi /
1594 antcomb->total_pkt_count);
1595 alt_rssi_avg = (antcomb->alt_total_rssi /
1596 antcomb->total_pkt_count);
1597 }
1598
1599
1600 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1601 curr_alt_set = div_ant_conf.alt_lna_conf;
1602 curr_main_set = div_ant_conf.main_lna_conf;
1603
1604 antcomb->count++;
1605
1606 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1607 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1608 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1609 main_rssi_avg);
1610 antcomb->alt_good = true;
1611 } else {
1612 antcomb->alt_good = false;
1613 }
1614
1615 antcomb->count = 0;
1616 antcomb->scan = true;
1617 antcomb->scan_not_start = true;
1618 }
1619
1620 if (!antcomb->scan) {
1621 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1622 alt_ratio, curr_main_set, curr_alt_set,
1623 alt_rssi_avg, main_rssi_avg)) {
1624 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1625 /* Switch main and alt LNA */
1626 div_ant_conf.main_lna_conf =
1627 ATH_ANT_DIV_COMB_LNA2;
1628 div_ant_conf.alt_lna_conf =
1629 ATH_ANT_DIV_COMB_LNA1;
1630 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1631 div_ant_conf.main_lna_conf =
1632 ATH_ANT_DIV_COMB_LNA1;
1633 div_ant_conf.alt_lna_conf =
1634 ATH_ANT_DIV_COMB_LNA2;
1635 }
1636
1637 goto div_comb_done;
1638 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1639 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1640 /* Set alt to another LNA */
1641 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1642 div_ant_conf.alt_lna_conf =
1643 ATH_ANT_DIV_COMB_LNA1;
1644 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1645 div_ant_conf.alt_lna_conf =
1646 ATH_ANT_DIV_COMB_LNA2;
1647
1648 goto div_comb_done;
1649 }
1650
1651 if ((alt_rssi_avg < (main_rssi_avg +
1652 div_ant_conf.lna1_lna2_delta)))
1653 goto div_comb_done;
1654 }
1655
1656 if (!antcomb->scan_not_start) {
1657 switch (curr_alt_set) {
1658 case ATH_ANT_DIV_COMB_LNA2:
1659 antcomb->rssi_lna2 = alt_rssi_avg;
1660 antcomb->rssi_lna1 = main_rssi_avg;
1661 antcomb->scan = true;
1662 /* set to A+B */
1663 div_ant_conf.main_lna_conf =
1664 ATH_ANT_DIV_COMB_LNA1;
1665 div_ant_conf.alt_lna_conf =
1666 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1667 break;
1668 case ATH_ANT_DIV_COMB_LNA1:
1669 antcomb->rssi_lna1 = alt_rssi_avg;
1670 antcomb->rssi_lna2 = main_rssi_avg;
1671 antcomb->scan = true;
1672 /* set to A+B */
1673 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1674 div_ant_conf.alt_lna_conf =
1675 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1676 break;
1677 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1678 antcomb->rssi_add = alt_rssi_avg;
1679 antcomb->scan = true;
1680 /* set to A-B */
1681 div_ant_conf.alt_lna_conf =
1682 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1683 break;
1684 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1685 antcomb->rssi_sub = alt_rssi_avg;
1686 antcomb->scan = false;
1687 if (antcomb->rssi_lna2 >
1688 (antcomb->rssi_lna1 +
1689 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1690 /* use LNA2 as main LNA */
1691 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1692 (antcomb->rssi_add > antcomb->rssi_sub)) {
1693 /* set to A+B */
1694 div_ant_conf.main_lna_conf =
1695 ATH_ANT_DIV_COMB_LNA2;
1696 div_ant_conf.alt_lna_conf =
1697 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1698 } else if (antcomb->rssi_sub >
1699 antcomb->rssi_lna1) {
1700 /* set to A-B */
1701 div_ant_conf.main_lna_conf =
1702 ATH_ANT_DIV_COMB_LNA2;
1703 div_ant_conf.alt_lna_conf =
1704 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1705 } else {
1706 /* set to LNA1 */
1707 div_ant_conf.main_lna_conf =
1708 ATH_ANT_DIV_COMB_LNA2;
1709 div_ant_conf.alt_lna_conf =
1710 ATH_ANT_DIV_COMB_LNA1;
1711 }
1712 } else {
1713 /* use LNA1 as main LNA */
1714 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1715 (antcomb->rssi_add > antcomb->rssi_sub)) {
1716 /* set to A+B */
1717 div_ant_conf.main_lna_conf =
1718 ATH_ANT_DIV_COMB_LNA1;
1719 div_ant_conf.alt_lna_conf =
1720 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1721 } else if (antcomb->rssi_sub >
1722 antcomb->rssi_lna1) {
1723 /* set to A-B */
1724 div_ant_conf.main_lna_conf =
1725 ATH_ANT_DIV_COMB_LNA1;
1726 div_ant_conf.alt_lna_conf =
1727 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1728 } else {
1729 /* set to LNA2 */
1730 div_ant_conf.main_lna_conf =
1731 ATH_ANT_DIV_COMB_LNA1;
1732 div_ant_conf.alt_lna_conf =
1733 ATH_ANT_DIV_COMB_LNA2;
1734 }
1735 }
1736 break;
1737 default:
1738 break;
1739 }
1740 } else {
1741 if (!antcomb->alt_good) {
1742 antcomb->scan_not_start = false;
1743 /* Set alt to another LNA */
1744 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1745 div_ant_conf.main_lna_conf =
1746 ATH_ANT_DIV_COMB_LNA2;
1747 div_ant_conf.alt_lna_conf =
1748 ATH_ANT_DIV_COMB_LNA1;
1749 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1750 div_ant_conf.main_lna_conf =
1751 ATH_ANT_DIV_COMB_LNA1;
1752 div_ant_conf.alt_lna_conf =
1753 ATH_ANT_DIV_COMB_LNA2;
1754 }
1755 goto div_comb_done;
1756 }
1757 }
1758
1759 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1760 main_rssi_avg, alt_rssi_avg,
1761 alt_ratio);
1762
1763 antcomb->quick_scan_cnt++;
1764
1765 div_comb_done:
1766 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
1767 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1768
1769 antcomb->scan_start_time = jiffies;
1770 antcomb->total_pkt_count = 0;
1771 antcomb->main_total_rssi = 0;
1772 antcomb->alt_total_rssi = 0;
1773 antcomb->main_recv_cnt = 0;
1774 antcomb->alt_recv_cnt = 0;
1775 }
1776
ath_rx_tasklet(struct ath_softc * sc,int flush,bool hp)1777 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1778 {
1779 struct ath_buf *bf;
1780 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1781 struct ieee80211_rx_status *rxs;
1782 struct ath_hw *ah = sc->sc_ah;
1783 struct ath_common *common = ath9k_hw_common(ah);
1784 struct ieee80211_hw *hw = sc->hw;
1785 struct ieee80211_hdr *hdr;
1786 int retval;
1787 struct ath_rx_status rs;
1788 enum ath9k_rx_qtype qtype;
1789 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1790 int dma_type;
1791 u8 rx_status_len = ah->caps.rx_status_len;
1792 u64 tsf = 0;
1793 u32 tsf_lower = 0;
1794 unsigned long flags;
1795
1796 if (edma)
1797 dma_type = DMA_BIDIRECTIONAL;
1798 else
1799 dma_type = DMA_FROM_DEVICE;
1800
1801 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1802 spin_lock_bh(&sc->rx.rxbuflock);
1803
1804 tsf = ath9k_hw_gettsf64(ah);
1805 tsf_lower = tsf & 0xffffffff;
1806
1807 do {
1808 bool decrypt_error = false;
1809 /* If handling rx interrupt and flush is in progress => exit */
1810 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1811 break;
1812
1813 memset(&rs, 0, sizeof(rs));
1814 if (edma)
1815 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1816 else
1817 bf = ath_get_next_rx_buf(sc, &rs);
1818
1819 if (!bf)
1820 break;
1821
1822 skb = bf->bf_mpdu;
1823 if (!skb)
1824 continue;
1825
1826 /*
1827 * Take frame header from the first fragment and RX status from
1828 * the last one.
1829 */
1830 if (sc->rx.frag)
1831 hdr_skb = sc->rx.frag;
1832 else
1833 hdr_skb = skb;
1834
1835 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1836 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1837 if (ieee80211_is_beacon(hdr->frame_control) &&
1838 !is_zero_ether_addr(common->curbssid) &&
1839 !compare_ether_addr(hdr->addr3, common->curbssid))
1840 rs.is_mybeacon = true;
1841 else
1842 rs.is_mybeacon = false;
1843
1844 ath_debug_stat_rx(sc, &rs);
1845
1846 /*
1847 * If we're asked to flush receive queue, directly
1848 * chain it back at the queue without processing it.
1849 */
1850 if (sc->sc_flags & SC_OP_RXFLUSH)
1851 goto requeue_drop_frag;
1852
1853 memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1854
1855 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1856 if (rs.rs_tstamp > tsf_lower &&
1857 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1858 rxs->mactime -= 0x100000000ULL;
1859
1860 if (rs.rs_tstamp < tsf_lower &&
1861 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1862 rxs->mactime += 0x100000000ULL;
1863
1864 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1865 rxs, &decrypt_error);
1866 if (retval)
1867 goto requeue_drop_frag;
1868
1869 /* Ensure we always have an skb to requeue once we are done
1870 * processing the current buffer's skb */
1871 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1872
1873 /* If there is no memory we ignore the current RX'd frame,
1874 * tell hardware it can give us a new frame using the old
1875 * skb and put it at the tail of the sc->rx.rxbuf list for
1876 * processing. */
1877 if (!requeue_skb)
1878 goto requeue_drop_frag;
1879
1880 /* Unmap the frame */
1881 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1882 common->rx_bufsize,
1883 dma_type);
1884
1885 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1886 if (ah->caps.rx_status_len)
1887 skb_pull(skb, ah->caps.rx_status_len);
1888
1889 if (!rs.rs_more)
1890 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1891 rxs, decrypt_error);
1892
1893 /* We will now give hardware our shiny new allocated skb */
1894 bf->bf_mpdu = requeue_skb;
1895 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1896 common->rx_bufsize,
1897 dma_type);
1898 if (unlikely(dma_mapping_error(sc->dev,
1899 bf->bf_buf_addr))) {
1900 dev_kfree_skb_any(requeue_skb);
1901 bf->bf_mpdu = NULL;
1902 bf->bf_buf_addr = 0;
1903 ath_err(common, "dma_mapping_error() on RX\n");
1904 ieee80211_rx(hw, skb);
1905 break;
1906 }
1907
1908 if (rs.rs_more) {
1909 /*
1910 * rs_more indicates chained descriptors which can be
1911 * used to link buffers together for a sort of
1912 * scatter-gather operation.
1913 */
1914 if (sc->rx.frag) {
1915 /* too many fragments - cannot handle frame */
1916 dev_kfree_skb_any(sc->rx.frag);
1917 dev_kfree_skb_any(skb);
1918 skb = NULL;
1919 }
1920 sc->rx.frag = skb;
1921 goto requeue;
1922 }
1923
1924 if (sc->rx.frag) {
1925 int space = skb->len - skb_tailroom(hdr_skb);
1926
1927 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1928 dev_kfree_skb(skb);
1929 goto requeue_drop_frag;
1930 }
1931
1932 sc->rx.frag = NULL;
1933
1934 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1935 skb->len);
1936 dev_kfree_skb_any(skb);
1937 skb = hdr_skb;
1938 }
1939
1940
1941 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1942
1943 /*
1944 * change the default rx antenna if rx diversity
1945 * chooses the other antenna 3 times in a row.
1946 */
1947 if (sc->rx.defant != rs.rs_antenna) {
1948 if (++sc->rx.rxotherant >= 3)
1949 ath_setdefantenna(sc, rs.rs_antenna);
1950 } else {
1951 sc->rx.rxotherant = 0;
1952 }
1953
1954 }
1955
1956 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1957 skb_trim(skb, skb->len - 8);
1958
1959 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1960
1961 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1962 PS_WAIT_FOR_CAB |
1963 PS_WAIT_FOR_PSPOLL_DATA)) ||
1964 ath9k_check_auto_sleep(sc))
1965 ath_rx_ps(sc, skb, rs.is_mybeacon);
1966 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1967
1968 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
1969 ath_ant_comb_scan(sc, &rs);
1970
1971 ieee80211_rx(hw, skb);
1972
1973 requeue_drop_frag:
1974 if (sc->rx.frag) {
1975 dev_kfree_skb_any(sc->rx.frag);
1976 sc->rx.frag = NULL;
1977 }
1978 requeue:
1979 list_add_tail(&bf->list, &sc->rx.rxbuf);
1980 if (flush)
1981 continue;
1982
1983 if (edma) {
1984 ath_rx_edma_buf_link(sc, qtype);
1985 } else {
1986 ath_rx_buf_relink(sc, bf);
1987 ath9k_hw_rxena(ah);
1988 }
1989 } while (1);
1990
1991 spin_unlock_bh(&sc->rx.rxbuflock);
1992
1993 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1994 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1995 ath9k_hw_set_interrupts(ah);
1996 }
1997
1998 return 0;
1999 }
2000