1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include <linux/export.h>
19
20 #define AR_BufLen 0x00000fff
21
ar9002_hw_rx_enable(struct ath_hw * ah)22 static void ar9002_hw_rx_enable(struct ath_hw *ah)
23 {
24 REG_WRITE(ah, AR_CR, AR_CR_RXE);
25 }
26
ar9002_hw_set_desc_link(void * ds,u32 ds_link)27 static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
28 {
29 ((struct ath_desc*) ds)->ds_link = ds_link;
30 }
31
ar9002_hw_get_isr(struct ath_hw * ah,enum ath9k_int * masked)32 static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
33 {
34 u32 isr = 0;
35 u32 mask2 = 0;
36 struct ath9k_hw_capabilities *pCap = &ah->caps;
37 u32 sync_cause = 0;
38 bool fatal_int = false;
39 struct ath_common *common = ath9k_hw_common(ah);
40
41 if (!AR_SREV_9100(ah)) {
42 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
43 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
44 == AR_RTC_STATUS_ON) {
45 isr = REG_READ(ah, AR_ISR);
46 }
47 }
48
49 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
50 AR_INTR_SYNC_DEFAULT;
51
52 *masked = 0;
53
54 if (!isr && !sync_cause)
55 return false;
56 } else {
57 *masked = 0;
58 isr = REG_READ(ah, AR_ISR);
59 }
60
61 if (isr) {
62 if (isr & AR_ISR_BCNMISC) {
63 u32 isr2;
64 isr2 = REG_READ(ah, AR_ISR_S2);
65 if (isr2 & AR_ISR_S2_TIM)
66 mask2 |= ATH9K_INT_TIM;
67 if (isr2 & AR_ISR_S2_DTIM)
68 mask2 |= ATH9K_INT_DTIM;
69 if (isr2 & AR_ISR_S2_DTIMSYNC)
70 mask2 |= ATH9K_INT_DTIMSYNC;
71 if (isr2 & (AR_ISR_S2_CABEND))
72 mask2 |= ATH9K_INT_CABEND;
73 if (isr2 & AR_ISR_S2_GTT)
74 mask2 |= ATH9K_INT_GTT;
75 if (isr2 & AR_ISR_S2_CST)
76 mask2 |= ATH9K_INT_CST;
77 if (isr2 & AR_ISR_S2_TSFOOR)
78 mask2 |= ATH9K_INT_TSFOOR;
79
80 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
81 REG_WRITE(ah, AR_ISR_S2, isr2);
82 isr &= ~AR_ISR_BCNMISC;
83 }
84 }
85
86 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
87 isr = REG_READ(ah, AR_ISR_RAC);
88
89 if (isr == 0xffffffff) {
90 *masked = 0;
91 return false;
92 }
93
94 *masked = isr & ATH9K_INT_COMMON;
95
96 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
97 AR_ISR_RXOK | AR_ISR_RXERR))
98 *masked |= ATH9K_INT_RX;
99
100 if (isr &
101 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
102 AR_ISR_TXEOL)) {
103 u32 s0_s, s1_s;
104
105 *masked |= ATH9K_INT_TX;
106
107 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
108 s0_s = REG_READ(ah, AR_ISR_S0_S);
109 s1_s = REG_READ(ah, AR_ISR_S1_S);
110 } else {
111 s0_s = REG_READ(ah, AR_ISR_S0);
112 REG_WRITE(ah, AR_ISR_S0, s0_s);
113 s1_s = REG_READ(ah, AR_ISR_S1);
114 REG_WRITE(ah, AR_ISR_S1, s1_s);
115
116 isr &= ~(AR_ISR_TXOK |
117 AR_ISR_TXDESC |
118 AR_ISR_TXERR |
119 AR_ISR_TXEOL);
120 }
121
122 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
123 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
124 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
125 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
126 }
127
128 if (isr & AR_ISR_RXORN) {
129 ath_dbg(common, INTERRUPT,
130 "receive FIFO overrun interrupt\n");
131 }
132
133 *masked |= mask2;
134 }
135
136 if (!AR_SREV_9100(ah) && (isr & AR_ISR_GENTMR)) {
137 u32 s5_s;
138
139 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
140 s5_s = REG_READ(ah, AR_ISR_S5_S);
141 } else {
142 s5_s = REG_READ(ah, AR_ISR_S5);
143 }
144
145 ah->intr_gen_timer_trigger =
146 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
147
148 ah->intr_gen_timer_thresh =
149 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
150
151 if (ah->intr_gen_timer_trigger)
152 *masked |= ATH9K_INT_GENTIMER;
153
154 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
155 !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
156 *masked |= ATH9K_INT_TIM_TIMER;
157
158 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
159 REG_WRITE(ah, AR_ISR_S5, s5_s);
160 isr &= ~AR_ISR_GENTMR;
161 }
162 }
163
164 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
165 REG_WRITE(ah, AR_ISR, isr);
166 REG_READ(ah, AR_ISR);
167 }
168
169 if (AR_SREV_9100(ah))
170 return true;
171
172 if (sync_cause) {
173 fatal_int =
174 (sync_cause &
175 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
176 ? true : false;
177
178 if (fatal_int) {
179 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
180 ath_dbg(common, ANY,
181 "received PCI FATAL interrupt\n");
182 }
183 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
184 ath_dbg(common, ANY,
185 "received PCI PERR interrupt\n");
186 }
187 *masked |= ATH9K_INT_FATAL;
188 }
189 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
190 ath_dbg(common, INTERRUPT,
191 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
192 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
193 REG_WRITE(ah, AR_RC, 0);
194 *masked |= ATH9K_INT_FATAL;
195 }
196 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
197 ath_dbg(common, INTERRUPT,
198 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
199 }
200
201 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
202 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
203 }
204
205 return true;
206 }
207
208 static void
ar9002_set_txdesc(struct ath_hw * ah,void * ds,struct ath_tx_info * i)209 ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
210 {
211 struct ar5416_desc *ads = AR5416DESC(ds);
212 u32 ctl1, ctl6;
213
214 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
215 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
216 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
217 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
218 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
219
220 ACCESS_ONCE(ads->ds_link) = i->link;
221 ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];
222
223 ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore);
224 ctl6 = SM(i->keytype, AR_EncrType);
225
226 if (AR_SREV_9285(ah)) {
227 ads->ds_ctl8 = 0;
228 ads->ds_ctl9 = 0;
229 ads->ds_ctl10 = 0;
230 ads->ds_ctl11 = 0;
231 }
232
233 if ((i->is_first || i->is_last) &&
234 i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
235 ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
236 | set11nTries(i->rates, 1)
237 | set11nTries(i->rates, 2)
238 | set11nTries(i->rates, 3)
239 | (i->dur_update ? AR_DurUpdateEna : 0)
240 | SM(0, AR_BurstDur);
241
242 ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
243 | set11nRate(i->rates, 1)
244 | set11nRate(i->rates, 2)
245 | set11nRate(i->rates, 3);
246 } else {
247 ACCESS_ONCE(ads->ds_ctl2) = 0;
248 ACCESS_ONCE(ads->ds_ctl3) = 0;
249 }
250
251 if (!i->is_first) {
252 ACCESS_ONCE(ads->ds_ctl0) = 0;
253 ACCESS_ONCE(ads->ds_ctl1) = ctl1;
254 ACCESS_ONCE(ads->ds_ctl6) = ctl6;
255 return;
256 }
257
258 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
259 | SM(i->type, AR_FrameType)
260 | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
261 | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
262 | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
263
264 switch (i->aggr) {
265 case AGGR_BUF_FIRST:
266 ctl6 |= SM(i->aggr_len, AR_AggrLen);
267 /* fall through */
268 case AGGR_BUF_MIDDLE:
269 ctl1 |= AR_IsAggr | AR_MoreAggr;
270 ctl6 |= SM(i->ndelim, AR_PadDelim);
271 break;
272 case AGGR_BUF_LAST:
273 ctl1 |= AR_IsAggr;
274 break;
275 case AGGR_BUF_NONE:
276 break;
277 }
278
279 ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
280 | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
281 | SM(i->txpower, AR_XmitPower)
282 | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
283 | (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
284 | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
285 | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
286 | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
287 (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
288
289 ACCESS_ONCE(ads->ds_ctl1) = ctl1;
290 ACCESS_ONCE(ads->ds_ctl6) = ctl6;
291
292 if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST)
293 return;
294
295 ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
296 | set11nPktDurRTSCTS(i->rates, 1);
297
298 ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
299 | set11nPktDurRTSCTS(i->rates, 3);
300
301 ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
302 | set11nRateFlags(i->rates, 1)
303 | set11nRateFlags(i->rates, 2)
304 | set11nRateFlags(i->rates, 3)
305 | SM(i->rtscts_rate, AR_RTSCTSRate);
306 }
307
ar9002_hw_proc_txdesc(struct ath_hw * ah,void * ds,struct ath_tx_status * ts)308 static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
309 struct ath_tx_status *ts)
310 {
311 struct ar5416_desc *ads = AR5416DESC(ds);
312 u32 status;
313
314 status = ACCESS_ONCE(ads->ds_txstatus9);
315 if ((status & AR_TxDone) == 0)
316 return -EINPROGRESS;
317
318 ts->ts_tstamp = ads->AR_SendTimestamp;
319 ts->ts_status = 0;
320 ts->ts_flags = 0;
321
322 if (status & AR_TxOpExceeded)
323 ts->ts_status |= ATH9K_TXERR_XTXOP;
324 ts->tid = MS(status, AR_TxTid);
325 ts->ts_rateindex = MS(status, AR_FinalTxIdx);
326 ts->ts_seqnum = MS(status, AR_SeqNum);
327
328 status = ACCESS_ONCE(ads->ds_txstatus0);
329 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
330 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
331 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
332 if (status & AR_TxBaStatus) {
333 ts->ts_flags |= ATH9K_TX_BA;
334 ts->ba_low = ads->AR_BaBitmapLow;
335 ts->ba_high = ads->AR_BaBitmapHigh;
336 }
337
338 status = ACCESS_ONCE(ads->ds_txstatus1);
339 if (status & AR_FrmXmitOK)
340 ts->ts_status |= ATH9K_TX_ACKED;
341 else {
342 if (status & AR_ExcessiveRetries)
343 ts->ts_status |= ATH9K_TXERR_XRETRY;
344 if (status & AR_Filtered)
345 ts->ts_status |= ATH9K_TXERR_FILT;
346 if (status & AR_FIFOUnderrun) {
347 ts->ts_status |= ATH9K_TXERR_FIFO;
348 ath9k_hw_updatetxtriglevel(ah, true);
349 }
350 }
351 if (status & AR_TxTimerExpired)
352 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
353 if (status & AR_DescCfgErr)
354 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
355 if (status & AR_TxDataUnderrun) {
356 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
357 ath9k_hw_updatetxtriglevel(ah, true);
358 }
359 if (status & AR_TxDelimUnderrun) {
360 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
361 ath9k_hw_updatetxtriglevel(ah, true);
362 }
363 ts->ts_shortretry = MS(status, AR_RTSFailCnt);
364 ts->ts_longretry = MS(status, AR_DataFailCnt);
365 ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
366
367 status = ACCESS_ONCE(ads->ds_txstatus5);
368 ts->ts_rssi = MS(status, AR_TxRSSICombined);
369 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
370 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
371 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
372
373 ts->evm0 = ads->AR_TxEVM0;
374 ts->evm1 = ads->AR_TxEVM1;
375 ts->evm2 = ads->AR_TxEVM2;
376
377 return 0;
378 }
379
ath9k_hw_setuprxdesc(struct ath_hw * ah,struct ath_desc * ds,u32 size,u32 flags)380 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
381 u32 size, u32 flags)
382 {
383 struct ar5416_desc *ads = AR5416DESC(ds);
384
385 ads->ds_ctl1 = size & AR_BufLen;
386 if (flags & ATH9K_RXDESC_INTREQ)
387 ads->ds_ctl1 |= AR_RxIntrReq;
388
389 memset(&ads->u.rx, 0, sizeof(ads->u.rx));
390 }
391 EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
392
ar9002_hw_attach_mac_ops(struct ath_hw * ah)393 void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
394 {
395 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
396
397 ops->rx_enable = ar9002_hw_rx_enable;
398 ops->set_desc_link = ar9002_hw_set_desc_link;
399 ops->get_isr = ar9002_hw_get_isr;
400 ops->set_txdesc = ar9002_set_txdesc;
401 ops->proc_txdesc = ar9002_hw_proc_txdesc;
402 }
403