1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include <linux/export.h>
20
ath9k_hw_set_txq_interrupts(struct ath_hw * ah,struct ath9k_tx_queue_info * qi)21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
22 struct ath9k_tx_queue_info *qi)
23 {
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT,
25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
28 ah->txurn_interrupt_mask);
29
30 ENABLE_REGWRITE_BUFFER(ah);
31
32 REG_WRITE(ah, AR_IMR_S0,
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
35 REG_WRITE(ah, AR_IMR_S1,
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
38
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
42
43 REGWRITE_BUFFER_FLUSH(ah);
44 }
45
ath9k_hw_gettxbuf(struct ath_hw * ah,u32 q)46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
47 {
48 return REG_READ(ah, AR_QTXDP(q));
49 }
50 EXPORT_SYMBOL(ath9k_hw_gettxbuf);
51
ath9k_hw_puttxbuf(struct ath_hw * ah,u32 q,u32 txdp)52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
53 {
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
55 }
56 EXPORT_SYMBOL(ath9k_hw_puttxbuf);
57
ath9k_hw_txstart(struct ath_hw * ah,u32 q)58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
59 {
60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q);
61 REG_WRITE(ah, AR_Q_TXE, 1 << q);
62 }
63 EXPORT_SYMBOL(ath9k_hw_txstart);
64
ath9k_hw_numtxpending(struct ath_hw * ah,u32 q)65 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
66 {
67 u32 npend;
68
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
70 if (npend == 0) {
71
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
73 npend = 1;
74 }
75
76 return npend;
77 }
78 EXPORT_SYMBOL(ath9k_hw_numtxpending);
79
80 /**
81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
82 *
83 * @ah: atheros hardware struct
84 * @bIncTrigLevel: whether or not the frame trigger level should be updated
85 *
86 * The frame trigger level specifies the minimum number of bytes,
87 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
88 * before the PCU will initiate sending the frame on the air. This can
89 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
90 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
91 * first)
92 *
93 * Caution must be taken to ensure to set the frame trigger level based
94 * on the DMA request size. For example if the DMA request size is set to
95 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
96 * there need to be enough space in the tx FIFO for the requested transfer
97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
98 * the threshold to a value beyond 6, then the transmit will hang.
99 *
100 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
101 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
102 * there is a hardware issue which forces us to use 2 KB instead so the
103 * frame trigger level must not exceed 2 KB for these chipsets.
104 */
ath9k_hw_updatetxtriglevel(struct ath_hw * ah,bool bIncTrigLevel)105 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
106 {
107 u32 txcfg, curLevel, newLevel;
108
109 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
110 return false;
111
112 ath9k_hw_disable_interrupts(ah);
113
114 txcfg = REG_READ(ah, AR_TXCFG);
115 curLevel = MS(txcfg, AR_FTRIG);
116 newLevel = curLevel;
117 if (bIncTrigLevel) {
118 if (curLevel < ah->config.max_txtrig_level)
119 newLevel++;
120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
121 newLevel--;
122 if (newLevel != curLevel)
123 REG_WRITE(ah, AR_TXCFG,
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
125
126 ath9k_hw_enable_interrupts(ah);
127
128 ah->tx_trig_level = newLevel;
129
130 return newLevel != curLevel;
131 }
132 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
133
ath9k_hw_abort_tx_dma(struct ath_hw * ah)134 void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
135 {
136 int i, q;
137
138 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
139
140 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
141 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
142 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
143
144 for (q = 0; q < AR_NUM_QCU; q++) {
145 for (i = 0; i < 1000; i++) {
146 if (i)
147 udelay(5);
148
149 if (!ath9k_hw_numtxpending(ah, q))
150 break;
151 }
152 }
153
154 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
155 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
156 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
157
158 REG_WRITE(ah, AR_Q_TXD, 0);
159 }
160 EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
161
ath9k_hw_stop_dma_queue(struct ath_hw * ah,u32 q)162 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
163 {
164 #define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
165 #define ATH9K_TIME_QUANTUM 100 /* usec */
166 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
167 int wait;
168
169 REG_WRITE(ah, AR_Q_TXD, 1 << q);
170
171 for (wait = wait_time; wait != 0; wait--) {
172 if (wait != wait_time)
173 udelay(ATH9K_TIME_QUANTUM);
174
175 if (ath9k_hw_numtxpending(ah, q) == 0)
176 break;
177 }
178
179 REG_WRITE(ah, AR_Q_TXD, 0);
180
181 return wait != 0;
182
183 #undef ATH9K_TX_STOP_DMA_TIMEOUT
184 #undef ATH9K_TIME_QUANTUM
185 }
186 EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
187
ath9k_hw_set_txq_props(struct ath_hw * ah,int q,const struct ath9k_tx_queue_info * qinfo)188 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
189 const struct ath9k_tx_queue_info *qinfo)
190 {
191 u32 cw;
192 struct ath_common *common = ath9k_hw_common(ah);
193 struct ath9k_tx_queue_info *qi;
194
195 qi = &ah->txq[q];
196 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
197 ath_dbg(common, QUEUE,
198 "Set TXQ properties, inactive queue: %u\n", q);
199 return false;
200 }
201
202 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q);
203
204 qi->tqi_ver = qinfo->tqi_ver;
205 qi->tqi_subtype = qinfo->tqi_subtype;
206 qi->tqi_qflags = qinfo->tqi_qflags;
207 qi->tqi_priority = qinfo->tqi_priority;
208 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
209 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
210 else
211 qi->tqi_aifs = INIT_AIFS;
212 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
213 cw = min(qinfo->tqi_cwmin, 1024U);
214 qi->tqi_cwmin = 1;
215 while (qi->tqi_cwmin < cw)
216 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
217 } else
218 qi->tqi_cwmin = qinfo->tqi_cwmin;
219 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
220 cw = min(qinfo->tqi_cwmax, 1024U);
221 qi->tqi_cwmax = 1;
222 while (qi->tqi_cwmax < cw)
223 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
224 } else
225 qi->tqi_cwmax = INIT_CWMAX;
226
227 if (qinfo->tqi_shretry != 0)
228 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
229 else
230 qi->tqi_shretry = INIT_SH_RETRY;
231 if (qinfo->tqi_lgretry != 0)
232 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
233 else
234 qi->tqi_lgretry = INIT_LG_RETRY;
235 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
236 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
237 qi->tqi_burstTime = qinfo->tqi_burstTime;
238 qi->tqi_readyTime = qinfo->tqi_readyTime;
239
240 switch (qinfo->tqi_subtype) {
241 case ATH9K_WME_UPSD:
242 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
243 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
244 break;
245 default:
246 break;
247 }
248
249 return true;
250 }
251 EXPORT_SYMBOL(ath9k_hw_set_txq_props);
252
ath9k_hw_get_txq_props(struct ath_hw * ah,int q,struct ath9k_tx_queue_info * qinfo)253 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
254 struct ath9k_tx_queue_info *qinfo)
255 {
256 struct ath_common *common = ath9k_hw_common(ah);
257 struct ath9k_tx_queue_info *qi;
258
259 qi = &ah->txq[q];
260 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
261 ath_dbg(common, QUEUE,
262 "Get TXQ properties, inactive queue: %u\n", q);
263 return false;
264 }
265
266 qinfo->tqi_qflags = qi->tqi_qflags;
267 qinfo->tqi_ver = qi->tqi_ver;
268 qinfo->tqi_subtype = qi->tqi_subtype;
269 qinfo->tqi_qflags = qi->tqi_qflags;
270 qinfo->tqi_priority = qi->tqi_priority;
271 qinfo->tqi_aifs = qi->tqi_aifs;
272 qinfo->tqi_cwmin = qi->tqi_cwmin;
273 qinfo->tqi_cwmax = qi->tqi_cwmax;
274 qinfo->tqi_shretry = qi->tqi_shretry;
275 qinfo->tqi_lgretry = qi->tqi_lgretry;
276 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
277 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
278 qinfo->tqi_burstTime = qi->tqi_burstTime;
279 qinfo->tqi_readyTime = qi->tqi_readyTime;
280
281 return true;
282 }
283 EXPORT_SYMBOL(ath9k_hw_get_txq_props);
284
ath9k_hw_setuptxqueue(struct ath_hw * ah,enum ath9k_tx_queue type,const struct ath9k_tx_queue_info * qinfo)285 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
286 const struct ath9k_tx_queue_info *qinfo)
287 {
288 struct ath_common *common = ath9k_hw_common(ah);
289 struct ath9k_tx_queue_info *qi;
290 int q;
291
292 switch (type) {
293 case ATH9K_TX_QUEUE_BEACON:
294 q = ATH9K_NUM_TX_QUEUES - 1;
295 break;
296 case ATH9K_TX_QUEUE_CAB:
297 q = ATH9K_NUM_TX_QUEUES - 2;
298 break;
299 case ATH9K_TX_QUEUE_PSPOLL:
300 q = 1;
301 break;
302 case ATH9K_TX_QUEUE_UAPSD:
303 q = ATH9K_NUM_TX_QUEUES - 3;
304 break;
305 case ATH9K_TX_QUEUE_DATA:
306 for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
307 if (ah->txq[q].tqi_type ==
308 ATH9K_TX_QUEUE_INACTIVE)
309 break;
310 if (q == ATH9K_NUM_TX_QUEUES) {
311 ath_err(common, "No available TX queue\n");
312 return -1;
313 }
314 break;
315 default:
316 ath_err(common, "Invalid TX queue type: %u\n", type);
317 return -1;
318 }
319
320 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q);
321
322 qi = &ah->txq[q];
323 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
324 ath_err(common, "TX queue: %u already active\n", q);
325 return -1;
326 }
327 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
328 qi->tqi_type = type;
329 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
330 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
331
332 return q;
333 }
334 EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
335
ath9k_hw_clear_queue_interrupts(struct ath_hw * ah,u32 q)336 static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q)
337 {
338 ah->txok_interrupt_mask &= ~(1 << q);
339 ah->txerr_interrupt_mask &= ~(1 << q);
340 ah->txdesc_interrupt_mask &= ~(1 << q);
341 ah->txeol_interrupt_mask &= ~(1 << q);
342 ah->txurn_interrupt_mask &= ~(1 << q);
343 }
344
ath9k_hw_releasetxqueue(struct ath_hw * ah,u32 q)345 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
346 {
347 struct ath_common *common = ath9k_hw_common(ah);
348 struct ath9k_tx_queue_info *qi;
349
350 qi = &ah->txq[q];
351 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
352 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q);
353 return false;
354 }
355
356 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q);
357
358 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
359 ath9k_hw_clear_queue_interrupts(ah, q);
360 ath9k_hw_set_txq_interrupts(ah, qi);
361
362 return true;
363 }
364 EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
365
ath9k_hw_resettxqueue(struct ath_hw * ah,u32 q)366 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
367 {
368 struct ath_common *common = ath9k_hw_common(ah);
369 struct ath9k_channel *chan = ah->curchan;
370 struct ath9k_tx_queue_info *qi;
371 u32 cwMin, chanCwMin, value;
372
373 qi = &ah->txq[q];
374 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
375 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
376 return true;
377 }
378
379 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);
380
381 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
382 if (chan && IS_CHAN_B(chan))
383 chanCwMin = INIT_CWMIN_11B;
384 else
385 chanCwMin = INIT_CWMIN;
386
387 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
388 } else
389 cwMin = qi->tqi_cwmin;
390
391 ENABLE_REGWRITE_BUFFER(ah);
392
393 REG_WRITE(ah, AR_DLCL_IFS(q),
394 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
395 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
396 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
397
398 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
399 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
400 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
401 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
402
403 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
404
405 if (AR_SREV_9340(ah))
406 REG_WRITE(ah, AR_DMISC(q),
407 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
408 else
409 REG_WRITE(ah, AR_DMISC(q),
410 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
411
412 if (qi->tqi_cbrPeriod) {
413 REG_WRITE(ah, AR_QCBRCFG(q),
414 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
415 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
416 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
417 (qi->tqi_cbrOverflowLimit ?
418 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
419 }
420 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
421 REG_WRITE(ah, AR_QRDYTIMECFG(q),
422 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
423 AR_Q_RDYTIMECFG_EN);
424 }
425
426 REG_WRITE(ah, AR_DCHNTIME(q),
427 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
428 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
429
430 if (qi->tqi_burstTime
431 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
432 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
433
434 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
435 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
436
437 REGWRITE_BUFFER_FLUSH(ah);
438
439 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
440 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
441
442 switch (qi->tqi_type) {
443 case ATH9K_TX_QUEUE_BEACON:
444 ENABLE_REGWRITE_BUFFER(ah);
445
446 REG_SET_BIT(ah, AR_QMISC(q),
447 AR_Q_MISC_FSP_DBA_GATED
448 | AR_Q_MISC_BEACON_USE
449 | AR_Q_MISC_CBR_INCR_DIS1);
450
451 REG_SET_BIT(ah, AR_DMISC(q),
452 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
453 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
454 | AR_D_MISC_BEACON_USE
455 | AR_D_MISC_POST_FR_BKOFF_DIS);
456
457 REGWRITE_BUFFER_FLUSH(ah);
458
459 /*
460 * cwmin and cwmax should be 0 for beacon queue
461 * but not for IBSS as we would create an imbalance
462 * on beaconing fairness for participating nodes.
463 */
464 if (AR_SREV_9300_20_OR_LATER(ah) &&
465 ah->opmode != NL80211_IFTYPE_ADHOC) {
466 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
467 | SM(0, AR_D_LCL_IFS_CWMAX)
468 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
469 }
470 break;
471 case ATH9K_TX_QUEUE_CAB:
472 ENABLE_REGWRITE_BUFFER(ah);
473
474 REG_SET_BIT(ah, AR_QMISC(q),
475 AR_Q_MISC_FSP_DBA_GATED
476 | AR_Q_MISC_CBR_INCR_DIS1
477 | AR_Q_MISC_CBR_INCR_DIS0);
478 value = (qi->tqi_readyTime -
479 (ah->config.sw_beacon_response_time -
480 ah->config.dma_beacon_response_time) -
481 ah->config.additional_swba_backoff) * 1024;
482 REG_WRITE(ah, AR_QRDYTIMECFG(q),
483 value | AR_Q_RDYTIMECFG_EN);
484 REG_SET_BIT(ah, AR_DMISC(q),
485 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
486 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
487
488 REGWRITE_BUFFER_FLUSH(ah);
489
490 break;
491 case ATH9K_TX_QUEUE_PSPOLL:
492 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
493 break;
494 case ATH9K_TX_QUEUE_UAPSD:
495 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
496 break;
497 default:
498 break;
499 }
500
501 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
502 REG_SET_BIT(ah, AR_DMISC(q),
503 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
504 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
505 AR_D_MISC_POST_FR_BKOFF_DIS);
506 }
507
508 if (AR_SREV_9300_20_OR_LATER(ah))
509 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
510
511 ath9k_hw_clear_queue_interrupts(ah, q);
512 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
513 ah->txok_interrupt_mask |= 1 << q;
514 ah->txerr_interrupt_mask |= 1 << q;
515 }
516 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
517 ah->txdesc_interrupt_mask |= 1 << q;
518 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
519 ah->txeol_interrupt_mask |= 1 << q;
520 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
521 ah->txurn_interrupt_mask |= 1 << q;
522 ath9k_hw_set_txq_interrupts(ah, qi);
523
524 return true;
525 }
526 EXPORT_SYMBOL(ath9k_hw_resettxqueue);
527
ath9k_hw_rxprocdesc(struct ath_hw * ah,struct ath_desc * ds,struct ath_rx_status * rs)528 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
529 struct ath_rx_status *rs)
530 {
531 struct ar5416_desc ads;
532 struct ar5416_desc *adsp = AR5416DESC(ds);
533 u32 phyerr;
534
535 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
536 return -EINPROGRESS;
537
538 ads.u.rx = adsp->u.rx;
539
540 rs->rs_status = 0;
541 rs->rs_flags = 0;
542
543 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
544 rs->rs_tstamp = ads.AR_RcvTimestamp;
545
546 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
547 rs->rs_rssi = ATH9K_RSSI_BAD;
548 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
549 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
550 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
551 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
552 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
553 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
554 } else {
555 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
556 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
557 AR_RxRSSIAnt00);
558 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
559 AR_RxRSSIAnt01);
560 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
561 AR_RxRSSIAnt02);
562 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
563 AR_RxRSSIAnt10);
564 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
565 AR_RxRSSIAnt11);
566 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
567 AR_RxRSSIAnt12);
568 }
569 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
570 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
571 else
572 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
573
574 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate);
575 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
576
577 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
578 rs->rs_moreaggr =
579 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
580 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
581 rs->rs_flags =
582 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
583 rs->rs_flags |=
584 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
585
586 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
587 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
588 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
589 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
590 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
591 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
592
593 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
594 /*
595 * Treat these errors as mutually exclusive to avoid spurious
596 * extra error reports from the hardware. If a CRC error is
597 * reported, then decryption and MIC errors are irrelevant,
598 * the frame is going to be dropped either way
599 */
600 if (ads.ds_rxstatus8 & AR_CRCErr)
601 rs->rs_status |= ATH9K_RXERR_CRC;
602 else if (ads.ds_rxstatus8 & AR_PHYErr) {
603 rs->rs_status |= ATH9K_RXERR_PHY;
604 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
605 rs->rs_phyerr = phyerr;
606 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
607 rs->rs_status |= ATH9K_RXERR_DECRYPT;
608 else if (ads.ds_rxstatus8 & AR_MichaelErr)
609 rs->rs_status |= ATH9K_RXERR_MIC;
610 }
611
612 if (ads.ds_rxstatus8 & AR_KeyMiss)
613 rs->rs_status |= ATH9K_RXERR_KEYMISS;
614
615 return 0;
616 }
617 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
618
619 /*
620 * This can stop or re-enables RX.
621 *
622 * If bool is set this will kill any frame which is currently being
623 * transferred between the MAC and baseband and also prevent any new
624 * frames from getting started.
625 */
ath9k_hw_setrxabort(struct ath_hw * ah,bool set)626 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
627 {
628 u32 reg;
629
630 if (set) {
631 REG_SET_BIT(ah, AR_DIAG_SW,
632 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
633
634 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
635 0, AH_WAIT_TIMEOUT)) {
636 REG_CLR_BIT(ah, AR_DIAG_SW,
637 (AR_DIAG_RX_DIS |
638 AR_DIAG_RX_ABORT));
639
640 reg = REG_READ(ah, AR_OBS_BUS_1);
641 ath_err(ath9k_hw_common(ah),
642 "RX failed to go idle in 10 ms RXSM=0x%x\n",
643 reg);
644
645 return false;
646 }
647 } else {
648 REG_CLR_BIT(ah, AR_DIAG_SW,
649 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
650 }
651
652 return true;
653 }
654 EXPORT_SYMBOL(ath9k_hw_setrxabort);
655
ath9k_hw_putrxbuf(struct ath_hw * ah,u32 rxdp)656 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
657 {
658 REG_WRITE(ah, AR_RXDP, rxdp);
659 }
660 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
661
ath9k_hw_startpcureceive(struct ath_hw * ah,bool is_scanning)662 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
663 {
664 ath9k_enable_mib_counters(ah);
665
666 ath9k_ani_reset(ah, is_scanning);
667
668 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
669 }
670 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
671
ath9k_hw_abortpcurecv(struct ath_hw * ah)672 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
673 {
674 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
675
676 ath9k_hw_disable_mib_counters(ah);
677 }
678 EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
679
ath9k_hw_stopdmarecv(struct ath_hw * ah,bool * reset)680 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
681 {
682 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
683 struct ath_common *common = ath9k_hw_common(ah);
684 u32 mac_status, last_mac_status = 0;
685 int i;
686
687 /* Enable access to the DMA observation bus */
688 REG_WRITE(ah, AR_MACMISC,
689 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
690 (AR_MACMISC_MISC_OBS_BUS_1 <<
691 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
692
693 REG_WRITE(ah, AR_CR, AR_CR_RXD);
694
695 /* Wait for rx enable bit to go low */
696 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
697 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
698 break;
699
700 if (!AR_SREV_9300_20_OR_LATER(ah)) {
701 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
702 if (mac_status == 0x1c0 && mac_status == last_mac_status) {
703 *reset = true;
704 break;
705 }
706
707 last_mac_status = mac_status;
708 }
709
710 udelay(AH_TIME_QUANTUM);
711 }
712
713 if (i == 0) {
714 ath_err(common,
715 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
716 AH_RX_STOP_DMA_TIMEOUT / 1000,
717 REG_READ(ah, AR_CR),
718 REG_READ(ah, AR_DIAG_SW),
719 REG_READ(ah, AR_DMADBG_7));
720 return false;
721 } else {
722 return true;
723 }
724
725 #undef AH_RX_STOP_DMA_TIMEOUT
726 }
727 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
728
ath9k_hw_beaconq_setup(struct ath_hw * ah)729 int ath9k_hw_beaconq_setup(struct ath_hw *ah)
730 {
731 struct ath9k_tx_queue_info qi;
732
733 memset(&qi, 0, sizeof(qi));
734 qi.tqi_aifs = 1;
735 qi.tqi_cwmin = 0;
736 qi.tqi_cwmax = 0;
737
738 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
739 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
740
741 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
742 }
743 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
744
ath9k_hw_intrpend(struct ath_hw * ah)745 bool ath9k_hw_intrpend(struct ath_hw *ah)
746 {
747 u32 host_isr;
748
749 if (AR_SREV_9100(ah))
750 return true;
751
752 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
753
754 if (((host_isr & AR_INTR_MAC_IRQ) ||
755 (host_isr & AR_INTR_ASYNC_MASK_MCI)) &&
756 (host_isr != AR_INTR_SPURIOUS))
757 return true;
758
759 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
760 if ((host_isr & AR_INTR_SYNC_DEFAULT)
761 && (host_isr != AR_INTR_SPURIOUS))
762 return true;
763
764 return false;
765 }
766 EXPORT_SYMBOL(ath9k_hw_intrpend);
767
ath9k_hw_disable_interrupts(struct ath_hw * ah)768 void ath9k_hw_disable_interrupts(struct ath_hw *ah)
769 {
770 struct ath_common *common = ath9k_hw_common(ah);
771
772 if (!(ah->imask & ATH9K_INT_GLOBAL))
773 atomic_set(&ah->intr_ref_cnt, -1);
774 else
775 atomic_dec(&ah->intr_ref_cnt);
776
777 ath_dbg(common, INTERRUPT, "disable IER\n");
778 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
779 (void) REG_READ(ah, AR_IER);
780 if (!AR_SREV_9100(ah)) {
781 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
782 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
783
784 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
785 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
786 }
787 }
788 EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
789
ath9k_hw_enable_interrupts(struct ath_hw * ah)790 void ath9k_hw_enable_interrupts(struct ath_hw *ah)
791 {
792 struct ath_common *common = ath9k_hw_common(ah);
793 u32 sync_default = AR_INTR_SYNC_DEFAULT;
794 u32 async_mask;
795
796 if (!(ah->imask & ATH9K_INT_GLOBAL))
797 return;
798
799 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) {
800 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n",
801 atomic_read(&ah->intr_ref_cnt));
802 return;
803 }
804
805 if (AR_SREV_9340(ah))
806 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
807
808 async_mask = AR_INTR_MAC_IRQ;
809
810 if (ah->imask & ATH9K_INT_MCI)
811 async_mask |= AR_INTR_ASYNC_MASK_MCI;
812
813 ath_dbg(common, INTERRUPT, "enable IER\n");
814 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
815 if (!AR_SREV_9100(ah)) {
816 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
817 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);
818
819 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
820 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
821 }
822 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
823 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
824 }
825 EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
826
ath9k_hw_set_interrupts(struct ath_hw * ah)827 void ath9k_hw_set_interrupts(struct ath_hw *ah)
828 {
829 enum ath9k_int ints = ah->imask;
830 u32 mask, mask2;
831 struct ath9k_hw_capabilities *pCap = &ah->caps;
832 struct ath_common *common = ath9k_hw_common(ah);
833
834 if (!(ints & ATH9K_INT_GLOBAL))
835 ath9k_hw_disable_interrupts(ah);
836
837 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints);
838
839 mask = ints & ATH9K_INT_COMMON;
840 mask2 = 0;
841
842 if (ints & ATH9K_INT_TX) {
843 if (ah->config.tx_intr_mitigation)
844 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
845 else {
846 if (ah->txok_interrupt_mask)
847 mask |= AR_IMR_TXOK;
848 if (ah->txdesc_interrupt_mask)
849 mask |= AR_IMR_TXDESC;
850 }
851 if (ah->txerr_interrupt_mask)
852 mask |= AR_IMR_TXERR;
853 if (ah->txeol_interrupt_mask)
854 mask |= AR_IMR_TXEOL;
855 }
856 if (ints & ATH9K_INT_RX) {
857 if (AR_SREV_9300_20_OR_LATER(ah)) {
858 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
859 if (ah->config.rx_intr_mitigation) {
860 mask &= ~AR_IMR_RXOK_LP;
861 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
862 } else {
863 mask |= AR_IMR_RXOK_LP;
864 }
865 } else {
866 if (ah->config.rx_intr_mitigation)
867 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
868 else
869 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
870 }
871 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
872 mask |= AR_IMR_GENTMR;
873 }
874
875 if (ints & ATH9K_INT_GENTIMER)
876 mask |= AR_IMR_GENTMR;
877
878 if (ints & (ATH9K_INT_BMISC)) {
879 mask |= AR_IMR_BCNMISC;
880 if (ints & ATH9K_INT_TIM)
881 mask2 |= AR_IMR_S2_TIM;
882 if (ints & ATH9K_INT_DTIM)
883 mask2 |= AR_IMR_S2_DTIM;
884 if (ints & ATH9K_INT_DTIMSYNC)
885 mask2 |= AR_IMR_S2_DTIMSYNC;
886 if (ints & ATH9K_INT_CABEND)
887 mask2 |= AR_IMR_S2_CABEND;
888 if (ints & ATH9K_INT_TSFOOR)
889 mask2 |= AR_IMR_S2_TSFOOR;
890 }
891
892 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
893 mask |= AR_IMR_BCNMISC;
894 if (ints & ATH9K_INT_GTT)
895 mask2 |= AR_IMR_S2_GTT;
896 if (ints & ATH9K_INT_CST)
897 mask2 |= AR_IMR_S2_CST;
898 }
899
900 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
901 REG_WRITE(ah, AR_IMR, mask);
902 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
903 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
904 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
905 ah->imrs2_reg |= mask2;
906 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
907
908 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
909 if (ints & ATH9K_INT_TIM_TIMER)
910 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
911 else
912 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
913 }
914
915 return;
916 }
917 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
918