1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include "hw.h"
18 #include "hw-ops.h"
19 
ath9k_hw_set_txq_interrupts(struct ath_hw * ah,struct ath9k_tx_queue_info * qi)20 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
21 					struct ath9k_tx_queue_info *qi)
22 {
23 	ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
24 		"tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
25 		ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
26 		ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
27 		ah->txurn_interrupt_mask);
28 
29 	ENABLE_REGWRITE_BUFFER(ah);
30 
31 	REG_WRITE(ah, AR_IMR_S0,
32 		  SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
33 		  | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
34 	REG_WRITE(ah, AR_IMR_S1,
35 		  SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
36 		  | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
37 
38 	ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
39 	ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
40 	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
41 
42 	REGWRITE_BUFFER_FLUSH(ah);
43 }
44 
ath9k_hw_gettxbuf(struct ath_hw * ah,u32 q)45 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
46 {
47 	return REG_READ(ah, AR_QTXDP(q));
48 }
49 EXPORT_SYMBOL(ath9k_hw_gettxbuf);
50 
ath9k_hw_puttxbuf(struct ath_hw * ah,u32 q,u32 txdp)51 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
52 {
53 	REG_WRITE(ah, AR_QTXDP(q), txdp);
54 }
55 EXPORT_SYMBOL(ath9k_hw_puttxbuf);
56 
ath9k_hw_txstart(struct ath_hw * ah,u32 q)57 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
58 {
59 	ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
60 		"Enable TXE on queue: %u\n", q);
61 	REG_WRITE(ah, AR_Q_TXE, 1 << q);
62 }
63 EXPORT_SYMBOL(ath9k_hw_txstart);
64 
ath9k_hw_cleartxdesc(struct ath_hw * ah,void * ds)65 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
66 {
67 	struct ar5416_desc *ads = AR5416DESC(ds);
68 
69 	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
70 	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
71 	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
72 	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
73 	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
74 }
75 EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
76 
ath9k_hw_numtxpending(struct ath_hw * ah,u32 q)77 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
78 {
79 	u32 npend;
80 
81 	npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
82 	if (npend == 0) {
83 
84 		if (REG_READ(ah, AR_Q_TXE) & (1 << q))
85 			npend = 1;
86 	}
87 
88 	return npend;
89 }
90 EXPORT_SYMBOL(ath9k_hw_numtxpending);
91 
92 /**
93  * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
94  *
95  * @ah: atheros hardware struct
96  * @bIncTrigLevel: whether or not the frame trigger level should be updated
97  *
98  * The frame trigger level specifies the minimum number of bytes,
99  * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
100  * before the PCU will initiate sending the frame on the air. This can
101  * mean we initiate transmit before a full frame is on the PCU TX FIFO.
102  * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
103  * first)
104  *
105  * Caution must be taken to ensure to set the frame trigger level based
106  * on the DMA request size. For example if the DMA request size is set to
107  * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
108  * there need to be enough space in the tx FIFO for the requested transfer
109  * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
110  * the threshold to a value beyond 6, then the transmit will hang.
111  *
112  * Current dual   stream devices have a PCU TX FIFO size of 8 KB.
113  * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
114  * there is a hardware issue which forces us to use 2 KB instead so the
115  * frame trigger level must not exceed 2 KB for these chipsets.
116  */
ath9k_hw_updatetxtriglevel(struct ath_hw * ah,bool bIncTrigLevel)117 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
118 {
119 	u32 txcfg, curLevel, newLevel;
120 
121 	if (ah->tx_trig_level >= ah->config.max_txtrig_level)
122 		return false;
123 
124 	ath9k_hw_disable_interrupts(ah);
125 
126 	txcfg = REG_READ(ah, AR_TXCFG);
127 	curLevel = MS(txcfg, AR_FTRIG);
128 	newLevel = curLevel;
129 	if (bIncTrigLevel) {
130 		if (curLevel < ah->config.max_txtrig_level)
131 			newLevel++;
132 	} else if (curLevel > MIN_TX_FIFO_THRESHOLD)
133 		newLevel--;
134 	if (newLevel != curLevel)
135 		REG_WRITE(ah, AR_TXCFG,
136 			  (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
137 
138 	ath9k_hw_enable_interrupts(ah);
139 
140 	ah->tx_trig_level = newLevel;
141 
142 	return newLevel != curLevel;
143 }
144 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
145 
ath9k_hw_abort_tx_dma(struct ath_hw * ah)146 void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
147 {
148 	int i, q;
149 
150 	REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
151 
152 	REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
153 	REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
154 	REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
155 
156 	for (q = 0; q < AR_NUM_QCU; q++) {
157 		for (i = 0; i < 1000; i++) {
158 			if (i)
159 				udelay(5);
160 
161 			if (!ath9k_hw_numtxpending(ah, q))
162 				break;
163 		}
164 	}
165 
166 	REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
167 	REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
168 	REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
169 
170 	REG_WRITE(ah, AR_Q_TXD, 0);
171 }
172 EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
173 
ath9k_hw_stop_dma_queue(struct ath_hw * ah,u32 q)174 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
175 {
176 #define ATH9K_TX_STOP_DMA_TIMEOUT	1000    /* usec */
177 #define ATH9K_TIME_QUANTUM		100     /* usec */
178 	int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
179 	int wait;
180 
181 	REG_WRITE(ah, AR_Q_TXD, 1 << q);
182 
183 	for (wait = wait_time; wait != 0; wait--) {
184 		if (wait != wait_time)
185 			udelay(ATH9K_TIME_QUANTUM);
186 
187 		if (ath9k_hw_numtxpending(ah, q) == 0)
188 			break;
189 	}
190 
191 	REG_WRITE(ah, AR_Q_TXD, 0);
192 
193 	return wait != 0;
194 
195 #undef ATH9K_TX_STOP_DMA_TIMEOUT
196 #undef ATH9K_TIME_QUANTUM
197 }
198 EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
199 
ath9k_hw_gettxintrtxqs(struct ath_hw * ah,u32 * txqs)200 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
201 {
202 	*txqs &= ah->intr_txqs;
203 	ah->intr_txqs &= ~(*txqs);
204 }
205 EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
206 
ath9k_hw_set_txq_props(struct ath_hw * ah,int q,const struct ath9k_tx_queue_info * qinfo)207 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
208 			    const struct ath9k_tx_queue_info *qinfo)
209 {
210 	u32 cw;
211 	struct ath_common *common = ath9k_hw_common(ah);
212 	struct ath9k_hw_capabilities *pCap = &ah->caps;
213 	struct ath9k_tx_queue_info *qi;
214 
215 	if (q >= pCap->total_queues) {
216 		ath_dbg(common, ATH_DBG_QUEUE,
217 			"Set TXQ properties, invalid queue: %u\n", q);
218 		return false;
219 	}
220 
221 	qi = &ah->txq[q];
222 	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
223 		ath_dbg(common, ATH_DBG_QUEUE,
224 			"Set TXQ properties, inactive queue: %u\n", q);
225 		return false;
226 	}
227 
228 	ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
229 
230 	qi->tqi_ver = qinfo->tqi_ver;
231 	qi->tqi_subtype = qinfo->tqi_subtype;
232 	qi->tqi_qflags = qinfo->tqi_qflags;
233 	qi->tqi_priority = qinfo->tqi_priority;
234 	if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
235 		qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
236 	else
237 		qi->tqi_aifs = INIT_AIFS;
238 	if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
239 		cw = min(qinfo->tqi_cwmin, 1024U);
240 		qi->tqi_cwmin = 1;
241 		while (qi->tqi_cwmin < cw)
242 			qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
243 	} else
244 		qi->tqi_cwmin = qinfo->tqi_cwmin;
245 	if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
246 		cw = min(qinfo->tqi_cwmax, 1024U);
247 		qi->tqi_cwmax = 1;
248 		while (qi->tqi_cwmax < cw)
249 			qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
250 	} else
251 		qi->tqi_cwmax = INIT_CWMAX;
252 
253 	if (qinfo->tqi_shretry != 0)
254 		qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
255 	else
256 		qi->tqi_shretry = INIT_SH_RETRY;
257 	if (qinfo->tqi_lgretry != 0)
258 		qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
259 	else
260 		qi->tqi_lgretry = INIT_LG_RETRY;
261 	qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
262 	qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
263 	qi->tqi_burstTime = qinfo->tqi_burstTime;
264 	qi->tqi_readyTime = qinfo->tqi_readyTime;
265 
266 	switch (qinfo->tqi_subtype) {
267 	case ATH9K_WME_UPSD:
268 		if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
269 			qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
270 		break;
271 	default:
272 		break;
273 	}
274 
275 	return true;
276 }
277 EXPORT_SYMBOL(ath9k_hw_set_txq_props);
278 
ath9k_hw_get_txq_props(struct ath_hw * ah,int q,struct ath9k_tx_queue_info * qinfo)279 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
280 			    struct ath9k_tx_queue_info *qinfo)
281 {
282 	struct ath_common *common = ath9k_hw_common(ah);
283 	struct ath9k_hw_capabilities *pCap = &ah->caps;
284 	struct ath9k_tx_queue_info *qi;
285 
286 	if (q >= pCap->total_queues) {
287 		ath_dbg(common, ATH_DBG_QUEUE,
288 			"Get TXQ properties, invalid queue: %u\n", q);
289 		return false;
290 	}
291 
292 	qi = &ah->txq[q];
293 	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
294 		ath_dbg(common, ATH_DBG_QUEUE,
295 			"Get TXQ properties, inactive queue: %u\n", q);
296 		return false;
297 	}
298 
299 	qinfo->tqi_qflags = qi->tqi_qflags;
300 	qinfo->tqi_ver = qi->tqi_ver;
301 	qinfo->tqi_subtype = qi->tqi_subtype;
302 	qinfo->tqi_qflags = qi->tqi_qflags;
303 	qinfo->tqi_priority = qi->tqi_priority;
304 	qinfo->tqi_aifs = qi->tqi_aifs;
305 	qinfo->tqi_cwmin = qi->tqi_cwmin;
306 	qinfo->tqi_cwmax = qi->tqi_cwmax;
307 	qinfo->tqi_shretry = qi->tqi_shretry;
308 	qinfo->tqi_lgretry = qi->tqi_lgretry;
309 	qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
310 	qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
311 	qinfo->tqi_burstTime = qi->tqi_burstTime;
312 	qinfo->tqi_readyTime = qi->tqi_readyTime;
313 
314 	return true;
315 }
316 EXPORT_SYMBOL(ath9k_hw_get_txq_props);
317 
ath9k_hw_setuptxqueue(struct ath_hw * ah,enum ath9k_tx_queue type,const struct ath9k_tx_queue_info * qinfo)318 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
319 			  const struct ath9k_tx_queue_info *qinfo)
320 {
321 	struct ath_common *common = ath9k_hw_common(ah);
322 	struct ath9k_tx_queue_info *qi;
323 	struct ath9k_hw_capabilities *pCap = &ah->caps;
324 	int q;
325 
326 	switch (type) {
327 	case ATH9K_TX_QUEUE_BEACON:
328 		q = pCap->total_queues - 1;
329 		break;
330 	case ATH9K_TX_QUEUE_CAB:
331 		q = pCap->total_queues - 2;
332 		break;
333 	case ATH9K_TX_QUEUE_PSPOLL:
334 		q = 1;
335 		break;
336 	case ATH9K_TX_QUEUE_UAPSD:
337 		q = pCap->total_queues - 3;
338 		break;
339 	case ATH9K_TX_QUEUE_DATA:
340 		for (q = 0; q < pCap->total_queues; q++)
341 			if (ah->txq[q].tqi_type ==
342 			    ATH9K_TX_QUEUE_INACTIVE)
343 				break;
344 		if (q == pCap->total_queues) {
345 			ath_err(common, "No available TX queue\n");
346 			return -1;
347 		}
348 		break;
349 	default:
350 		ath_err(common, "Invalid TX queue type: %u\n", type);
351 		return -1;
352 	}
353 
354 	ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
355 
356 	qi = &ah->txq[q];
357 	if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
358 		ath_err(common, "TX queue: %u already active\n", q);
359 		return -1;
360 	}
361 	memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
362 	qi->tqi_type = type;
363 	if (qinfo == NULL) {
364 		qi->tqi_qflags =
365 			TXQ_FLAG_TXOKINT_ENABLE
366 			| TXQ_FLAG_TXERRINT_ENABLE
367 			| TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
368 		qi->tqi_aifs = INIT_AIFS;
369 		qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
370 		qi->tqi_cwmax = INIT_CWMAX;
371 		qi->tqi_shretry = INIT_SH_RETRY;
372 		qi->tqi_lgretry = INIT_LG_RETRY;
373 		qi->tqi_physCompBuf = 0;
374 	} else {
375 		qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
376 		(void) ath9k_hw_set_txq_props(ah, q, qinfo);
377 	}
378 
379 	return q;
380 }
381 EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
382 
ath9k_hw_releasetxqueue(struct ath_hw * ah,u32 q)383 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
384 {
385 	struct ath9k_hw_capabilities *pCap = &ah->caps;
386 	struct ath_common *common = ath9k_hw_common(ah);
387 	struct ath9k_tx_queue_info *qi;
388 
389 	if (q >= pCap->total_queues) {
390 		ath_dbg(common, ATH_DBG_QUEUE,
391 			"Release TXQ, invalid queue: %u\n", q);
392 		return false;
393 	}
394 	qi = &ah->txq[q];
395 	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
396 		ath_dbg(common, ATH_DBG_QUEUE,
397 			"Release TXQ, inactive queue: %u\n", q);
398 		return false;
399 	}
400 
401 	ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
402 
403 	qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
404 	ah->txok_interrupt_mask &= ~(1 << q);
405 	ah->txerr_interrupt_mask &= ~(1 << q);
406 	ah->txdesc_interrupt_mask &= ~(1 << q);
407 	ah->txeol_interrupt_mask &= ~(1 << q);
408 	ah->txurn_interrupt_mask &= ~(1 << q);
409 	ath9k_hw_set_txq_interrupts(ah, qi);
410 
411 	return true;
412 }
413 EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
414 
ath9k_hw_resettxqueue(struct ath_hw * ah,u32 q)415 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
416 {
417 	struct ath9k_hw_capabilities *pCap = &ah->caps;
418 	struct ath_common *common = ath9k_hw_common(ah);
419 	struct ath9k_channel *chan = ah->curchan;
420 	struct ath9k_tx_queue_info *qi;
421 	u32 cwMin, chanCwMin, value;
422 
423 	if (q >= pCap->total_queues) {
424 		ath_dbg(common, ATH_DBG_QUEUE,
425 			"Reset TXQ, invalid queue: %u\n", q);
426 		return false;
427 	}
428 
429 	qi = &ah->txq[q];
430 	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
431 		ath_dbg(common, ATH_DBG_QUEUE,
432 			"Reset TXQ, inactive queue: %u\n", q);
433 		return true;
434 	}
435 
436 	ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
437 
438 	if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
439 		if (chan && IS_CHAN_B(chan))
440 			chanCwMin = INIT_CWMIN_11B;
441 		else
442 			chanCwMin = INIT_CWMIN;
443 
444 		for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
445 	} else
446 		cwMin = qi->tqi_cwmin;
447 
448 	ENABLE_REGWRITE_BUFFER(ah);
449 
450 	REG_WRITE(ah, AR_DLCL_IFS(q),
451 		  SM(cwMin, AR_D_LCL_IFS_CWMIN) |
452 		  SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
453 		  SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
454 
455 	REG_WRITE(ah, AR_DRETRY_LIMIT(q),
456 		  SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
457 		  SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
458 		  SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
459 
460 	REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
461 	REG_WRITE(ah, AR_DMISC(q),
462 		  AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
463 
464 	if (qi->tqi_cbrPeriod) {
465 		REG_WRITE(ah, AR_QCBRCFG(q),
466 			  SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
467 			  SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
468 		REG_WRITE(ah, AR_QMISC(q),
469 			  REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
470 			  (qi->tqi_cbrOverflowLimit ?
471 			   AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
472 	}
473 	if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
474 		REG_WRITE(ah, AR_QRDYTIMECFG(q),
475 			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
476 			  AR_Q_RDYTIMECFG_EN);
477 	}
478 
479 	REG_WRITE(ah, AR_DCHNTIME(q),
480 		  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
481 		  (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
482 
483 	if (qi->tqi_burstTime
484 	    && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
485 		REG_WRITE(ah, AR_QMISC(q),
486 			  REG_READ(ah, AR_QMISC(q)) |
487 			  AR_Q_MISC_RDYTIME_EXP_POLICY);
488 
489 	}
490 
491 	if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
492 		REG_WRITE(ah, AR_DMISC(q),
493 			  REG_READ(ah, AR_DMISC(q)) |
494 			  AR_D_MISC_POST_FR_BKOFF_DIS);
495 	}
496 
497 	REGWRITE_BUFFER_FLUSH(ah);
498 
499 	if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
500 		REG_WRITE(ah, AR_DMISC(q),
501 			  REG_READ(ah, AR_DMISC(q)) |
502 			  AR_D_MISC_FRAG_BKOFF_EN);
503 	}
504 	switch (qi->tqi_type) {
505 	case ATH9K_TX_QUEUE_BEACON:
506 		ENABLE_REGWRITE_BUFFER(ah);
507 
508 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
509 			  | AR_Q_MISC_FSP_DBA_GATED
510 			  | AR_Q_MISC_BEACON_USE
511 			  | AR_Q_MISC_CBR_INCR_DIS1);
512 
513 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
514 			  | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
515 			     AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
516 			  | AR_D_MISC_BEACON_USE
517 			  | AR_D_MISC_POST_FR_BKOFF_DIS);
518 
519 		REGWRITE_BUFFER_FLUSH(ah);
520 
521 		/*
522 		 * cwmin and cwmax should be 0 for beacon queue
523 		 * but not for IBSS as we would create an imbalance
524 		 * on beaconing fairness for participating nodes.
525 		 */
526 		if (AR_SREV_9300_20_OR_LATER(ah) &&
527 		    ah->opmode != NL80211_IFTYPE_ADHOC) {
528 			REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
529 				  | SM(0, AR_D_LCL_IFS_CWMAX)
530 				  | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
531 		}
532 		break;
533 	case ATH9K_TX_QUEUE_CAB:
534 		ENABLE_REGWRITE_BUFFER(ah);
535 
536 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
537 			  | AR_Q_MISC_FSP_DBA_GATED
538 			  | AR_Q_MISC_CBR_INCR_DIS1
539 			  | AR_Q_MISC_CBR_INCR_DIS0);
540 		value = (qi->tqi_readyTime -
541 			 (ah->config.sw_beacon_response_time -
542 			  ah->config.dma_beacon_response_time) -
543 			 ah->config.additional_swba_backoff) * 1024;
544 		REG_WRITE(ah, AR_QRDYTIMECFG(q),
545 			  value | AR_Q_RDYTIMECFG_EN);
546 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
547 			  | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
548 			     AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
549 
550 		REGWRITE_BUFFER_FLUSH(ah);
551 
552 		break;
553 	case ATH9K_TX_QUEUE_PSPOLL:
554 		REG_WRITE(ah, AR_QMISC(q),
555 			  REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
556 		break;
557 	case ATH9K_TX_QUEUE_UAPSD:
558 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
559 			  AR_D_MISC_POST_FR_BKOFF_DIS);
560 		break;
561 	default:
562 		break;
563 	}
564 
565 	if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
566 		REG_WRITE(ah, AR_DMISC(q),
567 			  REG_READ(ah, AR_DMISC(q)) |
568 			  SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
569 			     AR_D_MISC_ARB_LOCKOUT_CNTRL) |
570 			  AR_D_MISC_POST_FR_BKOFF_DIS);
571 	}
572 
573 	if (AR_SREV_9300_20_OR_LATER(ah))
574 		REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
575 
576 	if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
577 		ah->txok_interrupt_mask |= 1 << q;
578 	else
579 		ah->txok_interrupt_mask &= ~(1 << q);
580 	if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
581 		ah->txerr_interrupt_mask |= 1 << q;
582 	else
583 		ah->txerr_interrupt_mask &= ~(1 << q);
584 	if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
585 		ah->txdesc_interrupt_mask |= 1 << q;
586 	else
587 		ah->txdesc_interrupt_mask &= ~(1 << q);
588 	if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
589 		ah->txeol_interrupt_mask |= 1 << q;
590 	else
591 		ah->txeol_interrupt_mask &= ~(1 << q);
592 	if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
593 		ah->txurn_interrupt_mask |= 1 << q;
594 	else
595 		ah->txurn_interrupt_mask &= ~(1 << q);
596 	ath9k_hw_set_txq_interrupts(ah, qi);
597 
598 	return true;
599 }
600 EXPORT_SYMBOL(ath9k_hw_resettxqueue);
601 
ath9k_hw_rxprocdesc(struct ath_hw * ah,struct ath_desc * ds,struct ath_rx_status * rs,u64 tsf)602 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
603 			struct ath_rx_status *rs, u64 tsf)
604 {
605 	struct ar5416_desc ads;
606 	struct ar5416_desc *adsp = AR5416DESC(ds);
607 	u32 phyerr;
608 
609 	if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
610 		return -EINPROGRESS;
611 
612 	ads.u.rx = adsp->u.rx;
613 
614 	rs->rs_status = 0;
615 	rs->rs_flags = 0;
616 
617 	rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
618 	rs->rs_tstamp = ads.AR_RcvTimestamp;
619 
620 	if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
621 		rs->rs_rssi = ATH9K_RSSI_BAD;
622 		rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
623 		rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
624 		rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
625 		rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
626 		rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
627 		rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
628 	} else {
629 		rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
630 		rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
631 						AR_RxRSSIAnt00);
632 		rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
633 						AR_RxRSSIAnt01);
634 		rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
635 						AR_RxRSSIAnt02);
636 		rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
637 						AR_RxRSSIAnt10);
638 		rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
639 						AR_RxRSSIAnt11);
640 		rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
641 						AR_RxRSSIAnt12);
642 	}
643 	if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
644 		rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
645 	else
646 		rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
647 
648 	rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
649 	rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
650 
651 	rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
652 	rs->rs_moreaggr =
653 		(ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
654 	rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
655 	rs->rs_flags =
656 		(ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
657 	rs->rs_flags |=
658 		(ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
659 
660 	if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
661 		rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
662 	if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
663 		rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
664 	if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
665 		rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
666 
667 	if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
668 		/*
669 		 * Treat these errors as mutually exclusive to avoid spurious
670 		 * extra error reports from the hardware. If a CRC error is
671 		 * reported, then decryption and MIC errors are irrelevant,
672 		 * the frame is going to be dropped either way
673 		 */
674 		if (ads.ds_rxstatus8 & AR_CRCErr)
675 			rs->rs_status |= ATH9K_RXERR_CRC;
676 		else if (ads.ds_rxstatus8 & AR_PHYErr) {
677 			rs->rs_status |= ATH9K_RXERR_PHY;
678 			phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
679 			rs->rs_phyerr = phyerr;
680 		} else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
681 			rs->rs_status |= ATH9K_RXERR_DECRYPT;
682 		else if (ads.ds_rxstatus8 & AR_MichaelErr)
683 			rs->rs_status |= ATH9K_RXERR_MIC;
684 
685 		if (ads.ds_rxstatus8 & AR_KeyMiss)
686 			rs->rs_status |= ATH9K_RXERR_DECRYPT;
687 	}
688 
689 	return 0;
690 }
691 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
692 
693 /*
694  * This can stop or re-enables RX.
695  *
696  * If bool is set this will kill any frame which is currently being
697  * transferred between the MAC and baseband and also prevent any new
698  * frames from getting started.
699  */
ath9k_hw_setrxabort(struct ath_hw * ah,bool set)700 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
701 {
702 	u32 reg;
703 
704 	if (set) {
705 		REG_SET_BIT(ah, AR_DIAG_SW,
706 			    (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
707 
708 		if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
709 				   0, AH_WAIT_TIMEOUT)) {
710 			REG_CLR_BIT(ah, AR_DIAG_SW,
711 				    (AR_DIAG_RX_DIS |
712 				     AR_DIAG_RX_ABORT));
713 
714 			reg = REG_READ(ah, AR_OBS_BUS_1);
715 			ath_err(ath9k_hw_common(ah),
716 				"RX failed to go idle in 10 ms RXSM=0x%x\n",
717 				reg);
718 
719 			return false;
720 		}
721 	} else {
722 		REG_CLR_BIT(ah, AR_DIAG_SW,
723 			    (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
724 	}
725 
726 	return true;
727 }
728 EXPORT_SYMBOL(ath9k_hw_setrxabort);
729 
ath9k_hw_putrxbuf(struct ath_hw * ah,u32 rxdp)730 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
731 {
732 	REG_WRITE(ah, AR_RXDP, rxdp);
733 }
734 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
735 
ath9k_hw_startpcureceive(struct ath_hw * ah,bool is_scanning)736 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
737 {
738 	ath9k_enable_mib_counters(ah);
739 
740 	ath9k_ani_reset(ah, is_scanning);
741 
742 	REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
743 }
744 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
745 
ath9k_hw_abortpcurecv(struct ath_hw * ah)746 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
747 {
748 	REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
749 
750 	ath9k_hw_disable_mib_counters(ah);
751 }
752 EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
753 
ath9k_hw_stopdmarecv(struct ath_hw * ah,bool * reset)754 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
755 {
756 #define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
757 #define AH_RX_TIME_QUANTUM     100     /* usec */
758 	struct ath_common *common = ath9k_hw_common(ah);
759 	u32 mac_status, last_mac_status = 0;
760 	int i;
761 
762 	/* Enable access to the DMA observation bus */
763 	REG_WRITE(ah, AR_MACMISC,
764 		  ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
765 		   (AR_MACMISC_MISC_OBS_BUS_1 <<
766 		    AR_MACMISC_MISC_OBS_BUS_MSB_S)));
767 
768 	REG_WRITE(ah, AR_CR, AR_CR_RXD);
769 
770 	/* Wait for rx enable bit to go low */
771 	for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
772 		if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
773 			break;
774 
775 		if (!AR_SREV_9300_20_OR_LATER(ah)) {
776 			mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
777 			if (mac_status == 0x1c0 && mac_status == last_mac_status) {
778 				*reset = true;
779 				break;
780 			}
781 
782 			last_mac_status = mac_status;
783 		}
784 
785 		udelay(AH_TIME_QUANTUM);
786 	}
787 
788 	if (i == 0) {
789 		ath_err(common,
790 			"DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
791 			AH_RX_STOP_DMA_TIMEOUT / 1000,
792 			REG_READ(ah, AR_CR),
793 			REG_READ(ah, AR_DIAG_SW),
794 			REG_READ(ah, AR_DMADBG_7));
795 		return false;
796 	} else {
797 		return true;
798 	}
799 
800 #undef AH_RX_TIME_QUANTUM
801 #undef AH_RX_STOP_DMA_TIMEOUT
802 }
803 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
804 
ath9k_hw_beaconq_setup(struct ath_hw * ah)805 int ath9k_hw_beaconq_setup(struct ath_hw *ah)
806 {
807 	struct ath9k_tx_queue_info qi;
808 
809 	memset(&qi, 0, sizeof(qi));
810 	qi.tqi_aifs = 1;
811 	qi.tqi_cwmin = 0;
812 	qi.tqi_cwmax = 0;
813 	/* NB: don't enable any interrupts */
814 	return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
815 }
816 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
817 
ath9k_hw_intrpend(struct ath_hw * ah)818 bool ath9k_hw_intrpend(struct ath_hw *ah)
819 {
820 	u32 host_isr;
821 
822 	if (AR_SREV_9100(ah))
823 		return true;
824 
825 	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
826 	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
827 		return true;
828 
829 	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
830 	if ((host_isr & AR_INTR_SYNC_DEFAULT)
831 	    && (host_isr != AR_INTR_SPURIOUS))
832 		return true;
833 
834 	return false;
835 }
836 EXPORT_SYMBOL(ath9k_hw_intrpend);
837 
ath9k_hw_disable_interrupts(struct ath_hw * ah)838 void ath9k_hw_disable_interrupts(struct ath_hw *ah)
839 {
840 	struct ath_common *common = ath9k_hw_common(ah);
841 
842 	ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
843 	REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
844 	(void) REG_READ(ah, AR_IER);
845 	if (!AR_SREV_9100(ah)) {
846 		REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
847 		(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
848 
849 		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
850 		(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
851 	}
852 }
853 EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
854 
ath9k_hw_enable_interrupts(struct ath_hw * ah)855 void ath9k_hw_enable_interrupts(struct ath_hw *ah)
856 {
857 	struct ath_common *common = ath9k_hw_common(ah);
858 
859 	if (!(ah->imask & ATH9K_INT_GLOBAL))
860 		return;
861 
862 	ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
863 	REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
864 	if (!AR_SREV_9100(ah)) {
865 		REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
866 			  AR_INTR_MAC_IRQ);
867 		REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
868 
869 
870 		REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
871 			  AR_INTR_SYNC_DEFAULT);
872 		REG_WRITE(ah, AR_INTR_SYNC_MASK,
873 			  AR_INTR_SYNC_DEFAULT);
874 	}
875 	ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
876 		REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
877 }
878 EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
879 
ath9k_hw_set_interrupts(struct ath_hw * ah,enum ath9k_int ints)880 void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
881 {
882 	enum ath9k_int omask = ah->imask;
883 	u32 mask, mask2;
884 	struct ath9k_hw_capabilities *pCap = &ah->caps;
885 	struct ath_common *common = ath9k_hw_common(ah);
886 
887 	if (!(ints & ATH9K_INT_GLOBAL))
888 		ath9k_hw_disable_interrupts(ah);
889 
890 	ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
891 
892 	/* TODO: global int Ref count */
893 	mask = ints & ATH9K_INT_COMMON;
894 	mask2 = 0;
895 
896 	if (ints & ATH9K_INT_TX) {
897 		if (ah->config.tx_intr_mitigation)
898 			mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
899 		else {
900 			if (ah->txok_interrupt_mask)
901 				mask |= AR_IMR_TXOK;
902 			if (ah->txdesc_interrupt_mask)
903 				mask |= AR_IMR_TXDESC;
904 		}
905 		if (ah->txerr_interrupt_mask)
906 			mask |= AR_IMR_TXERR;
907 		if (ah->txeol_interrupt_mask)
908 			mask |= AR_IMR_TXEOL;
909 	}
910 	if (ints & ATH9K_INT_RX) {
911 		if (AR_SREV_9300_20_OR_LATER(ah)) {
912 			mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
913 			if (ah->config.rx_intr_mitigation) {
914 				mask &= ~AR_IMR_RXOK_LP;
915 				mask |=  AR_IMR_RXMINTR | AR_IMR_RXINTM;
916 			} else {
917 				mask |= AR_IMR_RXOK_LP;
918 			}
919 		} else {
920 			if (ah->config.rx_intr_mitigation)
921 				mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
922 			else
923 				mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
924 		}
925 		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
926 			mask |= AR_IMR_GENTMR;
927 	}
928 
929 	if (ints & (ATH9K_INT_BMISC)) {
930 		mask |= AR_IMR_BCNMISC;
931 		if (ints & ATH9K_INT_TIM)
932 			mask2 |= AR_IMR_S2_TIM;
933 		if (ints & ATH9K_INT_DTIM)
934 			mask2 |= AR_IMR_S2_DTIM;
935 		if (ints & ATH9K_INT_DTIMSYNC)
936 			mask2 |= AR_IMR_S2_DTIMSYNC;
937 		if (ints & ATH9K_INT_CABEND)
938 			mask2 |= AR_IMR_S2_CABEND;
939 		if (ints & ATH9K_INT_TSFOOR)
940 			mask2 |= AR_IMR_S2_TSFOOR;
941 	}
942 
943 	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
944 		mask |= AR_IMR_BCNMISC;
945 		if (ints & ATH9K_INT_GTT)
946 			mask2 |= AR_IMR_S2_GTT;
947 		if (ints & ATH9K_INT_CST)
948 			mask2 |= AR_IMR_S2_CST;
949 	}
950 
951 	ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
952 	REG_WRITE(ah, AR_IMR, mask);
953 	ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
954 			   AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
955 			   AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
956 	ah->imrs2_reg |= mask2;
957 	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
958 
959 	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
960 		if (ints & ATH9K_INT_TIM_TIMER)
961 			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
962 		else
963 			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
964 	}
965 
966 	if (ints & ATH9K_INT_GLOBAL)
967 		ath9k_hw_enable_interrupts(ah);
968 
969 	return;
970 }
971 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
972