1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
42 #include "hw.h"
43 #include "ar9002_phy.h"
44
45 /**
46 * ar9002_hw_set_channel - set channel on single-chip device
47 * @ah: atheros hardware structure
48 * @chan:
49 *
50 * This is the function to change channel on single-chip devices, that is
51 * all devices after ar9280.
52 *
53 * This function takes the channel value in MHz and sets
54 * hardware channel value. Assumes writes have been enabled to analog bus.
55 *
56 * Actual Expression,
57 *
58 * For 2GHz channel,
59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
60 * (freq_ref = 40MHz)
61 *
62 * For 5GHz channel,
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
64 * (freq_ref = 40MHz/(24>>amodeRefSel))
65 */
ar9002_hw_set_channel(struct ath_hw * ah,struct ath9k_channel * chan)66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
67 {
68 u16 bMode, fracMode, aModeRefSel = 0;
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70 struct chan_centers centers;
71 u32 refDivA = 24;
72
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
74 freq = centers.synth_center;
75
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
77 reg32 &= 0xc0000000;
78
79 if (freq < 4800) { /* 2 GHz, fractional mode */
80 u32 txctl;
81 int regWrites = 0;
82
83 bMode = 1;
84 fracMode = 1;
85 aModeRefSel = 0;
86 channelSel = CHANSEL_2G(freq);
87
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
89 if (freq == 2484) {
90 /* Enable channel spreading for channel 14 */
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
92 1, regWrites);
93 } else {
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
95 1, regWrites);
96 }
97 } else {
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
99 if (freq == 2484) {
100 /* Enable channel spreading for channel 14 */
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
102 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
103 } else {
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
105 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
106 }
107 }
108 } else {
109 bMode = 0;
110 fracMode = 0;
111
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
113 case 0:
114 if ((freq % 20) == 0)
115 aModeRefSel = 3;
116 else if ((freq % 10) == 0)
117 aModeRefSel = 2;
118 if (aModeRefSel)
119 break;
120 case 1:
121 default:
122 aModeRefSel = 0;
123 /*
124 * Enable 2G (fractional) mode for channels
125 * which are 5MHz spaced.
126 */
127 fracMode = 1;
128 refDivA = 1;
129 channelSel = CHANSEL_5G(freq);
130
131 /* RefDivA setting */
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
133 AR_AN_SYNTH9_REFDIVA, refDivA);
134
135 }
136
137 if (!fracMode) {
138 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
139 channelSel = ndiv & 0x1ff;
140 channelFrac = (ndiv & 0xfffffe00) * 2;
141 channelSel = (channelSel << 17) | channelFrac;
142 }
143 }
144
145 reg32 = reg32 |
146 (bMode << 29) |
147 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
148
149 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
150
151 ah->curchan = chan;
152 ah->curchan_rad_index = -1;
153
154 return 0;
155 }
156
157 /**
158 * ar9002_hw_spur_mitigate - convert baseband spur frequency
159 * @ah: atheros hardware structure
160 * @chan:
161 *
162 * For single-chip solutions. Converts to baseband spur frequency given the
163 * input channel frequency and compute register settings below.
164 */
ar9002_hw_spur_mitigate(struct ath_hw * ah,struct ath9k_channel * chan)165 static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
166 struct ath9k_channel *chan)
167 {
168 int bb_spur = AR_NO_SPUR;
169 int freq;
170 int bin, cur_bin;
171 int bb_spur_off, spur_subchannel_sd;
172 int spur_freq_sd;
173 int spur_delta_phase;
174 int denominator;
175 int upper, lower, cur_vit_mask;
176 int tmp, newVal;
177 int i;
178 static const int pilot_mask_reg[4] = {
179 AR_PHY_TIMING7, AR_PHY_TIMING8,
180 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
181 };
182 static const int chan_mask_reg[4] = {
183 AR_PHY_TIMING9, AR_PHY_TIMING10,
184 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
185 };
186 static const int inc[4] = { 0, 100, 0, 0 };
187 struct chan_centers centers;
188
189 int8_t mask_m[123];
190 int8_t mask_p[123];
191 int8_t mask_amt;
192 int tmp_mask;
193 int cur_bb_spur;
194 bool is2GHz = IS_CHAN_2GHZ(chan);
195
196 memset(&mask_m, 0, sizeof(int8_t) * 123);
197 memset(&mask_p, 0, sizeof(int8_t) * 123);
198
199 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
200 freq = centers.synth_center;
201
202 ah->config.spurmode = SPUR_ENABLE_EEPROM;
203 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
204 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
205
206 if (AR_NO_SPUR == cur_bb_spur)
207 break;
208
209 if (is2GHz)
210 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
211 else
212 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
213
214 cur_bb_spur = cur_bb_spur - freq;
215
216 if (IS_CHAN_HT40(chan)) {
217 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
218 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
219 bb_spur = cur_bb_spur;
220 break;
221 }
222 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
223 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
224 bb_spur = cur_bb_spur;
225 break;
226 }
227 }
228
229 if (AR_NO_SPUR == bb_spur) {
230 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
231 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
232 return;
233 } else {
234 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
235 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
236 }
237
238 bin = bb_spur * 320;
239
240 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
241
242 ENABLE_REGWRITE_BUFFER(ah);
243
244 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
245 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
246 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
247 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
248 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
249
250 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
251 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
252 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
253 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
254 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
255 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
256
257 if (IS_CHAN_HT40(chan)) {
258 if (bb_spur < 0) {
259 spur_subchannel_sd = 1;
260 bb_spur_off = bb_spur + 10;
261 } else {
262 spur_subchannel_sd = 0;
263 bb_spur_off = bb_spur - 10;
264 }
265 } else {
266 spur_subchannel_sd = 0;
267 bb_spur_off = bb_spur;
268 }
269
270 if (IS_CHAN_HT40(chan))
271 spur_delta_phase =
272 ((bb_spur * 262144) /
273 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
274 else
275 spur_delta_phase =
276 ((bb_spur * 524288) /
277 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
278
279 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
280 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
281
282 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
283 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
284 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
285 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
286
287 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
288 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
289
290 cur_bin = -6000;
291 upper = bin + 100;
292 lower = bin - 100;
293
294 for (i = 0; i < 4; i++) {
295 int pilot_mask = 0;
296 int chan_mask = 0;
297 int bp = 0;
298 for (bp = 0; bp < 30; bp++) {
299 if ((cur_bin > lower) && (cur_bin < upper)) {
300 pilot_mask = pilot_mask | 0x1 << bp;
301 chan_mask = chan_mask | 0x1 << bp;
302 }
303 cur_bin += 100;
304 }
305 cur_bin += inc[i];
306 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
307 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
308 }
309
310 cur_vit_mask = 6100;
311 upper = bin + 120;
312 lower = bin - 120;
313
314 for (i = 0; i < 123; i++) {
315 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
316
317 /* workaround for gcc bug #37014 */
318 volatile int tmp_v = abs(cur_vit_mask - bin);
319
320 if (tmp_v < 75)
321 mask_amt = 1;
322 else
323 mask_amt = 0;
324 if (cur_vit_mask < 0)
325 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
326 else
327 mask_p[cur_vit_mask / 100] = mask_amt;
328 }
329 cur_vit_mask -= 100;
330 }
331
332 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
333 | (mask_m[48] << 26) | (mask_m[49] << 24)
334 | (mask_m[50] << 22) | (mask_m[51] << 20)
335 | (mask_m[52] << 18) | (mask_m[53] << 16)
336 | (mask_m[54] << 14) | (mask_m[55] << 12)
337 | (mask_m[56] << 10) | (mask_m[57] << 8)
338 | (mask_m[58] << 6) | (mask_m[59] << 4)
339 | (mask_m[60] << 2) | (mask_m[61] << 0);
340 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
341 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
342
343 tmp_mask = (mask_m[31] << 28)
344 | (mask_m[32] << 26) | (mask_m[33] << 24)
345 | (mask_m[34] << 22) | (mask_m[35] << 20)
346 | (mask_m[36] << 18) | (mask_m[37] << 16)
347 | (mask_m[48] << 14) | (mask_m[39] << 12)
348 | (mask_m[40] << 10) | (mask_m[41] << 8)
349 | (mask_m[42] << 6) | (mask_m[43] << 4)
350 | (mask_m[44] << 2) | (mask_m[45] << 0);
351 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
352 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
353
354 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
355 | (mask_m[18] << 26) | (mask_m[18] << 24)
356 | (mask_m[20] << 22) | (mask_m[20] << 20)
357 | (mask_m[22] << 18) | (mask_m[22] << 16)
358 | (mask_m[24] << 14) | (mask_m[24] << 12)
359 | (mask_m[25] << 10) | (mask_m[26] << 8)
360 | (mask_m[27] << 6) | (mask_m[28] << 4)
361 | (mask_m[29] << 2) | (mask_m[30] << 0);
362 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
363 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
364
365 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
366 | (mask_m[2] << 26) | (mask_m[3] << 24)
367 | (mask_m[4] << 22) | (mask_m[5] << 20)
368 | (mask_m[6] << 18) | (mask_m[7] << 16)
369 | (mask_m[8] << 14) | (mask_m[9] << 12)
370 | (mask_m[10] << 10) | (mask_m[11] << 8)
371 | (mask_m[12] << 6) | (mask_m[13] << 4)
372 | (mask_m[14] << 2) | (mask_m[15] << 0);
373 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
374 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
375
376 tmp_mask = (mask_p[15] << 28)
377 | (mask_p[14] << 26) | (mask_p[13] << 24)
378 | (mask_p[12] << 22) | (mask_p[11] << 20)
379 | (mask_p[10] << 18) | (mask_p[9] << 16)
380 | (mask_p[8] << 14) | (mask_p[7] << 12)
381 | (mask_p[6] << 10) | (mask_p[5] << 8)
382 | (mask_p[4] << 6) | (mask_p[3] << 4)
383 | (mask_p[2] << 2) | (mask_p[1] << 0);
384 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
385 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
386
387 tmp_mask = (mask_p[30] << 28)
388 | (mask_p[29] << 26) | (mask_p[28] << 24)
389 | (mask_p[27] << 22) | (mask_p[26] << 20)
390 | (mask_p[25] << 18) | (mask_p[24] << 16)
391 | (mask_p[23] << 14) | (mask_p[22] << 12)
392 | (mask_p[21] << 10) | (mask_p[20] << 8)
393 | (mask_p[19] << 6) | (mask_p[18] << 4)
394 | (mask_p[17] << 2) | (mask_p[16] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
397
398 tmp_mask = (mask_p[45] << 28)
399 | (mask_p[44] << 26) | (mask_p[43] << 24)
400 | (mask_p[42] << 22) | (mask_p[41] << 20)
401 | (mask_p[40] << 18) | (mask_p[39] << 16)
402 | (mask_p[38] << 14) | (mask_p[37] << 12)
403 | (mask_p[36] << 10) | (mask_p[35] << 8)
404 | (mask_p[34] << 6) | (mask_p[33] << 4)
405 | (mask_p[32] << 2) | (mask_p[31] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
408
409 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
410 | (mask_p[59] << 26) | (mask_p[58] << 24)
411 | (mask_p[57] << 22) | (mask_p[56] << 20)
412 | (mask_p[55] << 18) | (mask_p[54] << 16)
413 | (mask_p[53] << 14) | (mask_p[52] << 12)
414 | (mask_p[51] << 10) | (mask_p[50] << 8)
415 | (mask_p[49] << 6) | (mask_p[48] << 4)
416 | (mask_p[47] << 2) | (mask_p[46] << 0);
417 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
419
420 REGWRITE_BUFFER_FLUSH(ah);
421 }
422
ar9002_olc_init(struct ath_hw * ah)423 static void ar9002_olc_init(struct ath_hw *ah)
424 {
425 u32 i;
426
427 if (!OLC_FOR_AR9280_20_LATER)
428 return;
429
430 if (OLC_FOR_AR9287_10_LATER) {
431 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
432 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
433 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
434 AR9287_AN_TXPC0_TXPCMODE,
435 AR9287_AN_TXPC0_TXPCMODE_S,
436 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
437 udelay(100);
438 } else {
439 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
440 ah->originalGain[i] =
441 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
442 AR_PHY_TX_GAIN);
443 ah->PDADCdelta = 0;
444 }
445 }
446
ar9002_hw_compute_pll_control(struct ath_hw * ah,struct ath9k_channel * chan)447 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
448 struct ath9k_channel *chan)
449 {
450 u32 pll;
451
452 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
453
454 if (chan && IS_CHAN_HALF_RATE(chan))
455 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
456 else if (chan && IS_CHAN_QUARTER_RATE(chan))
457 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
458
459 if (chan && IS_CHAN_5GHZ(chan)) {
460 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
461 pll = 0x142c;
462 else if (AR_SREV_9280_20(ah))
463 pll = 0x2850;
464 else
465 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
466 } else {
467 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
468 }
469
470 return pll;
471 }
472
ar9002_hw_do_getnf(struct ath_hw * ah,int16_t nfarray[NUM_NF_READINGS])473 static void ar9002_hw_do_getnf(struct ath_hw *ah,
474 int16_t nfarray[NUM_NF_READINGS])
475 {
476 int16_t nf;
477
478 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
479 nfarray[0] = sign_extend32(nf, 8);
480
481 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
482 if (IS_CHAN_HT40(ah->curchan))
483 nfarray[3] = sign_extend32(nf, 8);
484
485 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
486 return;
487
488 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
489 nfarray[1] = sign_extend32(nf, 8);
490
491 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
492 if (IS_CHAN_HT40(ah->curchan))
493 nfarray[4] = sign_extend32(nf, 8);
494 }
495
ar9002_hw_set_nf_limits(struct ath_hw * ah)496 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
497 {
498 if (AR_SREV_9285(ah)) {
499 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
500 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
501 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
502 } else if (AR_SREV_9287(ah)) {
503 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
504 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
505 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
506 } else if (AR_SREV_9271(ah)) {
507 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
508 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
509 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
510 } else {
511 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
512 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
513 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
514 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
515 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
516 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
517 }
518 }
519
ar9002_hw_attach_phy_ops(struct ath_hw * ah)520 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
521 {
522 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
523
524 priv_ops->set_rf_regs = NULL;
525 priv_ops->rf_alloc_ext_banks = NULL;
526 priv_ops->rf_free_ext_banks = NULL;
527 priv_ops->rf_set_freq = ar9002_hw_set_channel;
528 priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
529 priv_ops->olc_init = ar9002_olc_init;
530 priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
531 priv_ops->do_getnf = ar9002_hw_do_getnf;
532
533 ar9002_hw_set_nf_limits(ah);
534 }
535
ath9k_hw_antdiv_comb_conf_get(struct ath_hw * ah,struct ath_hw_antcomb_conf * antconf)536 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
537 struct ath_hw_antcomb_conf *antconf)
538 {
539 u32 regval;
540
541 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
542 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
543 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
544 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
545 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
546 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
547 AR_PHY_9285_FAST_DIV_BIAS_S;
548 }
549 EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_get);
550
ath9k_hw_antdiv_comb_conf_set(struct ath_hw * ah,struct ath_hw_antcomb_conf * antconf)551 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
552 struct ath_hw_antcomb_conf *antconf)
553 {
554 u32 regval;
555
556 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
557 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
558 AR_PHY_9285_ANT_DIV_ALT_LNACONF |
559 AR_PHY_9285_FAST_DIV_BIAS);
560 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
561 & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
562 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
563 & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
564 regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
565 & AR_PHY_9285_FAST_DIV_BIAS);
566
567 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
568 }
569 EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_set);
570