1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 */
18
19 /*************************************\
20 * Attach/Detach Functions and helpers *
21 \*************************************/
22
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include "ath5k.h"
26 #include "reg.h"
27 #include "debug.h"
28 #include "base.h"
29
30 /**
31 * ath5k_hw_post - Power On Self Test helper function
32 *
33 * @ah: The &struct ath5k_hw
34 */
ath5k_hw_post(struct ath5k_hw * ah)35 static int ath5k_hw_post(struct ath5k_hw *ah)
36 {
37
38 static const u32 static_pattern[4] = {
39 0x55555555, 0xaaaaaaaa,
40 0x66666666, 0x99999999
41 };
42 static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
43 int i, c;
44 u16 cur_reg;
45 u32 var_pattern;
46 u32 init_val;
47 u32 cur_val;
48
49 for (c = 0; c < 2; c++) {
50
51 cur_reg = regs[c];
52
53 /* Save previous value */
54 init_val = ath5k_hw_reg_read(ah, cur_reg);
55
56 for (i = 0; i < 256; i++) {
57 var_pattern = i << 16 | i;
58 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
59 cur_val = ath5k_hw_reg_read(ah, cur_reg);
60
61 if (cur_val != var_pattern) {
62 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
63 return -EAGAIN;
64 }
65
66 /* Found on ndiswrapper dumps */
67 var_pattern = 0x0039080f;
68 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
69 }
70
71 for (i = 0; i < 4; i++) {
72 var_pattern = static_pattern[i];
73 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
74 cur_val = ath5k_hw_reg_read(ah, cur_reg);
75
76 if (cur_val != var_pattern) {
77 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
78 return -EAGAIN;
79 }
80
81 /* Found on ndiswrapper dumps */
82 var_pattern = 0x003b080f;
83 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
84 }
85
86 /* Restore previous value */
87 ath5k_hw_reg_write(ah, init_val, cur_reg);
88
89 }
90
91 return 0;
92
93 }
94
95 /**
96 * ath5k_hw_init - Check if hw is supported and init the needed structs
97 *
98 * @sc: The &struct ath5k_softc we got from the driver's init_softc function
99 *
100 * Check if the device is supported, perform a POST and initialize the needed
101 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
102 * -ENODEV if the device is not supported or prints an error msg if something
103 * else went wrong.
104 */
ath5k_hw_init(struct ath5k_softc * sc)105 int ath5k_hw_init(struct ath5k_softc *sc)
106 {
107 struct ath5k_hw *ah = sc->ah;
108 struct ath_common *common = ath5k_hw_common(ah);
109 struct pci_dev *pdev = sc->pdev;
110 struct ath5k_eeprom_info *ee;
111 int ret;
112 u32 srev;
113
114 /*
115 * HW information
116 */
117 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
118 ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
120 ah->ah_imr = 0;
121 ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
122 ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
123 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
124 ah->ah_noise_floor = -95; /* until first NF calibration is run */
125 sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
126 ah->ah_current_channel = &sc->channels[0];
127
128 /*
129 * Find the mac version
130 */
131 ath5k_hw_read_srev(ah);
132 srev = ah->ah_mac_srev;
133 if (srev < AR5K_SREV_AR5311)
134 ah->ah_version = AR5K_AR5210;
135 else if (srev < AR5K_SREV_AR5212)
136 ah->ah_version = AR5K_AR5211;
137 else
138 ah->ah_version = AR5K_AR5212;
139
140 /* Get the MAC revision */
141 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
142 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
143
144 /* Fill the ath5k_hw struct with the needed functions */
145 ret = ath5k_hw_init_desc_functions(ah);
146 if (ret)
147 goto err;
148
149 /* Bring device out of sleep and reset its units */
150 ret = ath5k_hw_nic_wakeup(ah, 0, true);
151 if (ret)
152 goto err;
153
154 /* Get PHY and RADIO revisions */
155 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
156 0xffffffff;
157 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
158 CHANNEL_5GHZ);
159 ah->ah_phy = AR5K_PHY(0);
160
161 /* Try to identify radio chip based on its srev */
162 switch (ah->ah_radio_5ghz_revision & 0xf0) {
163 case AR5K_SREV_RAD_5111:
164 ah->ah_radio = AR5K_RF5111;
165 ah->ah_single_chip = false;
166 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
167 CHANNEL_2GHZ);
168 break;
169 case AR5K_SREV_RAD_5112:
170 case AR5K_SREV_RAD_2112:
171 ah->ah_radio = AR5K_RF5112;
172 ah->ah_single_chip = false;
173 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
174 CHANNEL_2GHZ);
175 break;
176 case AR5K_SREV_RAD_2413:
177 ah->ah_radio = AR5K_RF2413;
178 ah->ah_single_chip = true;
179 break;
180 case AR5K_SREV_RAD_5413:
181 ah->ah_radio = AR5K_RF5413;
182 ah->ah_single_chip = true;
183 break;
184 case AR5K_SREV_RAD_2316:
185 ah->ah_radio = AR5K_RF2316;
186 ah->ah_single_chip = true;
187 break;
188 case AR5K_SREV_RAD_2317:
189 ah->ah_radio = AR5K_RF2317;
190 ah->ah_single_chip = true;
191 break;
192 case AR5K_SREV_RAD_5424:
193 if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
194 ah->ah_mac_version == AR5K_SREV_AR2417){
195 ah->ah_radio = AR5K_RF2425;
196 ah->ah_single_chip = true;
197 } else {
198 ah->ah_radio = AR5K_RF5413;
199 ah->ah_single_chip = true;
200 }
201 break;
202 default:
203 /* Identify radio based on mac/phy srev */
204 if (ah->ah_version == AR5K_AR5210) {
205 ah->ah_radio = AR5K_RF5110;
206 ah->ah_single_chip = false;
207 } else if (ah->ah_version == AR5K_AR5211) {
208 ah->ah_radio = AR5K_RF5111;
209 ah->ah_single_chip = false;
210 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
211 CHANNEL_2GHZ);
212 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
213 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
214 ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
215 ah->ah_radio = AR5K_RF2425;
216 ah->ah_single_chip = true;
217 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
218 } else if (srev == AR5K_SREV_AR5213A &&
219 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
220 ah->ah_radio = AR5K_RF5112;
221 ah->ah_single_chip = false;
222 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
223 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
224 ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
225 ah->ah_radio = AR5K_RF2316;
226 ah->ah_single_chip = true;
227 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
228 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
229 ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
230 ah->ah_radio = AR5K_RF5413;
231 ah->ah_single_chip = true;
232 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
233 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
234 ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
235 ah->ah_radio = AR5K_RF2413;
236 ah->ah_single_chip = true;
237 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
238 } else {
239 ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
240 ret = -ENODEV;
241 goto err;
242 }
243 }
244
245
246 /* Return on unsuported chips (unsupported eeprom etc) */
247 if ((srev >= AR5K_SREV_AR5416) &&
248 (srev < AR5K_SREV_AR2425)) {
249 ATH5K_ERR(sc, "Device not yet supported.\n");
250 ret = -ENODEV;
251 goto err;
252 }
253
254 /*
255 * POST
256 */
257 ret = ath5k_hw_post(ah);
258 if (ret)
259 goto err;
260
261 /* Enable pci core retry fix on Hainan (5213A) and later chips */
262 if (srev >= AR5K_SREV_AR5213A)
263 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
264
265 /*
266 * Get card capabilities, calibration values etc
267 * TODO: EEPROM work
268 */
269 ret = ath5k_eeprom_init(ah);
270 if (ret) {
271 ATH5K_ERR(sc, "unable to init EEPROM\n");
272 goto err;
273 }
274
275 ee = &ah->ah_capabilities.cap_eeprom;
276
277 /*
278 * Write PCI-E power save settings
279 */
280 if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
281 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
282 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
283
284 /* Shut off RX when elecidle is asserted */
285 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
286 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
287
288 /* If serdes programing is enabled, increase PCI-E
289 * tx power for systems with long trace from host
290 * to minicard connector. */
291 if (ee->ee_serdes)
292 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
293 else
294 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
295
296 /* Shut off PLL and CLKREQ active in L1 */
297 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
298
299 /* Preserve other settings */
300 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
301 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
302 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
303
304 /* Reset SERDES to load new settings */
305 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
306 mdelay(1);
307 }
308
309 /* Get misc capabilities */
310 ret = ath5k_hw_set_capabilities(ah);
311 if (ret) {
312 ATH5K_ERR(sc, "unable to get device capabilities\n");
313 goto err;
314 }
315
316 /* Crypto settings */
317 common->keymax = (sc->ah->ah_version == AR5K_AR5210 ?
318 AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
319
320 if (srev >= AR5K_SREV_AR5212_V4 &&
321 (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
322 !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
323 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
324
325 if (srev >= AR5K_SREV_AR2414) {
326 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
327 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
328 AR5K_MISC_MODE_COMBINED_MIC);
329 }
330
331 /* MAC address is cleared until add_interface */
332 ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
333
334 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
335 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
336 ath5k_hw_set_bssid(ah);
337 ath5k_hw_set_opmode(ah, sc->opmode);
338
339 ath5k_hw_rfgain_opt_init(ah);
340
341 ath5k_hw_init_nfcal_hist(ah);
342
343 /* turn on HW LEDs */
344 ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
345
346 return 0;
347 err:
348 return ret;
349 }
350
351 /**
352 * ath5k_hw_deinit - Free the ath5k_hw struct
353 *
354 * @ah: The &struct ath5k_hw
355 */
ath5k_hw_deinit(struct ath5k_hw * ah)356 void ath5k_hw_deinit(struct ath5k_hw *ah)
357 {
358 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
359
360 if (ah->ah_rf_banks != NULL)
361 kfree(ah->ah_rf_banks);
362
363 ath5k_eeprom_detach(ah);
364
365 /* assume interrupts are down */
366 }
367