1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #include "debug.h"
7 #include "hal.h"
8 #include "hal_tx.h"
9 #include "hal_rx.h"
10 #include "hal_desc.h"
11 #include "hif.h"
12
ath11k_hal_reo_set_desc_hdr(struct hal_desc_header * hdr,u8 owner,u8 buffer_type,u32 magic)13 static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr,
14 u8 owner, u8 buffer_type, u32 magic)
15 {
16 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) |
17 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type);
18
19 /* Magic pattern in reserved bits for debugging */
20 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic);
21 }
22
ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)23 static int ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr *tlv,
24 struct ath11k_hal_reo_cmd *cmd)
25 {
26 struct hal_reo_get_queue_stats *desc;
27
28 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) |
29 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
30
31 desc = (struct hal_reo_get_queue_stats *)tlv->value;
32 memset_startat(desc, 0, queue_addr_lo);
33
34 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
35 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
36 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
37
38 desc->queue_addr_lo = cmd->addr_lo;
39 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI,
40 cmd->addr_hi);
41 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR)
42 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS;
43
44 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
45 }
46
ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal * hal,struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)47 static int ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal *hal, struct hal_tlv_hdr *tlv,
48 struct ath11k_hal_reo_cmd *cmd)
49 {
50 struct hal_reo_flush_cache *desc;
51 u8 avail_slot = ffz(hal->avail_blk_resource);
52
53 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
54 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES)
55 return -ENOSPC;
56
57 hal->current_blk_index = avail_slot;
58 }
59
60 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) |
61 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
62
63 desc = (struct hal_reo_flush_cache *)tlv->value;
64 memset_startat(desc, 0, cache_addr_lo);
65
66 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
67 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
68 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
69
70 desc->cache_addr_lo = cmd->addr_lo;
71 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI,
72 cmd->addr_hi);
73
74 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS)
75 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS;
76
77 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
78 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE;
79 desc->info0 |=
80 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX,
81 avail_slot);
82 }
83
84 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL)
85 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE;
86
87 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL)
88 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL;
89
90 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
91 }
92
ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)93 static int ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr *tlv,
94 struct ath11k_hal_reo_cmd *cmd)
95 {
96 struct hal_reo_update_rx_queue *desc;
97
98 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_UPDATE_RX_REO_QUEUE) |
99 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
100
101 desc = (struct hal_reo_update_rx_queue *)tlv->value;
102 memset_startat(desc, 0, queue_addr_lo);
103
104 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
105 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
106 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
107
108 desc->queue_addr_lo = cmd->addr_lo;
109 desc->info0 =
110 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI,
111 cmd->addr_hi) |
112 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM,
113 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM)) |
114 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD,
115 !!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD)) |
116 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT,
117 !!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC)) |
118 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION,
119 !!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION)) |
120 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN,
121 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN)) |
122 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC,
123 !!(cmd->upd0 & HAL_REO_CMD_UPD0_AC)) |
124 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR,
125 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR)) |
126 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY,
127 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY)) |
128 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE,
129 !!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE)) |
130 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE,
131 !!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE)) |
132 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE,
133 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE)) |
134 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK,
135 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK)) |
136 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN,
137 !!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN)) |
138 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN,
139 !!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN)) |
140 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE,
141 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE)) |
142 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE,
143 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE)) |
144 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG,
145 !!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG)) |
146 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD,
147 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD)) |
148 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN,
149 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN)) |
150 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR,
151 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR)) |
152 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID,
153 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID)) |
154 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN,
155 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN));
156
157 desc->info1 =
158 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER,
159 cmd->rx_queue_num) |
160 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD,
161 !!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD)) |
162 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER,
163 FIELD_GET(HAL_REO_CMD_UPD1_ALDC, cmd->upd1)) |
164 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION,
165 !!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION)) |
166 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN,
167 !!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN)) |
168 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC,
169 FIELD_GET(HAL_REO_CMD_UPD1_AC, cmd->upd1)) |
170 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR,
171 !!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR)) |
172 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE,
173 !!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE)) |
174 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY,
175 !!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY)) |
176 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE,
177 !!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE)) |
178 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK,
179 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK)) |
180 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN,
181 !!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN)) |
182 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN,
183 !!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN)) |
184 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE,
185 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE)) |
186 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG,
187 !!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG));
188
189 if (cmd->pn_size == 24)
190 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24;
191 else if (cmd->pn_size == 48)
192 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48;
193 else if (cmd->pn_size == 128)
194 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128;
195
196 if (cmd->ba_window_size < 1)
197 cmd->ba_window_size = 1;
198
199 if (cmd->ba_window_size == 1)
200 cmd->ba_window_size++;
201
202 desc->info2 =
203 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE,
204 cmd->ba_window_size - 1) |
205 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE, cmd->pn_size) |
206 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD,
207 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD)) |
208 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SSN,
209 FIELD_GET(HAL_REO_CMD_UPD2_SSN, cmd->upd2)) |
210 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR,
211 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR)) |
212 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR,
213 !!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR));
214
215 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
216 }
217
ath11k_hal_reo_cmd_send(struct ath11k_base * ab,struct hal_srng * srng,enum hal_reo_cmd_type type,struct ath11k_hal_reo_cmd * cmd)218 int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng,
219 enum hal_reo_cmd_type type,
220 struct ath11k_hal_reo_cmd *cmd)
221 {
222 struct hal_tlv_hdr *reo_desc;
223 int ret;
224
225 spin_lock_bh(&srng->lock);
226
227 ath11k_hal_srng_access_begin(ab, srng);
228 reo_desc = (struct hal_tlv_hdr *)ath11k_hal_srng_src_get_next_entry(ab, srng);
229 if (!reo_desc) {
230 ret = -ENOBUFS;
231 goto out;
232 }
233
234 switch (type) {
235 case HAL_REO_CMD_GET_QUEUE_STATS:
236 ret = ath11k_hal_reo_cmd_queue_stats(reo_desc, cmd);
237 break;
238 case HAL_REO_CMD_FLUSH_CACHE:
239 ret = ath11k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd);
240 break;
241 case HAL_REO_CMD_UPDATE_RX_QUEUE:
242 ret = ath11k_hal_reo_cmd_update_rx_queue(reo_desc, cmd);
243 break;
244 case HAL_REO_CMD_FLUSH_QUEUE:
245 case HAL_REO_CMD_UNBLOCK_CACHE:
246 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST:
247 ath11k_warn(ab, "Unsupported reo command %d\n", type);
248 ret = -ENOTSUPP;
249 break;
250 default:
251 ath11k_warn(ab, "Unknown reo command %d\n", type);
252 ret = -EINVAL;
253 break;
254 }
255
256 ath11k_dp_shadow_start_timer(ab, srng, &ab->dp.reo_cmd_timer);
257
258 out:
259 ath11k_hal_srng_access_end(ab, srng);
260 spin_unlock_bh(&srng->lock);
261
262 return ret;
263 }
264
ath11k_hal_rx_buf_addr_info_set(void * desc,dma_addr_t paddr,u32 cookie,u8 manager)265 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
266 u32 cookie, u8 manager)
267 {
268 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
269 u32 paddr_lo, paddr_hi;
270
271 paddr_lo = lower_32_bits(paddr);
272 paddr_hi = upper_32_bits(paddr);
273 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo);
274 binfo->info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, paddr_hi) |
275 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie) |
276 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, manager);
277 }
278
ath11k_hal_rx_buf_addr_info_get(void * desc,dma_addr_t * paddr,u32 * cookie,u8 * rbm)279 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
280 u32 *cookie, u8 *rbm)
281 {
282 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
283
284 *paddr =
285 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, binfo->info1)) << 32) |
286 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0);
287 *cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, binfo->info1);
288 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, binfo->info1);
289 }
290
ath11k_hal_rx_msdu_link_info_get(void * link_desc,u32 * num_msdus,u32 * msdu_cookies,enum hal_rx_buf_return_buf_manager * rbm)291 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
292 u32 *msdu_cookies,
293 enum hal_rx_buf_return_buf_manager *rbm)
294 {
295 struct hal_rx_msdu_link *link = (struct hal_rx_msdu_link *)link_desc;
296 struct hal_rx_msdu_details *msdu;
297 int i;
298
299 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC;
300
301 msdu = &link->msdu_link[0];
302 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
303 msdu->buf_addr_info.info1);
304
305 for (i = 0; i < *num_msdus; i++) {
306 msdu = &link->msdu_link[i];
307
308 if (!FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
309 msdu->buf_addr_info.info0)) {
310 *num_msdus = i;
311 break;
312 }
313 *msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
314 msdu->buf_addr_info.info1);
315 msdu_cookies++;
316 }
317 }
318
ath11k_hal_desc_reo_parse_err(struct ath11k_base * ab,u32 * rx_desc,dma_addr_t * paddr,u32 * desc_bank)319 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
320 dma_addr_t *paddr, u32 *desc_bank)
321 {
322 struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc;
323 enum hal_reo_dest_ring_push_reason push_reason;
324 enum hal_reo_dest_ring_error_code err_code;
325
326 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
327 desc->info0);
328 err_code = FIELD_GET(HAL_REO_DEST_RING_INFO0_ERROR_CODE,
329 desc->info0);
330 ab->soc_stats.reo_error[err_code]++;
331
332 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED &&
333 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
334 ath11k_warn(ab, "expected error push reason code, received %d\n",
335 push_reason);
336 return -EINVAL;
337 }
338
339 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) !=
340 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) {
341 ath11k_warn(ab, "expected buffer type link_desc");
342 return -EINVAL;
343 }
344
345 ath11k_hal_rx_reo_ent_paddr_get(ab, rx_desc, paddr, desc_bank);
346
347 return 0;
348 }
349
ath11k_hal_wbm_desc_parse_err(struct ath11k_base * ab,void * desc,struct hal_rx_wbm_rel_info * rel_info)350 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
351 struct hal_rx_wbm_rel_info *rel_info)
352 {
353 struct hal_wbm_release_ring *wbm_desc = desc;
354 enum hal_wbm_rel_desc_type type;
355 enum hal_wbm_rel_src_module rel_src;
356 enum hal_rx_buf_return_buf_manager ret_buf_mgr;
357
358 type = FIELD_GET(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
359 wbm_desc->info0);
360 /* We expect only WBM_REL buffer type */
361 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) {
362 WARN_ON(1);
363 return -EINVAL;
364 }
365
366 rel_src = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
367 wbm_desc->info0);
368 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA &&
369 rel_src != HAL_WBM_REL_SRC_MODULE_REO)
370 return -EINVAL;
371
372 ret_buf_mgr = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
373 wbm_desc->buf_addr_info.info1);
374 if (ret_buf_mgr != HAL_RX_BUF_RBM_SW3_BM) {
375 ab->soc_stats.invalid_rbm++;
376 return -EINVAL;
377 }
378
379 rel_info->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
380 wbm_desc->buf_addr_info.info1);
381 rel_info->err_rel_src = rel_src;
382 if (rel_src == HAL_WBM_REL_SRC_MODULE_REO) {
383 rel_info->push_reason =
384 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON,
385 wbm_desc->info0);
386 rel_info->err_code =
387 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE,
388 wbm_desc->info0);
389 } else {
390 rel_info->push_reason =
391 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON,
392 wbm_desc->info0);
393 rel_info->err_code =
394 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE,
395 wbm_desc->info0);
396 }
397
398 rel_info->first_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_FIRST_MSDU,
399 wbm_desc->info2);
400 rel_info->last_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_LAST_MSDU,
401 wbm_desc->info2);
402 return 0;
403 }
404
ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base * ab,void * desc,dma_addr_t * paddr,u32 * desc_bank)405 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
406 dma_addr_t *paddr, u32 *desc_bank)
407 {
408 struct ath11k_buffer_addr *buff_addr = desc;
409
410 *paddr = ((u64)(FIELD_GET(BUFFER_ADDR_INFO1_ADDR, buff_addr->info1)) << 32) |
411 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0);
412
413 *desc_bank = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, buff_addr->info1);
414 }
415
ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base * ab,void * desc,void * link_desc,enum hal_wbm_rel_bm_act action)416 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
417 void *link_desc,
418 enum hal_wbm_rel_bm_act action)
419 {
420 struct hal_wbm_release_ring *dst_desc = desc;
421 struct hal_wbm_release_ring *src_desc = link_desc;
422
423 dst_desc->buf_addr_info = src_desc->buf_addr_info;
424 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
425 HAL_WBM_REL_SRC_MODULE_SW) |
426 FIELD_PREP(HAL_WBM_RELEASE_INFO0_BM_ACTION, action) |
427 FIELD_PREP(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
428 HAL_WBM_REL_DESC_TYPE_MSDU_LINK);
429 }
430
ath11k_hal_reo_status_queue_stats(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)431 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
432 struct hal_reo_status *status)
433 {
434 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
435 struct hal_reo_get_queue_stats_status *desc =
436 (struct hal_reo_get_queue_stats_status *)tlv->value;
437
438 status->uniform_hdr.cmd_num =
439 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
440 desc->hdr.info0);
441 status->uniform_hdr.cmd_status =
442 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
443 desc->hdr.info0);
444
445 ath11k_dbg(ab, ATH11k_DBG_HAL, "Queue stats status:\n");
446 ath11k_dbg(ab, ATH11k_DBG_HAL, "header: cmd_num %d status %d\n",
447 status->uniform_hdr.cmd_num,
448 status->uniform_hdr.cmd_status);
449 ath11k_dbg(ab, ATH11k_DBG_HAL, "ssn %ld cur_idx %ld\n",
450 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN,
451 desc->info0),
452 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX,
453 desc->info0));
454 ath11k_dbg(ab, ATH11k_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
455 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]);
456 ath11k_dbg(ab, ATH11k_DBG_HAL,
457 "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n",
458 desc->last_rx_enqueue_timestamp,
459 desc->last_rx_dequeue_timestamp);
460 ath11k_dbg(ab, ATH11k_DBG_HAL,
461 "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n",
462 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2],
463 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5],
464 desc->rx_bitmap[6], desc->rx_bitmap[7]);
465 ath11k_dbg(ab, ATH11k_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n",
466 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT,
467 desc->info1),
468 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT,
469 desc->info1));
470 ath11k_dbg(ab, ATH11k_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n",
471 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT,
472 desc->info2),
473 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT,
474 desc->info2),
475 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT,
476 desc->info2));
477 ath11k_dbg(ab, ATH11k_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n",
478 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT,
479 desc->info3),
480 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT,
481 desc->info3));
482 ath11k_dbg(ab, ATH11k_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
483 desc->num_mpdu_frames, desc->num_msdu_frames,
484 desc->total_bytes);
485 ath11k_dbg(ab, ATH11k_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n",
486 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU,
487 desc->info4),
488 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K,
489 desc->info4),
490 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT,
491 desc->info4));
492 ath11k_dbg(ab, ATH11k_DBG_HAL, "looping count %ld\n",
493 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT,
494 desc->info5));
495 }
496
ath11k_hal_reo_process_status(u8 * reo_desc,u8 * status)497 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status)
498 {
499 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
500 struct hal_reo_status_hdr *hdr;
501
502 hdr = (struct hal_reo_status_hdr *)tlv->value;
503 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0);
504
505 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0);
506 }
507
ath11k_hal_reo_flush_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)508 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
509 struct hal_reo_status *status)
510 {
511 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
512 struct hal_reo_flush_queue_status *desc =
513 (struct hal_reo_flush_queue_status *)tlv->value;
514
515 status->uniform_hdr.cmd_num =
516 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
517 desc->hdr.info0);
518 status->uniform_hdr.cmd_status =
519 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
520 desc->hdr.info0);
521 status->u.flush_queue.err_detected =
522 FIELD_GET(HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED,
523 desc->info0);
524 }
525
ath11k_hal_reo_flush_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)526 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
527 struct hal_reo_status *status)
528 {
529 struct ath11k_hal *hal = &ab->hal;
530 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
531 struct hal_reo_flush_cache_status *desc =
532 (struct hal_reo_flush_cache_status *)tlv->value;
533
534 status->uniform_hdr.cmd_num =
535 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
536 desc->hdr.info0);
537 status->uniform_hdr.cmd_status =
538 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
539 desc->hdr.info0);
540
541 status->u.flush_cache.err_detected =
542 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR,
543 desc->info0);
544 status->u.flush_cache.err_code =
545 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE,
546 desc->info0);
547 if (!status->u.flush_cache.err_code)
548 hal->avail_blk_resource |= BIT(hal->current_blk_index);
549
550 status->u.flush_cache.cache_controller_flush_status_hit =
551 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT,
552 desc->info0);
553
554 status->u.flush_cache.cache_controller_flush_status_desc_type =
555 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE,
556 desc->info0);
557 status->u.flush_cache.cache_controller_flush_status_client_id =
558 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID,
559 desc->info0);
560 status->u.flush_cache.cache_controller_flush_status_err =
561 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR,
562 desc->info0);
563 status->u.flush_cache.cache_controller_flush_status_cnt =
564 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT,
565 desc->info0);
566 }
567
ath11k_hal_reo_unblk_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)568 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
569 struct hal_reo_status *status)
570 {
571 struct ath11k_hal *hal = &ab->hal;
572 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
573 struct hal_reo_unblock_cache_status *desc =
574 (struct hal_reo_unblock_cache_status *)tlv->value;
575
576 status->uniform_hdr.cmd_num =
577 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
578 desc->hdr.info0);
579 status->uniform_hdr.cmd_status =
580 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
581 desc->hdr.info0);
582
583 status->u.unblock_cache.err_detected =
584 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR,
585 desc->info0);
586 status->u.unblock_cache.unblock_type =
587 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE,
588 desc->info0);
589
590 if (!status->u.unblock_cache.err_detected &&
591 status->u.unblock_cache.unblock_type ==
592 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE)
593 hal->avail_blk_resource &= ~BIT(hal->current_blk_index);
594 }
595
ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)596 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
597 u32 *reo_desc,
598 struct hal_reo_status *status)
599 {
600 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
601 struct hal_reo_flush_timeout_list_status *desc =
602 (struct hal_reo_flush_timeout_list_status *)tlv->value;
603
604 status->uniform_hdr.cmd_num =
605 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
606 desc->hdr.info0);
607 status->uniform_hdr.cmd_status =
608 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
609 desc->hdr.info0);
610
611 status->u.timeout_list.err_detected =
612 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR,
613 desc->info0);
614 status->u.timeout_list.list_empty =
615 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY,
616 desc->info0);
617
618 status->u.timeout_list.release_desc_cnt =
619 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT,
620 desc->info1);
621 status->u.timeout_list.fwd_buf_cnt =
622 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT,
623 desc->info1);
624 }
625
ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)626 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
627 u32 *reo_desc,
628 struct hal_reo_status *status)
629 {
630 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
631 struct hal_reo_desc_thresh_reached_status *desc =
632 (struct hal_reo_desc_thresh_reached_status *)tlv->value;
633
634 status->uniform_hdr.cmd_num =
635 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
636 desc->hdr.info0);
637 status->uniform_hdr.cmd_status =
638 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
639 desc->hdr.info0);
640
641 status->u.desc_thresh_reached.threshold_idx =
642 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX,
643 desc->info0);
644
645 status->u.desc_thresh_reached.link_desc_counter0 =
646 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0,
647 desc->info1);
648
649 status->u.desc_thresh_reached.link_desc_counter1 =
650 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1,
651 desc->info2);
652
653 status->u.desc_thresh_reached.link_desc_counter2 =
654 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2,
655 desc->info3);
656
657 status->u.desc_thresh_reached.link_desc_counter_sum =
658 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM,
659 desc->info4);
660 }
661
ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)662 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
663 u32 *reo_desc,
664 struct hal_reo_status *status)
665 {
666 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
667 struct hal_reo_status_hdr *desc =
668 (struct hal_reo_status_hdr *)tlv->value;
669
670 status->uniform_hdr.cmd_num =
671 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
672 desc->info0);
673 status->uniform_hdr.cmd_status =
674 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
675 desc->info0);
676 }
677
ath11k_hal_reo_qdesc_size(u32 ba_window_size,u8 tid)678 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid)
679 {
680 u32 num_ext_desc;
681
682 if (ba_window_size <= 1) {
683 if (tid != HAL_DESC_REO_NON_QOS_TID)
684 num_ext_desc = 1;
685 else
686 num_ext_desc = 0;
687 } else if (ba_window_size <= 105) {
688 num_ext_desc = 1;
689 } else if (ba_window_size <= 210) {
690 num_ext_desc = 2;
691 } else {
692 num_ext_desc = 3;
693 }
694
695 return sizeof(struct hal_rx_reo_queue) +
696 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext));
697 }
698
ath11k_hal_reo_qdesc_setup(void * vaddr,int tid,u32 ba_window_size,u32 start_seq,enum hal_pn_type type)699 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
700 u32 start_seq, enum hal_pn_type type)
701 {
702 struct hal_rx_reo_queue *qdesc = (struct hal_rx_reo_queue *)vaddr;
703 struct hal_rx_reo_queue_ext *ext_desc;
704
705 memset(qdesc, 0, sizeof(*qdesc));
706
707 ath11k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED,
708 HAL_DESC_REO_QUEUE_DESC,
709 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0);
710
711 qdesc->rx_queue_num = FIELD_PREP(HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER, tid);
712
713 qdesc->info0 =
714 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_VLD, 1) |
715 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER, 1) |
716 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_AC, ath11k_tid_to_ac(tid));
717
718 if (ba_window_size < 1)
719 ba_window_size = 1;
720
721 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID)
722 ba_window_size++;
723
724 if (ba_window_size == 1)
725 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1);
726
727 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE,
728 ba_window_size - 1);
729 switch (type) {
730 case HAL_PN_TYPE_NONE:
731 case HAL_PN_TYPE_WAPI_EVEN:
732 case HAL_PN_TYPE_WAPI_UNEVEN:
733 break;
734 case HAL_PN_TYPE_WPA:
735 qdesc->info0 |=
736 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_CHECK, 1) |
737 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_SIZE,
738 HAL_RX_REO_QUEUE_PN_SIZE_48);
739 break;
740 }
741
742 /* TODO: Set Ignore ampdu flags based on BA window size and/or
743 * AMPDU capabilities
744 */
745 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1);
746
747 qdesc->info1 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SVLD, 0);
748
749 if (start_seq <= 0xfff)
750 qdesc->info1 = FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SSN,
751 start_seq);
752
753 if (tid == HAL_DESC_REO_NON_QOS_TID)
754 return;
755
756 ext_desc = qdesc->ext_desc;
757
758 /* TODO: HW queue descriptors are currently allocated for max BA
759 * window size for all QOS TIDs so that same descriptor can be used
760 * later when ADDBA request is recevied. This should be changed to
761 * allocate HW queue descriptors based on BA window size being
762 * negotiated (0 for non BA cases), and reallocate when BA window
763 * size changes and also send WMI message to FW to change the REO
764 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
765 */
766 memset(ext_desc, 0, sizeof(*ext_desc));
767 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
768 HAL_DESC_REO_QUEUE_EXT_DESC,
769 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1);
770 ext_desc++;
771 memset(ext_desc, 0, sizeof(*ext_desc));
772 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
773 HAL_DESC_REO_QUEUE_EXT_DESC,
774 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2);
775 ext_desc++;
776 memset(ext_desc, 0, sizeof(*ext_desc));
777 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
778 HAL_DESC_REO_QUEUE_EXT_DESC,
779 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3);
780 }
781
ath11k_hal_reo_init_cmd_ring(struct ath11k_base * ab,struct hal_srng * srng)782 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
783 struct hal_srng *srng)
784 {
785 struct hal_srng_params params;
786 struct hal_tlv_hdr *tlv;
787 struct hal_reo_get_queue_stats *desc;
788 int i, cmd_num = 1;
789 int entry_size;
790 u8 *entry;
791
792 memset(¶ms, 0, sizeof(params));
793
794 entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_REO_CMD);
795 ath11k_hal_srng_get_params(ab, srng, ¶ms);
796 entry = (u8 *)params.ring_base_vaddr;
797
798 for (i = 0; i < params.num_entries; i++) {
799 tlv = (struct hal_tlv_hdr *)entry;
800 desc = (struct hal_reo_get_queue_stats *)tlv->value;
801 desc->cmd.info0 =
802 FIELD_PREP(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, cmd_num++);
803 entry += entry_size;
804 }
805 }
806
807 #define HAL_MAX_UL_MU_USERS 37
808 static inline void
ath11k_hal_rx_handle_ofdma_info(void * rx_tlv,struct hal_rx_user_status * rx_user_status)809 ath11k_hal_rx_handle_ofdma_info(void *rx_tlv,
810 struct hal_rx_user_status *rx_user_status)
811 {
812 struct hal_rx_ppdu_end_user_stats *ppdu_end_user =
813 (struct hal_rx_ppdu_end_user_stats *)rx_tlv;
814
815 rx_user_status->ul_ofdma_user_v0_word0 = __le32_to_cpu(ppdu_end_user->info6);
816
817 rx_user_status->ul_ofdma_user_v0_word1 = __le32_to_cpu(ppdu_end_user->rsvd2[10]);
818 }
819
820 static inline void
ath11k_hal_rx_populate_byte_count(void * rx_tlv,void * ppduinfo,struct hal_rx_user_status * rx_user_status)821 ath11k_hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
822 struct hal_rx_user_status *rx_user_status)
823 {
824 struct hal_rx_ppdu_end_user_stats *ppdu_end_user =
825 (struct hal_rx_ppdu_end_user_stats *)rx_tlv;
826
827 rx_user_status->mpdu_ok_byte_count =
828 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_6_MPDU_OK_BYTE_COUNT,
829 __le32_to_cpu(ppdu_end_user->rsvd2[6]));
830 rx_user_status->mpdu_err_byte_count =
831 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_8_MPDU_ERR_BYTE_COUNT,
832 __le32_to_cpu(ppdu_end_user->rsvd2[8]));
833 }
834
835 static inline void
ath11k_hal_rx_populate_mu_user_info(void * rx_tlv,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * rx_user_status)836 ath11k_hal_rx_populate_mu_user_info(void *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info,
837 struct hal_rx_user_status *rx_user_status)
838 {
839 rx_user_status->ast_index = ppdu_info->ast_index;
840 rx_user_status->tid = ppdu_info->tid;
841 rx_user_status->tcp_msdu_count =
842 ppdu_info->tcp_msdu_count;
843 rx_user_status->udp_msdu_count =
844 ppdu_info->udp_msdu_count;
845 rx_user_status->other_msdu_count =
846 ppdu_info->other_msdu_count;
847 rx_user_status->frame_control = ppdu_info->frame_control;
848 rx_user_status->frame_control_info_valid =
849 ppdu_info->frame_control_info_valid;
850 rx_user_status->data_sequence_control_info_valid =
851 ppdu_info->data_sequence_control_info_valid;
852 rx_user_status->first_data_seq_ctrl =
853 ppdu_info->first_data_seq_ctrl;
854 rx_user_status->preamble_type = ppdu_info->preamble_type;
855 rx_user_status->ht_flags = ppdu_info->ht_flags;
856 rx_user_status->vht_flags = ppdu_info->vht_flags;
857 rx_user_status->he_flags = ppdu_info->he_flags;
858 rx_user_status->rs_flags = ppdu_info->rs_flags;
859
860 rx_user_status->mpdu_cnt_fcs_ok =
861 ppdu_info->num_mpdu_fcs_ok;
862 rx_user_status->mpdu_cnt_fcs_err =
863 ppdu_info->num_mpdu_fcs_err;
864
865 ath11k_hal_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
866 }
867
868 static enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,u32 tlv_tag,u8 * tlv_data,u32 userid)869 ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
870 struct hal_rx_mon_ppdu_info *ppdu_info,
871 u32 tlv_tag, u8 *tlv_data, u32 userid)
872 {
873 u32 info0, info1, value;
874 u8 he_dcm = 0, he_stbc = 0;
875 u16 he_gi = 0, he_ltf = 0;
876
877 switch (tlv_tag) {
878 case HAL_RX_PPDU_START: {
879 struct hal_rx_ppdu_start *ppdu_start =
880 (struct hal_rx_ppdu_start *)tlv_data;
881
882 ppdu_info->ppdu_id =
883 FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
884 __le32_to_cpu(ppdu_start->info0));
885 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num);
886 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts);
887 break;
888 }
889 case HAL_RX_PPDU_END_USER_STATS: {
890 struct hal_rx_ppdu_end_user_stats *eu_stats =
891 (struct hal_rx_ppdu_end_user_stats *)tlv_data;
892
893 info0 = __le32_to_cpu(eu_stats->info0);
894 info1 = __le32_to_cpu(eu_stats->info1);
895
896 ppdu_info->ast_index =
897 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX,
898 __le32_to_cpu(eu_stats->info2));
899 ppdu_info->tid =
900 ffs(FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP,
901 __le32_to_cpu(eu_stats->info6))) - 1;
902 ppdu_info->tcp_msdu_count =
903 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT,
904 __le32_to_cpu(eu_stats->info4));
905 ppdu_info->udp_msdu_count =
906 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT,
907 __le32_to_cpu(eu_stats->info4));
908 ppdu_info->other_msdu_count =
909 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT,
910 __le32_to_cpu(eu_stats->info5));
911 ppdu_info->tcp_ack_msdu_count =
912 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT,
913 __le32_to_cpu(eu_stats->info5));
914 ppdu_info->preamble_type =
915 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE, info1);
916 ppdu_info->num_mpdu_fcs_ok =
917 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK,
918 info1);
919 ppdu_info->num_mpdu_fcs_err =
920 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR,
921 info0);
922 switch (ppdu_info->preamble_type) {
923 case HAL_RX_PREAMBLE_11N:
924 ppdu_info->ht_flags = 1;
925 break;
926 case HAL_RX_PREAMBLE_11AC:
927 ppdu_info->vht_flags = 1;
928 break;
929 case HAL_RX_PREAMBLE_11AX:
930 ppdu_info->he_flags = 1;
931 break;
932 default:
933 break;
934 }
935
936 if (userid < HAL_MAX_UL_MU_USERS) {
937 struct hal_rx_user_status *rxuser_stats =
938 &ppdu_info->userstats;
939
940 ath11k_hal_rx_handle_ofdma_info(tlv_data, rxuser_stats);
941 ath11k_hal_rx_populate_mu_user_info(tlv_data, ppdu_info,
942 rxuser_stats);
943 }
944 ppdu_info->userstats.mpdu_fcs_ok_bitmap[0] =
945 __le32_to_cpu(eu_stats->rsvd1[0]);
946 ppdu_info->userstats.mpdu_fcs_ok_bitmap[1] =
947 __le32_to_cpu(eu_stats->rsvd1[1]);
948
949 break;
950 }
951 case HAL_RX_PPDU_END_USER_STATS_EXT: {
952 struct hal_rx_ppdu_end_user_stats_ext *eu_stats =
953 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data;
954 ppdu_info->userstats.mpdu_fcs_ok_bitmap[2] = eu_stats->info1;
955 ppdu_info->userstats.mpdu_fcs_ok_bitmap[3] = eu_stats->info2;
956 ppdu_info->userstats.mpdu_fcs_ok_bitmap[4] = eu_stats->info3;
957 ppdu_info->userstats.mpdu_fcs_ok_bitmap[5] = eu_stats->info4;
958 ppdu_info->userstats.mpdu_fcs_ok_bitmap[6] = eu_stats->info5;
959 ppdu_info->userstats.mpdu_fcs_ok_bitmap[7] = eu_stats->info6;
960 break;
961 }
962 case HAL_PHYRX_HT_SIG: {
963 struct hal_rx_ht_sig_info *ht_sig =
964 (struct hal_rx_ht_sig_info *)tlv_data;
965
966 info0 = __le32_to_cpu(ht_sig->info0);
967 info1 = __le32_to_cpu(ht_sig->info1);
968
969 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0);
970 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0);
971 ppdu_info->is_stbc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_STBC,
972 info1);
973 ppdu_info->ldpc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING, info1);
974 ppdu_info->gi = info1 & HAL_RX_HT_SIG_INFO_INFO1_GI;
975
976 switch (ppdu_info->mcs) {
977 case 0 ... 7:
978 ppdu_info->nss = 1;
979 break;
980 case 8 ... 15:
981 ppdu_info->nss = 2;
982 break;
983 case 16 ... 23:
984 ppdu_info->nss = 3;
985 break;
986 case 24 ... 31:
987 ppdu_info->nss = 4;
988 break;
989 }
990
991 if (ppdu_info->nss > 1)
992 ppdu_info->mcs = ppdu_info->mcs % 8;
993
994 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
995 break;
996 }
997 case HAL_PHYRX_L_SIG_B: {
998 struct hal_rx_lsig_b_info *lsigb =
999 (struct hal_rx_lsig_b_info *)tlv_data;
1000
1001 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_B_INFO_INFO0_RATE,
1002 __le32_to_cpu(lsigb->info0));
1003 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1004 break;
1005 }
1006 case HAL_PHYRX_L_SIG_A: {
1007 struct hal_rx_lsig_a_info *lsiga =
1008 (struct hal_rx_lsig_a_info *)tlv_data;
1009
1010 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_A_INFO_INFO0_RATE,
1011 __le32_to_cpu(lsiga->info0));
1012 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1013 break;
1014 }
1015 case HAL_PHYRX_VHT_SIG_A: {
1016 struct hal_rx_vht_sig_a_info *vht_sig =
1017 (struct hal_rx_vht_sig_a_info *)tlv_data;
1018 u32 nsts;
1019 u32 group_id;
1020 u8 gi_setting;
1021
1022 info0 = __le32_to_cpu(vht_sig->info0);
1023 info1 = __le32_to_cpu(vht_sig->info1);
1024
1025 ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING,
1026 info0);
1027 ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS,
1028 info1);
1029 gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING,
1030 info1);
1031 switch (gi_setting) {
1032 case HAL_RX_VHT_SIG_A_NORMAL_GI:
1033 ppdu_info->gi = HAL_RX_GI_0_8_US;
1034 break;
1035 case HAL_RX_VHT_SIG_A_SHORT_GI:
1036 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
1037 ppdu_info->gi = HAL_RX_GI_0_4_US;
1038 break;
1039 }
1040
1041 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC;
1042 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0);
1043 if (ppdu_info->is_stbc && nsts > 0)
1044 nsts = ((nsts + 1) >> 1) - 1;
1045
1046 ppdu_info->nss = (nsts & VHT_SIG_SU_NSS_MASK) + 1;
1047 ppdu_info->bw = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_BW,
1048 info0);
1049 ppdu_info->beamformed = info1 &
1050 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED;
1051 group_id = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID,
1052 info0);
1053 if (group_id == 0 || group_id == 63)
1054 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1055 else
1056 ppdu_info->reception_type =
1057 HAL_RX_RECEPTION_TYPE_MU_MIMO;
1058 ppdu_info->vht_flag_values5 = group_id;
1059 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
1060 ppdu_info->nss);
1061 ppdu_info->vht_flag_values2 = ppdu_info->bw;
1062 ppdu_info->vht_flag_values4 =
1063 FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, info1);
1064 break;
1065 }
1066 case HAL_PHYRX_HE_SIG_A_SU: {
1067 struct hal_rx_he_sig_a_su_info *he_sig_a =
1068 (struct hal_rx_he_sig_a_su_info *)tlv_data;
1069
1070 ppdu_info->he_flags = 1;
1071 info0 = __le32_to_cpu(he_sig_a->info0);
1072 info1 = __le32_to_cpu(he_sig_a->info1);
1073
1074 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND, info0);
1075
1076 if (value == 0)
1077 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG;
1078 else
1079 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU;
1080
1081 ppdu_info->he_data1 |=
1082 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
1083 IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN |
1084 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
1085 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1086 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN |
1087 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
1088 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
1089 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
1090 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN |
1091 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN;
1092
1093 ppdu_info->he_data2 |=
1094 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN |
1095 IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN |
1096 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN |
1097 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
1098 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN |
1099 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
1100 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN;
1101
1102 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR, info0);
1103 ppdu_info->he_data3 =
1104 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value);
1105 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE, info0);
1106 ppdu_info->he_data3 |=
1107 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE, value);
1108 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG, info0);
1109 ppdu_info->he_data3 |=
1110 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value);
1111 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS, info0);
1112 ppdu_info->mcs = value;
1113 ppdu_info->he_data3 |=
1114 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, value);
1115
1116 he_dcm = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM, info0);
1117 ppdu_info->dcm = he_dcm;
1118 ppdu_info->he_data3 |=
1119 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, he_dcm);
1120 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING, info1);
1121 ppdu_info->ldpc = (value == HAL_RX_SU_MU_CODING_LDPC) ? 1 : 0;
1122 ppdu_info->he_data3 |=
1123 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1124 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA, info1);
1125 ppdu_info->he_data3 |=
1126 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value);
1127 he_stbc = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC, info1);
1128 ppdu_info->is_stbc = he_stbc;
1129 ppdu_info->he_data3 |=
1130 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, he_stbc);
1131
1132 /* data4 */
1133 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE, info0);
1134 ppdu_info->he_data4 =
1135 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value);
1136
1137 /* data5 */
1138 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW, info0);
1139 ppdu_info->bw = value;
1140 ppdu_info->he_data5 =
1141 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value);
1142 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE, info0);
1143 switch (value) {
1144 case 0:
1145 he_gi = HE_GI_0_8;
1146 he_ltf = HE_LTF_1_X;
1147 break;
1148 case 1:
1149 he_gi = HE_GI_0_8;
1150 he_ltf = HE_LTF_2_X;
1151 break;
1152 case 2:
1153 he_gi = HE_GI_1_6;
1154 he_ltf = HE_LTF_2_X;
1155 break;
1156 case 3:
1157 if (he_dcm && he_stbc) {
1158 he_gi = HE_GI_0_8;
1159 he_ltf = HE_LTF_4_X;
1160 } else {
1161 he_gi = HE_GI_3_2;
1162 he_ltf = HE_LTF_4_X;
1163 }
1164 break;
1165 }
1166 ppdu_info->gi = he_gi;
1167 he_gi = (he_gi != 0) ? he_gi - 1 : 0;
1168 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi);
1169 ppdu_info->ltf_size = he_ltf;
1170 ppdu_info->he_data5 |=
1171 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE,
1172 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf);
1173
1174 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1175 ppdu_info->he_data5 |=
1176 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value);
1177
1178 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR, info1);
1179 ppdu_info->he_data5 |=
1180 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value);
1181
1182 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF, info1);
1183 ppdu_info->beamformed = value;
1184 ppdu_info->he_data5 |=
1185 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_TXBF, value);
1186 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM, info1);
1187 ppdu_info->he_data5 |=
1188 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value);
1189
1190 /* data6 */
1191 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1192 value++;
1193 ppdu_info->nss = value;
1194 ppdu_info->he_data6 =
1195 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_NSTS, value);
1196 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND, info1);
1197 ppdu_info->he_data6 |=
1198 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value);
1199 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION, info1);
1200 ppdu_info->he_data6 |=
1201 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value);
1202
1203 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1204 break;
1205 }
1206 case HAL_PHYRX_HE_SIG_A_MU_DL: {
1207 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl =
1208 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data;
1209
1210 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
1211 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
1212
1213 ppdu_info->he_mu_flags = 1;
1214
1215 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU;
1216 ppdu_info->he_data1 |=
1217 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
1218 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
1219 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
1220 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
1221 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN |
1222 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN;
1223
1224 ppdu_info->he_data2 =
1225 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN |
1226 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN |
1227 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
1228 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN |
1229 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
1230 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN;
1231
1232 /*data3*/
1233 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR, info0);
1234 ppdu_info->he_data3 =
1235 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value);
1236
1237 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG, info0);
1238 ppdu_info->he_data3 |=
1239 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value);
1240
1241 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA, info1);
1242 ppdu_info->he_data3 |=
1243 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value);
1244
1245 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC, info1);
1246 he_stbc = value;
1247 ppdu_info->he_data3 |=
1248 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, value);
1249
1250 /*data4*/
1251 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE, info0);
1252 ppdu_info->he_data4 =
1253 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value);
1254
1255 /*data5*/
1256 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1257 ppdu_info->bw = value;
1258 ppdu_info->he_data5 =
1259 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value);
1260
1261 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE, info0);
1262 switch (value) {
1263 case 0:
1264 he_gi = HE_GI_0_8;
1265 he_ltf = HE_LTF_4_X;
1266 break;
1267 case 1:
1268 he_gi = HE_GI_0_8;
1269 he_ltf = HE_LTF_2_X;
1270 break;
1271 case 2:
1272 he_gi = HE_GI_1_6;
1273 he_ltf = HE_LTF_2_X;
1274 break;
1275 case 3:
1276 he_gi = HE_GI_3_2;
1277 he_ltf = HE_LTF_4_X;
1278 break;
1279 }
1280 ppdu_info->gi = he_gi;
1281 he_gi = (he_gi != 0) ? he_gi - 1 : 0;
1282 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi);
1283 ppdu_info->ltf_size = he_ltf;
1284 ppdu_info->he_data5 |=
1285 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE,
1286 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf);
1287
1288 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB, info1);
1289 ppdu_info->he_data5 |=
1290 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value);
1291
1292 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR,
1293 info1);
1294 ppdu_info->he_data5 |=
1295 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value);
1296
1297 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM,
1298 info1);
1299 ppdu_info->he_data5 |=
1300 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value);
1301
1302 /*data6*/
1303 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION,
1304 info0);
1305 ppdu_info->he_data6 |=
1306 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value);
1307
1308 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION, info1);
1309 ppdu_info->he_data6 |=
1310 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value);
1311
1312 /* HE-MU Flags */
1313 /* HE-MU-flags1 */
1314 ppdu_info->he_flags1 =
1315 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN |
1316 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN |
1317 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN |
1318 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN |
1319 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN;
1320
1321 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB, info0);
1322 ppdu_info->he_flags1 |=
1323 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN,
1324 value);
1325 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB, info0);
1326 ppdu_info->he_flags1 |=
1327 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN,
1328 value);
1329
1330 /* HE-MU-flags2 */
1331 ppdu_info->he_flags2 =
1332 IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN;
1333
1334 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1335 ppdu_info->he_flags2 |=
1336 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW,
1337 value);
1338 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB, info0);
1339 ppdu_info->he_flags2 |=
1340 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP, value);
1341 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB, info0);
1342 value = value - 1;
1343 ppdu_info->he_flags2 |=
1344 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS,
1345 value);
1346
1347 ppdu_info->is_stbc = info1 &
1348 HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC;
1349 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1350 break;
1351 }
1352 case HAL_PHYRX_HE_SIG_B1_MU: {
1353 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu =
1354 (struct hal_rx_he_sig_b1_mu_info *)tlv_data;
1355 u16 ru_tones;
1356
1357 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
1358
1359 ru_tones = FIELD_GET(HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION,
1360 info0);
1361 ppdu_info->ru_alloc =
1362 ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(ru_tones);
1363 ppdu_info->he_RU[0] = ru_tones;
1364 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1365 break;
1366 }
1367 case HAL_PHYRX_HE_SIG_B2_MU: {
1368 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu =
1369 (struct hal_rx_he_sig_b2_mu_info *)tlv_data;
1370
1371 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
1372
1373 ppdu_info->he_data1 |= IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1374 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN;
1375
1376 ppdu_info->mcs =
1377 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS, info0);
1378 ppdu_info->he_data3 |=
1379 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs);
1380
1381 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING, info0);
1382 ppdu_info->ldpc = value;
1383 ppdu_info->he_data3 |=
1384 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1385
1386 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID, info0);
1387 ppdu_info->he_data4 |=
1388 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value);
1389
1390 ppdu_info->nss =
1391 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS, info0) + 1;
1392 break;
1393 }
1394 case HAL_PHYRX_HE_SIG_B2_OFDMA: {
1395 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma =
1396 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data;
1397
1398 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
1399
1400 ppdu_info->he_data1 |=
1401 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1402 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN |
1403 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN;
1404
1405 /* HE-data2 */
1406 ppdu_info->he_data2 |= IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN;
1407
1408 ppdu_info->mcs =
1409 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS,
1410 info0);
1411 ppdu_info->he_data3 |=
1412 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs);
1413
1414 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM, info0);
1415 he_dcm = value;
1416 ppdu_info->he_data3 |=
1417 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, value);
1418
1419 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING, info0);
1420 ppdu_info->ldpc = value;
1421 ppdu_info->he_data3 |=
1422 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1423
1424 /* HE-data4 */
1425 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID, info0);
1426 ppdu_info->he_data4 |=
1427 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value);
1428
1429 ppdu_info->nss =
1430 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS,
1431 info0) + 1;
1432 ppdu_info->beamformed =
1433 info0 & HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF;
1434 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
1435 break;
1436 }
1437 case HAL_PHYRX_RSSI_LEGACY: {
1438 int i;
1439 bool db2dbm = test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
1440 ab->wmi_ab.svc_map);
1441 struct hal_rx_phyrx_rssi_legacy_info *rssi =
1442 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data;
1443
1444 /* TODO: Please note that the combined rssi will not be accurate
1445 * in MU case. Rssi in MU needs to be retrieved from
1446 * PHYRX_OTHER_RECEIVE_INFO TLV.
1447 */
1448 ppdu_info->rssi_comb =
1449 FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB,
1450 __le32_to_cpu(rssi->info0));
1451
1452 if (db2dbm) {
1453 for (i = 0; i < ARRAY_SIZE(rssi->preamble); i++) {
1454 ppdu_info->rssi_chain_pri20[i] =
1455 le32_get_bits(rssi->preamble[i].rssi_2040,
1456 HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20);
1457 }
1458 }
1459 break;
1460 }
1461 case HAL_RX_MPDU_START: {
1462 u16 peer_id;
1463
1464 peer_id = ab->hw_params.hw_ops->mpdu_info_get_peerid(tlv_data);
1465 if (peer_id)
1466 ppdu_info->peer_id = peer_id;
1467 break;
1468 }
1469 case HAL_RXPCU_PPDU_END_INFO: {
1470 struct hal_rx_ppdu_end_duration *ppdu_rx_duration =
1471 (struct hal_rx_ppdu_end_duration *)tlv_data;
1472 ppdu_info->rx_duration =
1473 FIELD_GET(HAL_RX_PPDU_END_DURATION,
1474 __le32_to_cpu(ppdu_rx_duration->info0));
1475 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
1476 ppdu_info->tsft = (ppdu_info->tsft << 32) |
1477 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
1478 break;
1479 }
1480 case HAL_DUMMY:
1481 return HAL_RX_MON_STATUS_BUF_DONE;
1482 case HAL_RX_PPDU_END_STATUS_DONE:
1483 case 0:
1484 return HAL_RX_MON_STATUS_PPDU_DONE;
1485 default:
1486 break;
1487 }
1488
1489 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
1490 }
1491
1492 enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,struct sk_buff * skb)1493 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
1494 struct hal_rx_mon_ppdu_info *ppdu_info,
1495 struct sk_buff *skb)
1496 {
1497 struct hal_tlv_hdr *tlv;
1498 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1499 u16 tlv_tag;
1500 u16 tlv_len;
1501 u32 tlv_userid = 0;
1502 u8 *ptr = skb->data;
1503
1504 do {
1505 tlv = (struct hal_tlv_hdr *)ptr;
1506 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl);
1507 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
1508 tlv_userid = FIELD_GET(HAL_TLV_USR_ID, tlv->tl);
1509 ptr += sizeof(*tlv);
1510
1511 /* The actual length of PPDU_END is the combined length of many PHY
1512 * TLVs that follow. Skip the TLV header and
1513 * rx_rxpcu_classification_overview that follows the header to get to
1514 * next TLV.
1515 */
1516 if (tlv_tag == HAL_RX_PPDU_END)
1517 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1518
1519 hal_status = ath11k_hal_rx_parse_mon_status_tlv(ab, ppdu_info,
1520 tlv_tag, ptr, tlv_userid);
1521 ptr += tlv_len;
1522 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1523
1524 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1525 break;
1526 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE);
1527
1528 return hal_status;
1529 }
1530
ath11k_hal_rx_reo_ent_buf_paddr_get(void * rx_desc,dma_addr_t * paddr,u32 * sw_cookie,void ** pp_buf_addr,u8 * rbm,u32 * msdu_cnt)1531 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr,
1532 u32 *sw_cookie, void **pp_buf_addr,
1533 u8 *rbm, u32 *msdu_cnt)
1534 {
1535 struct hal_reo_entrance_ring *reo_ent_ring =
1536 (struct hal_reo_entrance_ring *)rx_desc;
1537 struct ath11k_buffer_addr *buf_addr_info;
1538 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
1539
1540 rx_mpdu_desc_info_details =
1541 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info;
1542
1543 *msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
1544 rx_mpdu_desc_info_details->info0);
1545
1546 buf_addr_info = (struct ath11k_buffer_addr *)&reo_ent_ring->buf_addr_info;
1547
1548 *paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1549 buf_addr_info->info1)) << 32) |
1550 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1551 buf_addr_info->info0);
1552
1553 *sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1554 buf_addr_info->info1);
1555 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
1556 buf_addr_info->info1);
1557
1558 *pp_buf_addr = (void *)buf_addr_info;
1559 }
1560
1561 void
ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void * rx_desc,struct hal_sw_mon_ring_entries * sw_mon_entries)1562 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
1563 struct hal_sw_mon_ring_entries *sw_mon_entries)
1564 {
1565 struct hal_sw_monitor_ring *sw_mon_ring = rx_desc;
1566 struct ath11k_buffer_addr *buf_addr_info;
1567 struct ath11k_buffer_addr *status_buf_addr_info;
1568 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
1569
1570 rx_mpdu_desc_info_details = &sw_mon_ring->rx_mpdu_info;
1571
1572 sw_mon_entries->msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
1573 rx_mpdu_desc_info_details->info0);
1574
1575 buf_addr_info = &sw_mon_ring->buf_addr_info;
1576 status_buf_addr_info = &sw_mon_ring->status_buf_addr_info;
1577
1578 sw_mon_entries->mon_dst_paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1579 buf_addr_info->info1)) << 32) |
1580 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1581 buf_addr_info->info0);
1582
1583 sw_mon_entries->mon_status_paddr =
1584 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1585 status_buf_addr_info->info1)) << 32) |
1586 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1587 status_buf_addr_info->info0);
1588
1589 sw_mon_entries->mon_dst_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1590 buf_addr_info->info1);
1591
1592 sw_mon_entries->mon_status_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1593 status_buf_addr_info->info1);
1594
1595 sw_mon_entries->status_buf_count = FIELD_GET(HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT,
1596 sw_mon_ring->info0);
1597
1598 sw_mon_entries->dst_buf_addr_info = buf_addr_info;
1599 sw_mon_entries->status_buf_addr_info = status_buf_addr_info;
1600
1601 sw_mon_entries->ppdu_id =
1602 FIELD_GET(HAL_SW_MON_RING_INFO1_PHY_PPDU_ID, sw_mon_ring->info1);
1603 }
1604