1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "core.h"
8 #include "dp_tx.h"
9 #include "debug.h"
10 #include "debugfs_sta.h"
11 #include "hw.h"
12 #include "peer.h"
13 #include "mac.h"
14
15 static enum hal_tcl_encap_type
ath11k_dp_tx_get_encap_type(struct ath11k_vif * arvif,struct sk_buff * skb)16 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
17 {
18 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
19 struct ath11k_base *ab = arvif->ar->ab;
20
21 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
22 return HAL_TCL_ENCAP_TYPE_RAW;
23
24 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
25 return HAL_TCL_ENCAP_TYPE_ETHERNET;
26
27 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
28 }
29
ath11k_dp_tx_encap_nwifi(struct sk_buff * skb)30 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb)
31 {
32 struct ieee80211_hdr *hdr = (void *)skb->data;
33 u8 *qos_ctl;
34
35 if (!ieee80211_is_data_qos(hdr->frame_control))
36 return;
37
38 qos_ctl = ieee80211_get_qos_ctl(hdr);
39 memmove(skb->data + IEEE80211_QOS_CTL_LEN,
40 skb->data, (void *)qos_ctl - (void *)skb->data);
41 skb_pull(skb, IEEE80211_QOS_CTL_LEN);
42
43 hdr = (void *)skb->data;
44 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
45 }
46
ath11k_dp_tx_get_tid(struct sk_buff * skb)47 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb)
48 {
49 struct ieee80211_hdr *hdr = (void *)skb->data;
50 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb);
51
52 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP)
53 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
54 else if (!ieee80211_is_data_qos(hdr->frame_control))
55 return HAL_DESC_REO_NON_QOS_TID;
56 else
57 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
58 }
59
ath11k_dp_tx_get_encrypt_type(u32 cipher)60 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher)
61 {
62 switch (cipher) {
63 case WLAN_CIPHER_SUITE_WEP40:
64 return HAL_ENCRYPT_TYPE_WEP_40;
65 case WLAN_CIPHER_SUITE_WEP104:
66 return HAL_ENCRYPT_TYPE_WEP_104;
67 case WLAN_CIPHER_SUITE_TKIP:
68 return HAL_ENCRYPT_TYPE_TKIP_MIC;
69 case WLAN_CIPHER_SUITE_CCMP:
70 return HAL_ENCRYPT_TYPE_CCMP_128;
71 case WLAN_CIPHER_SUITE_CCMP_256:
72 return HAL_ENCRYPT_TYPE_CCMP_256;
73 case WLAN_CIPHER_SUITE_GCMP:
74 return HAL_ENCRYPT_TYPE_GCMP_128;
75 case WLAN_CIPHER_SUITE_GCMP_256:
76 return HAL_ENCRYPT_TYPE_AES_GCMP_256;
77 default:
78 return HAL_ENCRYPT_TYPE_OPEN;
79 }
80 }
81
ath11k_dp_tx(struct ath11k * ar,struct ath11k_vif * arvif,struct ath11k_sta * arsta,struct sk_buff * skb)82 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif,
83 struct ath11k_sta *arsta, struct sk_buff *skb)
84 {
85 struct ath11k_base *ab = ar->ab;
86 struct ath11k_dp *dp = &ab->dp;
87 struct hal_tx_info ti = {0};
88 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
89 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
90 struct hal_srng *tcl_ring;
91 struct ieee80211_hdr *hdr = (void *)skb->data;
92 struct dp_tx_ring *tx_ring;
93 void *hal_tcl_desc;
94 u8 pool_id;
95 u8 hal_ring_id;
96 int ret;
97 u32 ring_selector = 0;
98 u8 ring_map = 0;
99 bool tcl_ring_retry;
100
101 if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)))
102 return -ESHUTDOWN;
103
104 if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
105 !ieee80211_is_data(hdr->frame_control)))
106 return -ENOTSUPP;
107
108 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1);
109
110 ring_selector = ab->hw_params.hw_ops->get_ring_selector(skb);
111
112 tcl_ring_sel:
113 tcl_ring_retry = false;
114
115 ti.ring_id = ring_selector % ab->hw_params.max_tx_ring;
116 ti.rbm_id = ab->hw_params.hal_params->tcl2wbm_rbm_map[ti.ring_id].rbm_id;
117
118 ring_map |= BIT(ti.ring_id);
119
120 tx_ring = &dp->tx_ring[ti.ring_id];
121
122 spin_lock_bh(&tx_ring->tx_idr_lock);
123 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0,
124 DP_TX_IDR_SIZE - 1, GFP_ATOMIC);
125 spin_unlock_bh(&tx_ring->tx_idr_lock);
126
127 if (unlikely(ret < 0)) {
128 if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1) ||
129 !ab->hw_params.tcl_ring_retry) {
130 atomic_inc(&ab->soc_stats.tx_err.misc_fail);
131 return -ENOSPC;
132 }
133
134 /* Check if the next ring is available */
135 ring_selector++;
136 goto tcl_ring_sel;
137 }
138
139 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) |
140 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) |
141 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id);
142 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb);
143
144 if (ieee80211_has_a4(hdr->frame_control) &&
145 is_multicast_ether_addr(hdr->addr3) && arsta &&
146 arsta->use_4addr_set) {
147 ti.meta_data_flags = arsta->tcl_metadata;
148 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1);
149 } else {
150 ti.meta_data_flags = arvif->tcl_metadata;
151 }
152
153 if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) {
154 if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) {
155 ti.encrypt_type =
156 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher);
157
158 if (ieee80211_has_protected(hdr->frame_control))
159 skb_put(skb, IEEE80211_CCMP_MIC_LEN);
160 } else {
161 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
162 }
163 }
164
165 ti.addr_search_flags = arvif->hal_addr_search_flags;
166 ti.search_type = arvif->search_type;
167 ti.type = HAL_TCL_DESC_TYPE_BUFFER;
168 ti.pkt_offset = 0;
169 ti.lmac_id = ar->lmac_id;
170 ti.bss_ast_hash = arvif->ast_hash;
171 ti.bss_ast_idx = arvif->ast_idx;
172 ti.dscp_tid_tbl_idx = 0;
173
174 if (likely(skb->ip_summed == CHECKSUM_PARTIAL &&
175 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) {
176 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) |
177 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) |
178 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) |
179 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) |
180 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1);
181 }
182
183 if (ieee80211_vif_is_mesh(arvif->vif))
184 ti.enable_mesh = true;
185
186 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);
187
188 ti.tid = ath11k_dp_tx_get_tid(skb);
189
190 switch (ti.encap_type) {
191 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
192 ath11k_dp_tx_encap_nwifi(skb);
193 break;
194 case HAL_TCL_ENCAP_TYPE_RAW:
195 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) {
196 ret = -EINVAL;
197 goto fail_remove_idr;
198 }
199 break;
200 case HAL_TCL_ENCAP_TYPE_ETHERNET:
201 /* no need to encap */
202 break;
203 case HAL_TCL_ENCAP_TYPE_802_3:
204 default:
205 /* TODO: Take care of other encap modes as well */
206 ret = -EINVAL;
207 atomic_inc(&ab->soc_stats.tx_err.misc_fail);
208 goto fail_remove_idr;
209 }
210
211 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
212 if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) {
213 atomic_inc(&ab->soc_stats.tx_err.misc_fail);
214 ath11k_warn(ab, "failed to DMA map data Tx buffer\n");
215 ret = -ENOMEM;
216 goto fail_remove_idr;
217 }
218
219 ti.data_len = skb->len;
220 skb_cb->paddr = ti.paddr;
221 skb_cb->vif = arvif->vif;
222 skb_cb->ar = ar;
223
224 hal_ring_id = tx_ring->tcl_data_ring.ring_id;
225 tcl_ring = &ab->hal.srng_list[hal_ring_id];
226
227 spin_lock_bh(&tcl_ring->lock);
228
229 ath11k_hal_srng_access_begin(ab, tcl_ring);
230
231 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring);
232 if (unlikely(!hal_tcl_desc)) {
233 /* NOTE: It is highly unlikely we'll be running out of tcl_ring
234 * desc because the desc is directly enqueued onto hw queue.
235 */
236 ath11k_hal_srng_access_end(ab, tcl_ring);
237 ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
238 spin_unlock_bh(&tcl_ring->lock);
239 ret = -ENOMEM;
240
241 /* Checking for available tcl descritors in another ring in
242 * case of failure due to full tcl ring now, is better than
243 * checking this ring earlier for each pkt tx.
244 * Restart ring selection if some rings are not checked yet.
245 */
246 if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) &&
247 ab->hw_params.tcl_ring_retry && ab->hw_params.max_tx_ring > 1) {
248 tcl_ring_retry = true;
249 ring_selector++;
250 }
251
252 goto fail_unmap_dma;
253 }
254
255 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc +
256 sizeof(struct hal_tlv_hdr), &ti);
257
258 ath11k_hal_srng_access_end(ab, tcl_ring);
259
260 ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]);
261
262 spin_unlock_bh(&tcl_ring->lock);
263
264 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ",
265 skb->data, skb->len);
266
267 atomic_inc(&ar->dp.num_tx_pending);
268
269 return 0;
270
271 fail_unmap_dma:
272 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
273
274 fail_remove_idr:
275 spin_lock_bh(&tx_ring->tx_idr_lock);
276 idr_remove(&tx_ring->txbuf_idr,
277 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id));
278 spin_unlock_bh(&tx_ring->tx_idr_lock);
279
280 if (tcl_ring_retry)
281 goto tcl_ring_sel;
282
283 return ret;
284 }
285
ath11k_dp_tx_free_txbuf(struct ath11k_base * ab,u8 mac_id,int msdu_id,struct dp_tx_ring * tx_ring)286 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id,
287 int msdu_id,
288 struct dp_tx_ring *tx_ring)
289 {
290 struct ath11k *ar;
291 struct sk_buff *msdu;
292 struct ath11k_skb_cb *skb_cb;
293
294 spin_lock(&tx_ring->tx_idr_lock);
295 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
296 spin_unlock(&tx_ring->tx_idr_lock);
297
298 if (unlikely(!msdu)) {
299 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
300 msdu_id);
301 return;
302 }
303
304 skb_cb = ATH11K_SKB_CB(msdu);
305
306 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
307 dev_kfree_skb_any(msdu);
308
309 ar = ab->pdevs[mac_id].ar;
310 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
311 wake_up(&ar->dp.tx_empty_waitq);
312 }
313
314 static void
ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base * ab,struct dp_tx_ring * tx_ring,struct ath11k_dp_htt_wbm_tx_status * ts)315 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab,
316 struct dp_tx_ring *tx_ring,
317 struct ath11k_dp_htt_wbm_tx_status *ts)
318 {
319 struct sk_buff *msdu;
320 struct ieee80211_tx_info *info;
321 struct ath11k_skb_cb *skb_cb;
322 struct ath11k *ar;
323
324 spin_lock(&tx_ring->tx_idr_lock);
325 msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id);
326 spin_unlock(&tx_ring->tx_idr_lock);
327
328 if (unlikely(!msdu)) {
329 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n",
330 ts->msdu_id);
331 return;
332 }
333
334 skb_cb = ATH11K_SKB_CB(msdu);
335 info = IEEE80211_SKB_CB(msdu);
336
337 ar = skb_cb->ar;
338
339 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
340 wake_up(&ar->dp.tx_empty_waitq);
341
342 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
343
344 memset(&info->status, 0, sizeof(info->status));
345
346 if (ts->acked) {
347 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
348 info->flags |= IEEE80211_TX_STAT_ACK;
349 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
350 ts->ack_rssi;
351 info->status.flags |=
352 IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
353 } else {
354 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
355 }
356 }
357
358 ieee80211_tx_status(ar->hw, msdu);
359 }
360
361 static void
ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base * ab,void * desc,u8 mac_id,u32 msdu_id,struct dp_tx_ring * tx_ring)362 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab,
363 void *desc, u8 mac_id,
364 u32 msdu_id, struct dp_tx_ring *tx_ring)
365 {
366 struct htt_tx_wbm_completion *status_desc;
367 struct ath11k_dp_htt_wbm_tx_status ts = {0};
368 enum hal_wbm_htt_tx_comp_status wbm_status;
369
370 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
371
372 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS,
373 status_desc->info0);
374 switch (wbm_status) {
375 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
376 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
377 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
378 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
379 ts.msdu_id = msdu_id;
380 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI,
381 status_desc->info1);
382 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts);
383 break;
384 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
385 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
386 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring);
387 break;
388 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
389 /* This event is to be handled only when the driver decides to
390 * use WDS offload functionality.
391 */
392 break;
393 default:
394 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
395 break;
396 }
397 }
398
ath11k_dp_tx_cache_peer_stats(struct ath11k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)399 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar,
400 struct sk_buff *msdu,
401 struct hal_tx_status *ts)
402 {
403 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
404
405 if (ts->try_cnt > 1) {
406 peer_stats->retry_pkts += ts->try_cnt - 1;
407 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len;
408
409 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) {
410 peer_stats->failed_pkts += 1;
411 peer_stats->failed_bytes += msdu->len;
412 }
413 }
414 }
415
ath11k_dp_tx_update_txcompl(struct ath11k * ar,struct hal_tx_status * ts)416 void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts)
417 {
418 struct ath11k_base *ab = ar->ab;
419 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
420 enum hal_tx_rate_stats_pkt_type pkt_type;
421 enum hal_tx_rate_stats_sgi sgi;
422 enum hal_tx_rate_stats_bw bw;
423 struct ath11k_peer *peer;
424 struct ath11k_sta *arsta;
425 struct ieee80211_sta *sta;
426 u16 rate, ru_tones;
427 u8 mcs, rate_idx = 0, ofdma;
428 int ret;
429
430 spin_lock_bh(&ab->base_lock);
431 peer = ath11k_peer_find_by_id(ab, ts->peer_id);
432 if (!peer || !peer->sta) {
433 ath11k_dbg(ab, ATH11K_DBG_DP_TX,
434 "failed to find the peer by id %u\n", ts->peer_id);
435 goto err_out;
436 }
437
438 sta = peer->sta;
439 arsta = (struct ath11k_sta *)sta->drv_priv;
440
441 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
442 pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE,
443 ts->rate_stats);
444 mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS,
445 ts->rate_stats);
446 sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI,
447 ts->rate_stats);
448 bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, ts->rate_stats);
449 ru_tones = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, ts->rate_stats);
450 ofdma = FIELD_GET(HAL_TX_RATE_STATS_INFO0_OFDMA_TX, ts->rate_stats);
451
452 /* This is to prefer choose the real NSS value arsta->last_txrate.nss,
453 * if it is invalid, then choose the NSS value while assoc.
454 */
455 if (arsta->last_txrate.nss)
456 arsta->txrate.nss = arsta->last_txrate.nss;
457 else
458 arsta->txrate.nss = arsta->peer_nss;
459
460 if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11A ||
461 pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11B) {
462 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
463 pkt_type,
464 &rate_idx,
465 &rate);
466 if (ret < 0)
467 goto err_out;
468 arsta->txrate.legacy = rate;
469 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11N) {
470 if (mcs > 7) {
471 ath11k_warn(ab, "Invalid HT mcs index %d\n", mcs);
472 goto err_out;
473 }
474
475 if (arsta->txrate.nss != 0)
476 arsta->txrate.mcs = mcs + 8 * (arsta->txrate.nss - 1);
477 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
478 if (sgi)
479 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
480 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AC) {
481 if (mcs > 9) {
482 ath11k_warn(ab, "Invalid VHT mcs index %d\n", mcs);
483 goto err_out;
484 }
485
486 arsta->txrate.mcs = mcs;
487 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
488 if (sgi)
489 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
490 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
491 if (mcs > 11) {
492 ath11k_warn(ab, "Invalid HE mcs index %d\n", mcs);
493 goto err_out;
494 }
495
496 arsta->txrate.mcs = mcs;
497 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
498 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
499 }
500
501 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
502 if (ofdma && pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
503 arsta->txrate.bw = RATE_INFO_BW_HE_RU;
504 arsta->txrate.he_ru_alloc =
505 ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
506 }
507
508 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
509 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
510
511 err_out:
512 spin_unlock_bh(&ab->base_lock);
513 }
514
ath11k_dp_tx_complete_msdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)515 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
516 struct sk_buff *msdu,
517 struct hal_tx_status *ts)
518 {
519 struct ieee80211_tx_status status = { 0 };
520 struct ieee80211_rate_status status_rate = { 0 };
521 struct ath11k_base *ab = ar->ab;
522 struct ieee80211_tx_info *info;
523 struct ath11k_skb_cb *skb_cb;
524 struct ath11k_peer *peer;
525 struct ath11k_sta *arsta;
526 struct rate_info rate;
527
528 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
529 /* Must not happen */
530 return;
531 }
532
533 skb_cb = ATH11K_SKB_CB(msdu);
534
535 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
536
537 if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) {
538 dev_kfree_skb_any(msdu);
539 return;
540 }
541
542 if (unlikely(!skb_cb->vif)) {
543 dev_kfree_skb_any(msdu);
544 return;
545 }
546
547 info = IEEE80211_SKB_CB(msdu);
548 memset(&info->status, 0, sizeof(info->status));
549
550 /* skip tx rate update from ieee80211_status*/
551 info->status.rates[0].idx = -1;
552
553 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
554 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
555 info->flags |= IEEE80211_TX_STAT_ACK;
556 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
557 ts->ack_rssi;
558 info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
559 }
560
561 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
562 (info->flags & IEEE80211_TX_CTL_NO_ACK))
563 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
564
565 if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar)) ||
566 ab->hw_params.single_pdev_only) {
567 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
568 if (ar->last_ppdu_id == 0) {
569 ar->last_ppdu_id = ts->ppdu_id;
570 } else if (ar->last_ppdu_id == ts->ppdu_id ||
571 ar->cached_ppdu_id == ar->last_ppdu_id) {
572 ar->cached_ppdu_id = ar->last_ppdu_id;
573 ar->cached_stats.is_ampdu = true;
574 ath11k_dp_tx_update_txcompl(ar, ts);
575 memset(&ar->cached_stats, 0,
576 sizeof(struct ath11k_per_peer_tx_stats));
577 } else {
578 ar->cached_stats.is_ampdu = false;
579 ath11k_dp_tx_update_txcompl(ar, ts);
580 memset(&ar->cached_stats, 0,
581 sizeof(struct ath11k_per_peer_tx_stats));
582 }
583 ar->last_ppdu_id = ts->ppdu_id;
584 }
585
586 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts);
587 }
588
589 spin_lock_bh(&ab->base_lock);
590 peer = ath11k_peer_find_by_id(ab, ts->peer_id);
591 if (!peer || !peer->sta) {
592 ath11k_dbg(ab, ATH11K_DBG_DATA,
593 "dp_tx: failed to find the peer with peer_id %d\n",
594 ts->peer_id);
595 spin_unlock_bh(&ab->base_lock);
596 dev_kfree_skb_any(msdu);
597 return;
598 }
599 arsta = (struct ath11k_sta *)peer->sta->drv_priv;
600 status.sta = peer->sta;
601 status.skb = msdu;
602 status.info = info;
603 rate = arsta->last_txrate;
604
605 status_rate.rate_idx = rate;
606 status_rate.try_count = 1;
607
608 status.rates = &status_rate;
609 status.n_rates = 1;
610
611 spin_unlock_bh(&ab->base_lock);
612
613 ieee80211_tx_status_ext(ar->hw, &status);
614 }
615
ath11k_dp_tx_status_parse(struct ath11k_base * ab,struct hal_wbm_release_ring * desc,struct hal_tx_status * ts)616 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab,
617 struct hal_wbm_release_ring *desc,
618 struct hal_tx_status *ts)
619 {
620 ts->buf_rel_source =
621 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0);
622 if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
623 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM))
624 return;
625
626 if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW))
627 return;
628
629 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON,
630 desc->info0);
631 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER,
632 desc->info1);
633 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT,
634 desc->info1);
635 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI,
636 desc->info2);
637 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU)
638 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU;
639 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3);
640 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3);
641 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)
642 ts->rate_stats = desc->rate_stats.info0;
643 else
644 ts->rate_stats = 0;
645 }
646
ath11k_dp_tx_completion_handler(struct ath11k_base * ab,int ring_id)647 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id)
648 {
649 struct ath11k *ar;
650 struct ath11k_dp *dp = &ab->dp;
651 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
652 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
653 struct sk_buff *msdu;
654 struct hal_tx_status ts = { 0 };
655 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
656 u32 *desc;
657 u32 msdu_id;
658 u8 mac_id;
659
660 spin_lock_bh(&status_ring->lock);
661
662 ath11k_hal_srng_access_begin(ab, status_ring);
663
664 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) !=
665 tx_ring->tx_status_tail) &&
666 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) {
667 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
668 desc, sizeof(struct hal_wbm_release_ring));
669 tx_ring->tx_status_head =
670 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head);
671 }
672
673 if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) &&
674 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) ==
675 tx_ring->tx_status_tail))) {
676 /* TODO: Process pending tx_status messages when kfifo_is_full() */
677 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
678 }
679
680 ath11k_hal_srng_access_end(ab, status_ring);
681
682 spin_unlock_bh(&status_ring->lock);
683
684 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
685 struct hal_wbm_release_ring *tx_status;
686 u32 desc_id;
687
688 tx_ring->tx_status_tail =
689 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
690 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
691 ath11k_dp_tx_status_parse(ab, tx_status, &ts);
692
693 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
694 tx_status->buf_addr_info.info1);
695 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id);
696 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id);
697
698 if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) {
699 ath11k_dp_tx_process_htt_tx_complete(ab,
700 (void *)tx_status,
701 mac_id, msdu_id,
702 tx_ring);
703 continue;
704 }
705
706 spin_lock(&tx_ring->tx_idr_lock);
707 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
708 if (unlikely(!msdu)) {
709 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
710 msdu_id);
711 spin_unlock(&tx_ring->tx_idr_lock);
712 continue;
713 }
714
715 spin_unlock(&tx_ring->tx_idr_lock);
716
717 ar = ab->pdevs[mac_id].ar;
718
719 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
720 wake_up(&ar->dp.tx_empty_waitq);
721
722 ath11k_dp_tx_complete_msdu(ar, msdu, &ts);
723 }
724 }
725
ath11k_dp_tx_send_reo_cmd(struct ath11k_base * ab,struct dp_rx_tid * rx_tid,enum hal_reo_cmd_type type,struct ath11k_hal_reo_cmd * cmd,void (* cb)(struct ath11k_dp *,void *,enum hal_reo_cmd_status))726 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid,
727 enum hal_reo_cmd_type type,
728 struct ath11k_hal_reo_cmd *cmd,
729 void (*cb)(struct ath11k_dp *, void *,
730 enum hal_reo_cmd_status))
731 {
732 struct ath11k_dp *dp = &ab->dp;
733 struct dp_reo_cmd *dp_cmd;
734 struct hal_srng *cmd_ring;
735 int cmd_num;
736
737 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
738 return -ESHUTDOWN;
739
740 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
741 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
742
743 /* cmd_num should start from 1, during failure return the error code */
744 if (cmd_num < 0)
745 return cmd_num;
746
747 /* reo cmd ring descriptors has cmd_num starting from 1 */
748 if (cmd_num == 0)
749 return -EINVAL;
750
751 if (!cb)
752 return 0;
753
754 /* Can this be optimized so that we keep the pending command list only
755 * for tid delete command to free up the resource on the command status
756 * indication?
757 */
758 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
759
760 if (!dp_cmd)
761 return -ENOMEM;
762
763 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid));
764 dp_cmd->cmd_num = cmd_num;
765 dp_cmd->handler = cb;
766
767 spin_lock_bh(&dp->reo_cmd_lock);
768 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
769 spin_unlock_bh(&dp->reo_cmd_lock);
770
771 return 0;
772 }
773
774 static int
ath11k_dp_tx_get_ring_id_type(struct ath11k_base * ab,int mac_id,u32 ring_id,enum hal_ring_type ring_type,enum htt_srng_ring_type * htt_ring_type,enum htt_srng_ring_id * htt_ring_id)775 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab,
776 int mac_id, u32 ring_id,
777 enum hal_ring_type ring_type,
778 enum htt_srng_ring_type *htt_ring_type,
779 enum htt_srng_ring_id *htt_ring_id)
780 {
781 int lmac_ring_id_offset = 0;
782 int ret = 0;
783
784 switch (ring_type) {
785 case HAL_RXDMA_BUF:
786 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC;
787
788 /* for QCA6390, host fills rx buffer to fw and fw fills to
789 * rxbuf ring for each rxdma
790 */
791 if (!ab->hw_params.rx_mac_buf_ring) {
792 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF +
793 lmac_ring_id_offset) ||
794 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF +
795 lmac_ring_id_offset))) {
796 ret = -EINVAL;
797 }
798 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
799 *htt_ring_type = HTT_SW_TO_HW_RING;
800 } else {
801 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) {
802 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
803 *htt_ring_type = HTT_SW_TO_SW_RING;
804 } else {
805 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
806 *htt_ring_type = HTT_SW_TO_HW_RING;
807 }
808 }
809 break;
810 case HAL_RXDMA_DST:
811 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
812 *htt_ring_type = HTT_HW_TO_SW_RING;
813 break;
814 case HAL_RXDMA_MONITOR_BUF:
815 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
816 *htt_ring_type = HTT_SW_TO_HW_RING;
817 break;
818 case HAL_RXDMA_MONITOR_STATUS:
819 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
820 *htt_ring_type = HTT_SW_TO_HW_RING;
821 break;
822 case HAL_RXDMA_MONITOR_DST:
823 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
824 *htt_ring_type = HTT_HW_TO_SW_RING;
825 break;
826 case HAL_RXDMA_MONITOR_DESC:
827 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
828 *htt_ring_type = HTT_SW_TO_HW_RING;
829 break;
830 default:
831 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
832 ret = -EINVAL;
833 }
834 return ret;
835 }
836
ath11k_dp_tx_htt_srng_setup(struct ath11k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type)837 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
838 int mac_id, enum hal_ring_type ring_type)
839 {
840 struct htt_srng_setup_cmd *cmd;
841 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
842 struct hal_srng_params params;
843 struct sk_buff *skb;
844 u32 ring_entry_sz;
845 int len = sizeof(*cmd);
846 dma_addr_t hp_addr, tp_addr;
847 enum htt_srng_ring_type htt_ring_type;
848 enum htt_srng_ring_id htt_ring_id;
849 int ret;
850
851 skb = ath11k_htc_alloc_skb(ab, len);
852 if (!skb)
853 return -ENOMEM;
854
855 memset(¶ms, 0, sizeof(params));
856 ath11k_hal_srng_get_params(ab, srng, ¶ms);
857
858 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng);
859 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng);
860
861 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
862 ring_type, &htt_ring_type,
863 &htt_ring_id);
864 if (ret)
865 goto err_free;
866
867 skb_put(skb, len);
868 cmd = (struct htt_srng_setup_cmd *)skb->data;
869 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE,
870 HTT_H2T_MSG_TYPE_SRING_SETUP);
871 if (htt_ring_type == HTT_SW_TO_HW_RING ||
872 htt_ring_type == HTT_HW_TO_SW_RING)
873 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
874 DP_SW2HW_MACID(mac_id));
875 else
876 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
877 mac_id);
878 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE,
879 htt_ring_type);
880 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id);
881
882 cmd->ring_base_addr_lo = params.ring_base_paddr &
883 HAL_ADDR_LSB_REG_MASK;
884
885 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >>
886 HAL_ADDR_MSB_REG_SHIFT;
887
888 ret = ath11k_hal_srng_get_entrysize(ab, ring_type);
889 if (ret < 0)
890 goto err_free;
891
892 ring_entry_sz = ret;
893
894 ring_entry_sz >>= 2;
895 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE,
896 ring_entry_sz);
897 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE,
898 params.num_entries * ring_entry_sz);
899 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP,
900 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
901 cmd->info1 |= FIELD_PREP(
902 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP,
903 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
904 cmd->info1 |= FIELD_PREP(
905 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP,
906 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP));
907 if (htt_ring_type == HTT_SW_TO_HW_RING)
908 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS;
909
910 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK;
911 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >>
912 HAL_ADDR_MSB_REG_SHIFT;
913
914 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK;
915 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
916 HAL_ADDR_MSB_REG_SHIFT;
917
918 cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr);
919 cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr);
920 cmd->msi_data = params.msi_data;
921
922 cmd->intr_info = FIELD_PREP(
923 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH,
924 params.intr_batch_cntr_thres_entries * ring_entry_sz);
925 cmd->intr_info |= FIELD_PREP(
926 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH,
927 params.intr_timer_thres_us >> 3);
928
929 cmd->info2 = 0;
930 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
931 cmd->info2 = FIELD_PREP(
932 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH,
933 params.low_threshold);
934 }
935
936 ath11k_dbg(ab, ATH11k_DBG_HAL,
937 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
938 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
939 cmd->msi_data);
940
941 ath11k_dbg(ab, ATH11k_DBG_HAL,
942 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
943 ring_id, ring_type, cmd->intr_info, cmd->info2);
944
945 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
946 if (ret)
947 goto err_free;
948
949 return 0;
950
951 err_free:
952 dev_kfree_skb_any(skb);
953
954 return ret;
955 }
956
957 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
958
ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base * ab)959 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab)
960 {
961 struct ath11k_dp *dp = &ab->dp;
962 struct sk_buff *skb;
963 struct htt_ver_req_cmd *cmd;
964 int len = sizeof(*cmd);
965 int ret;
966
967 init_completion(&dp->htt_tgt_version_received);
968
969 skb = ath11k_htc_alloc_skb(ab, len);
970 if (!skb)
971 return -ENOMEM;
972
973 skb_put(skb, len);
974 cmd = (struct htt_ver_req_cmd *)skb->data;
975 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID,
976 HTT_H2T_MSG_TYPE_VERSION_REQ);
977
978 ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
979 if (ret) {
980 dev_kfree_skb_any(skb);
981 return ret;
982 }
983
984 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
985 HTT_TARGET_VERSION_TIMEOUT_HZ);
986 if (ret == 0) {
987 ath11k_warn(ab, "htt target version request timed out\n");
988 return -ETIMEDOUT;
989 }
990
991 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
992 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n",
993 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
994 return -ENOTSUPP;
995 }
996
997 return 0;
998 }
999
ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k * ar,u32 mask)1000 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask)
1001 {
1002 struct ath11k_base *ab = ar->ab;
1003 struct ath11k_dp *dp = &ab->dp;
1004 struct sk_buff *skb;
1005 struct htt_ppdu_stats_cfg_cmd *cmd;
1006 int len = sizeof(*cmd);
1007 u8 pdev_mask;
1008 int ret;
1009 int i;
1010
1011 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1012 skb = ath11k_htc_alloc_skb(ab, len);
1013 if (!skb)
1014 return -ENOMEM;
1015
1016 skb_put(skb, len);
1017 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
1018 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE,
1019 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG);
1020
1021 pdev_mask = 1 << (ar->pdev_idx + i);
1022 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask);
1023 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask);
1024
1025 ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1026 if (ret) {
1027 dev_kfree_skb_any(skb);
1028 return ret;
1029 }
1030 }
1031
1032 return 0;
1033 }
1034
ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type,int rx_buf_size,struct htt_rx_ring_tlv_filter * tlv_filter)1035 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
1036 int mac_id, enum hal_ring_type ring_type,
1037 int rx_buf_size,
1038 struct htt_rx_ring_tlv_filter *tlv_filter)
1039 {
1040 struct htt_rx_ring_selection_cfg_cmd *cmd;
1041 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1042 struct hal_srng_params params;
1043 struct sk_buff *skb;
1044 int len = sizeof(*cmd);
1045 enum htt_srng_ring_type htt_ring_type;
1046 enum htt_srng_ring_id htt_ring_id;
1047 int ret;
1048
1049 skb = ath11k_htc_alloc_skb(ab, len);
1050 if (!skb)
1051 return -ENOMEM;
1052
1053 memset(¶ms, 0, sizeof(params));
1054 ath11k_hal_srng_get_params(ab, srng, ¶ms);
1055
1056 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1057 ring_type, &htt_ring_type,
1058 &htt_ring_id);
1059 if (ret)
1060 goto err_free;
1061
1062 skb_put(skb, len);
1063 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
1064 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE,
1065 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG);
1066 if (htt_ring_type == HTT_SW_TO_HW_RING ||
1067 htt_ring_type == HTT_HW_TO_SW_RING)
1068 cmd->info0 |=
1069 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
1070 DP_SW2HW_MACID(mac_id));
1071 else
1072 cmd->info0 |=
1073 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
1074 mac_id);
1075 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID,
1076 htt_ring_id);
1077 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS,
1078 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
1079 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS,
1080 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
1081
1082 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE,
1083 rx_buf_size);
1084 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0;
1085 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1;
1086 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2;
1087 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3;
1088 cmd->rx_filter_tlv = tlv_filter->rx_filter;
1089
1090 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
1091 if (ret)
1092 goto err_free;
1093
1094 return 0;
1095
1096 err_free:
1097 dev_kfree_skb_any(skb);
1098
1099 return ret;
1100 }
1101
1102 int
ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k * ar,u8 type,struct htt_ext_stats_cfg_params * cfg_params,u64 cookie)1103 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
1104 struct htt_ext_stats_cfg_params *cfg_params,
1105 u64 cookie)
1106 {
1107 struct ath11k_base *ab = ar->ab;
1108 struct ath11k_dp *dp = &ab->dp;
1109 struct sk_buff *skb;
1110 struct htt_ext_stats_cfg_cmd *cmd;
1111 u32 pdev_id;
1112 int len = sizeof(*cmd);
1113 int ret;
1114
1115 skb = ath11k_htc_alloc_skb(ab, len);
1116 if (!skb)
1117 return -ENOMEM;
1118
1119 skb_put(skb, len);
1120
1121 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
1122 memset(cmd, 0, sizeof(*cmd));
1123 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
1124
1125 if (ab->hw_params.single_pdev_only)
1126 pdev_id = ath11k_mac_get_target_pdev_id(ar);
1127 else
1128 pdev_id = ar->pdev->pdev_id;
1129
1130 cmd->hdr.pdev_mask = 1 << pdev_id;
1131
1132 cmd->hdr.stats_type = type;
1133 cmd->cfg_param0 = cfg_params->cfg0;
1134 cmd->cfg_param1 = cfg_params->cfg1;
1135 cmd->cfg_param2 = cfg_params->cfg2;
1136 cmd->cfg_param3 = cfg_params->cfg3;
1137 cmd->cookie_lsb = lower_32_bits(cookie);
1138 cmd->cookie_msb = upper_32_bits(cookie);
1139
1140 ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1141 if (ret) {
1142 ath11k_warn(ab, "failed to send htt type stats request: %d",
1143 ret);
1144 dev_kfree_skb_any(skb);
1145 return ret;
1146 }
1147
1148 return 0;
1149 }
1150
ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k * ar,bool reset)1151 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
1152 {
1153 struct ath11k_pdev_dp *dp = &ar->dp;
1154 struct ath11k_base *ab = ar->ab;
1155 struct htt_rx_ring_tlv_filter tlv_filter = {0};
1156 int ret = 0, ring_id = 0, i;
1157
1158 if (ab->hw_params.full_monitor_mode) {
1159 ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab,
1160 dp->mac_id, !reset);
1161 if (ret < 0) {
1162 ath11k_err(ab, "failed to setup full monitor %d\n", ret);
1163 return ret;
1164 }
1165 }
1166
1167 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
1168
1169 if (!reset) {
1170 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
1171 tlv_filter.pkt_filter_flags0 =
1172 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
1173 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
1174 tlv_filter.pkt_filter_flags1 =
1175 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
1176 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
1177 tlv_filter.pkt_filter_flags2 =
1178 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
1179 HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
1180 tlv_filter.pkt_filter_flags3 =
1181 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
1182 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
1183 HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
1184 HTT_RX_MON_MO_DATA_FILTER_FLASG3;
1185 }
1186
1187 if (ab->hw_params.rxdma1_enable) {
1188 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
1189 HAL_RXDMA_MONITOR_BUF,
1190 DP_RXDMA_REFILL_RING_SIZE,
1191 &tlv_filter);
1192 } else if (!reset) {
1193 /* set in monitor mode only */
1194 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1195 ring_id = dp->rx_mac_buf_ring[i].ring_id;
1196 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
1197 dp->mac_id + i,
1198 HAL_RXDMA_BUF,
1199 1024,
1200 &tlv_filter);
1201 }
1202 }
1203
1204 if (ret)
1205 return ret;
1206
1207 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1208 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
1209 if (!reset) {
1210 tlv_filter.rx_filter =
1211 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
1212 } else {
1213 tlv_filter = ath11k_mac_mon_status_filter_default;
1214
1215 if (ath11k_debugfs_is_extd_rx_stats_enabled(ar))
1216 tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar);
1217 }
1218
1219 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id,
1220 dp->mac_id + i,
1221 HAL_RXDMA_MONITOR_STATUS,
1222 DP_RXDMA_REFILL_RING_SIZE,
1223 &tlv_filter);
1224 }
1225
1226 if (!ar->ab->hw_params.rxdma1_enable)
1227 mod_timer(&ar->ab->mon_reap_timer, jiffies +
1228 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
1229
1230 return ret;
1231 }
1232
ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base * ab,int mac_id,bool config)1233 int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id,
1234 bool config)
1235 {
1236 struct htt_rx_full_monitor_mode_cfg_cmd *cmd;
1237 struct sk_buff *skb;
1238 int ret, len = sizeof(*cmd);
1239
1240 skb = ath11k_htc_alloc_skb(ab, len);
1241 if (!skb)
1242 return -ENOMEM;
1243
1244 skb_put(skb, len);
1245 cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data;
1246 memset(cmd, 0, sizeof(*cmd));
1247 cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE,
1248 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE);
1249
1250 cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id);
1251
1252 cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE |
1253 FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING,
1254 HTT_RX_MON_RING_SW);
1255 if (config) {
1256 cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END |
1257 HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END;
1258 }
1259
1260 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
1261 if (ret)
1262 goto err_free;
1263
1264 return 0;
1265
1266 err_free:
1267 dev_kfree_skb_any(skb);
1268
1269 return ret;
1270 }
1271