1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19
20 unsigned int ath11k_debug_mask;
21 EXPORT_SYMBOL(ath11k_debug_mask);
22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
23 MODULE_PARM_DESC(debug_mask, "Debugging mask");
24
25 static unsigned int ath11k_crypto_mode;
26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
28
29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
32 MODULE_PARM_DESC(frame_mode,
33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
34
35 static const struct ath11k_hw_params ath11k_hw_params[] = {
36 {
37 .hw_rev = ATH11K_HW_IPQ8074,
38 .name = "ipq8074 hw2.0",
39 .fw = {
40 .dir = "IPQ8074/hw2.0",
41 .board_size = 256 * 1024,
42 .cal_offset = 128 * 1024,
43 },
44 .max_radios = 3,
45 .bdf_addr = 0x4B0C0000,
46 .hw_ops = &ipq8074_ops,
47 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
48 .internal_sleep_clock = false,
49 .regs = &ipq8074_regs,
50 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
51 .host_ce_config = ath11k_host_ce_config_ipq8074,
52 .ce_count = 12,
53 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
54 .target_ce_count = 11,
55 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
56 .svc_to_ce_map_len = 21,
57 .rfkill_pin = 0,
58 .rfkill_cfg = 0,
59 .rfkill_on_level = 0,
60 .single_pdev_only = false,
61 .rxdma1_enable = true,
62 .num_rxmda_per_pdev = 1,
63 .rx_mac_buf_ring = false,
64 .vdev_start_delay = false,
65 .htt_peer_map_v2 = true,
66
67 .spectral = {
68 .fft_sz = 2,
69 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
70 * so added pad size as 2 bytes to compensate the BIN size
71 */
72 .fft_pad_sz = 2,
73 .summary_pad_sz = 0,
74 .fft_hdr_len = 16,
75 .max_fft_bins = 512,
76 },
77
78 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
79 BIT(NL80211_IFTYPE_AP) |
80 BIT(NL80211_IFTYPE_MESH_POINT),
81 .supports_monitor = true,
82 .full_monitor_mode = false,
83 .supports_shadow_regs = false,
84 .idle_ps = false,
85 .supports_sta_ps = false,
86 .cold_boot_calib = true,
87 .fw_mem_mode = 0,
88 .num_vdevs = 16 + 1,
89 .num_peers = 512,
90 .supports_suspend = false,
91 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
92 .supports_regdb = false,
93 .fix_l1ss = true,
94 .credit_flow = false,
95 .max_tx_ring = DP_TCL_NUM_RING_MAX,
96 .hal_params = &ath11k_hw_hal_params_ipq8074,
97 .supports_dynamic_smps_6ghz = false,
98 .alloc_cacheable_memory = true,
99 .supports_rssi_stats = false,
100 .fw_wmi_diag_event = false,
101 .current_cc_support = false,
102 .dbr_debug_support = true,
103 .global_reset = false,
104 .bios_sar_capa = NULL,
105 .m3_fw_support = false,
106 .fixed_bdf_addr = true,
107 .fixed_mem_region = true,
108 .static_window_map = false,
109 .hybrid_bus_type = false,
110 .fixed_fw_mem = false,
111 .support_off_channel_tx = false,
112 },
113 {
114 .hw_rev = ATH11K_HW_IPQ6018_HW10,
115 .name = "ipq6018 hw1.0",
116 .fw = {
117 .dir = "IPQ6018/hw1.0",
118 .board_size = 256 * 1024,
119 .cal_offset = 128 * 1024,
120 },
121 .max_radios = 2,
122 .bdf_addr = 0x4ABC0000,
123 .hw_ops = &ipq6018_ops,
124 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
125 .internal_sleep_clock = false,
126 .regs = &ipq8074_regs,
127 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
128 .host_ce_config = ath11k_host_ce_config_ipq8074,
129 .ce_count = 12,
130 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
131 .target_ce_count = 11,
132 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
133 .svc_to_ce_map_len = 19,
134 .rfkill_pin = 0,
135 .rfkill_cfg = 0,
136 .rfkill_on_level = 0,
137 .single_pdev_only = false,
138 .rxdma1_enable = true,
139 .num_rxmda_per_pdev = 1,
140 .rx_mac_buf_ring = false,
141 .vdev_start_delay = false,
142 .htt_peer_map_v2 = true,
143
144 .spectral = {
145 .fft_sz = 4,
146 .fft_pad_sz = 0,
147 .summary_pad_sz = 0,
148 .fft_hdr_len = 16,
149 .max_fft_bins = 512,
150 },
151
152 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
153 BIT(NL80211_IFTYPE_AP) |
154 BIT(NL80211_IFTYPE_MESH_POINT),
155 .supports_monitor = true,
156 .full_monitor_mode = false,
157 .supports_shadow_regs = false,
158 .idle_ps = false,
159 .supports_sta_ps = false,
160 .cold_boot_calib = true,
161 .fw_mem_mode = 0,
162 .num_vdevs = 16 + 1,
163 .num_peers = 512,
164 .supports_suspend = false,
165 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
166 .supports_regdb = false,
167 .fix_l1ss = true,
168 .credit_flow = false,
169 .max_tx_ring = DP_TCL_NUM_RING_MAX,
170 .hal_params = &ath11k_hw_hal_params_ipq8074,
171 .supports_dynamic_smps_6ghz = false,
172 .alloc_cacheable_memory = true,
173 .supports_rssi_stats = false,
174 .fw_wmi_diag_event = false,
175 .current_cc_support = false,
176 .dbr_debug_support = true,
177 .global_reset = false,
178 .bios_sar_capa = NULL,
179 .m3_fw_support = false,
180 .fixed_bdf_addr = true,
181 .fixed_mem_region = true,
182 .static_window_map = false,
183 .hybrid_bus_type = false,
184 .fixed_fw_mem = false,
185 .support_off_channel_tx = false,
186 },
187 {
188 .name = "qca6390 hw2.0",
189 .hw_rev = ATH11K_HW_QCA6390_HW20,
190 .fw = {
191 .dir = "QCA6390/hw2.0",
192 .board_size = 256 * 1024,
193 .cal_offset = 128 * 1024,
194 },
195 .max_radios = 3,
196 .bdf_addr = 0x4B0C0000,
197 .hw_ops = &qca6390_ops,
198 .ring_mask = &ath11k_hw_ring_mask_qca6390,
199 .internal_sleep_clock = true,
200 .regs = &qca6390_regs,
201 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
202 .host_ce_config = ath11k_host_ce_config_qca6390,
203 .ce_count = 9,
204 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
205 .target_ce_count = 9,
206 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
207 .svc_to_ce_map_len = 14,
208 .rfkill_pin = 48,
209 .rfkill_cfg = 0,
210 .rfkill_on_level = 1,
211 .single_pdev_only = true,
212 .rxdma1_enable = false,
213 .num_rxmda_per_pdev = 2,
214 .rx_mac_buf_ring = true,
215 .vdev_start_delay = true,
216 .htt_peer_map_v2 = false,
217
218 .spectral = {
219 .fft_sz = 0,
220 .fft_pad_sz = 0,
221 .summary_pad_sz = 0,
222 .fft_hdr_len = 0,
223 .max_fft_bins = 0,
224 },
225
226 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
227 BIT(NL80211_IFTYPE_AP),
228 .supports_monitor = false,
229 .full_monitor_mode = false,
230 .supports_shadow_regs = true,
231 .idle_ps = true,
232 .supports_sta_ps = true,
233 .cold_boot_calib = false,
234 .fw_mem_mode = 0,
235 .num_vdevs = 16 + 1,
236 .num_peers = 512,
237 .supports_suspend = true,
238 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
239 .supports_regdb = false,
240 .fix_l1ss = true,
241 .credit_flow = true,
242 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
243 .hal_params = &ath11k_hw_hal_params_qca6390,
244 .supports_dynamic_smps_6ghz = false,
245 .alloc_cacheable_memory = false,
246 .supports_rssi_stats = true,
247 .fw_wmi_diag_event = true,
248 .current_cc_support = true,
249 .dbr_debug_support = false,
250 .global_reset = true,
251 .bios_sar_capa = NULL,
252 .m3_fw_support = true,
253 .fixed_bdf_addr = false,
254 .fixed_mem_region = false,
255 .static_window_map = false,
256 .hybrid_bus_type = false,
257 .fixed_fw_mem = false,
258 .support_off_channel_tx = true,
259 },
260 {
261 .name = "qcn9074 hw1.0",
262 .hw_rev = ATH11K_HW_QCN9074_HW10,
263 .fw = {
264 .dir = "QCN9074/hw1.0",
265 .board_size = 256 * 1024,
266 .cal_offset = 128 * 1024,
267 },
268 .max_radios = 1,
269 .single_pdev_only = false,
270 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
271 .hw_ops = &qcn9074_ops,
272 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
273 .internal_sleep_clock = false,
274 .regs = &qcn9074_regs,
275 .host_ce_config = ath11k_host_ce_config_qcn9074,
276 .ce_count = 6,
277 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
278 .target_ce_count = 9,
279 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
280 .svc_to_ce_map_len = 18,
281 .rfkill_pin = 0,
282 .rfkill_cfg = 0,
283 .rfkill_on_level = 0,
284 .rxdma1_enable = true,
285 .num_rxmda_per_pdev = 1,
286 .rx_mac_buf_ring = false,
287 .vdev_start_delay = false,
288 .htt_peer_map_v2 = true,
289
290 .spectral = {
291 .fft_sz = 2,
292 .fft_pad_sz = 0,
293 .summary_pad_sz = 16,
294 .fft_hdr_len = 24,
295 .max_fft_bins = 1024,
296 },
297
298 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
299 BIT(NL80211_IFTYPE_AP) |
300 BIT(NL80211_IFTYPE_MESH_POINT),
301 .supports_monitor = true,
302 .full_monitor_mode = true,
303 .supports_shadow_regs = false,
304 .idle_ps = false,
305 .supports_sta_ps = false,
306 .cold_boot_calib = false,
307 .fw_mem_mode = 2,
308 .num_vdevs = 8,
309 .num_peers = 128,
310 .supports_suspend = false,
311 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
312 .supports_regdb = false,
313 .fix_l1ss = true,
314 .credit_flow = false,
315 .max_tx_ring = DP_TCL_NUM_RING_MAX,
316 .hal_params = &ath11k_hw_hal_params_ipq8074,
317 .supports_dynamic_smps_6ghz = true,
318 .alloc_cacheable_memory = true,
319 .supports_rssi_stats = false,
320 .fw_wmi_diag_event = false,
321 .current_cc_support = false,
322 .dbr_debug_support = true,
323 .global_reset = false,
324 .bios_sar_capa = NULL,
325 .m3_fw_support = true,
326 .fixed_bdf_addr = false,
327 .fixed_mem_region = false,
328 .static_window_map = true,
329 .hybrid_bus_type = false,
330 .fixed_fw_mem = false,
331 .support_off_channel_tx = false,
332 },
333 {
334 .name = "wcn6855 hw2.0",
335 .hw_rev = ATH11K_HW_WCN6855_HW20,
336 .fw = {
337 .dir = "WCN6855/hw2.0",
338 .board_size = 256 * 1024,
339 .cal_offset = 128 * 1024,
340 },
341 .max_radios = 3,
342 .bdf_addr = 0x4B0C0000,
343 .hw_ops = &wcn6855_ops,
344 .ring_mask = &ath11k_hw_ring_mask_qca6390,
345 .internal_sleep_clock = true,
346 .regs = &wcn6855_regs,
347 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
348 .host_ce_config = ath11k_host_ce_config_qca6390,
349 .ce_count = 9,
350 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
351 .target_ce_count = 9,
352 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
353 .svc_to_ce_map_len = 14,
354 .rfkill_pin = 0,
355 .rfkill_cfg = 0,
356 .rfkill_on_level = 0,
357 .single_pdev_only = true,
358 .rxdma1_enable = false,
359 .num_rxmda_per_pdev = 2,
360 .rx_mac_buf_ring = true,
361 .vdev_start_delay = true,
362 .htt_peer_map_v2 = false,
363
364 .spectral = {
365 .fft_sz = 0,
366 .fft_pad_sz = 0,
367 .summary_pad_sz = 0,
368 .fft_hdr_len = 0,
369 .max_fft_bins = 0,
370 },
371
372 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
373 BIT(NL80211_IFTYPE_AP),
374 .supports_monitor = false,
375 .full_monitor_mode = false,
376 .supports_shadow_regs = true,
377 .idle_ps = true,
378 .supports_sta_ps = true,
379 .cold_boot_calib = false,
380 .fw_mem_mode = 0,
381 .num_vdevs = 16 + 1,
382 .num_peers = 512,
383 .supports_suspend = true,
384 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
385 .supports_regdb = true,
386 .fix_l1ss = false,
387 .credit_flow = true,
388 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
389 .hal_params = &ath11k_hw_hal_params_qca6390,
390 .supports_dynamic_smps_6ghz = false,
391 .alloc_cacheable_memory = false,
392 .supports_rssi_stats = true,
393 .fw_wmi_diag_event = true,
394 .current_cc_support = true,
395 .dbr_debug_support = false,
396 .global_reset = true,
397 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
398 .m3_fw_support = true,
399 .fixed_bdf_addr = false,
400 .fixed_mem_region = false,
401 .static_window_map = false,
402 .hybrid_bus_type = false,
403 .fixed_fw_mem = false,
404 .support_off_channel_tx = true,
405 },
406 {
407 .name = "wcn6855 hw2.1",
408 .hw_rev = ATH11K_HW_WCN6855_HW21,
409 .fw = {
410 .dir = "WCN6855/hw2.1",
411 .board_size = 256 * 1024,
412 .cal_offset = 128 * 1024,
413 },
414 .max_radios = 3,
415 .bdf_addr = 0x4B0C0000,
416 .hw_ops = &wcn6855_ops,
417 .ring_mask = &ath11k_hw_ring_mask_qca6390,
418 .internal_sleep_clock = true,
419 .regs = &wcn6855_regs,
420 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
421 .host_ce_config = ath11k_host_ce_config_qca6390,
422 .ce_count = 9,
423 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
424 .target_ce_count = 9,
425 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
426 .svc_to_ce_map_len = 14,
427 .rfkill_pin = 0,
428 .rfkill_cfg = 0,
429 .rfkill_on_level = 0,
430 .single_pdev_only = true,
431 .rxdma1_enable = false,
432 .num_rxmda_per_pdev = 2,
433 .rx_mac_buf_ring = true,
434 .vdev_start_delay = true,
435 .htt_peer_map_v2 = false,
436
437 .spectral = {
438 .fft_sz = 0,
439 .fft_pad_sz = 0,
440 .summary_pad_sz = 0,
441 .fft_hdr_len = 0,
442 .max_fft_bins = 0,
443 },
444
445 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
446 BIT(NL80211_IFTYPE_AP),
447 .supports_monitor = false,
448 .supports_shadow_regs = true,
449 .idle_ps = true,
450 .supports_sta_ps = true,
451 .cold_boot_calib = false,
452 .fw_mem_mode = 0,
453 .num_vdevs = 16 + 1,
454 .num_peers = 512,
455 .supports_suspend = true,
456 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
457 .supports_regdb = true,
458 .fix_l1ss = false,
459 .credit_flow = true,
460 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
461 .hal_params = &ath11k_hw_hal_params_qca6390,
462 .supports_dynamic_smps_6ghz = false,
463 .alloc_cacheable_memory = false,
464 .supports_rssi_stats = true,
465 .fw_wmi_diag_event = true,
466 .current_cc_support = true,
467 .dbr_debug_support = false,
468 .global_reset = true,
469 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
470 .m3_fw_support = true,
471 .fixed_bdf_addr = false,
472 .fixed_mem_region = false,
473 .static_window_map = false,
474 .hybrid_bus_type = false,
475 .fixed_fw_mem = false,
476 .support_off_channel_tx = true,
477 },
478 {
479 .name = "wcn6750 hw1.0",
480 .hw_rev = ATH11K_HW_WCN6750_HW10,
481 .fw = {
482 .dir = "WCN6750/hw1.0",
483 .board_size = 256 * 1024,
484 .cal_offset = 128 * 1024,
485 },
486 .max_radios = 1,
487 .bdf_addr = 0x4B0C0000,
488 .hw_ops = &wcn6750_ops,
489 .ring_mask = &ath11k_hw_ring_mask_qca6390,
490 .internal_sleep_clock = false,
491 .regs = &wcn6750_regs,
492 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
493 .host_ce_config = ath11k_host_ce_config_qca6390,
494 .ce_count = 9,
495 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
496 .target_ce_count = 9,
497 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
498 .svc_to_ce_map_len = 14,
499 .rfkill_pin = 0,
500 .rfkill_cfg = 0,
501 .rfkill_on_level = 0,
502 .single_pdev_only = true,
503 .rxdma1_enable = false,
504 .num_rxmda_per_pdev = 1,
505 .rx_mac_buf_ring = true,
506 .vdev_start_delay = true,
507 .htt_peer_map_v2 = false,
508
509 .spectral = {
510 .fft_sz = 0,
511 .fft_pad_sz = 0,
512 .summary_pad_sz = 0,
513 .fft_hdr_len = 0,
514 .max_fft_bins = 0,
515 },
516
517 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
518 BIT(NL80211_IFTYPE_AP),
519 .supports_monitor = false,
520 .supports_shadow_regs = true,
521 .idle_ps = true,
522 .supports_sta_ps = true,
523 .cold_boot_calib = false,
524 .fw_mem_mode = 0,
525 .num_vdevs = 16 + 1,
526 .num_peers = 512,
527 .supports_suspend = false,
528 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
529 .supports_regdb = true,
530 .fix_l1ss = false,
531 .credit_flow = true,
532 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
533 .hal_params = &ath11k_hw_hal_params_qca6390,
534 .supports_dynamic_smps_6ghz = false,
535 .alloc_cacheable_memory = false,
536 .supports_rssi_stats = true,
537 .fw_wmi_diag_event = false,
538 .current_cc_support = true,
539 .dbr_debug_support = false,
540 .global_reset = false,
541 .bios_sar_capa = NULL,
542 .m3_fw_support = false,
543 .fixed_bdf_addr = false,
544 .fixed_mem_region = false,
545 .static_window_map = true,
546 .hybrid_bus_type = true,
547 .fixed_fw_mem = true,
548 .support_off_channel_tx = false,
549 },
550 };
551
ath11k_core_get_single_pdev(struct ath11k_base * ab)552 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
553 {
554 WARN_ON(!ab->hw_params.single_pdev_only);
555
556 return &ab->pdevs[0];
557 }
558
ath11k_core_suspend(struct ath11k_base * ab)559 int ath11k_core_suspend(struct ath11k_base *ab)
560 {
561 int ret;
562 struct ath11k_pdev *pdev;
563 struct ath11k *ar;
564
565 if (!ab->hw_params.supports_suspend)
566 return -EOPNOTSUPP;
567
568 /* so far single_pdev_only chips have supports_suspend as true
569 * and only the first pdev is valid.
570 */
571 pdev = ath11k_core_get_single_pdev(ab);
572 ar = pdev->ar;
573 if (!ar || ar->state != ATH11K_STATE_OFF)
574 return 0;
575
576 ret = ath11k_dp_rx_pktlog_stop(ab, true);
577 if (ret) {
578 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
579 ret);
580 return ret;
581 }
582
583 ret = ath11k_mac_wait_tx_complete(ar);
584 if (ret) {
585 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
586 return ret;
587 }
588
589 ret = ath11k_wow_enable(ab);
590 if (ret) {
591 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
592 return ret;
593 }
594
595 ret = ath11k_dp_rx_pktlog_stop(ab, false);
596 if (ret) {
597 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
598 ret);
599 return ret;
600 }
601
602 ath11k_ce_stop_shadow_timers(ab);
603 ath11k_dp_stop_shadow_timers(ab);
604
605 ath11k_hif_irq_disable(ab);
606 ath11k_hif_ce_irq_disable(ab);
607
608 ret = ath11k_hif_suspend(ab);
609 if (ret) {
610 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
611 return ret;
612 }
613
614 return 0;
615 }
616 EXPORT_SYMBOL(ath11k_core_suspend);
617
ath11k_core_resume(struct ath11k_base * ab)618 int ath11k_core_resume(struct ath11k_base *ab)
619 {
620 int ret;
621 struct ath11k_pdev *pdev;
622 struct ath11k *ar;
623
624 if (!ab->hw_params.supports_suspend)
625 return -EOPNOTSUPP;
626
627 /* so far signle_pdev_only chips have supports_suspend as true
628 * and only the first pdev is valid.
629 */
630 pdev = ath11k_core_get_single_pdev(ab);
631 ar = pdev->ar;
632 if (!ar || ar->state != ATH11K_STATE_OFF)
633 return 0;
634
635 ret = ath11k_hif_resume(ab);
636 if (ret) {
637 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
638 return ret;
639 }
640
641 ath11k_hif_ce_irq_enable(ab);
642 ath11k_hif_irq_enable(ab);
643
644 ret = ath11k_dp_rx_pktlog_start(ab);
645 if (ret) {
646 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
647 ret);
648 return ret;
649 }
650
651 ret = ath11k_wow_wakeup(ab);
652 if (ret) {
653 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
654 return ret;
655 }
656
657 return 0;
658 }
659 EXPORT_SYMBOL(ath11k_core_resume);
660
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)661 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
662 {
663 struct ath11k_base *ab = data;
664 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
665 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
666 ssize_t copied;
667 size_t len;
668 int i;
669
670 if (ab->qmi.target.bdf_ext[0] != '\0')
671 return;
672
673 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
674 return;
675
676 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
677 ath11k_dbg(ab, ATH11K_DBG_BOOT,
678 "wrong smbios bdf ext type length (%d).\n",
679 hdr->length);
680 return;
681 }
682
683 spin_lock_bh(&ab->base_lock);
684
685 switch (smbios->country_code_flag) {
686 case ATH11K_SMBIOS_CC_ISO:
687 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
688 ab->new_alpha2[1] = smbios->cc_code & 0xff;
689 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios cc_code %c%c\n",
690 ab->new_alpha2[0], ab->new_alpha2[1]);
691 break;
692 case ATH11K_SMBIOS_CC_WW:
693 ab->new_alpha2[0] = '0';
694 ab->new_alpha2[1] = '0';
695 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios worldwide regdomain\n");
696 break;
697 default:
698 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot ignore smbios country code setting %d\n",
699 smbios->country_code_flag);
700 break;
701 }
702
703 spin_unlock_bh(&ab->base_lock);
704
705 if (!smbios->bdf_enabled) {
706 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
707 return;
708 }
709
710 /* Only one string exists (per spec) */
711 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
712 ath11k_dbg(ab, ATH11K_DBG_BOOT,
713 "bdf variant magic does not match.\n");
714 return;
715 }
716
717 len = min_t(size_t,
718 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
719 for (i = 0; i < len; i++) {
720 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
721 ath11k_dbg(ab, ATH11K_DBG_BOOT,
722 "bdf variant name contains non ascii chars.\n");
723 return;
724 }
725 }
726
727 /* Copy extension name without magic prefix */
728 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
729 sizeof(ab->qmi.target.bdf_ext));
730 if (copied < 0) {
731 ath11k_dbg(ab, ATH11K_DBG_BOOT,
732 "bdf variant string is longer than the buffer can accommodate\n");
733 return;
734 }
735
736 ath11k_dbg(ab, ATH11K_DBG_BOOT,
737 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
738 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
739 }
740
ath11k_core_check_smbios(struct ath11k_base * ab)741 int ath11k_core_check_smbios(struct ath11k_base *ab)
742 {
743 ab->qmi.target.bdf_ext[0] = '\0';
744 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
745
746 if (ab->qmi.target.bdf_ext[0] == '\0')
747 return -ENODATA;
748
749 return 0;
750 }
751
ath11k_core_check_dt(struct ath11k_base * ab)752 int ath11k_core_check_dt(struct ath11k_base *ab)
753 {
754 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
755 const char *variant = NULL;
756 struct device_node *node;
757
758 node = ab->dev->of_node;
759 if (!node)
760 return -ENOENT;
761
762 of_property_read_string(node, "qcom,ath11k-calibration-variant",
763 &variant);
764 if (!variant)
765 return -ENODATA;
766
767 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
768 ath11k_dbg(ab, ATH11K_DBG_BOOT,
769 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
770 variant);
771
772 return 0;
773 }
774
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant)775 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
776 size_t name_len, bool with_variant)
777 {
778 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
779 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
780
781 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
782 scnprintf(variant, sizeof(variant), ",variant=%s",
783 ab->qmi.target.bdf_ext);
784
785 switch (ab->id.bdf_search) {
786 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
787 scnprintf(name, name_len,
788 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
789 ath11k_bus_str(ab->hif.bus),
790 ab->id.vendor, ab->id.device,
791 ab->id.subsystem_vendor,
792 ab->id.subsystem_device,
793 ab->qmi.target.chip_id,
794 ab->qmi.target.board_id,
795 variant);
796 break;
797 default:
798 scnprintf(name, name_len,
799 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
800 ath11k_bus_str(ab->hif.bus),
801 ab->qmi.target.chip_id,
802 ab->qmi.target.board_id, variant);
803 break;
804 }
805
806 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot using board name '%s'\n", name);
807
808 return 0;
809 }
810
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)811 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
812 size_t name_len)
813 {
814 return __ath11k_core_create_board_name(ab, name, name_len, true);
815 }
816
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)817 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
818 size_t name_len)
819 {
820 return __ath11k_core_create_board_name(ab, name, name_len, false);
821 }
822
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)823 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
824 const char *file)
825 {
826 const struct firmware *fw;
827 char path[100];
828 int ret;
829
830 if (file == NULL)
831 return ERR_PTR(-ENOENT);
832
833 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
834
835 ret = firmware_request_nowarn(&fw, path, ab->dev);
836 if (ret)
837 return ERR_PTR(ret);
838
839 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot firmware request %s size %zu\n",
840 path, fw->size);
841
842 return fw;
843 }
844
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)845 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
846 {
847 if (!IS_ERR(bd->fw))
848 release_firmware(bd->fw);
849
850 memset(bd, 0, sizeof(*bd));
851 }
852
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)853 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
854 struct ath11k_board_data *bd,
855 const void *buf, size_t buf_len,
856 const char *boardname,
857 int ie_id,
858 int name_id,
859 int data_id)
860 {
861 const struct ath11k_fw_ie *hdr;
862 bool name_match_found;
863 int ret, board_ie_id;
864 size_t board_ie_len;
865 const void *board_ie_data;
866
867 name_match_found = false;
868
869 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
870 while (buf_len > sizeof(struct ath11k_fw_ie)) {
871 hdr = buf;
872 board_ie_id = le32_to_cpu(hdr->id);
873 board_ie_len = le32_to_cpu(hdr->len);
874 board_ie_data = hdr->data;
875
876 buf_len -= sizeof(*hdr);
877 buf += sizeof(*hdr);
878
879 if (buf_len < ALIGN(board_ie_len, 4)) {
880 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
881 ath11k_bd_ie_type_str(ie_id),
882 buf_len, ALIGN(board_ie_len, 4));
883 ret = -EINVAL;
884 goto out;
885 }
886
887 if (board_ie_id == name_id) {
888 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
889 board_ie_data, board_ie_len);
890
891 if (board_ie_len != strlen(boardname))
892 goto next;
893
894 ret = memcmp(board_ie_data, boardname, strlen(boardname));
895 if (ret)
896 goto next;
897
898 name_match_found = true;
899 ath11k_dbg(ab, ATH11K_DBG_BOOT,
900 "boot found match %s for name '%s'",
901 ath11k_bd_ie_type_str(ie_id),
902 boardname);
903 } else if (board_ie_id == data_id) {
904 if (!name_match_found)
905 /* no match found */
906 goto next;
907
908 ath11k_dbg(ab, ATH11K_DBG_BOOT,
909 "boot found %s for '%s'",
910 ath11k_bd_ie_type_str(ie_id),
911 boardname);
912
913 bd->data = board_ie_data;
914 bd->len = board_ie_len;
915
916 ret = 0;
917 goto out;
918 } else {
919 ath11k_warn(ab, "unknown %s id found: %d\n",
920 ath11k_bd_ie_type_str(ie_id),
921 board_ie_id);
922 }
923 next:
924 /* jump over the padding */
925 board_ie_len = ALIGN(board_ie_len, 4);
926
927 buf_len -= board_ie_len;
928 buf += board_ie_len;
929 }
930
931 /* no match found */
932 ret = -ENOENT;
933
934 out:
935 return ret;
936 }
937
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)938 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
939 struct ath11k_board_data *bd,
940 const char *boardname,
941 int ie_id_match,
942 int name_id,
943 int data_id)
944 {
945 size_t len, magic_len;
946 const u8 *data;
947 char *filename, filepath[100];
948 size_t ie_len;
949 struct ath11k_fw_ie *hdr;
950 int ret, ie_id;
951
952 filename = ATH11K_BOARD_API2_FILE;
953
954 if (!bd->fw)
955 bd->fw = ath11k_core_firmware_request(ab, filename);
956
957 if (IS_ERR(bd->fw))
958 return PTR_ERR(bd->fw);
959
960 data = bd->fw->data;
961 len = bd->fw->size;
962
963 ath11k_core_create_firmware_path(ab, filename,
964 filepath, sizeof(filepath));
965
966 /* magic has extra null byte padded */
967 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
968 if (len < magic_len) {
969 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
970 filepath, len);
971 ret = -EINVAL;
972 goto err;
973 }
974
975 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
976 ath11k_err(ab, "found invalid board magic\n");
977 ret = -EINVAL;
978 goto err;
979 }
980
981 /* magic is padded to 4 bytes */
982 magic_len = ALIGN(magic_len, 4);
983 if (len < magic_len) {
984 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
985 filepath, len);
986 ret = -EINVAL;
987 goto err;
988 }
989
990 data += magic_len;
991 len -= magic_len;
992
993 while (len > sizeof(struct ath11k_fw_ie)) {
994 hdr = (struct ath11k_fw_ie *)data;
995 ie_id = le32_to_cpu(hdr->id);
996 ie_len = le32_to_cpu(hdr->len);
997
998 len -= sizeof(*hdr);
999 data = hdr->data;
1000
1001 if (len < ALIGN(ie_len, 4)) {
1002 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1003 ie_id, ie_len, len);
1004 ret = -EINVAL;
1005 goto err;
1006 }
1007
1008 if (ie_id == ie_id_match) {
1009 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1010 ie_len,
1011 boardname,
1012 ie_id_match,
1013 name_id,
1014 data_id);
1015 if (ret == -ENOENT)
1016 /* no match found, continue */
1017 goto next;
1018 else if (ret)
1019 /* there was an error, bail out */
1020 goto err;
1021 /* either found or error, so stop searching */
1022 goto out;
1023 }
1024 next:
1025 /* jump over the padding */
1026 ie_len = ALIGN(ie_len, 4);
1027
1028 len -= ie_len;
1029 data += ie_len;
1030 }
1031
1032 out:
1033 if (!bd->data || !bd->len) {
1034 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1035 "failed to fetch %s for %s from %s\n",
1036 ath11k_bd_ie_type_str(ie_id_match),
1037 boardname, filepath);
1038 ret = -ENODATA;
1039 goto err;
1040 }
1041
1042 return 0;
1043
1044 err:
1045 ath11k_core_free_bdf(ab, bd);
1046 return ret;
1047 }
1048
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1049 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1050 struct ath11k_board_data *bd,
1051 const char *name)
1052 {
1053 bd->fw = ath11k_core_firmware_request(ab, name);
1054
1055 if (IS_ERR(bd->fw))
1056 return PTR_ERR(bd->fw);
1057
1058 bd->data = bd->fw->data;
1059 bd->len = bd->fw->size;
1060
1061 return 0;
1062 }
1063
1064 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1065 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1066 {
1067 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE];
1068 char *filename, filepath[100];
1069 int ret;
1070
1071 filename = ATH11K_BOARD_API2_FILE;
1072
1073 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname));
1074 if (ret) {
1075 ath11k_err(ab, "failed to create board name: %d", ret);
1076 return ret;
1077 }
1078
1079 ab->bd_api = 2;
1080 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1081 ATH11K_BD_IE_BOARD,
1082 ATH11K_BD_IE_BOARD_NAME,
1083 ATH11K_BD_IE_BOARD_DATA);
1084 if (!ret)
1085 goto success;
1086
1087 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1088 sizeof(fallback_boardname));
1089 if (ret) {
1090 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1091 return ret;
1092 }
1093
1094 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1095 ATH11K_BD_IE_BOARD,
1096 ATH11K_BD_IE_BOARD_NAME,
1097 ATH11K_BD_IE_BOARD_DATA);
1098 if (!ret)
1099 goto success;
1100
1101 ab->bd_api = 1;
1102 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1103 if (ret) {
1104 ath11k_core_create_firmware_path(ab, filename,
1105 filepath, sizeof(filepath));
1106 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1107 boardname, filepath);
1108 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1109 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1110 fallback_boardname, filepath);
1111
1112 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1113 ab->hw_params.fw.dir);
1114 return ret;
1115 }
1116
1117 success:
1118 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api);
1119 return 0;
1120 }
1121
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1122 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1123 {
1124 char boardname[BOARD_NAME_SIZE];
1125 int ret;
1126
1127 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1128 if (ret) {
1129 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1130 "failed to create board name for regdb: %d", ret);
1131 goto exit;
1132 }
1133
1134 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1135 ATH11K_BD_IE_REGDB,
1136 ATH11K_BD_IE_REGDB_NAME,
1137 ATH11K_BD_IE_REGDB_DATA);
1138 if (!ret)
1139 goto exit;
1140
1141 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1142 if (ret)
1143 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1144 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1145
1146 exit:
1147 if (!ret)
1148 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1149
1150 return ret;
1151 }
1152
ath11k_core_stop(struct ath11k_base * ab)1153 static void ath11k_core_stop(struct ath11k_base *ab)
1154 {
1155 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1156 ath11k_qmi_firmware_stop(ab);
1157
1158 ath11k_hif_stop(ab);
1159 ath11k_wmi_detach(ab);
1160 ath11k_dp_pdev_reo_cleanup(ab);
1161
1162 /* De-Init of components as needed */
1163 }
1164
ath11k_core_soc_create(struct ath11k_base * ab)1165 static int ath11k_core_soc_create(struct ath11k_base *ab)
1166 {
1167 int ret;
1168
1169 ret = ath11k_qmi_init_service(ab);
1170 if (ret) {
1171 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1172 return ret;
1173 }
1174
1175 ret = ath11k_debugfs_soc_create(ab);
1176 if (ret) {
1177 ath11k_err(ab, "failed to create ath11k debugfs\n");
1178 goto err_qmi_deinit;
1179 }
1180
1181 ret = ath11k_hif_power_up(ab);
1182 if (ret) {
1183 ath11k_err(ab, "failed to power up :%d\n", ret);
1184 goto err_debugfs_reg;
1185 }
1186
1187 return 0;
1188
1189 err_debugfs_reg:
1190 ath11k_debugfs_soc_destroy(ab);
1191 err_qmi_deinit:
1192 ath11k_qmi_deinit_service(ab);
1193 return ret;
1194 }
1195
ath11k_core_soc_destroy(struct ath11k_base * ab)1196 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1197 {
1198 ath11k_debugfs_soc_destroy(ab);
1199 ath11k_dp_free(ab);
1200 ath11k_reg_free(ab);
1201 ath11k_qmi_deinit_service(ab);
1202 }
1203
ath11k_core_pdev_create(struct ath11k_base * ab)1204 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1205 {
1206 int ret;
1207
1208 ret = ath11k_debugfs_pdev_create(ab);
1209 if (ret) {
1210 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1211 return ret;
1212 }
1213
1214 ret = ath11k_dp_pdev_alloc(ab);
1215 if (ret) {
1216 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1217 goto err_pdev_debug;
1218 }
1219
1220 ret = ath11k_mac_register(ab);
1221 if (ret) {
1222 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1223 goto err_dp_pdev_free;
1224 }
1225
1226 ret = ath11k_thermal_register(ab);
1227 if (ret) {
1228 ath11k_err(ab, "could not register thermal device: %d\n",
1229 ret);
1230 goto err_mac_unregister;
1231 }
1232
1233 ret = ath11k_spectral_init(ab);
1234 if (ret) {
1235 ath11k_err(ab, "failed to init spectral %d\n", ret);
1236 goto err_thermal_unregister;
1237 }
1238
1239 return 0;
1240
1241 err_thermal_unregister:
1242 ath11k_thermal_unregister(ab);
1243 err_mac_unregister:
1244 ath11k_mac_unregister(ab);
1245 err_dp_pdev_free:
1246 ath11k_dp_pdev_free(ab);
1247 err_pdev_debug:
1248 ath11k_debugfs_pdev_destroy(ab);
1249
1250 return ret;
1251 }
1252
ath11k_core_pdev_destroy(struct ath11k_base * ab)1253 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1254 {
1255 ath11k_spectral_deinit(ab);
1256 ath11k_thermal_unregister(ab);
1257 ath11k_mac_unregister(ab);
1258 ath11k_hif_irq_disable(ab);
1259 ath11k_dp_pdev_free(ab);
1260 ath11k_debugfs_pdev_destroy(ab);
1261 }
1262
ath11k_core_start(struct ath11k_base * ab)1263 static int ath11k_core_start(struct ath11k_base *ab)
1264 {
1265 int ret;
1266
1267 ret = ath11k_wmi_attach(ab);
1268 if (ret) {
1269 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1270 return ret;
1271 }
1272
1273 ret = ath11k_htc_init(ab);
1274 if (ret) {
1275 ath11k_err(ab, "failed to init htc: %d\n", ret);
1276 goto err_wmi_detach;
1277 }
1278
1279 ret = ath11k_hif_start(ab);
1280 if (ret) {
1281 ath11k_err(ab, "failed to start HIF: %d\n", ret);
1282 goto err_wmi_detach;
1283 }
1284
1285 ret = ath11k_htc_wait_target(&ab->htc);
1286 if (ret) {
1287 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1288 goto err_hif_stop;
1289 }
1290
1291 ret = ath11k_dp_htt_connect(&ab->dp);
1292 if (ret) {
1293 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1294 goto err_hif_stop;
1295 }
1296
1297 ret = ath11k_wmi_connect(ab);
1298 if (ret) {
1299 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1300 goto err_hif_stop;
1301 }
1302
1303 ret = ath11k_htc_start(&ab->htc);
1304 if (ret) {
1305 ath11k_err(ab, "failed to start HTC: %d\n", ret);
1306 goto err_hif_stop;
1307 }
1308
1309 ret = ath11k_wmi_wait_for_service_ready(ab);
1310 if (ret) {
1311 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1312 ret);
1313 goto err_hif_stop;
1314 }
1315
1316 ret = ath11k_mac_allocate(ab);
1317 if (ret) {
1318 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1319 ret);
1320 goto err_hif_stop;
1321 }
1322
1323 ath11k_dp_pdev_pre_alloc(ab);
1324
1325 ret = ath11k_dp_pdev_reo_setup(ab);
1326 if (ret) {
1327 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1328 goto err_mac_destroy;
1329 }
1330
1331 ret = ath11k_wmi_cmd_init(ab);
1332 if (ret) {
1333 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1334 goto err_reo_cleanup;
1335 }
1336
1337 ret = ath11k_wmi_wait_for_unified_ready(ab);
1338 if (ret) {
1339 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1340 ret);
1341 goto err_reo_cleanup;
1342 }
1343
1344 /* put hardware to DBS mode */
1345 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) {
1346 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1347 if (ret) {
1348 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1349 goto err_hif_stop;
1350 }
1351 }
1352
1353 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1354 if (ret) {
1355 ath11k_err(ab, "failed to send htt version request message: %d\n",
1356 ret);
1357 goto err_reo_cleanup;
1358 }
1359
1360 return 0;
1361
1362 err_reo_cleanup:
1363 ath11k_dp_pdev_reo_cleanup(ab);
1364 err_mac_destroy:
1365 ath11k_mac_destroy(ab);
1366 err_hif_stop:
1367 ath11k_hif_stop(ab);
1368 err_wmi_detach:
1369 ath11k_wmi_detach(ab);
1370
1371 return ret;
1372 }
1373
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1374 static int ath11k_core_start_firmware(struct ath11k_base *ab,
1375 enum ath11k_firmware_mode mode)
1376 {
1377 int ret;
1378
1379 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1380 &ab->qmi.ce_cfg.shadow_reg_v2_len);
1381
1382 ret = ath11k_qmi_firmware_start(ab, mode);
1383 if (ret) {
1384 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1385 return ret;
1386 }
1387
1388 return ret;
1389 }
1390
ath11k_core_rfkill_config(struct ath11k_base * ab)1391 static int ath11k_core_rfkill_config(struct ath11k_base *ab)
1392 {
1393 struct ath11k *ar;
1394 int ret = 0, i;
1395
1396 if (!(ab->target_caps.sys_cap_info & WMI_SYS_CAP_INFO_RFKILL))
1397 return 0;
1398
1399 for (i = 0; i < ab->num_radios; i++) {
1400 ar = ab->pdevs[i].ar;
1401
1402 ret = ath11k_mac_rfkill_config(ar);
1403 if (ret && ret != -EOPNOTSUPP) {
1404 ath11k_warn(ab, "failed to configure rfkill: %d", ret);
1405 return ret;
1406 }
1407 }
1408
1409 return ret;
1410 }
1411
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1412 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1413 {
1414 int ret;
1415
1416 ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL);
1417 if (ret) {
1418 ath11k_err(ab, "failed to start firmware: %d\n", ret);
1419 return ret;
1420 }
1421
1422 ret = ath11k_ce_init_pipes(ab);
1423 if (ret) {
1424 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1425 goto err_firmware_stop;
1426 }
1427
1428 ret = ath11k_dp_alloc(ab);
1429 if (ret) {
1430 ath11k_err(ab, "failed to init DP: %d\n", ret);
1431 goto err_firmware_stop;
1432 }
1433
1434 switch (ath11k_crypto_mode) {
1435 case ATH11K_CRYPT_MODE_SW:
1436 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1437 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1438 break;
1439 case ATH11K_CRYPT_MODE_HW:
1440 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1441 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1442 break;
1443 default:
1444 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1445 return -EINVAL;
1446 }
1447
1448 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1449 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1450
1451 mutex_lock(&ab->core_lock);
1452 ret = ath11k_core_start(ab);
1453 if (ret) {
1454 ath11k_err(ab, "failed to start core: %d\n", ret);
1455 goto err_dp_free;
1456 }
1457
1458 ret = ath11k_core_pdev_create(ab);
1459 if (ret) {
1460 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1461 goto err_core_stop;
1462 }
1463 ath11k_hif_irq_enable(ab);
1464
1465 ret = ath11k_core_rfkill_config(ab);
1466 if (ret && ret != -EOPNOTSUPP) {
1467 ath11k_err(ab, "failed to config rfkill: %d\n", ret);
1468 goto err_core_stop;
1469 }
1470
1471 mutex_unlock(&ab->core_lock);
1472
1473 return 0;
1474
1475 err_core_stop:
1476 ath11k_core_stop(ab);
1477 ath11k_mac_destroy(ab);
1478 err_dp_free:
1479 ath11k_dp_free(ab);
1480 mutex_unlock(&ab->core_lock);
1481 err_firmware_stop:
1482 ath11k_qmi_firmware_stop(ab);
1483
1484 return ret;
1485 }
1486
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)1487 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
1488 {
1489 int ret;
1490
1491 mutex_lock(&ab->core_lock);
1492 ath11k_thermal_unregister(ab);
1493 ath11k_hif_irq_disable(ab);
1494 ath11k_dp_pdev_free(ab);
1495 ath11k_spectral_deinit(ab);
1496 ath11k_hif_stop(ab);
1497 ath11k_wmi_detach(ab);
1498 ath11k_dp_pdev_reo_cleanup(ab);
1499 mutex_unlock(&ab->core_lock);
1500
1501 ath11k_dp_free(ab);
1502 ath11k_hal_srng_deinit(ab);
1503
1504 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
1505
1506 ret = ath11k_hal_srng_init(ab);
1507 if (ret)
1508 return ret;
1509
1510 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
1511
1512 ret = ath11k_core_qmi_firmware_ready(ab);
1513 if (ret)
1514 goto err_hal_srng_deinit;
1515
1516 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
1517
1518 return 0;
1519
1520 err_hal_srng_deinit:
1521 ath11k_hal_srng_deinit(ab);
1522 return ret;
1523 }
1524
ath11k_core_halt(struct ath11k * ar)1525 void ath11k_core_halt(struct ath11k *ar)
1526 {
1527 struct ath11k_base *ab = ar->ab;
1528
1529 lockdep_assert_held(&ar->conf_mutex);
1530
1531 ar->num_created_vdevs = 0;
1532 ar->allocated_vdev_map = 0;
1533
1534 ath11k_mac_scan_finish(ar);
1535 ath11k_mac_peer_cleanup_all(ar);
1536 cancel_delayed_work_sync(&ar->scan.timeout);
1537 cancel_work_sync(&ar->regd_update_work);
1538 cancel_work_sync(&ab->update_11d_work);
1539 cancel_work_sync(&ab->rfkill_work);
1540
1541 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
1542 synchronize_rcu();
1543 INIT_LIST_HEAD(&ar->arvifs);
1544 idr_init(&ar->txmgmt_idr);
1545 }
1546
ath11k_rfkill_work(struct work_struct * work)1547 static void ath11k_rfkill_work(struct work_struct *work)
1548 {
1549 struct ath11k_base *ab = container_of(work, struct ath11k_base, rfkill_work);
1550 struct ath11k *ar;
1551 bool rfkill_radio_on;
1552 int i;
1553
1554 spin_lock_bh(&ab->base_lock);
1555 rfkill_radio_on = ab->rfkill_radio_on;
1556 spin_unlock_bh(&ab->base_lock);
1557
1558 for (i = 0; i < ab->num_radios; i++) {
1559 ar = ab->pdevs[i].ar;
1560 if (!ar)
1561 continue;
1562
1563 /* notify cfg80211 radio state change */
1564 ath11k_mac_rfkill_enable_radio(ar, rfkill_radio_on);
1565 wiphy_rfkill_set_hw_state(ar->hw->wiphy, !rfkill_radio_on);
1566 }
1567 }
1568
ath11k_update_11d(struct work_struct * work)1569 static void ath11k_update_11d(struct work_struct *work)
1570 {
1571 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
1572 struct ath11k *ar;
1573 struct ath11k_pdev *pdev;
1574 struct wmi_set_current_country_params set_current_param = {};
1575 int ret, i;
1576
1577 spin_lock_bh(&ab->base_lock);
1578 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2);
1579 spin_unlock_bh(&ab->base_lock);
1580
1581 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n",
1582 set_current_param.alpha2[0],
1583 set_current_param.alpha2[1]);
1584
1585 for (i = 0; i < ab->num_radios; i++) {
1586 pdev = &ab->pdevs[i];
1587 ar = pdev->ar;
1588
1589 memcpy(&ar->alpha2, &set_current_param.alpha2, 2);
1590 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param);
1591 if (ret)
1592 ath11k_warn(ar->ab,
1593 "pdev id %d failed set current country code: %d\n",
1594 i, ret);
1595 }
1596 }
1597
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)1598 static void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
1599 {
1600 struct ath11k *ar;
1601 struct ath11k_pdev *pdev;
1602 int i;
1603
1604 spin_lock_bh(&ab->base_lock);
1605 ab->stats.fw_crash_counter++;
1606 spin_unlock_bh(&ab->base_lock);
1607
1608 for (i = 0; i < ab->num_radios; i++) {
1609 pdev = &ab->pdevs[i];
1610 ar = pdev->ar;
1611 if (!ar || ar->state == ATH11K_STATE_OFF)
1612 continue;
1613
1614 ieee80211_stop_queues(ar->hw);
1615 ath11k_mac_drain_tx(ar);
1616 ar->state_11d = ATH11K_11D_IDLE;
1617 complete(&ar->completed_11d_scan);
1618 complete(&ar->scan.started);
1619 complete(&ar->scan.completed);
1620 complete(&ar->scan.on_channel);
1621 complete(&ar->peer_assoc_done);
1622 complete(&ar->peer_delete_done);
1623 complete(&ar->install_key_done);
1624 complete(&ar->vdev_setup_done);
1625 complete(&ar->vdev_delete_done);
1626 complete(&ar->bss_survey_done);
1627 complete(&ar->thermal.wmi_sync);
1628
1629 wake_up(&ar->dp.tx_empty_waitq);
1630 idr_for_each(&ar->txmgmt_idr,
1631 ath11k_mac_tx_mgmt_pending_free, ar);
1632 idr_destroy(&ar->txmgmt_idr);
1633 wake_up(&ar->txmgmt_empty_waitq);
1634 }
1635
1636 wake_up(&ab->wmi_ab.tx_credits_wq);
1637 wake_up(&ab->peer_mapping_wq);
1638 }
1639
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)1640 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
1641 {
1642 struct ath11k *ar;
1643 struct ath11k_pdev *pdev;
1644 int i;
1645
1646 for (i = 0; i < ab->num_radios; i++) {
1647 pdev = &ab->pdevs[i];
1648 ar = pdev->ar;
1649 if (!ar || ar->state == ATH11K_STATE_OFF)
1650 continue;
1651
1652 mutex_lock(&ar->conf_mutex);
1653
1654 switch (ar->state) {
1655 case ATH11K_STATE_ON:
1656 ar->state = ATH11K_STATE_RESTARTING;
1657 ath11k_core_halt(ar);
1658 ieee80211_restart_hw(ar->hw);
1659 break;
1660 case ATH11K_STATE_OFF:
1661 ath11k_warn(ab,
1662 "cannot restart radio %d that hasn't been started\n",
1663 i);
1664 break;
1665 case ATH11K_STATE_RESTARTING:
1666 break;
1667 case ATH11K_STATE_RESTARTED:
1668 ar->state = ATH11K_STATE_WEDGED;
1669 fallthrough;
1670 case ATH11K_STATE_WEDGED:
1671 ath11k_warn(ab,
1672 "device is wedged, will not restart radio %d\n", i);
1673 break;
1674 }
1675 mutex_unlock(&ar->conf_mutex);
1676 }
1677 complete(&ab->driver_recovery);
1678 }
1679
ath11k_core_restart(struct work_struct * work)1680 static void ath11k_core_restart(struct work_struct *work)
1681 {
1682 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
1683 int ret;
1684
1685 if (!ab->is_reset)
1686 ath11k_core_pre_reconfigure_recovery(ab);
1687
1688 ret = ath11k_core_reconfigure_on_crash(ab);
1689 if (ret) {
1690 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
1691 return;
1692 }
1693
1694 if (ab->is_reset)
1695 complete_all(&ab->reconfigure_complete);
1696
1697 if (!ab->is_reset)
1698 ath11k_core_post_reconfigure_recovery(ab);
1699 }
1700
ath11k_core_reset(struct work_struct * work)1701 static void ath11k_core_reset(struct work_struct *work)
1702 {
1703 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
1704 int reset_count, fail_cont_count;
1705 long time_left;
1706
1707 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
1708 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
1709 return;
1710 }
1711
1712 /* Sometimes the recovery will fail and then the next all recovery fail,
1713 * this is to avoid infinite recovery since it can not recovery success.
1714 */
1715 fail_cont_count = atomic_read(&ab->fail_cont_count);
1716
1717 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
1718 return;
1719
1720 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
1721 time_before(jiffies, ab->reset_fail_timeout))
1722 return;
1723
1724 reset_count = atomic_inc_return(&ab->reset_count);
1725
1726 if (reset_count > 1) {
1727 /* Sometimes it happened another reset worker before the previous one
1728 * completed, then the second reset worker will destroy the previous one,
1729 * thus below is to avoid that.
1730 */
1731 ath11k_warn(ab, "already resetting count %d\n", reset_count);
1732
1733 reinit_completion(&ab->reset_complete);
1734 time_left = wait_for_completion_timeout(&ab->reset_complete,
1735 ATH11K_RESET_TIMEOUT_HZ);
1736
1737 if (time_left) {
1738 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
1739 atomic_dec(&ab->reset_count);
1740 return;
1741 }
1742
1743 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
1744 /* Record the continuous recovery fail count when recovery failed*/
1745 atomic_inc(&ab->fail_cont_count);
1746 }
1747
1748 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
1749
1750 ab->is_reset = true;
1751 atomic_set(&ab->recovery_count, 0);
1752 reinit_completion(&ab->recovery_start);
1753 atomic_set(&ab->recovery_start_count, 0);
1754
1755 ath11k_core_pre_reconfigure_recovery(ab);
1756
1757 reinit_completion(&ab->reconfigure_complete);
1758 ath11k_core_post_reconfigure_recovery(ab);
1759
1760 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
1761
1762 time_left = wait_for_completion_timeout(&ab->recovery_start,
1763 ATH11K_RECOVER_START_TIMEOUT_HZ);
1764
1765 ath11k_hif_power_down(ab);
1766 ath11k_hif_power_up(ab);
1767
1768 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
1769 }
1770
ath11k_init_hw_params(struct ath11k_base * ab)1771 static int ath11k_init_hw_params(struct ath11k_base *ab)
1772 {
1773 const struct ath11k_hw_params *hw_params = NULL;
1774 int i;
1775
1776 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
1777 hw_params = &ath11k_hw_params[i];
1778
1779 if (hw_params->hw_rev == ab->hw_rev)
1780 break;
1781 }
1782
1783 if (i == ARRAY_SIZE(ath11k_hw_params)) {
1784 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
1785 return -EINVAL;
1786 }
1787
1788 ab->hw_params = *hw_params;
1789
1790 ath11k_info(ab, "%s\n", ab->hw_params.name);
1791
1792 return 0;
1793 }
1794
ath11k_core_pre_init(struct ath11k_base * ab)1795 int ath11k_core_pre_init(struct ath11k_base *ab)
1796 {
1797 int ret;
1798
1799 ret = ath11k_init_hw_params(ab);
1800 if (ret) {
1801 ath11k_err(ab, "failed to get hw params: %d\n", ret);
1802 return ret;
1803 }
1804
1805 return 0;
1806 }
1807 EXPORT_SYMBOL(ath11k_core_pre_init);
1808
ath11k_core_init(struct ath11k_base * ab)1809 int ath11k_core_init(struct ath11k_base *ab)
1810 {
1811 int ret;
1812
1813 ret = ath11k_core_soc_create(ab);
1814 if (ret) {
1815 ath11k_err(ab, "failed to create soc core: %d\n", ret);
1816 return ret;
1817 }
1818
1819 return 0;
1820 }
1821 EXPORT_SYMBOL(ath11k_core_init);
1822
ath11k_core_deinit(struct ath11k_base * ab)1823 void ath11k_core_deinit(struct ath11k_base *ab)
1824 {
1825 mutex_lock(&ab->core_lock);
1826
1827 ath11k_core_pdev_destroy(ab);
1828 ath11k_core_stop(ab);
1829
1830 mutex_unlock(&ab->core_lock);
1831
1832 ath11k_hif_power_down(ab);
1833 ath11k_mac_destroy(ab);
1834 ath11k_core_soc_destroy(ab);
1835 }
1836 EXPORT_SYMBOL(ath11k_core_deinit);
1837
ath11k_core_free(struct ath11k_base * ab)1838 void ath11k_core_free(struct ath11k_base *ab)
1839 {
1840 destroy_workqueue(ab->workqueue_aux);
1841 destroy_workqueue(ab->workqueue);
1842
1843 kfree(ab);
1844 }
1845 EXPORT_SYMBOL(ath11k_core_free);
1846
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)1847 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
1848 enum ath11k_bus bus)
1849 {
1850 struct ath11k_base *ab;
1851
1852 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
1853 if (!ab)
1854 return NULL;
1855
1856 init_completion(&ab->driver_recovery);
1857
1858 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
1859 if (!ab->workqueue)
1860 goto err_sc_free;
1861
1862 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
1863 if (!ab->workqueue_aux)
1864 goto err_free_wq;
1865
1866 mutex_init(&ab->core_lock);
1867 mutex_init(&ab->tbl_mtx_lock);
1868 spin_lock_init(&ab->base_lock);
1869 mutex_init(&ab->vdev_id_11d_lock);
1870 init_completion(&ab->reset_complete);
1871 init_completion(&ab->reconfigure_complete);
1872 init_completion(&ab->recovery_start);
1873
1874 INIT_LIST_HEAD(&ab->peers);
1875 init_waitqueue_head(&ab->peer_mapping_wq);
1876 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
1877 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
1878 INIT_WORK(&ab->restart_work, ath11k_core_restart);
1879 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
1880 INIT_WORK(&ab->rfkill_work, ath11k_rfkill_work);
1881 INIT_WORK(&ab->reset_work, ath11k_core_reset);
1882 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
1883 init_completion(&ab->htc_suspend);
1884 init_completion(&ab->wow.wakeup_completed);
1885
1886 ab->dev = dev;
1887 ab->hif.bus = bus;
1888
1889 return ab;
1890
1891 err_free_wq:
1892 destroy_workqueue(ab->workqueue);
1893 err_sc_free:
1894 kfree(ab);
1895 return NULL;
1896 }
1897 EXPORT_SYMBOL(ath11k_core_alloc);
1898
1899 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
1900 MODULE_LICENSE("Dual BSD/GPL");
1901