1 // SPDX-License-Identifier: ISC
2 /*
3  * Copyright (c) 2005-2011 Atheros Communications Inc.
4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5  */
6 
7 #include <linux/slab.h>
8 #include <linux/if_ether.h>
9 
10 #include "htt.h"
11 #include "core.h"
12 #include "debug.h"
13 #include "hif.h"
14 
15 static const enum htt_t2h_msg_type htt_main_t2h_msg_types[] = {
16 	[HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
17 	[HTT_MAIN_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
18 	[HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
19 	[HTT_MAIN_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
20 	[HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
21 	[HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
22 	[HTT_MAIN_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
23 	[HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
24 	[HTT_MAIN_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
25 	[HTT_MAIN_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
26 	[HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
27 	[HTT_MAIN_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
28 	[HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND] =
29 		HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
30 	[HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
31 		HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
32 	[HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
33 		HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
34 	[HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
35 	[HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
36 		HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
37 	[HTT_MAIN_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
38 };
39 
40 static const enum htt_t2h_msg_type htt_10x_t2h_msg_types[] = {
41 	[HTT_10X_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
42 	[HTT_10X_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
43 	[HTT_10X_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
44 	[HTT_10X_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
45 	[HTT_10X_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
46 	[HTT_10X_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
47 	[HTT_10X_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
48 	[HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
49 	[HTT_10X_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
50 	[HTT_10X_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
51 	[HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
52 	[HTT_10X_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
53 	[HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
54 	[HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND] = HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
55 	[HTT_10X_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
56 	[HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
57 	[HTT_10X_T2H_MSG_TYPE_AGGR_CONF] = HTT_T2H_MSG_TYPE_AGGR_CONF,
58 	[HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD] = HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
59 	[HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
60 		HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
61 };
62 
63 static const enum htt_t2h_msg_type htt_tlv_t2h_msg_types[] = {
64 	[HTT_TLV_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
65 	[HTT_TLV_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
66 	[HTT_TLV_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
67 	[HTT_TLV_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
68 	[HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
69 	[HTT_TLV_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
70 	[HTT_TLV_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
71 	[HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
72 	[HTT_TLV_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
73 	[HTT_TLV_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
74 	[HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
75 	[HTT_TLV_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
76 	[HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
77 	[HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND] = HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
78 	[HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
79 		HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
80 	[HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
81 		HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
82 	[HTT_TLV_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
83 	[HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
84 		HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
85 	[HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND] =
86 		HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
87 	[HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE] =
88 		HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
89 	[HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
90 	[HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR] =
91 		HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
92 	[HTT_TLV_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
93 };
94 
95 static const enum htt_t2h_msg_type htt_10_4_t2h_msg_types[] = {
96 	[HTT_10_4_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
97 	[HTT_10_4_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
98 	[HTT_10_4_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
99 	[HTT_10_4_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
100 	[HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
101 	[HTT_10_4_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
102 	[HTT_10_4_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
103 	[HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
104 	[HTT_10_4_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
105 	[HTT_10_4_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
106 	[HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
107 	[HTT_10_4_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
108 	[HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
109 	[HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND] =
110 				HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
111 	[HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
112 				HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
113 	[HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
114 	[HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
115 				HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
116 	[HTT_10_4_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
117 	[HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
118 				HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
119 	[HTT_10_4_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
120 	[HTT_10_4_T2H_MSG_TYPE_EN_STATS] = HTT_T2H_MSG_TYPE_EN_STATS,
121 	[HTT_10_4_T2H_MSG_TYPE_AGGR_CONF] = HTT_T2H_MSG_TYPE_AGGR_CONF,
122 	[HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND] =
123 				HTT_T2H_MSG_TYPE_TX_FETCH_IND,
124 	[HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM] =
125 				HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
126 	[HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD] =
127 				HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
128 	[HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND] =
129 				HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
130 	[HTT_10_4_T2H_MSG_TYPE_PEER_STATS] =
131 				HTT_T2H_MSG_TYPE_PEER_STATS,
132 };
133 
134 const struct ath10k_htt_rx_desc_ops qca988x_rx_desc_ops = {
135 	.rx_desc_size = sizeof(struct htt_rx_desc_v1),
136 	.rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v1, msdu_payload)
137 };
138 
ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc * rxd)139 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
140 {
141 	struct htt_rx_desc_v1 *rx_desc = container_of(rxd,
142 						      struct htt_rx_desc_v1,
143 						      base);
144 
145 	return MS(__le32_to_cpu(rx_desc->msdu_end.qca99x0.info1),
146 		  RX_MSDU_END_INFO1_L3_HDR_PAD);
147 }
148 
ath10k_qca99x0_rx_desc_msdu_limit_error(struct htt_rx_desc * rxd)149 static bool ath10k_qca99x0_rx_desc_msdu_limit_error(struct htt_rx_desc *rxd)
150 {
151 	struct htt_rx_desc_v1 *rx_desc = container_of(rxd,
152 						      struct htt_rx_desc_v1,
153 						      base);
154 
155 	return !!(rx_desc->msdu_end.common.info0 &
156 		  __cpu_to_le32(RX_MSDU_END_INFO0_MSDU_LIMIT_ERR));
157 }
158 
159 const struct ath10k_htt_rx_desc_ops qca99x0_rx_desc_ops = {
160 	.rx_desc_size = sizeof(struct htt_rx_desc_v1),
161 	.rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v1, msdu_payload),
162 
163 	.rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
164 	.rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
165 };
166 
ath10k_rx_desc_wcn3990_get_offsets(struct htt_rx_ring_rx_desc_offsets * off)167 static void ath10k_rx_desc_wcn3990_get_offsets(struct htt_rx_ring_rx_desc_offsets *off)
168 {
169 #define desc_offset(x) (offsetof(struct htt_rx_desc_v2, x) / 4)
170 	off->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
171 	off->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
172 	off->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
173 	off->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
174 	off->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
175 	off->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
176 	off->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
177 	off->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
178 	off->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
179 	off->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
180 #undef desc_offset
181 }
182 
183 static struct htt_rx_desc *
ath10k_rx_desc_wcn3990_from_raw_buffer(void * buff)184 ath10k_rx_desc_wcn3990_from_raw_buffer(void *buff)
185 {
186 	return &((struct htt_rx_desc_v2 *)buff)->base;
187 }
188 
189 static struct rx_attention *
ath10k_rx_desc_wcn3990_get_attention(struct htt_rx_desc * rxd)190 ath10k_rx_desc_wcn3990_get_attention(struct htt_rx_desc *rxd)
191 {
192 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
193 
194 	return &rx_desc->attention;
195 }
196 
197 static struct rx_frag_info_common *
ath10k_rx_desc_wcn3990_get_frag_info(struct htt_rx_desc * rxd)198 ath10k_rx_desc_wcn3990_get_frag_info(struct htt_rx_desc *rxd)
199 {
200 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
201 
202 	return &rx_desc->frag_info.common;
203 }
204 
205 static struct rx_mpdu_start *
ath10k_rx_desc_wcn3990_get_mpdu_start(struct htt_rx_desc * rxd)206 ath10k_rx_desc_wcn3990_get_mpdu_start(struct htt_rx_desc *rxd)
207 {
208 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
209 
210 	return &rx_desc->mpdu_start;
211 }
212 
213 static struct rx_mpdu_end *
ath10k_rx_desc_wcn3990_get_mpdu_end(struct htt_rx_desc * rxd)214 ath10k_rx_desc_wcn3990_get_mpdu_end(struct htt_rx_desc *rxd)
215 {
216 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
217 
218 	return &rx_desc->mpdu_end;
219 }
220 
221 static struct rx_msdu_start_common *
ath10k_rx_desc_wcn3990_get_msdu_start(struct htt_rx_desc * rxd)222 ath10k_rx_desc_wcn3990_get_msdu_start(struct htt_rx_desc *rxd)
223 {
224 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
225 
226 	return &rx_desc->msdu_start.common;
227 }
228 
229 static struct rx_msdu_end_common *
ath10k_rx_desc_wcn3990_get_msdu_end(struct htt_rx_desc * rxd)230 ath10k_rx_desc_wcn3990_get_msdu_end(struct htt_rx_desc *rxd)
231 {
232 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
233 
234 	return &rx_desc->msdu_end.common;
235 }
236 
237 static struct rx_ppdu_start *
ath10k_rx_desc_wcn3990_get_ppdu_start(struct htt_rx_desc * rxd)238 ath10k_rx_desc_wcn3990_get_ppdu_start(struct htt_rx_desc *rxd)
239 {
240 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
241 
242 	return &rx_desc->ppdu_start;
243 }
244 
245 static struct rx_ppdu_end_common *
ath10k_rx_desc_wcn3990_get_ppdu_end(struct htt_rx_desc * rxd)246 ath10k_rx_desc_wcn3990_get_ppdu_end(struct htt_rx_desc *rxd)
247 {
248 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
249 
250 	return &rx_desc->ppdu_end.common;
251 }
252 
253 static u8 *
ath10k_rx_desc_wcn3990_get_rx_hdr_status(struct htt_rx_desc * rxd)254 ath10k_rx_desc_wcn3990_get_rx_hdr_status(struct htt_rx_desc *rxd)
255 {
256 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
257 
258 	return rx_desc->rx_hdr_status;
259 }
260 
261 static u8 *
ath10k_rx_desc_wcn3990_get_msdu_payload(struct htt_rx_desc * rxd)262 ath10k_rx_desc_wcn3990_get_msdu_payload(struct htt_rx_desc *rxd)
263 {
264 	struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
265 
266 	return rx_desc->msdu_payload;
267 }
268 
269 const struct ath10k_htt_rx_desc_ops wcn3990_rx_desc_ops = {
270 	.rx_desc_size = sizeof(struct htt_rx_desc_v2),
271 	.rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v2, msdu_payload),
272 
273 	.rx_desc_from_raw_buffer = ath10k_rx_desc_wcn3990_from_raw_buffer,
274 	.rx_desc_get_offsets = ath10k_rx_desc_wcn3990_get_offsets,
275 	.rx_desc_get_attention = ath10k_rx_desc_wcn3990_get_attention,
276 	.rx_desc_get_frag_info = ath10k_rx_desc_wcn3990_get_frag_info,
277 	.rx_desc_get_mpdu_start = ath10k_rx_desc_wcn3990_get_mpdu_start,
278 	.rx_desc_get_mpdu_end = ath10k_rx_desc_wcn3990_get_mpdu_end,
279 	.rx_desc_get_msdu_start = ath10k_rx_desc_wcn3990_get_msdu_start,
280 	.rx_desc_get_msdu_end = ath10k_rx_desc_wcn3990_get_msdu_end,
281 	.rx_desc_get_ppdu_start = ath10k_rx_desc_wcn3990_get_ppdu_start,
282 	.rx_desc_get_ppdu_end = ath10k_rx_desc_wcn3990_get_ppdu_end,
283 	.rx_desc_get_rx_hdr_status = ath10k_rx_desc_wcn3990_get_rx_hdr_status,
284 	.rx_desc_get_msdu_payload = ath10k_rx_desc_wcn3990_get_msdu_payload,
285 };
286 
ath10k_htt_connect(struct ath10k_htt * htt)287 int ath10k_htt_connect(struct ath10k_htt *htt)
288 {
289 	struct ath10k_htc_svc_conn_req conn_req;
290 	struct ath10k_htc_svc_conn_resp conn_resp;
291 	struct ath10k *ar = htt->ar;
292 	struct ath10k_htc_ep *ep;
293 	int status;
294 
295 	memset(&conn_req, 0, sizeof(conn_req));
296 	memset(&conn_resp, 0, sizeof(conn_resp));
297 
298 	conn_req.ep_ops.ep_tx_complete = ath10k_htt_htc_tx_complete;
299 	conn_req.ep_ops.ep_rx_complete = ath10k_htt_htc_t2h_msg_handler;
300 	conn_req.ep_ops.ep_tx_credits = ath10k_htt_op_ep_tx_credits;
301 
302 	/* connect to control service */
303 	conn_req.service_id = ATH10K_HTC_SVC_ID_HTT_DATA_MSG;
304 
305 	status = ath10k_htc_connect_service(&htt->ar->htc, &conn_req,
306 					    &conn_resp);
307 
308 	if (status)
309 		return status;
310 
311 	htt->eid = conn_resp.eid;
312 
313 	if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) {
314 		ep = &ar->htc.endpoint[htt->eid];
315 		ath10k_htc_setup_tx_req(ep);
316 	}
317 
318 	htt->disable_tx_comp = ath10k_hif_get_htt_tx_complete(htt->ar);
319 	if (htt->disable_tx_comp)
320 		ath10k_htc_change_tx_credit_flow(&htt->ar->htc, htt->eid, true);
321 
322 	return 0;
323 }
324 
ath10k_htt_init(struct ath10k * ar)325 int ath10k_htt_init(struct ath10k *ar)
326 {
327 	struct ath10k_htt *htt = &ar->htt;
328 
329 	htt->ar = ar;
330 
331 	/*
332 	 * Prefetch enough data to satisfy target
333 	 * classification engine.
334 	 * This is for LL chips. HL chips will probably
335 	 * transfer all frame in the tx fragment.
336 	 */
337 	htt->prefetch_len =
338 		36 + /* 802.11 + qos + ht */
339 		4 + /* 802.1q */
340 		8 + /* llc snap */
341 		2; /* ip4 dscp or ip6 priority */
342 
343 	switch (ar->running_fw->fw_file.htt_op_version) {
344 	case ATH10K_FW_HTT_OP_VERSION_10_4:
345 		ar->htt.t2h_msg_types = htt_10_4_t2h_msg_types;
346 		ar->htt.t2h_msg_types_max = HTT_10_4_T2H_NUM_MSGS;
347 		break;
348 	case ATH10K_FW_HTT_OP_VERSION_10_1:
349 		ar->htt.t2h_msg_types = htt_10x_t2h_msg_types;
350 		ar->htt.t2h_msg_types_max = HTT_10X_T2H_NUM_MSGS;
351 		break;
352 	case ATH10K_FW_HTT_OP_VERSION_TLV:
353 		ar->htt.t2h_msg_types = htt_tlv_t2h_msg_types;
354 		ar->htt.t2h_msg_types_max = HTT_TLV_T2H_NUM_MSGS;
355 		break;
356 	case ATH10K_FW_HTT_OP_VERSION_MAIN:
357 		ar->htt.t2h_msg_types = htt_main_t2h_msg_types;
358 		ar->htt.t2h_msg_types_max = HTT_MAIN_T2H_NUM_MSGS;
359 		break;
360 	case ATH10K_FW_HTT_OP_VERSION_MAX:
361 	case ATH10K_FW_HTT_OP_VERSION_UNSET:
362 		WARN_ON(1);
363 		return -EINVAL;
364 	}
365 	ath10k_htt_set_tx_ops(htt);
366 	ath10k_htt_set_rx_ops(htt);
367 
368 	return 0;
369 }
370 
371 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
372 
ath10k_htt_verify_version(struct ath10k_htt * htt)373 static int ath10k_htt_verify_version(struct ath10k_htt *htt)
374 {
375 	struct ath10k *ar = htt->ar;
376 
377 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt target version %d.%d\n",
378 		   htt->target_version_major, htt->target_version_minor);
379 
380 	if (htt->target_version_major != 2 &&
381 	    htt->target_version_major != 3) {
382 		ath10k_err(ar, "unsupported htt major version %d. supported versions are 2 and 3\n",
383 			   htt->target_version_major);
384 		return -ENOTSUPP;
385 	}
386 
387 	return 0;
388 }
389 
ath10k_htt_setup(struct ath10k_htt * htt)390 int ath10k_htt_setup(struct ath10k_htt *htt)
391 {
392 	struct ath10k *ar = htt->ar;
393 	int status;
394 
395 	init_completion(&htt->target_version_received);
396 
397 	status = ath10k_htt_h2t_ver_req_msg(htt);
398 	if (status)
399 		return status;
400 
401 	status = wait_for_completion_timeout(&htt->target_version_received,
402 					     HTT_TARGET_VERSION_TIMEOUT_HZ);
403 	if (status == 0) {
404 		ath10k_warn(ar, "htt version request timed out\n");
405 		return -ETIMEDOUT;
406 	}
407 
408 	status = ath10k_htt_verify_version(htt);
409 	if (status) {
410 		ath10k_warn(ar, "failed to verify htt version: %d\n",
411 			    status);
412 		return status;
413 	}
414 
415 	status = ath10k_htt_send_frag_desc_bank_cfg(htt);
416 	if (status)
417 		return status;
418 
419 	status = ath10k_htt_send_rx_ring_cfg(htt);
420 	if (status) {
421 		ath10k_warn(ar, "failed to setup rx ring: %d\n",
422 			    status);
423 		return status;
424 	}
425 
426 	status = ath10k_htt_h2t_aggr_cfg_msg(htt,
427 					     htt->max_num_ampdu,
428 					     htt->max_num_amsdu);
429 	if (status) {
430 		ath10k_warn(ar, "failed to setup amsdu/ampdu limit: %d\n",
431 			    status);
432 		return status;
433 	}
434 
435 	return 0;
436 }
437