1 /*
2 * arch/arm/mach-at91/at91sam9260.c
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14 #include <linux/pm.h>
15
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <mach/cpu.h>
20 #include <mach/at91sam9260.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 #include <mach/at91_shdwc.h>
24
25 #include "generic.h"
26 #include "clock.h"
27
28 static struct map_desc at91sam9260_io_desc[] __initdata = {
29 {
30 .virtual = AT91_VA_BASE_SYS,
31 .pfn = __phys_to_pfn(AT91_BASE_SYS),
32 .length = SZ_16K,
33 .type = MT_DEVICE,
34 }
35 };
36
37 static struct map_desc at91sam9260_sram_desc[] __initdata = {
38 {
39 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
40 .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
41 .length = AT91SAM9260_SRAM0_SIZE,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
45 .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
46 .length = AT91SAM9260_SRAM1_SIZE,
47 .type = MT_DEVICE,
48 }
49 };
50
51 static struct map_desc at91sam9g20_sram_desc[] __initdata = {
52 {
53 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
54 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
55 .length = AT91SAM9G20_SRAM0_SIZE,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
59 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
60 .length = AT91SAM9G20_SRAM1_SIZE,
61 .type = MT_DEVICE,
62 }
63 };
64
65 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
66 {
67 .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
68 .type = MT_DEVICE,
69 }
70 };
71
72 /* --------------------------------------------------------------------
73 * Clocks
74 * -------------------------------------------------------------------- */
75
76 /*
77 * The peripheral clocks.
78 */
79 static struct clk pioA_clk = {
80 .name = "pioA_clk",
81 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
82 .type = CLK_TYPE_PERIPHERAL,
83 };
84 static struct clk pioB_clk = {
85 .name = "pioB_clk",
86 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
87 .type = CLK_TYPE_PERIPHERAL,
88 };
89 static struct clk pioC_clk = {
90 .name = "pioC_clk",
91 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
92 .type = CLK_TYPE_PERIPHERAL,
93 };
94 static struct clk adc_clk = {
95 .name = "adc_clk",
96 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
97 .type = CLK_TYPE_PERIPHERAL,
98 };
99 static struct clk usart0_clk = {
100 .name = "usart0_clk",
101 .pmc_mask = 1 << AT91SAM9260_ID_US0,
102 .type = CLK_TYPE_PERIPHERAL,
103 };
104 static struct clk usart1_clk = {
105 .name = "usart1_clk",
106 .pmc_mask = 1 << AT91SAM9260_ID_US1,
107 .type = CLK_TYPE_PERIPHERAL,
108 };
109 static struct clk usart2_clk = {
110 .name = "usart2_clk",
111 .pmc_mask = 1 << AT91SAM9260_ID_US2,
112 .type = CLK_TYPE_PERIPHERAL,
113 };
114 static struct clk mmc_clk = {
115 .name = "mci_clk",
116 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
117 .type = CLK_TYPE_PERIPHERAL,
118 };
119 static struct clk udc_clk = {
120 .name = "udc_clk",
121 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
122 .type = CLK_TYPE_PERIPHERAL,
123 };
124 static struct clk twi_clk = {
125 .name = "twi_clk",
126 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
127 .type = CLK_TYPE_PERIPHERAL,
128 };
129 static struct clk spi0_clk = {
130 .name = "spi0_clk",
131 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
132 .type = CLK_TYPE_PERIPHERAL,
133 };
134 static struct clk spi1_clk = {
135 .name = "spi1_clk",
136 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
137 .type = CLK_TYPE_PERIPHERAL,
138 };
139 static struct clk ssc_clk = {
140 .name = "ssc_clk",
141 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
142 .type = CLK_TYPE_PERIPHERAL,
143 };
144 static struct clk tc0_clk = {
145 .name = "tc0_clk",
146 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
147 .type = CLK_TYPE_PERIPHERAL,
148 };
149 static struct clk tc1_clk = {
150 .name = "tc1_clk",
151 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
152 .type = CLK_TYPE_PERIPHERAL,
153 };
154 static struct clk tc2_clk = {
155 .name = "tc2_clk",
156 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
157 .type = CLK_TYPE_PERIPHERAL,
158 };
159 static struct clk ohci_clk = {
160 .name = "ohci_clk",
161 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
162 .type = CLK_TYPE_PERIPHERAL,
163 };
164 static struct clk macb_clk = {
165 .name = "macb_clk",
166 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
167 .type = CLK_TYPE_PERIPHERAL,
168 };
169 static struct clk isi_clk = {
170 .name = "isi_clk",
171 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
172 .type = CLK_TYPE_PERIPHERAL,
173 };
174 static struct clk usart3_clk = {
175 .name = "usart3_clk",
176 .pmc_mask = 1 << AT91SAM9260_ID_US3,
177 .type = CLK_TYPE_PERIPHERAL,
178 };
179 static struct clk usart4_clk = {
180 .name = "usart4_clk",
181 .pmc_mask = 1 << AT91SAM9260_ID_US4,
182 .type = CLK_TYPE_PERIPHERAL,
183 };
184 static struct clk usart5_clk = {
185 .name = "usart5_clk",
186 .pmc_mask = 1 << AT91SAM9260_ID_US5,
187 .type = CLK_TYPE_PERIPHERAL,
188 };
189 static struct clk tc3_clk = {
190 .name = "tc3_clk",
191 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
192 .type = CLK_TYPE_PERIPHERAL,
193 };
194 static struct clk tc4_clk = {
195 .name = "tc4_clk",
196 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
197 .type = CLK_TYPE_PERIPHERAL,
198 };
199 static struct clk tc5_clk = {
200 .name = "tc5_clk",
201 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
202 .type = CLK_TYPE_PERIPHERAL,
203 };
204
205 static struct clk *periph_clocks[] __initdata = {
206 &pioA_clk,
207 &pioB_clk,
208 &pioC_clk,
209 &adc_clk,
210 &usart0_clk,
211 &usart1_clk,
212 &usart2_clk,
213 &mmc_clk,
214 &udc_clk,
215 &twi_clk,
216 &spi0_clk,
217 &spi1_clk,
218 &ssc_clk,
219 &tc0_clk,
220 &tc1_clk,
221 &tc2_clk,
222 &ohci_clk,
223 &macb_clk,
224 &isi_clk,
225 &usart3_clk,
226 &usart4_clk,
227 &usart5_clk,
228 &tc3_clk,
229 &tc4_clk,
230 &tc5_clk,
231 // irq0 .. irq2
232 };
233
234 /*
235 * The two programmable clocks.
236 * You must configure pin multiplexing to bring these signals out.
237 */
238 static struct clk pck0 = {
239 .name = "pck0",
240 .pmc_mask = AT91_PMC_PCK0,
241 .type = CLK_TYPE_PROGRAMMABLE,
242 .id = 0,
243 };
244 static struct clk pck1 = {
245 .name = "pck1",
246 .pmc_mask = AT91_PMC_PCK1,
247 .type = CLK_TYPE_PROGRAMMABLE,
248 .id = 1,
249 };
250
at91sam9260_register_clocks(void)251 static void __init at91sam9260_register_clocks(void)
252 {
253 int i;
254
255 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
256 clk_register(periph_clocks[i]);
257
258 clk_register(&pck0);
259 clk_register(&pck1);
260 }
261
262 /* --------------------------------------------------------------------
263 * GPIO
264 * -------------------------------------------------------------------- */
265
266 static struct at91_gpio_bank at91sam9260_gpio[] = {
267 {
268 .id = AT91SAM9260_ID_PIOA,
269 .offset = AT91_PIOA,
270 .clock = &pioA_clk,
271 }, {
272 .id = AT91SAM9260_ID_PIOB,
273 .offset = AT91_PIOB,
274 .clock = &pioB_clk,
275 }, {
276 .id = AT91SAM9260_ID_PIOC,
277 .offset = AT91_PIOC,
278 .clock = &pioC_clk,
279 }
280 };
281
at91sam9260_poweroff(void)282 static void at91sam9260_poweroff(void)
283 {
284 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
285 }
286
287
288 /* --------------------------------------------------------------------
289 * AT91SAM9260 processor initialization
290 * -------------------------------------------------------------------- */
291
at91sam9xe_initialize(void)292 static void __init at91sam9xe_initialize(void)
293 {
294 unsigned long cidr, sram_size;
295
296 cidr = at91_sys_read(AT91_DBGU_CIDR);
297
298 switch (cidr & AT91_CIDR_SRAMSIZ) {
299 case AT91_CIDR_SRAMSIZ_32K:
300 sram_size = 2 * SZ_16K;
301 break;
302 case AT91_CIDR_SRAMSIZ_16K:
303 default:
304 sram_size = SZ_16K;
305 }
306
307 at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
308 at91sam9xe_sram_desc->length = sram_size;
309
310 iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
311 }
312
at91sam9260_initialize(unsigned long main_clock)313 void __init at91sam9260_initialize(unsigned long main_clock)
314 {
315 /* Map peripherals */
316 iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
317
318 if (cpu_is_at91sam9xe())
319 at91sam9xe_initialize();
320 else if (cpu_is_at91sam9g20())
321 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
322 else
323 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
324
325 at91_arch_reset = at91sam9_alt_reset;
326 pm_power_off = at91sam9260_poweroff;
327 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
328 | (1 << AT91SAM9260_ID_IRQ2);
329
330 /* Init clock subsystem */
331 at91_clock_init(main_clock);
332
333 /* Register the processor-specific clocks */
334 at91sam9260_register_clocks();
335
336 /* Register GPIO subsystem */
337 at91_gpio_init(at91sam9260_gpio, 3);
338 }
339
340 /* --------------------------------------------------------------------
341 * Interrupt initialization
342 * -------------------------------------------------------------------- */
343
344 /*
345 * The default interrupt priority levels (0 = lowest, 7 = highest).
346 */
347 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
348 7, /* Advanced Interrupt Controller */
349 7, /* System Peripherals */
350 1, /* Parallel IO Controller A */
351 1, /* Parallel IO Controller B */
352 1, /* Parallel IO Controller C */
353 0, /* Analog-to-Digital Converter */
354 5, /* USART 0 */
355 5, /* USART 1 */
356 5, /* USART 2 */
357 0, /* Multimedia Card Interface */
358 2, /* USB Device Port */
359 6, /* Two-Wire Interface */
360 5, /* Serial Peripheral Interface 0 */
361 5, /* Serial Peripheral Interface 1 */
362 5, /* Serial Synchronous Controller */
363 0,
364 0,
365 0, /* Timer Counter 0 */
366 0, /* Timer Counter 1 */
367 0, /* Timer Counter 2 */
368 2, /* USB Host port */
369 3, /* Ethernet */
370 0, /* Image Sensor Interface */
371 5, /* USART 3 */
372 5, /* USART 4 */
373 5, /* USART 5 */
374 0, /* Timer Counter 3 */
375 0, /* Timer Counter 4 */
376 0, /* Timer Counter 5 */
377 0, /* Advanced Interrupt Controller */
378 0, /* Advanced Interrupt Controller */
379 0, /* Advanced Interrupt Controller */
380 };
381
at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])382 void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
383 {
384 if (!priority)
385 priority = at91sam9260_default_irq_priority;
386
387 /* Initialize the AIC interrupt controller */
388 at91_aic_init(priority);
389
390 /* Enable GPIO interrupts */
391 at91_gpio_irq_setup();
392 }
393