1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29 /*
30 * register values to turn OFDM weak signal detection OFF
31 */
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
42
43 /**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
ar9003_hw_set_channel(struct ath_hw * ah,struct ath9k_channel * chan)68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69 {
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
80 u32 chan_frac;
81 u32 div;
82
83 if (ah->is_clk_25mhz)
84 div = 75;
85 else
86 div = 120;
87
88 channelSel = (freq * 4) / div;
89 chan_frac = (((freq * 4) % div) * 0x20000) / div;
90 channelSel = (channelSel << 17) | chan_frac;
91 } else if (AR_SREV_9485(ah)) {
92 u32 chan_frac;
93
94 /*
95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
98 */
99 channelSel = (freq * 4) / 120;
100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101 channelSel = (channelSel << 17) | chan_frac;
102 } else if (AR_SREV_9340(ah)) {
103 if (ah->is_clk_25mhz) {
104 u32 chan_frac;
105
106 channelSel = (freq * 2) / 75;
107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108 channelSel = (channelSel << 17) | chan_frac;
109 } else
110 channelSel = CHANSEL_2G(freq) >> 1;
111 } else
112 channelSel = CHANSEL_2G(freq);
113 /* Set to 2G mode */
114 bMode = 1;
115 } else {
116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
117 u32 chan_frac;
118
119 channelSel = (freq * 2) / 75;
120 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
121 channelSel = (channelSel << 17) | chan_frac;
122 } else {
123 channelSel = CHANSEL_5G(freq);
124 /* Doubler is ON, so, divide channelSel by 2. */
125 channelSel >>= 1;
126 }
127 /* Set to 5G mode */
128 bMode = 0;
129 }
130
131 /* Enable fractional mode for all channels */
132 fracMode = 1;
133 aModeRefSel = 0;
134 loadSynthChannel = 0;
135
136 reg32 = (bMode << 29);
137 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
138
139 /* Enable Long shift Select for Synthesizer */
140 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
141 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
142
143 /* Program Synth. setting */
144 reg32 = (channelSel << 2) | (fracMode << 30) |
145 (aModeRefSel << 28) | (loadSynthChannel << 31);
146 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
147
148 /* Toggle Load Synth channel bit */
149 loadSynthChannel = 1;
150 reg32 = (channelSel << 2) | (fracMode << 30) |
151 (aModeRefSel << 28) | (loadSynthChannel << 31);
152 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
153
154 ah->curchan = chan;
155 ah->curchan_rad_index = -1;
156
157 return 0;
158 }
159
160 /**
161 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
162 * @ah: atheros hardware structure
163 * @chan:
164 *
165 * For single-chip solutions. Converts to baseband spur frequency given the
166 * input channel frequency and compute register settings below.
167 *
168 * Spur mitigation for MRC CCK
169 */
ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw * ah,struct ath9k_channel * chan)170 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
171 struct ath9k_channel *chan)
172 {
173 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
174 int cur_bb_spur, negative = 0, cck_spur_freq;
175 int i;
176 int range, max_spur_cnts, synth_freq;
177 u8 *spur_fbin_ptr = NULL;
178
179 /*
180 * Need to verify range +/- 10 MHz in control channel, otherwise spur
181 * is out-of-band and can be ignored.
182 */
183
184 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
185 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
186 IS_CHAN_2GHZ(chan));
187 if (spur_fbin_ptr[0] == 0) /* No spur */
188 return;
189 max_spur_cnts = 5;
190 if (IS_CHAN_HT40(chan)) {
191 range = 19;
192 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
193 AR_PHY_GC_DYN2040_PRI_CH) == 0)
194 synth_freq = chan->channel + 10;
195 else
196 synth_freq = chan->channel - 10;
197 } else {
198 range = 10;
199 synth_freq = chan->channel;
200 }
201 } else {
202 range = AR_SREV_9462(ah) ? 5 : 10;
203 max_spur_cnts = 4;
204 synth_freq = chan->channel;
205 }
206
207 for (i = 0; i < max_spur_cnts; i++) {
208 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
209 continue;
210 negative = 0;
211 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
212 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
213 IS_CHAN_2GHZ(chan)) - synth_freq;
214 else
215 cur_bb_spur = spur_freq[i] - synth_freq;
216
217 if (cur_bb_spur < 0) {
218 negative = 1;
219 cur_bb_spur = -cur_bb_spur;
220 }
221 if (cur_bb_spur < range) {
222 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
223
224 if (negative == 1)
225 cck_spur_freq = -cck_spur_freq;
226
227 cck_spur_freq = cck_spur_freq & 0xfffff;
228
229 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
230 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
231 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
232 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
234 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
235 0x2);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
238 0x1);
239 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
240 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
241 cck_spur_freq);
242
243 return;
244 }
245 }
246
247 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
248 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
249 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
250 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
251 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
252 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
253 }
254
255 /* Clean all spur register fields */
ar9003_hw_spur_ofdm_clear(struct ath_hw * ah)256 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
257 {
258 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
259 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
260 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
261 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
262 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
263 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
264 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
265 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
266 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
267 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
268 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
269 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
270 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
271 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
272 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
273 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
275 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
276
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
279 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
280 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
281 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
282 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
283 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
284 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
285 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
286 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
287 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
288 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
289 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
290 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
291 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
292 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
293 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
294 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
295 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
296 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
297 }
298
ar9003_hw_spur_ofdm(struct ath_hw * ah,int freq_offset,int spur_freq_sd,int spur_delta_phase,int spur_subchannel_sd)299 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
300 int freq_offset,
301 int spur_freq_sd,
302 int spur_delta_phase,
303 int spur_subchannel_sd)
304 {
305 int mask_index = 0;
306
307 /* OFDM Spur mitigation */
308 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
309 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
310 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
311 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
312 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
313 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
314 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
315 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
316 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
317 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
318 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
319 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
320 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
321 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
322 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
323 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
324 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
325 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
326
327 if (REG_READ_FIELD(ah, AR_PHY_MODE,
328 AR_PHY_MODE_DYNAMIC) == 0x1)
329 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
330 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
331
332 mask_index = (freq_offset << 4) / 5;
333 if (mask_index < 0)
334 mask_index = mask_index - 1;
335
336 mask_index = mask_index & 0x7f;
337
338 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
339 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
341 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
342 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
343 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
344 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
345 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
346 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
347 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
348 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
349 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
350 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
351 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
352 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
353 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
354 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
355 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
356 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
357 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
358 }
359
ar9003_hw_spur_ofdm_work(struct ath_hw * ah,struct ath9k_channel * chan,int freq_offset)360 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
361 struct ath9k_channel *chan,
362 int freq_offset)
363 {
364 int spur_freq_sd = 0;
365 int spur_subchannel_sd = 0;
366 int spur_delta_phase = 0;
367
368 if (IS_CHAN_HT40(chan)) {
369 if (freq_offset < 0) {
370 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
371 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
372 spur_subchannel_sd = 1;
373 else
374 spur_subchannel_sd = 0;
375
376 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
377
378 } else {
379 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
380 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
381 spur_subchannel_sd = 0;
382 else
383 spur_subchannel_sd = 1;
384
385 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
386
387 }
388
389 spur_delta_phase = (freq_offset << 17) / 5;
390
391 } else {
392 spur_subchannel_sd = 0;
393 spur_freq_sd = (freq_offset << 9) /11;
394 spur_delta_phase = (freq_offset << 18) / 5;
395 }
396
397 spur_freq_sd = spur_freq_sd & 0x3ff;
398 spur_delta_phase = spur_delta_phase & 0xfffff;
399
400 ar9003_hw_spur_ofdm(ah,
401 freq_offset,
402 spur_freq_sd,
403 spur_delta_phase,
404 spur_subchannel_sd);
405 }
406
407 /* Spur mitigation for OFDM */
ar9003_hw_spur_mitigate_ofdm(struct ath_hw * ah,struct ath9k_channel * chan)408 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
409 struct ath9k_channel *chan)
410 {
411 int synth_freq;
412 int range = 10;
413 int freq_offset = 0;
414 int mode;
415 u8* spurChansPtr;
416 unsigned int i;
417 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
418
419 if (IS_CHAN_5GHZ(chan)) {
420 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
421 mode = 0;
422 }
423 else {
424 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
425 mode = 1;
426 }
427
428 if (spurChansPtr[0] == 0)
429 return; /* No spur in the mode */
430
431 if (IS_CHAN_HT40(chan)) {
432 range = 19;
433 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
434 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
435 synth_freq = chan->channel - 10;
436 else
437 synth_freq = chan->channel + 10;
438 } else {
439 range = 10;
440 synth_freq = chan->channel;
441 }
442
443 ar9003_hw_spur_ofdm_clear(ah);
444
445 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
446 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
447 if (abs(freq_offset) < range) {
448 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
449 break;
450 }
451 }
452 }
453
ar9003_hw_spur_mitigate(struct ath_hw * ah,struct ath9k_channel * chan)454 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
455 struct ath9k_channel *chan)
456 {
457 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
458 ar9003_hw_spur_mitigate_ofdm(ah, chan);
459 }
460
ar9003_hw_compute_pll_control(struct ath_hw * ah,struct ath9k_channel * chan)461 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
462 struct ath9k_channel *chan)
463 {
464 u32 pll;
465
466 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
467
468 if (chan && IS_CHAN_HALF_RATE(chan))
469 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
470 else if (chan && IS_CHAN_QUARTER_RATE(chan))
471 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
472
473 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
474
475 return pll;
476 }
477
ar9003_hw_set_channel_regs(struct ath_hw * ah,struct ath9k_channel * chan)478 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
479 struct ath9k_channel *chan)
480 {
481 u32 phymode;
482 u32 enableDacFifo = 0;
483
484 enableDacFifo =
485 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
486
487 /* Enable 11n HT, 20 MHz */
488 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
489 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
490
491 /* Configure baseband for dynamic 20/40 operation */
492 if (IS_CHAN_HT40(chan)) {
493 phymode |= AR_PHY_GC_DYN2040_EN;
494 /* Configure control (primary) channel at +-10MHz */
495 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
496 (chan->chanmode == CHANNEL_G_HT40PLUS))
497 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
498
499 }
500
501 /* make sure we preserve INI settings */
502 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
503 /* turn off Green Field detection for STA for now */
504 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
505
506 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
507
508 /* Configure MAC for 20/40 operation */
509 ath9k_hw_set11nmac2040(ah);
510
511 /* global transmit timeout (25 TUs default)*/
512 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
513 /* carrier sense timeout */
514 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
515 }
516
ar9003_hw_init_bb(struct ath_hw * ah,struct ath9k_channel * chan)517 static void ar9003_hw_init_bb(struct ath_hw *ah,
518 struct ath9k_channel *chan)
519 {
520 u32 synthDelay;
521
522 /*
523 * Wait for the frequency synth to settle (synth goes on
524 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
525 * Value is in 100ns increments.
526 */
527 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
528 if (IS_CHAN_B(chan))
529 synthDelay = (4 * synthDelay) / 22;
530 else
531 synthDelay /= 10;
532
533 /* Activate the PHY (includes baseband activate + synthesizer on) */
534 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
535
536 /*
537 * There is an issue if the AP starts the calibration before
538 * the base band timeout completes. This could result in the
539 * rx_clear false triggering. As a workaround we add delay an
540 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
541 * does not happen.
542 */
543 udelay(synthDelay + BASE_ACTIVATE_DELAY);
544 }
545
ar9003_hw_set_chain_masks(struct ath_hw * ah,u8 rx,u8 tx)546 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
547 {
548 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
549 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
550 AR_PHY_SWAP_ALT_CHAIN);
551
552 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
553 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
554
555 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
556 tx = 3;
557 else if (AR_SREV_9462(ah))
558 /* xxx only when MCI support is enabled */
559 tx = 3;
560
561 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
562 }
563
564 /*
565 * Override INI values with chip specific configuration.
566 */
ar9003_hw_override_ini(struct ath_hw * ah)567 static void ar9003_hw_override_ini(struct ath_hw *ah)
568 {
569 u32 val;
570
571 /*
572 * Set the RX_ABORT and RX_DIS and clear it only after
573 * RXE is set for MAC. This prevents frames with
574 * corrupted descriptor status.
575 */
576 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
577
578 /*
579 * For AR9280 and above, there is a new feature that allows
580 * Multicast search based on both MAC Address and Key ID. By default,
581 * this feature is enabled. But since the driver is not using this
582 * feature, we switch it off; otherwise multicast search based on
583 * MAC addr only will fail.
584 */
585 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
586 REG_WRITE(ah, AR_PCU_MISC_MODE2,
587 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
588
589 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
590 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
591 }
592
ar9003_hw_prog_ini(struct ath_hw * ah,struct ar5416IniArray * iniArr,int column)593 static void ar9003_hw_prog_ini(struct ath_hw *ah,
594 struct ar5416IniArray *iniArr,
595 int column)
596 {
597 unsigned int i, regWrites = 0;
598
599 /* New INI format: Array may be undefined (pre, core, post arrays) */
600 if (!iniArr->ia_array)
601 return;
602
603 /*
604 * New INI format: Pre, core, and post arrays for a given subsystem
605 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
606 * the array is non-modal and force the column to 1.
607 */
608 if (column >= iniArr->ia_columns)
609 column = 1;
610
611 for (i = 0; i < iniArr->ia_rows; i++) {
612 u32 reg = INI_RA(iniArr, i, 0);
613 u32 val = INI_RA(iniArr, i, column);
614
615 REG_WRITE(ah, reg, val);
616
617 DO_DELAY(regWrites);
618 }
619 }
620
ar9003_hw_process_ini(struct ath_hw * ah,struct ath9k_channel * chan)621 static int ar9003_hw_process_ini(struct ath_hw *ah,
622 struct ath9k_channel *chan)
623 {
624 unsigned int regWrites = 0, i;
625 u32 modesIndex;
626
627 switch (chan->chanmode) {
628 case CHANNEL_A:
629 case CHANNEL_A_HT20:
630 modesIndex = 1;
631 break;
632 case CHANNEL_A_HT40PLUS:
633 case CHANNEL_A_HT40MINUS:
634 modesIndex = 2;
635 break;
636 case CHANNEL_G:
637 case CHANNEL_G_HT20:
638 case CHANNEL_B:
639 modesIndex = 4;
640 break;
641 case CHANNEL_G_HT40PLUS:
642 case CHANNEL_G_HT40MINUS:
643 modesIndex = 3;
644 break;
645
646 default:
647 return -EINVAL;
648 }
649
650 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
651 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
652 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
653 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
654 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
655 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
656 ar9003_hw_prog_ini(ah,
657 &ah->ini_radio_post_sys2ant,
658 modesIndex);
659 }
660
661 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
662 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
663
664 /*
665 * For 5GHz channels requiring Fast Clock, apply
666 * different modal values.
667 */
668 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
669 REG_WRITE_ARRAY(&ah->iniModesFastClock,
670 modesIndex, regWrites);
671
672 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
673
674 if (AR_SREV_9462(ah))
675 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
676
677 if (chan->channel == 2484)
678 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
679
680 ah->modes_index = modesIndex;
681 ar9003_hw_override_ini(ah);
682 ar9003_hw_set_channel_regs(ah, chan);
683 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
684 ath9k_hw_apply_txpower(ah, chan, false);
685
686 if (AR_SREV_9462(ah)) {
687 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
688 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
689 ah->enabled_cals |= TX_IQ_CAL;
690 else
691 ah->enabled_cals &= ~TX_IQ_CAL;
692
693 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
694 ah->enabled_cals |= TX_CL_CAL;
695 else
696 ah->enabled_cals &= ~TX_CL_CAL;
697 }
698
699 return 0;
700 }
701
ar9003_hw_set_rfmode(struct ath_hw * ah,struct ath9k_channel * chan)702 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
703 struct ath9k_channel *chan)
704 {
705 u32 rfMode = 0;
706
707 if (chan == NULL)
708 return;
709
710 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
711 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
712
713 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
714 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
715
716 REG_WRITE(ah, AR_PHY_MODE, rfMode);
717 }
718
ar9003_hw_mark_phy_inactive(struct ath_hw * ah)719 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
720 {
721 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
722 }
723
ar9003_hw_set_delta_slope(struct ath_hw * ah,struct ath9k_channel * chan)724 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
725 struct ath9k_channel *chan)
726 {
727 u32 coef_scaled, ds_coef_exp, ds_coef_man;
728 u32 clockMhzScaled = 0x64000000;
729 struct chan_centers centers;
730
731 /*
732 * half and quarter rate can divide the scaled clock by 2 or 4
733 * scale for selected channel bandwidth
734 */
735 if (IS_CHAN_HALF_RATE(chan))
736 clockMhzScaled = clockMhzScaled >> 1;
737 else if (IS_CHAN_QUARTER_RATE(chan))
738 clockMhzScaled = clockMhzScaled >> 2;
739
740 /*
741 * ALGO -> coef = 1e8/fcarrier*fclock/40;
742 * scaled coef to provide precision for this floating calculation
743 */
744 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
745 coef_scaled = clockMhzScaled / centers.synth_center;
746
747 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
748 &ds_coef_exp);
749
750 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
751 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
752 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
753 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
754
755 /*
756 * For Short GI,
757 * scaled coeff is 9/10 that of normal coeff
758 */
759 coef_scaled = (9 * coef_scaled) / 10;
760
761 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
762 &ds_coef_exp);
763
764 /* for short gi */
765 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
766 AR_PHY_SGI_DSC_MAN, ds_coef_man);
767 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
768 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
769 }
770
ar9003_hw_rfbus_req(struct ath_hw * ah)771 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
772 {
773 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
774 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
775 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
776 }
777
778 /*
779 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
780 * Read the phy active delay register. Value is in 100ns increments.
781 */
ar9003_hw_rfbus_done(struct ath_hw * ah)782 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
783 {
784 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
785 if (IS_CHAN_B(ah->curchan))
786 synthDelay = (4 * synthDelay) / 22;
787 else
788 synthDelay /= 10;
789
790 udelay(synthDelay + BASE_ACTIVATE_DELAY);
791
792 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
793 }
794
ar9003_hw_ani_control(struct ath_hw * ah,enum ath9k_ani_cmd cmd,int param)795 static bool ar9003_hw_ani_control(struct ath_hw *ah,
796 enum ath9k_ani_cmd cmd, int param)
797 {
798 struct ath_common *common = ath9k_hw_common(ah);
799 struct ath9k_channel *chan = ah->curchan;
800 struct ar5416AniState *aniState = &chan->ani;
801 s32 value, value2;
802
803 switch (cmd & ah->ani_function) {
804 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
805 /*
806 * on == 1 means ofdm weak signal detection is ON
807 * on == 1 is the default, for less noise immunity
808 *
809 * on == 0 means ofdm weak signal detection is OFF
810 * on == 0 means more noise imm
811 */
812 u32 on = param ? 1 : 0;
813 /*
814 * make register setting for default
815 * (weak sig detect ON) come from INI file
816 */
817 int m1ThreshLow = on ?
818 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
819 int m2ThreshLow = on ?
820 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
821 int m1Thresh = on ?
822 aniState->iniDef.m1Thresh : m1Thresh_off;
823 int m2Thresh = on ?
824 aniState->iniDef.m2Thresh : m2Thresh_off;
825 int m2CountThr = on ?
826 aniState->iniDef.m2CountThr : m2CountThr_off;
827 int m2CountThrLow = on ?
828 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
829 int m1ThreshLowExt = on ?
830 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
831 int m2ThreshLowExt = on ?
832 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
833 int m1ThreshExt = on ?
834 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
835 int m2ThreshExt = on ?
836 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
837
838 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
839 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
840 m1ThreshLow);
841 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
842 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
843 m2ThreshLow);
844 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
845 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
846 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
847 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
848 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
849 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
850 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
851 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
852 m2CountThrLow);
853
854 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
855 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
856 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
857 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
858 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
859 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
860 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
861 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
862
863 if (on)
864 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
865 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
866 else
867 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
868 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
869
870 if (!on != aniState->ofdmWeakSigDetectOff) {
871 ath_dbg(common, ANI,
872 "** ch %d: ofdm weak signal: %s=>%s\n",
873 chan->channel,
874 !aniState->ofdmWeakSigDetectOff ?
875 "on" : "off",
876 on ? "on" : "off");
877 if (on)
878 ah->stats.ast_ani_ofdmon++;
879 else
880 ah->stats.ast_ani_ofdmoff++;
881 aniState->ofdmWeakSigDetectOff = !on;
882 }
883 break;
884 }
885 case ATH9K_ANI_FIRSTEP_LEVEL:{
886 u32 level = param;
887
888 if (level >= ARRAY_SIZE(firstep_table)) {
889 ath_dbg(common, ANI,
890 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
891 level, ARRAY_SIZE(firstep_table));
892 return false;
893 }
894
895 /*
896 * make register setting relative to default
897 * from INI file & cap value
898 */
899 value = firstep_table[level] -
900 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
901 aniState->iniDef.firstep;
902 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
903 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
904 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
905 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
906 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
907 AR_PHY_FIND_SIG_FIRSTEP,
908 value);
909 /*
910 * we need to set first step low register too
911 * make register setting relative to default
912 * from INI file & cap value
913 */
914 value2 = firstep_table[level] -
915 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
916 aniState->iniDef.firstepLow;
917 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
918 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
919 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
920 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
921
922 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
923 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
924
925 if (level != aniState->firstepLevel) {
926 ath_dbg(common, ANI,
927 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
928 chan->channel,
929 aniState->firstepLevel,
930 level,
931 ATH9K_ANI_FIRSTEP_LVL_NEW,
932 value,
933 aniState->iniDef.firstep);
934 ath_dbg(common, ANI,
935 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
936 chan->channel,
937 aniState->firstepLevel,
938 level,
939 ATH9K_ANI_FIRSTEP_LVL_NEW,
940 value2,
941 aniState->iniDef.firstepLow);
942 if (level > aniState->firstepLevel)
943 ah->stats.ast_ani_stepup++;
944 else if (level < aniState->firstepLevel)
945 ah->stats.ast_ani_stepdown++;
946 aniState->firstepLevel = level;
947 }
948 break;
949 }
950 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
951 u32 level = param;
952
953 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
954 ath_dbg(common, ANI,
955 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
956 level, ARRAY_SIZE(cycpwrThr1_table));
957 return false;
958 }
959 /*
960 * make register setting relative to default
961 * from INI file & cap value
962 */
963 value = cycpwrThr1_table[level] -
964 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
965 aniState->iniDef.cycpwrThr1;
966 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
967 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
968 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
969 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
970 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
971 AR_PHY_TIMING5_CYCPWR_THR1,
972 value);
973
974 /*
975 * set AR_PHY_EXT_CCA for extension channel
976 * make register setting relative to default
977 * from INI file & cap value
978 */
979 value2 = cycpwrThr1_table[level] -
980 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
981 aniState->iniDef.cycpwrThr1Ext;
982 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
983 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
984 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
985 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
986 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
987 AR_PHY_EXT_CYCPWR_THR1, value2);
988
989 if (level != aniState->spurImmunityLevel) {
990 ath_dbg(common, ANI,
991 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
992 chan->channel,
993 aniState->spurImmunityLevel,
994 level,
995 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
996 value,
997 aniState->iniDef.cycpwrThr1);
998 ath_dbg(common, ANI,
999 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1000 chan->channel,
1001 aniState->spurImmunityLevel,
1002 level,
1003 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1004 value2,
1005 aniState->iniDef.cycpwrThr1Ext);
1006 if (level > aniState->spurImmunityLevel)
1007 ah->stats.ast_ani_spurup++;
1008 else if (level < aniState->spurImmunityLevel)
1009 ah->stats.ast_ani_spurdown++;
1010 aniState->spurImmunityLevel = level;
1011 }
1012 break;
1013 }
1014 case ATH9K_ANI_MRC_CCK:{
1015 /*
1016 * is_on == 1 means MRC CCK ON (default, less noise imm)
1017 * is_on == 0 means MRC CCK is OFF (more noise imm)
1018 */
1019 bool is_on = param ? 1 : 0;
1020
1021 if (ah->caps.rx_chainmask == 1)
1022 break;
1023
1024 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1025 AR_PHY_MRC_CCK_ENABLE, is_on);
1026 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1027 AR_PHY_MRC_CCK_MUX_REG, is_on);
1028 if (!is_on != aniState->mrcCCKOff) {
1029 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1030 chan->channel,
1031 !aniState->mrcCCKOff ? "on" : "off",
1032 is_on ? "on" : "off");
1033 if (is_on)
1034 ah->stats.ast_ani_ccklow++;
1035 else
1036 ah->stats.ast_ani_cckhigh++;
1037 aniState->mrcCCKOff = !is_on;
1038 }
1039 break;
1040 }
1041 case ATH9K_ANI_PRESENT:
1042 break;
1043 default:
1044 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1045 return false;
1046 }
1047
1048 ath_dbg(common, ANI,
1049 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1050 aniState->spurImmunityLevel,
1051 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1052 aniState->firstepLevel,
1053 !aniState->mrcCCKOff ? "on" : "off",
1054 aniState->listenTime,
1055 aniState->ofdmPhyErrCount,
1056 aniState->cckPhyErrCount);
1057 return true;
1058 }
1059
ar9003_hw_do_getnf(struct ath_hw * ah,int16_t nfarray[NUM_NF_READINGS])1060 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1061 int16_t nfarray[NUM_NF_READINGS])
1062 {
1063 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1064 #define AR_PHY_CH_MINCCA_PWR_S 20
1065 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1066 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1067
1068 int16_t nf;
1069 int i;
1070
1071 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1072 if (ah->rxchainmask & BIT(i)) {
1073 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1074 AR_PHY_CH_MINCCA_PWR);
1075 nfarray[i] = sign_extend32(nf, 8);
1076
1077 if (IS_CHAN_HT40(ah->curchan)) {
1078 u8 ext_idx = AR9300_MAX_CHAINS + i;
1079
1080 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1081 AR_PHY_CH_EXT_MINCCA_PWR);
1082 nfarray[ext_idx] = sign_extend32(nf, 8);
1083 }
1084 }
1085 }
1086 }
1087
ar9003_hw_set_nf_limits(struct ath_hw * ah)1088 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1089 {
1090 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1091 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1092 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1093 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1094 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1095 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1096
1097 if (AR_SREV_9330(ah))
1098 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1099
1100 if (AR_SREV_9462(ah)) {
1101 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1102 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1103 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1104 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1105 }
1106 }
1107
1108 /*
1109 * Initialize the ANI register values with default (ini) values.
1110 * This routine is called during a (full) hardware reset after
1111 * all the registers are initialised from the INI.
1112 */
ar9003_hw_ani_cache_ini_regs(struct ath_hw * ah)1113 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1114 {
1115 struct ar5416AniState *aniState;
1116 struct ath_common *common = ath9k_hw_common(ah);
1117 struct ath9k_channel *chan = ah->curchan;
1118 struct ath9k_ani_default *iniDef;
1119 u32 val;
1120
1121 aniState = &ah->curchan->ani;
1122 iniDef = &aniState->iniDef;
1123
1124 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1125 ah->hw_version.macVersion,
1126 ah->hw_version.macRev,
1127 ah->opmode,
1128 chan->channel,
1129 chan->channelFlags);
1130
1131 val = REG_READ(ah, AR_PHY_SFCORR);
1132 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1133 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1134 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1135
1136 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1137 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1138 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1139 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1140
1141 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1142 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1143 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1144 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1145 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1146 iniDef->firstep = REG_READ_FIELD(ah,
1147 AR_PHY_FIND_SIG,
1148 AR_PHY_FIND_SIG_FIRSTEP);
1149 iniDef->firstepLow = REG_READ_FIELD(ah,
1150 AR_PHY_FIND_SIG_LOW,
1151 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1152 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1153 AR_PHY_TIMING5,
1154 AR_PHY_TIMING5_CYCPWR_THR1);
1155 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1156 AR_PHY_EXT_CCA,
1157 AR_PHY_EXT_CYCPWR_THR1);
1158
1159 /* these levels just got reset to defaults by the INI */
1160 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1161 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1162 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1163 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1164 }
1165
ar9003_hw_set_radar_params(struct ath_hw * ah,struct ath_hw_radar_conf * conf)1166 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1167 struct ath_hw_radar_conf *conf)
1168 {
1169 u32 radar_0 = 0, radar_1 = 0;
1170
1171 if (!conf) {
1172 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1173 return;
1174 }
1175
1176 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1177 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1178 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1179 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1180 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1181 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1182
1183 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1184 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1185 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1186 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1187 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1188
1189 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1190 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1191 if (conf->ext_channel)
1192 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1193 else
1194 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1195 }
1196
ar9003_hw_set_radar_conf(struct ath_hw * ah)1197 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1198 {
1199 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1200
1201 conf->fir_power = -28;
1202 conf->radar_rssi = 0;
1203 conf->pulse_height = 10;
1204 conf->pulse_rssi = 24;
1205 conf->pulse_inband = 8;
1206 conf->pulse_maxlen = 255;
1207 conf->pulse_inband_step = 12;
1208 conf->radar_inband = 8;
1209 }
1210
ar9003_hw_antdiv_comb_conf_get(struct ath_hw * ah,struct ath_hw_antcomb_conf * antconf)1211 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1212 struct ath_hw_antcomb_conf *antconf)
1213 {
1214 u32 regval;
1215
1216 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1217 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1218 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1219 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1220 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1221 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1222 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1223
1224 if (AR_SREV_9330_11(ah)) {
1225 antconf->lna1_lna2_delta = -9;
1226 antconf->div_group = 1;
1227 } else if (AR_SREV_9485(ah)) {
1228 antconf->lna1_lna2_delta = -9;
1229 antconf->div_group = 2;
1230 } else {
1231 antconf->lna1_lna2_delta = -3;
1232 antconf->div_group = 0;
1233 }
1234 }
1235
ar9003_hw_antdiv_comb_conf_set(struct ath_hw * ah,struct ath_hw_antcomb_conf * antconf)1236 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1237 struct ath_hw_antcomb_conf *antconf)
1238 {
1239 u32 regval;
1240
1241 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1242 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1243 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1244 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1245 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1246 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1247 regval |= ((antconf->main_lna_conf <<
1248 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1249 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1250 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1251 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1252 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1253 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1254 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1255 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1256 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1257 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1258
1259 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1260 }
1261
ar9003_hw_fast_chan_change(struct ath_hw * ah,struct ath9k_channel * chan,u8 * ini_reloaded)1262 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1263 struct ath9k_channel *chan,
1264 u8 *ini_reloaded)
1265 {
1266 unsigned int regWrites = 0;
1267 u32 modesIndex;
1268
1269 switch (chan->chanmode) {
1270 case CHANNEL_A:
1271 case CHANNEL_A_HT20:
1272 modesIndex = 1;
1273 break;
1274 case CHANNEL_A_HT40PLUS:
1275 case CHANNEL_A_HT40MINUS:
1276 modesIndex = 2;
1277 break;
1278 case CHANNEL_G:
1279 case CHANNEL_G_HT20:
1280 case CHANNEL_B:
1281 modesIndex = 4;
1282 break;
1283 case CHANNEL_G_HT40PLUS:
1284 case CHANNEL_G_HT40MINUS:
1285 modesIndex = 3;
1286 break;
1287
1288 default:
1289 return -EINVAL;
1290 }
1291
1292 if (modesIndex == ah->modes_index) {
1293 *ini_reloaded = false;
1294 goto set_rfmode;
1295 }
1296
1297 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1298 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1299 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1300 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1301 if (AR_SREV_9462_20(ah))
1302 ar9003_hw_prog_ini(ah,
1303 &ah->ini_radio_post_sys2ant,
1304 modesIndex);
1305
1306 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1307
1308 /*
1309 * For 5GHz channels requiring Fast Clock, apply
1310 * different modal values.
1311 */
1312 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1313 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1314
1315 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1316
1317 ah->modes_index = modesIndex;
1318 *ini_reloaded = true;
1319
1320 set_rfmode:
1321 ar9003_hw_set_rfmode(ah, chan);
1322 return 0;
1323 }
1324
ar9003_hw_attach_phy_ops(struct ath_hw * ah)1325 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1326 {
1327 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1328 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1329 static const u32 ar9300_cca_regs[6] = {
1330 AR_PHY_CCA_0,
1331 AR_PHY_CCA_1,
1332 AR_PHY_CCA_2,
1333 AR_PHY_EXT_CCA,
1334 AR_PHY_EXT_CCA_1,
1335 AR_PHY_EXT_CCA_2,
1336 };
1337
1338 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1339 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1340 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1341 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1342 priv_ops->init_bb = ar9003_hw_init_bb;
1343 priv_ops->process_ini = ar9003_hw_process_ini;
1344 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1345 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1346 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1347 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1348 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1349 priv_ops->ani_control = ar9003_hw_ani_control;
1350 priv_ops->do_getnf = ar9003_hw_do_getnf;
1351 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1352 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1353 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1354
1355 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1356 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1357
1358 ar9003_hw_set_nf_limits(ah);
1359 ar9003_hw_set_radar_conf(ah);
1360 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1361 }
1362
ar9003_hw_bb_watchdog_config(struct ath_hw * ah)1363 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1364 {
1365 struct ath_common *common = ath9k_hw_common(ah);
1366 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1367 u32 val, idle_count;
1368
1369 if (!idle_tmo_ms) {
1370 /* disable IRQ, disable chip-reset for BB panic */
1371 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1372 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1373 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1374 AR_PHY_WATCHDOG_IRQ_ENABLE));
1375
1376 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1377 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1378 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1379 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1380 AR_PHY_WATCHDOG_IDLE_ENABLE));
1381
1382 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1383 return;
1384 }
1385
1386 /* enable IRQ, disable chip-reset for BB watchdog */
1387 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1388 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1389 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1390 ~AR_PHY_WATCHDOG_RST_ENABLE);
1391
1392 /* bound limit to 10 secs */
1393 if (idle_tmo_ms > 10000)
1394 idle_tmo_ms = 10000;
1395
1396 /*
1397 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1398 *
1399 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1400 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1401 *
1402 * Given we use fast clock now in 5 GHz, these time units should
1403 * be common for both 2 GHz and 5 GHz.
1404 */
1405 idle_count = (100 * idle_tmo_ms) / 74;
1406 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1407 idle_count = (100 * idle_tmo_ms) / 37;
1408
1409 /*
1410 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1411 * set idle time-out.
1412 */
1413 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1414 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1415 AR_PHY_WATCHDOG_IDLE_MASK |
1416 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1417
1418 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1419 idle_tmo_ms);
1420 }
1421
ar9003_hw_bb_watchdog_read(struct ath_hw * ah)1422 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1423 {
1424 /*
1425 * we want to avoid printing in ISR context so we save the
1426 * watchdog status to be printed later in bottom half context.
1427 */
1428 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1429
1430 /*
1431 * the watchdog timer should reset on status read but to be sure
1432 * sure we write 0 to the watchdog status bit.
1433 */
1434 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1435 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1436 }
1437
ar9003_hw_bb_watchdog_dbg_info(struct ath_hw * ah)1438 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1439 {
1440 struct ath_common *common = ath9k_hw_common(ah);
1441 u32 status;
1442
1443 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1444 return;
1445
1446 status = ah->bb_watchdog_last_status;
1447 ath_dbg(common, RESET,
1448 "\n==== BB update: BB status=0x%08x ====\n", status);
1449 ath_dbg(common, RESET,
1450 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1451 MS(status, AR_PHY_WATCHDOG_INFO),
1452 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1453 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1454 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1455 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1456 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1457 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1458 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1459 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1460
1461 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1462 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1463 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1464 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1465 REG_READ(ah, AR_PHY_GEN_CTRL));
1466
1467 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1468 if (common->cc_survey.cycles)
1469 ath_dbg(common, RESET,
1470 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1471 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1472
1473 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1474 }
1475 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1476
ar9003_hw_disable_phy_restart(struct ath_hw * ah)1477 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1478 {
1479 u32 val;
1480
1481 /* While receiving unsupported rate frame rx state machine
1482 * gets into a state 0xb and if phy_restart happens in that
1483 * state, BB would go hang. If RXSM is in 0xb state after
1484 * first bb panic, ensure to disable the phy_restart.
1485 */
1486 if (!((MS(ah->bb_watchdog_last_status,
1487 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1488 ah->bb_hang_rx_ofdm))
1489 return;
1490
1491 ah->bb_hang_rx_ofdm = true;
1492 val = REG_READ(ah, AR_PHY_RESTART);
1493 val &= ~AR_PHY_RESTART_ENA;
1494
1495 REG_WRITE(ah, AR_PHY_RESTART, val);
1496 }
1497 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
1498