1 /*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "ar9003_phy.h"
19
20 static const int firstep_table[] =
21 /* level: 0 1 2 3 4 5 6 7 8 */
22 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
23
24 static const int cycpwrThr1_table[] =
25 /* level: 0 1 2 3 4 5 6 7 8 */
26 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
27
28 /*
29 * register values to turn OFDM weak signal detection OFF
30 */
31 static const int m1ThreshLow_off = 127;
32 static const int m2ThreshLow_off = 127;
33 static const int m1Thresh_off = 127;
34 static const int m2Thresh_off = 127;
35 static const int m2CountThr_off = 31;
36 static const int m2CountThrLow_off = 63;
37 static const int m1ThreshLowExt_off = 127;
38 static const int m2ThreshLowExt_off = 127;
39 static const int m1ThreshExt_off = 127;
40 static const int m2ThreshExt_off = 127;
41
42 /**
43 * ar9003_hw_set_channel - set channel on single-chip device
44 * @ah: atheros hardware structure
45 * @chan:
46 *
47 * This is the function to change channel on single-chip devices, that is
48 * all devices after ar9280.
49 *
50 * This function takes the channel value in MHz and sets
51 * hardware channel value. Assumes writes have been enabled to analog bus.
52 *
53 * Actual Expression,
54 *
55 * For 2GHz channel,
56 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
57 * (freq_ref = 40MHz)
58 *
59 * For 5GHz channel,
60 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
61 * (freq_ref = 40MHz/(24>>amodeRefSel))
62 *
63 * For 5GHz channels which are 5MHz spaced,
64 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65 * (freq_ref = 40MHz)
66 */
ar9003_hw_set_channel(struct ath_hw * ah,struct ath9k_channel * chan)67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68 {
69 u16 bMode, fracMode = 0, aModeRefSel = 0;
70 u32 freq, channelSel = 0, reg32 = 0;
71 struct chan_centers centers;
72 int loadSynthChannel;
73
74 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
75 freq = centers.synth_center;
76
77 if (freq < 4800) { /* 2 GHz, fractional mode */
78 if (AR_SREV_9485(ah))
79 channelSel = CHANSEL_2G_9485(freq);
80 else
81 channelSel = CHANSEL_2G(freq);
82 /* Set to 2G mode */
83 bMode = 1;
84 } else {
85 channelSel = CHANSEL_5G(freq);
86 /* Doubler is ON, so, divide channelSel by 2. */
87 channelSel >>= 1;
88 /* Set to 5G mode */
89 bMode = 0;
90 }
91
92 /* Enable fractional mode for all channels */
93 fracMode = 1;
94 aModeRefSel = 0;
95 loadSynthChannel = 0;
96
97 reg32 = (bMode << 29);
98 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
99
100 /* Enable Long shift Select for Synthesizer */
101 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
102 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
103
104 /* Program Synth. setting */
105 reg32 = (channelSel << 2) | (fracMode << 30) |
106 (aModeRefSel << 28) | (loadSynthChannel << 31);
107 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
108
109 /* Toggle Load Synth channel bit */
110 loadSynthChannel = 1;
111 reg32 = (channelSel << 2) | (fracMode << 30) |
112 (aModeRefSel << 28) | (loadSynthChannel << 31);
113 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
114
115 ah->curchan = chan;
116 ah->curchan_rad_index = -1;
117
118 return 0;
119 }
120
121 /**
122 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
123 * @ah: atheros hardware structure
124 * @chan:
125 *
126 * For single-chip solutions. Converts to baseband spur frequency given the
127 * input channel frequency and compute register settings below.
128 *
129 * Spur mitigation for MRC CCK
130 */
ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw * ah,struct ath9k_channel * chan)131 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
132 struct ath9k_channel *chan)
133 {
134 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
135 int cur_bb_spur, negative = 0, cck_spur_freq;
136 int i;
137 int range, max_spur_cnts, synth_freq;
138 u8 *spur_fbin_ptr = NULL;
139
140 /*
141 * Need to verify range +/- 10 MHz in control channel, otherwise spur
142 * is out-of-band and can be ignored.
143 */
144
145 if (AR_SREV_9485(ah)) {
146 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
147 IS_CHAN_2GHZ(chan));
148 if (spur_fbin_ptr[0] == 0) /* No spur */
149 return;
150 max_spur_cnts = 5;
151 if (IS_CHAN_HT40(chan)) {
152 range = 19;
153 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
154 AR_PHY_GC_DYN2040_PRI_CH) == 0)
155 synth_freq = chan->channel + 10;
156 else
157 synth_freq = chan->channel - 10;
158 } else {
159 range = 10;
160 synth_freq = chan->channel;
161 }
162 } else {
163 range = 10;
164 max_spur_cnts = 4;
165 synth_freq = chan->channel;
166 }
167
168 for (i = 0; i < max_spur_cnts; i++) {
169 negative = 0;
170 if (AR_SREV_9485(ah))
171 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
172 IS_CHAN_2GHZ(chan)) - synth_freq;
173 else
174 cur_bb_spur = spur_freq[i] - synth_freq;
175
176 if (cur_bb_spur < 0) {
177 negative = 1;
178 cur_bb_spur = -cur_bb_spur;
179 }
180 if (cur_bb_spur < range) {
181 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
182
183 if (negative == 1)
184 cck_spur_freq = -cck_spur_freq;
185
186 cck_spur_freq = cck_spur_freq & 0xfffff;
187
188 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
189 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
190 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
191 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
192 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
193 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
194 0x2);
195 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
196 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
197 0x1);
198 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
199 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
200 cck_spur_freq);
201
202 return;
203 }
204 }
205
206 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
207 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
208 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
209 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
210 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
211 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
212 }
213
214 /* Clean all spur register fields */
ar9003_hw_spur_ofdm_clear(struct ath_hw * ah)215 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
216 {
217 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
218 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
219 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
220 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
221 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
222 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
223 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
224 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
225 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
226 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
227 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
228 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
229 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
230 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
231 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
232 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
233 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
234 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
235
236 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
237 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
238 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
239 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
240 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
241 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
242 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
243 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
244 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
245 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
246 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
247 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
248 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
249 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
250 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
251 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
252 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
253 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
254 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
255 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
256 }
257
ar9003_hw_spur_ofdm(struct ath_hw * ah,int freq_offset,int spur_freq_sd,int spur_delta_phase,int spur_subchannel_sd)258 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
259 int freq_offset,
260 int spur_freq_sd,
261 int spur_delta_phase,
262 int spur_subchannel_sd)
263 {
264 int mask_index = 0;
265
266 /* OFDM Spur mitigation */
267 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
268 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
269 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
270 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
273 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
274 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
276 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
277 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
278 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
279 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
280 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
281 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
282 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
283 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
284 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
285
286 if (REG_READ_FIELD(ah, AR_PHY_MODE,
287 AR_PHY_MODE_DYNAMIC) == 0x1)
288 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
289 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
290
291 mask_index = (freq_offset << 4) / 5;
292 if (mask_index < 0)
293 mask_index = mask_index - 1;
294
295 mask_index = mask_index & 0x7f;
296
297 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
298 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
299 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
300 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
301 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
302 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
303 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
304 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
305 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
306 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
307 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
308 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
309 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
310 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
311 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
312 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
313 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
314 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
315 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
316 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
317 }
318
ar9003_hw_spur_ofdm_work(struct ath_hw * ah,struct ath9k_channel * chan,int freq_offset)319 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
320 struct ath9k_channel *chan,
321 int freq_offset)
322 {
323 int spur_freq_sd = 0;
324 int spur_subchannel_sd = 0;
325 int spur_delta_phase = 0;
326
327 if (IS_CHAN_HT40(chan)) {
328 if (freq_offset < 0) {
329 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
330 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
331 spur_subchannel_sd = 1;
332 else
333 spur_subchannel_sd = 0;
334
335 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
336
337 } else {
338 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
339 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
340 spur_subchannel_sd = 0;
341 else
342 spur_subchannel_sd = 1;
343
344 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
345
346 }
347
348 spur_delta_phase = (freq_offset << 17) / 5;
349
350 } else {
351 spur_subchannel_sd = 0;
352 spur_freq_sd = (freq_offset << 9) /11;
353 spur_delta_phase = (freq_offset << 18) / 5;
354 }
355
356 spur_freq_sd = spur_freq_sd & 0x3ff;
357 spur_delta_phase = spur_delta_phase & 0xfffff;
358
359 ar9003_hw_spur_ofdm(ah,
360 freq_offset,
361 spur_freq_sd,
362 spur_delta_phase,
363 spur_subchannel_sd);
364 }
365
366 /* Spur mitigation for OFDM */
ar9003_hw_spur_mitigate_ofdm(struct ath_hw * ah,struct ath9k_channel * chan)367 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
368 struct ath9k_channel *chan)
369 {
370 int synth_freq;
371 int range = 10;
372 int freq_offset = 0;
373 int mode;
374 u8* spurChansPtr;
375 unsigned int i;
376 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
377
378 if (IS_CHAN_5GHZ(chan)) {
379 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
380 mode = 0;
381 }
382 else {
383 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
384 mode = 1;
385 }
386
387 if (spurChansPtr[0] == 0)
388 return; /* No spur in the mode */
389
390 if (IS_CHAN_HT40(chan)) {
391 range = 19;
392 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
393 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
394 synth_freq = chan->channel - 10;
395 else
396 synth_freq = chan->channel + 10;
397 } else {
398 range = 10;
399 synth_freq = chan->channel;
400 }
401
402 ar9003_hw_spur_ofdm_clear(ah);
403
404 for (i = 0; spurChansPtr[i] && i < 5; i++) {
405 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
406 if (abs(freq_offset) < range) {
407 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
408 break;
409 }
410 }
411 }
412
ar9003_hw_spur_mitigate(struct ath_hw * ah,struct ath9k_channel * chan)413 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
414 struct ath9k_channel *chan)
415 {
416 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
417 ar9003_hw_spur_mitigate_ofdm(ah, chan);
418 }
419
ar9003_hw_compute_pll_control(struct ath_hw * ah,struct ath9k_channel * chan)420 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
421 struct ath9k_channel *chan)
422 {
423 u32 pll;
424
425 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
426
427 if (chan && IS_CHAN_HALF_RATE(chan))
428 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
429 else if (chan && IS_CHAN_QUARTER_RATE(chan))
430 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
431
432 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
433
434 return pll;
435 }
436
ar9003_hw_set_channel_regs(struct ath_hw * ah,struct ath9k_channel * chan)437 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
438 struct ath9k_channel *chan)
439 {
440 u32 phymode;
441 u32 enableDacFifo = 0;
442
443 enableDacFifo =
444 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
445
446 /* Enable 11n HT, 20 MHz */
447 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
448 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
449
450 /* Configure baseband for dynamic 20/40 operation */
451 if (IS_CHAN_HT40(chan)) {
452 phymode |= AR_PHY_GC_DYN2040_EN;
453 /* Configure control (primary) channel at +-10MHz */
454 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
455 (chan->chanmode == CHANNEL_G_HT40PLUS))
456 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
457
458 }
459
460 /* make sure we preserve INI settings */
461 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
462 /* turn off Green Field detection for STA for now */
463 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
464
465 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
466
467 /* Configure MAC for 20/40 operation */
468 ath9k_hw_set11nmac2040(ah);
469
470 /* global transmit timeout (25 TUs default)*/
471 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
472 /* carrier sense timeout */
473 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
474 }
475
ar9003_hw_init_bb(struct ath_hw * ah,struct ath9k_channel * chan)476 static void ar9003_hw_init_bb(struct ath_hw *ah,
477 struct ath9k_channel *chan)
478 {
479 u32 synthDelay;
480
481 /*
482 * Wait for the frequency synth to settle (synth goes on
483 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
484 * Value is in 100ns increments.
485 */
486 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
487 if (IS_CHAN_B(chan))
488 synthDelay = (4 * synthDelay) / 22;
489 else
490 synthDelay /= 10;
491
492 /* Activate the PHY (includes baseband activate + synthesizer on) */
493 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
494
495 /*
496 * There is an issue if the AP starts the calibration before
497 * the base band timeout completes. This could result in the
498 * rx_clear false triggering. As a workaround we add delay an
499 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
500 * does not happen.
501 */
502 udelay(synthDelay + BASE_ACTIVATE_DELAY);
503 }
504
ar9003_hw_set_chain_masks(struct ath_hw * ah,u8 rx,u8 tx)505 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
506 {
507 switch (rx) {
508 case 0x5:
509 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
510 AR_PHY_SWAP_ALT_CHAIN);
511 case 0x3:
512 case 0x1:
513 case 0x2:
514 case 0x7:
515 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
516 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
517 break;
518 default:
519 break;
520 }
521
522 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
523 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
524 else
525 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
526
527 if (tx == 0x5) {
528 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
529 AR_PHY_SWAP_ALT_CHAIN);
530 }
531 }
532
533 /*
534 * Override INI values with chip specific configuration.
535 */
ar9003_hw_override_ini(struct ath_hw * ah)536 static void ar9003_hw_override_ini(struct ath_hw *ah)
537 {
538 u32 val;
539
540 /*
541 * Set the RX_ABORT and RX_DIS and clear it only after
542 * RXE is set for MAC. This prevents frames with
543 * corrupted descriptor status.
544 */
545 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
546
547 /*
548 * For AR9280 and above, there is a new feature that allows
549 * Multicast search based on both MAC Address and Key ID. By default,
550 * this feature is enabled. But since the driver is not using this
551 * feature, we switch it off; otherwise multicast search based on
552 * MAC addr only will fail.
553 */
554 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
555 REG_WRITE(ah, AR_PCU_MISC_MODE2,
556 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
557 }
558
ar9003_hw_prog_ini(struct ath_hw * ah,struct ar5416IniArray * iniArr,int column)559 static void ar9003_hw_prog_ini(struct ath_hw *ah,
560 struct ar5416IniArray *iniArr,
561 int column)
562 {
563 unsigned int i, regWrites = 0;
564
565 /* New INI format: Array may be undefined (pre, core, post arrays) */
566 if (!iniArr->ia_array)
567 return;
568
569 /*
570 * New INI format: Pre, core, and post arrays for a given subsystem
571 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
572 * the array is non-modal and force the column to 1.
573 */
574 if (column >= iniArr->ia_columns)
575 column = 1;
576
577 for (i = 0; i < iniArr->ia_rows; i++) {
578 u32 reg = INI_RA(iniArr, i, 0);
579 u32 val = INI_RA(iniArr, i, column);
580
581 REG_WRITE(ah, reg, val);
582
583 DO_DELAY(regWrites);
584 }
585 }
586
ar9003_hw_process_ini(struct ath_hw * ah,struct ath9k_channel * chan)587 static int ar9003_hw_process_ini(struct ath_hw *ah,
588 struct ath9k_channel *chan)
589 {
590 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
591 unsigned int regWrites = 0, i;
592 struct ieee80211_channel *channel = chan->chan;
593 u32 modesIndex, freqIndex;
594
595 switch (chan->chanmode) {
596 case CHANNEL_A:
597 case CHANNEL_A_HT20:
598 modesIndex = 1;
599 freqIndex = 1;
600 break;
601 case CHANNEL_A_HT40PLUS:
602 case CHANNEL_A_HT40MINUS:
603 modesIndex = 2;
604 freqIndex = 1;
605 break;
606 case CHANNEL_G:
607 case CHANNEL_G_HT20:
608 case CHANNEL_B:
609 modesIndex = 4;
610 freqIndex = 2;
611 break;
612 case CHANNEL_G_HT40PLUS:
613 case CHANNEL_G_HT40MINUS:
614 modesIndex = 3;
615 freqIndex = 2;
616 break;
617
618 default:
619 return -EINVAL;
620 }
621
622 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
623 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
624 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
625 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
626 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
627 }
628
629 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
630 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
631
632 /*
633 * For 5GHz channels requiring Fast Clock, apply
634 * different modal values.
635 */
636 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
637 REG_WRITE_ARRAY(&ah->iniModesAdditional,
638 modesIndex, regWrites);
639
640 ar9003_hw_override_ini(ah);
641 ar9003_hw_set_channel_regs(ah, chan);
642 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
643
644 /* Set TX power */
645 ah->eep_ops->set_txpower(ah, chan,
646 ath9k_regd_get_ctl(regulatory, chan),
647 channel->max_antenna_gain * 2,
648 channel->max_power * 2,
649 min((u32) MAX_RATE_POWER,
650 (u32) regulatory->power_limit), false);
651
652 return 0;
653 }
654
ar9003_hw_set_rfmode(struct ath_hw * ah,struct ath9k_channel * chan)655 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
656 struct ath9k_channel *chan)
657 {
658 u32 rfMode = 0;
659
660 if (chan == NULL)
661 return;
662
663 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
664 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
665
666 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
667 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
668
669 REG_WRITE(ah, AR_PHY_MODE, rfMode);
670 }
671
ar9003_hw_mark_phy_inactive(struct ath_hw * ah)672 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
673 {
674 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
675 }
676
ar9003_hw_set_delta_slope(struct ath_hw * ah,struct ath9k_channel * chan)677 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
678 struct ath9k_channel *chan)
679 {
680 u32 coef_scaled, ds_coef_exp, ds_coef_man;
681 u32 clockMhzScaled = 0x64000000;
682 struct chan_centers centers;
683
684 /*
685 * half and quarter rate can divide the scaled clock by 2 or 4
686 * scale for selected channel bandwidth
687 */
688 if (IS_CHAN_HALF_RATE(chan))
689 clockMhzScaled = clockMhzScaled >> 1;
690 else if (IS_CHAN_QUARTER_RATE(chan))
691 clockMhzScaled = clockMhzScaled >> 2;
692
693 /*
694 * ALGO -> coef = 1e8/fcarrier*fclock/40;
695 * scaled coef to provide precision for this floating calculation
696 */
697 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
698 coef_scaled = clockMhzScaled / centers.synth_center;
699
700 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
701 &ds_coef_exp);
702
703 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
704 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
705 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
706 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
707
708 /*
709 * For Short GI,
710 * scaled coeff is 9/10 that of normal coeff
711 */
712 coef_scaled = (9 * coef_scaled) / 10;
713
714 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
715 &ds_coef_exp);
716
717 /* for short gi */
718 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
719 AR_PHY_SGI_DSC_MAN, ds_coef_man);
720 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
721 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
722 }
723
ar9003_hw_rfbus_req(struct ath_hw * ah)724 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
725 {
726 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
727 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
728 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
729 }
730
731 /*
732 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
733 * Read the phy active delay register. Value is in 100ns increments.
734 */
ar9003_hw_rfbus_done(struct ath_hw * ah)735 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
736 {
737 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
738 if (IS_CHAN_B(ah->curchan))
739 synthDelay = (4 * synthDelay) / 22;
740 else
741 synthDelay /= 10;
742
743 udelay(synthDelay + BASE_ACTIVATE_DELAY);
744
745 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
746 }
747
ar9003_hw_set_diversity(struct ath_hw * ah,bool value)748 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
749 {
750 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
751 if (value)
752 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
753 else
754 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
755 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
756 }
757
ar9003_hw_ani_control(struct ath_hw * ah,enum ath9k_ani_cmd cmd,int param)758 static bool ar9003_hw_ani_control(struct ath_hw *ah,
759 enum ath9k_ani_cmd cmd, int param)
760 {
761 struct ath_common *common = ath9k_hw_common(ah);
762 struct ath9k_channel *chan = ah->curchan;
763 struct ar5416AniState *aniState = &chan->ani;
764 s32 value, value2;
765
766 switch (cmd & ah->ani_function) {
767 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
768 /*
769 * on == 1 means ofdm weak signal detection is ON
770 * on == 1 is the default, for less noise immunity
771 *
772 * on == 0 means ofdm weak signal detection is OFF
773 * on == 0 means more noise imm
774 */
775 u32 on = param ? 1 : 0;
776 /*
777 * make register setting for default
778 * (weak sig detect ON) come from INI file
779 */
780 int m1ThreshLow = on ?
781 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
782 int m2ThreshLow = on ?
783 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
784 int m1Thresh = on ?
785 aniState->iniDef.m1Thresh : m1Thresh_off;
786 int m2Thresh = on ?
787 aniState->iniDef.m2Thresh : m2Thresh_off;
788 int m2CountThr = on ?
789 aniState->iniDef.m2CountThr : m2CountThr_off;
790 int m2CountThrLow = on ?
791 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
792 int m1ThreshLowExt = on ?
793 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
794 int m2ThreshLowExt = on ?
795 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
796 int m1ThreshExt = on ?
797 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
798 int m2ThreshExt = on ?
799 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
800
801 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
802 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
803 m1ThreshLow);
804 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
805 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
806 m2ThreshLow);
807 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
808 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
809 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
810 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
811 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
812 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
813 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
814 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
815 m2CountThrLow);
816
817 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
818 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
819 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
820 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
821 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
822 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
823 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
824 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
825
826 if (on)
827 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
828 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
829 else
830 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
831 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
832
833 if (!on != aniState->ofdmWeakSigDetectOff) {
834 ath_dbg(common, ATH_DBG_ANI,
835 "** ch %d: ofdm weak signal: %s=>%s\n",
836 chan->channel,
837 !aniState->ofdmWeakSigDetectOff ?
838 "on" : "off",
839 on ? "on" : "off");
840 if (on)
841 ah->stats.ast_ani_ofdmon++;
842 else
843 ah->stats.ast_ani_ofdmoff++;
844 aniState->ofdmWeakSigDetectOff = !on;
845 }
846 break;
847 }
848 case ATH9K_ANI_FIRSTEP_LEVEL:{
849 u32 level = param;
850
851 if (level >= ARRAY_SIZE(firstep_table)) {
852 ath_dbg(common, ATH_DBG_ANI,
853 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
854 level, ARRAY_SIZE(firstep_table));
855 return false;
856 }
857
858 /*
859 * make register setting relative to default
860 * from INI file & cap value
861 */
862 value = firstep_table[level] -
863 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
864 aniState->iniDef.firstep;
865 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
866 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
867 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
868 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
869 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
870 AR_PHY_FIND_SIG_FIRSTEP,
871 value);
872 /*
873 * we need to set first step low register too
874 * make register setting relative to default
875 * from INI file & cap value
876 */
877 value2 = firstep_table[level] -
878 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
879 aniState->iniDef.firstepLow;
880 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
881 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
882 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
883 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
884
885 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
886 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
887
888 if (level != aniState->firstepLevel) {
889 ath_dbg(common, ATH_DBG_ANI,
890 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
891 chan->channel,
892 aniState->firstepLevel,
893 level,
894 ATH9K_ANI_FIRSTEP_LVL_NEW,
895 value,
896 aniState->iniDef.firstep);
897 ath_dbg(common, ATH_DBG_ANI,
898 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
899 chan->channel,
900 aniState->firstepLevel,
901 level,
902 ATH9K_ANI_FIRSTEP_LVL_NEW,
903 value2,
904 aniState->iniDef.firstepLow);
905 if (level > aniState->firstepLevel)
906 ah->stats.ast_ani_stepup++;
907 else if (level < aniState->firstepLevel)
908 ah->stats.ast_ani_stepdown++;
909 aniState->firstepLevel = level;
910 }
911 break;
912 }
913 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
914 u32 level = param;
915
916 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
917 ath_dbg(common, ATH_DBG_ANI,
918 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
919 level, ARRAY_SIZE(cycpwrThr1_table));
920 return false;
921 }
922 /*
923 * make register setting relative to default
924 * from INI file & cap value
925 */
926 value = cycpwrThr1_table[level] -
927 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
928 aniState->iniDef.cycpwrThr1;
929 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
930 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
931 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
932 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
933 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
934 AR_PHY_TIMING5_CYCPWR_THR1,
935 value);
936
937 /*
938 * set AR_PHY_EXT_CCA for extension channel
939 * make register setting relative to default
940 * from INI file & cap value
941 */
942 value2 = cycpwrThr1_table[level] -
943 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
944 aniState->iniDef.cycpwrThr1Ext;
945 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
946 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
947 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
948 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
949 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
950 AR_PHY_EXT_CYCPWR_THR1, value2);
951
952 if (level != aniState->spurImmunityLevel) {
953 ath_dbg(common, ATH_DBG_ANI,
954 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
955 chan->channel,
956 aniState->spurImmunityLevel,
957 level,
958 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
959 value,
960 aniState->iniDef.cycpwrThr1);
961 ath_dbg(common, ATH_DBG_ANI,
962 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
963 chan->channel,
964 aniState->spurImmunityLevel,
965 level,
966 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
967 value2,
968 aniState->iniDef.cycpwrThr1Ext);
969 if (level > aniState->spurImmunityLevel)
970 ah->stats.ast_ani_spurup++;
971 else if (level < aniState->spurImmunityLevel)
972 ah->stats.ast_ani_spurdown++;
973 aniState->spurImmunityLevel = level;
974 }
975 break;
976 }
977 case ATH9K_ANI_MRC_CCK:{
978 /*
979 * is_on == 1 means MRC CCK ON (default, less noise imm)
980 * is_on == 0 means MRC CCK is OFF (more noise imm)
981 */
982 bool is_on = param ? 1 : 0;
983 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
984 AR_PHY_MRC_CCK_ENABLE, is_on);
985 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
986 AR_PHY_MRC_CCK_MUX_REG, is_on);
987 if (!is_on != aniState->mrcCCKOff) {
988 ath_dbg(common, ATH_DBG_ANI,
989 "** ch %d: MRC CCK: %s=>%s\n",
990 chan->channel,
991 !aniState->mrcCCKOff ? "on" : "off",
992 is_on ? "on" : "off");
993 if (is_on)
994 ah->stats.ast_ani_ccklow++;
995 else
996 ah->stats.ast_ani_cckhigh++;
997 aniState->mrcCCKOff = !is_on;
998 }
999 break;
1000 }
1001 case ATH9K_ANI_PRESENT:
1002 break;
1003 default:
1004 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1005 return false;
1006 }
1007
1008 ath_dbg(common, ATH_DBG_ANI,
1009 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1010 aniState->spurImmunityLevel,
1011 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1012 aniState->firstepLevel,
1013 !aniState->mrcCCKOff ? "on" : "off",
1014 aniState->listenTime,
1015 aniState->ofdmPhyErrCount,
1016 aniState->cckPhyErrCount);
1017 return true;
1018 }
1019
ar9003_hw_do_getnf(struct ath_hw * ah,int16_t nfarray[NUM_NF_READINGS])1020 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1021 int16_t nfarray[NUM_NF_READINGS])
1022 {
1023 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1024 #define AR_PHY_CH_MINCCA_PWR_S 20
1025 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1026 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1027
1028 int16_t nf;
1029 int i;
1030
1031 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1032 if (ah->rxchainmask & BIT(i)) {
1033 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1034 AR_PHY_CH_MINCCA_PWR);
1035 nfarray[i] = sign_extend32(nf, 8);
1036
1037 if (IS_CHAN_HT40(ah->curchan)) {
1038 u8 ext_idx = AR9300_MAX_CHAINS + i;
1039
1040 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1041 AR_PHY_CH_EXT_MINCCA_PWR);
1042 nfarray[ext_idx] = sign_extend32(nf, 8);
1043 }
1044 }
1045 }
1046 }
1047
ar9003_hw_set_nf_limits(struct ath_hw * ah)1048 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1049 {
1050 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1051 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1052 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1053 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1054 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1055 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1056 }
1057
1058 /*
1059 * Initialize the ANI register values with default (ini) values.
1060 * This routine is called during a (full) hardware reset after
1061 * all the registers are initialised from the INI.
1062 */
ar9003_hw_ani_cache_ini_regs(struct ath_hw * ah)1063 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1064 {
1065 struct ar5416AniState *aniState;
1066 struct ath_common *common = ath9k_hw_common(ah);
1067 struct ath9k_channel *chan = ah->curchan;
1068 struct ath9k_ani_default *iniDef;
1069 u32 val;
1070
1071 aniState = &ah->curchan->ani;
1072 iniDef = &aniState->iniDef;
1073
1074 ath_dbg(common, ATH_DBG_ANI,
1075 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1076 ah->hw_version.macVersion,
1077 ah->hw_version.macRev,
1078 ah->opmode,
1079 chan->channel,
1080 chan->channelFlags);
1081
1082 val = REG_READ(ah, AR_PHY_SFCORR);
1083 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1084 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1085 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1086
1087 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1088 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1089 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1090 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1091
1092 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1093 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1094 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1095 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1096 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1097 iniDef->firstep = REG_READ_FIELD(ah,
1098 AR_PHY_FIND_SIG,
1099 AR_PHY_FIND_SIG_FIRSTEP);
1100 iniDef->firstepLow = REG_READ_FIELD(ah,
1101 AR_PHY_FIND_SIG_LOW,
1102 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1103 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1104 AR_PHY_TIMING5,
1105 AR_PHY_TIMING5_CYCPWR_THR1);
1106 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1107 AR_PHY_EXT_CCA,
1108 AR_PHY_EXT_CYCPWR_THR1);
1109
1110 /* these levels just got reset to defaults by the INI */
1111 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1112 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1113 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1114 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1115 }
1116
ar9003_hw_set_radar_params(struct ath_hw * ah,struct ath_hw_radar_conf * conf)1117 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1118 struct ath_hw_radar_conf *conf)
1119 {
1120 u32 radar_0 = 0, radar_1 = 0;
1121
1122 if (!conf) {
1123 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1124 return;
1125 }
1126
1127 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1128 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1129 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1130 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1131 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1132 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1133
1134 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1135 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1136 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1137 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1138 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1139
1140 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1141 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1142 if (conf->ext_channel)
1143 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1144 else
1145 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1146 }
1147
ar9003_hw_set_radar_conf(struct ath_hw * ah)1148 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1149 {
1150 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1151
1152 conf->fir_power = -28;
1153 conf->radar_rssi = 0;
1154 conf->pulse_height = 10;
1155 conf->pulse_rssi = 24;
1156 conf->pulse_inband = 8;
1157 conf->pulse_maxlen = 255;
1158 conf->pulse_inband_step = 12;
1159 conf->radar_inband = 8;
1160 }
1161
ar9003_hw_attach_phy_ops(struct ath_hw * ah)1162 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1163 {
1164 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1165 static const u32 ar9300_cca_regs[6] = {
1166 AR_PHY_CCA_0,
1167 AR_PHY_CCA_1,
1168 AR_PHY_CCA_2,
1169 AR_PHY_EXT_CCA,
1170 AR_PHY_EXT_CCA_1,
1171 AR_PHY_EXT_CCA_2,
1172 };
1173
1174 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1175 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1176 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1177 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1178 priv_ops->init_bb = ar9003_hw_init_bb;
1179 priv_ops->process_ini = ar9003_hw_process_ini;
1180 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1181 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1182 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1183 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1184 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1185 priv_ops->set_diversity = ar9003_hw_set_diversity;
1186 priv_ops->ani_control = ar9003_hw_ani_control;
1187 priv_ops->do_getnf = ar9003_hw_do_getnf;
1188 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1189 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1190
1191 ar9003_hw_set_nf_limits(ah);
1192 ar9003_hw_set_radar_conf(ah);
1193 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1194 }
1195
ar9003_hw_bb_watchdog_config(struct ath_hw * ah)1196 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1197 {
1198 struct ath_common *common = ath9k_hw_common(ah);
1199 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1200 u32 val, idle_count;
1201
1202 if (!idle_tmo_ms) {
1203 /* disable IRQ, disable chip-reset for BB panic */
1204 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1205 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1206 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1207 AR_PHY_WATCHDOG_IRQ_ENABLE));
1208
1209 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1210 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1211 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1212 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1213 AR_PHY_WATCHDOG_IDLE_ENABLE));
1214
1215 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1216 return;
1217 }
1218
1219 /* enable IRQ, disable chip-reset for BB watchdog */
1220 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1221 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1222 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1223 ~AR_PHY_WATCHDOG_RST_ENABLE);
1224
1225 /* bound limit to 10 secs */
1226 if (idle_tmo_ms > 10000)
1227 idle_tmo_ms = 10000;
1228
1229 /*
1230 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1231 *
1232 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1233 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1234 *
1235 * Given we use fast clock now in 5 GHz, these time units should
1236 * be common for both 2 GHz and 5 GHz.
1237 */
1238 idle_count = (100 * idle_tmo_ms) / 74;
1239 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1240 idle_count = (100 * idle_tmo_ms) / 37;
1241
1242 /*
1243 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1244 * set idle time-out.
1245 */
1246 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1247 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1248 AR_PHY_WATCHDOG_IDLE_MASK |
1249 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1250
1251 ath_dbg(common, ATH_DBG_RESET,
1252 "Enabled BB Watchdog timeout (%u ms)\n",
1253 idle_tmo_ms);
1254 }
1255
ar9003_hw_bb_watchdog_read(struct ath_hw * ah)1256 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1257 {
1258 /*
1259 * we want to avoid printing in ISR context so we save the
1260 * watchdog status to be printed later in bottom half context.
1261 */
1262 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1263
1264 /*
1265 * the watchdog timer should reset on status read but to be sure
1266 * sure we write 0 to the watchdog status bit.
1267 */
1268 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1269 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1270 }
1271
ar9003_hw_bb_watchdog_dbg_info(struct ath_hw * ah)1272 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1273 {
1274 struct ath_common *common = ath9k_hw_common(ah);
1275 u32 status;
1276
1277 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1278 return;
1279
1280 status = ah->bb_watchdog_last_status;
1281 ath_dbg(common, ATH_DBG_RESET,
1282 "\n==== BB update: BB status=0x%08x ====\n", status);
1283 ath_dbg(common, ATH_DBG_RESET,
1284 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1285 MS(status, AR_PHY_WATCHDOG_INFO),
1286 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1287 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1288 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1289 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1290 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1291 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1292 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1293 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1294
1295 ath_dbg(common, ATH_DBG_RESET,
1296 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1297 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1298 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1299 ath_dbg(common, ATH_DBG_RESET,
1300 "** BB mode: BB_gen_controls=0x%08x **\n",
1301 REG_READ(ah, AR_PHY_GEN_CTRL));
1302
1303 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1304 if (common->cc_survey.cycles)
1305 ath_dbg(common, ATH_DBG_RESET,
1306 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1307 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1308
1309 ath_dbg(common, ATH_DBG_RESET,
1310 "==== BB update: done ====\n\n");
1311 }
1312 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1313