1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "ar9003_mac.h"
19 #include "ar9003_2p2_initvals.h"
20 #include "ar9485_initvals.h"
21 #include "ar9340_initvals.h"
22 #include "ar9330_1p1_initvals.h"
23 #include "ar9330_1p2_initvals.h"
24 #include "ar9580_1p0_initvals.h"
25 #include "ar9462_2p0_initvals.h"
26
27 /* General hardware code for the AR9003 hadware family */
28
29 /*
30 * The AR9003 family uses a new INI format (pre, core, post
31 * arrays per subsystem). This provides support for the
32 * AR9003 2.2 chipsets.
33 */
ar9003_hw_init_mode_regs(struct ath_hw * ah)34 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
35 {
36 #define AR9462_BB_CTX_COEFJ(x) \
37 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
38
39 #define AR9462_BBC_TXIFR_COEFFJ \
40 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
41 if (AR_SREV_9330_11(ah)) {
42 /* mac */
43 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
44 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
45 ar9331_1p1_mac_core,
46 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
48 ar9331_1p1_mac_postamble,
49 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
50
51 /* bb */
52 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
54 ar9331_1p1_baseband_core,
55 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
57 ar9331_1p1_baseband_postamble,
58 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
59
60 /* radio */
61 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
62 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
63 ar9331_1p1_radio_core,
64 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
66
67 /* soc */
68 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
69 ar9331_1p1_soc_preamble,
70 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
71 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
72 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
73 ar9331_1p1_soc_postamble,
74 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
75
76 /* rx/tx gain */
77 INIT_INI_ARRAY(&ah->iniModesRxGain,
78 ar9331_common_rx_gain_1p1,
79 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
80 INIT_INI_ARRAY(&ah->iniModesTxGain,
81 ar9331_modes_lowest_ob_db_tx_gain_1p1,
82 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
83 5);
84
85 /* additional clock settings */
86 if (ah->is_clk_25mhz)
87 INIT_INI_ARRAY(&ah->iniAdditional,
88 ar9331_1p1_xtal_25M,
89 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
90 else
91 INIT_INI_ARRAY(&ah->iniAdditional,
92 ar9331_1p1_xtal_40M,
93 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
94 } else if (AR_SREV_9330_12(ah)) {
95 /* mac */
96 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
97 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
98 ar9331_1p2_mac_core,
99 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
100 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
101 ar9331_1p2_mac_postamble,
102 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
103
104 /* bb */
105 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
106 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
107 ar9331_1p2_baseband_core,
108 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
109 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
110 ar9331_1p2_baseband_postamble,
111 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
112
113 /* radio */
114 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
115 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
116 ar9331_1p2_radio_core,
117 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
118 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
119
120 /* soc */
121 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
122 ar9331_1p2_soc_preamble,
123 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
124 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
125 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
126 ar9331_1p2_soc_postamble,
127 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
128
129 /* rx/tx gain */
130 INIT_INI_ARRAY(&ah->iniModesRxGain,
131 ar9331_common_rx_gain_1p2,
132 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
133 INIT_INI_ARRAY(&ah->iniModesTxGain,
134 ar9331_modes_lowest_ob_db_tx_gain_1p2,
135 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
136 5);
137
138 /* additional clock settings */
139 if (ah->is_clk_25mhz)
140 INIT_INI_ARRAY(&ah->iniAdditional,
141 ar9331_1p2_xtal_25M,
142 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
143 else
144 INIT_INI_ARRAY(&ah->iniAdditional,
145 ar9331_1p2_xtal_40M,
146 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
147 } else if (AR_SREV_9340(ah)) {
148 /* mac */
149 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
150 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
151 ar9340_1p0_mac_core,
152 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
154 ar9340_1p0_mac_postamble,
155 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
156
157 /* bb */
158 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
159 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
160 ar9340_1p0_baseband_core,
161 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
163 ar9340_1p0_baseband_postamble,
164 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
165
166 /* radio */
167 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
168 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
169 ar9340_1p0_radio_core,
170 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
172 ar9340_1p0_radio_postamble,
173 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
174
175 /* soc */
176 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
177 ar9340_1p0_soc_preamble,
178 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
179 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
180 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
181 ar9340_1p0_soc_postamble,
182 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
183
184 /* rx/tx gain */
185 INIT_INI_ARRAY(&ah->iniModesRxGain,
186 ar9340Common_wo_xlna_rx_gain_table_1p0,
187 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
188 5);
189 INIT_INI_ARRAY(&ah->iniModesTxGain,
190 ar9340Modes_high_ob_db_tx_gain_table_1p0,
191 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
192 5);
193
194 INIT_INI_ARRAY(&ah->iniModesFastClock,
195 ar9340Modes_fast_clock_1p0,
196 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
197 3);
198
199 if (!ah->is_clk_25mhz)
200 INIT_INI_ARRAY(&ah->iniAdditional,
201 ar9340_1p0_radio_core_40M,
202 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
203 2);
204 } else if (AR_SREV_9485_11(ah)) {
205 /* mac */
206 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
207 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
208 ar9485_1_1_mac_core,
209 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
211 ar9485_1_1_mac_postamble,
212 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
213
214 /* bb */
215 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
216 ARRAY_SIZE(ar9485_1_1), 2);
217 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
218 ar9485_1_1_baseband_core,
219 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
220 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
221 ar9485_1_1_baseband_postamble,
222 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
223
224 /* radio */
225 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
226 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
227 ar9485_1_1_radio_core,
228 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
229 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
230 ar9485_1_1_radio_postamble,
231 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
232
233 /* soc */
234 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
235 ar9485_1_1_soc_preamble,
236 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
237 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
238 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
239
240 /* rx/tx gain */
241 INIT_INI_ARRAY(&ah->iniModesRxGain,
242 ar9485Common_wo_xlna_rx_gain_1_1,
243 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
244 INIT_INI_ARRAY(&ah->iniModesTxGain,
245 ar9485_modes_lowest_ob_db_tx_gain_1_1,
246 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
247 5);
248
249 /* Load PCIE SERDES settings from INI */
250
251 /* Awake Setting */
252
253 INIT_INI_ARRAY(&ah->iniPcieSerdes,
254 ar9485_1_1_pcie_phy_clkreq_disable_L1,
255 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
256 2);
257
258 /* Sleep Setting */
259
260 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
261 ar9485_1_1_pcie_phy_clkreq_disable_L1,
262 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
263 2);
264 } else if (AR_SREV_9462_20(ah)) {
265
266 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
267 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
268 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
270 ar9462_2p0_mac_postamble,
271 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
272
273 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
274 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
275 ar9462_2p0_baseband_core,
276 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
278 ar9462_2p0_baseband_postamble,
279 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
280
281 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
282 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
283 ar9462_2p0_radio_core,
284 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
286 ar9462_2p0_radio_postamble,
287 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
288 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
289 ar9462_2p0_radio_postamble_sys2ant,
290 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
291 5);
292
293 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
294 ar9462_2p0_soc_preamble,
295 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
298 ar9462_2p0_soc_postamble,
299 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
300
301 INIT_INI_ARRAY(&ah->iniModesRxGain,
302 ar9462_common_rx_gain_table_2p0,
303 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
304
305 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
306 ar9462_2p0_BTCOEX_MAX_TXPWR_table,
307 ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
308 2);
309
310 /* Awake -> Sleep Setting */
311 INIT_INI_ARRAY(&ah->iniPcieSerdes,
312 ar9462_pciephy_clkreq_disable_L1_2p0,
313 ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0),
314 2);
315 /* Sleep -> Awake Setting */
316 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
317 ar9462_pciephy_clkreq_disable_L1_2p0,
318 ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0),
319 2);
320
321 /* Fast clock modal settings */
322 INIT_INI_ARRAY(&ah->iniModesFastClock,
323 ar9462_modes_fast_clock_2p0,
324 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
325
326 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
327 AR9462_BB_CTX_COEFJ(2p0),
328 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
329
330 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
331 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
332
333 } else if (AR_SREV_9580(ah)) {
334 /* mac */
335 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
336 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
337 ar9580_1p0_mac_core,
338 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
339 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
340 ar9580_1p0_mac_postamble,
341 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
342
343 /* bb */
344 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
345 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
346 ar9580_1p0_baseband_core,
347 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
348 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
349 ar9580_1p0_baseband_postamble,
350 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
351
352 /* radio */
353 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
354 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
355 ar9580_1p0_radio_core,
356 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
357 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
358 ar9580_1p0_radio_postamble,
359 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
360
361 /* soc */
362 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
363 ar9580_1p0_soc_preamble,
364 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
365 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
366 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
367 ar9580_1p0_soc_postamble,
368 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
369
370 /* rx/tx gain */
371 INIT_INI_ARRAY(&ah->iniModesRxGain,
372 ar9580_1p0_rx_gain_table,
373 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
374 INIT_INI_ARRAY(&ah->iniModesTxGain,
375 ar9580_1p0_low_ob_db_tx_gain_table,
376 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
377 5);
378
379 INIT_INI_ARRAY(&ah->iniModesFastClock,
380 ar9580_1p0_modes_fast_clock,
381 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
382 3);
383 } else {
384 /* mac */
385 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
386 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
387 ar9300_2p2_mac_core,
388 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
389 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
390 ar9300_2p2_mac_postamble,
391 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
392
393 /* bb */
394 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
395 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
396 ar9300_2p2_baseband_core,
397 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
398 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
399 ar9300_2p2_baseband_postamble,
400 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
401
402 /* radio */
403 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
404 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
405 ar9300_2p2_radio_core,
406 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
407 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
408 ar9300_2p2_radio_postamble,
409 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
410
411 /* soc */
412 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
413 ar9300_2p2_soc_preamble,
414 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
415 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
416 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
417 ar9300_2p2_soc_postamble,
418 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
419
420 /* rx/tx gain */
421 INIT_INI_ARRAY(&ah->iniModesRxGain,
422 ar9300Common_rx_gain_table_2p2,
423 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
424 INIT_INI_ARRAY(&ah->iniModesTxGain,
425 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
426 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
427 5);
428
429 /* Load PCIE SERDES settings from INI */
430
431 /* Awake Setting */
432
433 INIT_INI_ARRAY(&ah->iniPcieSerdes,
434 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
435 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
436 2);
437
438 /* Sleep Setting */
439
440 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
441 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
442 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
443 2);
444
445 /* Fast clock modal settings */
446 INIT_INI_ARRAY(&ah->iniModesFastClock,
447 ar9300Modes_fast_clock_2p2,
448 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
449 3);
450 }
451 }
452
ar9003_tx_gain_table_mode0(struct ath_hw * ah)453 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
454 {
455 if (AR_SREV_9330_12(ah))
456 INIT_INI_ARRAY(&ah->iniModesTxGain,
457 ar9331_modes_lowest_ob_db_tx_gain_1p2,
458 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
459 5);
460 else if (AR_SREV_9330_11(ah))
461 INIT_INI_ARRAY(&ah->iniModesTxGain,
462 ar9331_modes_lowest_ob_db_tx_gain_1p1,
463 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
464 5);
465 else if (AR_SREV_9340(ah))
466 INIT_INI_ARRAY(&ah->iniModesTxGain,
467 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
468 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
469 5);
470 else if (AR_SREV_9485_11(ah))
471 INIT_INI_ARRAY(&ah->iniModesTxGain,
472 ar9485_modes_lowest_ob_db_tx_gain_1_1,
473 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
474 5);
475 else if (AR_SREV_9580(ah))
476 INIT_INI_ARRAY(&ah->iniModesTxGain,
477 ar9580_1p0_lowest_ob_db_tx_gain_table,
478 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
479 5);
480 else if (AR_SREV_9462_20(ah))
481 INIT_INI_ARRAY(&ah->iniModesTxGain,
482 ar9462_modes_low_ob_db_tx_gain_table_2p0,
483 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
484 5);
485 else
486 INIT_INI_ARRAY(&ah->iniModesTxGain,
487 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
488 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
489 5);
490 }
491
ar9003_tx_gain_table_mode1(struct ath_hw * ah)492 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
493 {
494 if (AR_SREV_9330_12(ah))
495 INIT_INI_ARRAY(&ah->iniModesTxGain,
496 ar9331_modes_high_ob_db_tx_gain_1p2,
497 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
498 5);
499 else if (AR_SREV_9330_11(ah))
500 INIT_INI_ARRAY(&ah->iniModesTxGain,
501 ar9331_modes_high_ob_db_tx_gain_1p1,
502 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
503 5);
504 else if (AR_SREV_9340(ah))
505 INIT_INI_ARRAY(&ah->iniModesTxGain,
506 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
507 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
508 5);
509 else if (AR_SREV_9485_11(ah))
510 INIT_INI_ARRAY(&ah->iniModesTxGain,
511 ar9485Modes_high_ob_db_tx_gain_1_1,
512 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
513 5);
514 else if (AR_SREV_9580(ah))
515 INIT_INI_ARRAY(&ah->iniModesTxGain,
516 ar9580_1p0_high_ob_db_tx_gain_table,
517 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
518 5);
519 else if (AR_SREV_9462_20(ah))
520 INIT_INI_ARRAY(&ah->iniModesTxGain,
521 ar9462_modes_high_ob_db_tx_gain_table_2p0,
522 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
523 5);
524 else
525 INIT_INI_ARRAY(&ah->iniModesTxGain,
526 ar9300Modes_high_ob_db_tx_gain_table_2p2,
527 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
528 5);
529 }
530
ar9003_tx_gain_table_mode2(struct ath_hw * ah)531 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
532 {
533 if (AR_SREV_9330_12(ah))
534 INIT_INI_ARRAY(&ah->iniModesTxGain,
535 ar9331_modes_low_ob_db_tx_gain_1p2,
536 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
537 5);
538 else if (AR_SREV_9330_11(ah))
539 INIT_INI_ARRAY(&ah->iniModesTxGain,
540 ar9331_modes_low_ob_db_tx_gain_1p1,
541 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
542 5);
543 else if (AR_SREV_9340(ah))
544 INIT_INI_ARRAY(&ah->iniModesTxGain,
545 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
546 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
547 5);
548 else if (AR_SREV_9485_11(ah))
549 INIT_INI_ARRAY(&ah->iniModesTxGain,
550 ar9485Modes_low_ob_db_tx_gain_1_1,
551 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
552 5);
553 else if (AR_SREV_9580(ah))
554 INIT_INI_ARRAY(&ah->iniModesTxGain,
555 ar9580_1p0_low_ob_db_tx_gain_table,
556 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
557 5);
558 else
559 INIT_INI_ARRAY(&ah->iniModesTxGain,
560 ar9300Modes_low_ob_db_tx_gain_table_2p2,
561 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
562 5);
563 }
564
ar9003_tx_gain_table_mode3(struct ath_hw * ah)565 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
566 {
567 if (AR_SREV_9330_12(ah))
568 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9331_modes_high_power_tx_gain_1p2,
570 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
571 5);
572 else if (AR_SREV_9330_11(ah))
573 INIT_INI_ARRAY(&ah->iniModesTxGain,
574 ar9331_modes_high_power_tx_gain_1p1,
575 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
576 5);
577 else if (AR_SREV_9340(ah))
578 INIT_INI_ARRAY(&ah->iniModesTxGain,
579 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
580 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
581 5);
582 else if (AR_SREV_9485_11(ah))
583 INIT_INI_ARRAY(&ah->iniModesTxGain,
584 ar9485Modes_high_power_tx_gain_1_1,
585 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
586 5);
587 else if (AR_SREV_9580(ah))
588 INIT_INI_ARRAY(&ah->iniModesTxGain,
589 ar9580_1p0_high_power_tx_gain_table,
590 ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
591 5);
592 else
593 INIT_INI_ARRAY(&ah->iniModesTxGain,
594 ar9300Modes_high_power_tx_gain_table_2p2,
595 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
596 5);
597 }
598
ar9003_tx_gain_table_apply(struct ath_hw * ah)599 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
600 {
601 switch (ar9003_hw_get_tx_gain_idx(ah)) {
602 case 0:
603 default:
604 ar9003_tx_gain_table_mode0(ah);
605 break;
606 case 1:
607 ar9003_tx_gain_table_mode1(ah);
608 break;
609 case 2:
610 ar9003_tx_gain_table_mode2(ah);
611 break;
612 case 3:
613 ar9003_tx_gain_table_mode3(ah);
614 break;
615 }
616 }
617
ar9003_rx_gain_table_mode0(struct ath_hw * ah)618 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
619 {
620 if (AR_SREV_9330_12(ah))
621 INIT_INI_ARRAY(&ah->iniModesRxGain,
622 ar9331_common_rx_gain_1p2,
623 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
624 2);
625 else if (AR_SREV_9330_11(ah))
626 INIT_INI_ARRAY(&ah->iniModesRxGain,
627 ar9331_common_rx_gain_1p1,
628 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
629 2);
630 else if (AR_SREV_9340(ah))
631 INIT_INI_ARRAY(&ah->iniModesRxGain,
632 ar9340Common_rx_gain_table_1p0,
633 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
634 2);
635 else if (AR_SREV_9485_11(ah))
636 INIT_INI_ARRAY(&ah->iniModesRxGain,
637 ar9485_common_rx_gain_1_1,
638 ARRAY_SIZE(ar9485_common_rx_gain_1_1),
639 2);
640 else if (AR_SREV_9580(ah))
641 INIT_INI_ARRAY(&ah->iniModesRxGain,
642 ar9580_1p0_rx_gain_table,
643 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
644 2);
645 else if (AR_SREV_9462_20(ah))
646 INIT_INI_ARRAY(&ah->iniModesRxGain,
647 ar9462_common_rx_gain_table_2p0,
648 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
649 2);
650 else
651 INIT_INI_ARRAY(&ah->iniModesRxGain,
652 ar9300Common_rx_gain_table_2p2,
653 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
654 2);
655 }
656
ar9003_rx_gain_table_mode1(struct ath_hw * ah)657 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
658 {
659 if (AR_SREV_9330_12(ah))
660 INIT_INI_ARRAY(&ah->iniModesRxGain,
661 ar9331_common_wo_xlna_rx_gain_1p2,
662 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
663 2);
664 else if (AR_SREV_9330_11(ah))
665 INIT_INI_ARRAY(&ah->iniModesRxGain,
666 ar9331_common_wo_xlna_rx_gain_1p1,
667 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
668 2);
669 else if (AR_SREV_9340(ah))
670 INIT_INI_ARRAY(&ah->iniModesRxGain,
671 ar9340Common_wo_xlna_rx_gain_table_1p0,
672 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
673 2);
674 else if (AR_SREV_9485_11(ah))
675 INIT_INI_ARRAY(&ah->iniModesRxGain,
676 ar9485Common_wo_xlna_rx_gain_1_1,
677 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
678 2);
679 else if (AR_SREV_9462_20(ah))
680 INIT_INI_ARRAY(&ah->iniModesRxGain,
681 ar9462_common_wo_xlna_rx_gain_table_2p0,
682 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
683 2);
684 else if (AR_SREV_9580(ah))
685 INIT_INI_ARRAY(&ah->iniModesRxGain,
686 ar9580_1p0_wo_xlna_rx_gain_table,
687 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
688 2);
689 else
690 INIT_INI_ARRAY(&ah->iniModesRxGain,
691 ar9300Common_wo_xlna_rx_gain_table_2p2,
692 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
693 2);
694 }
695
ar9003_rx_gain_table_mode2(struct ath_hw * ah)696 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
697 {
698 if (AR_SREV_9462_20(ah))
699 INIT_INI_ARRAY(&ah->iniModesRxGain,
700 ar9462_common_mixed_rx_gain_table_2p0,
701 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
702 }
703
ar9003_rx_gain_table_apply(struct ath_hw * ah)704 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
705 {
706 switch (ar9003_hw_get_rx_gain_idx(ah)) {
707 case 0:
708 default:
709 ar9003_rx_gain_table_mode0(ah);
710 break;
711 case 1:
712 ar9003_rx_gain_table_mode1(ah);
713 break;
714 case 2:
715 ar9003_rx_gain_table_mode2(ah);
716 break;
717 }
718 }
719
720 /* set gain table pointers according to values read from the eeprom */
ar9003_hw_init_mode_gain_regs(struct ath_hw * ah)721 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
722 {
723 ar9003_tx_gain_table_apply(ah);
724 ar9003_rx_gain_table_apply(ah);
725 }
726
727 /*
728 * Helper for ASPM support.
729 *
730 * Disable PLL when in L0s as well as receiver clock when in L1.
731 * This power saving option must be enabled through the SerDes.
732 *
733 * Programming the SerDes must go through the same 288 bit serial shift
734 * register as the other analog registers. Hence the 9 writes.
735 */
ar9003_hw_configpcipowersave(struct ath_hw * ah,bool power_off)736 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
737 bool power_off)
738 {
739 /* Nothing to do on restore for 11N */
740 if (!power_off /* !restore */) {
741 /* set bit 19 to allow forcing of pcie core into L1 state */
742 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
743
744 /* Several PCIe massages to ensure proper behaviour */
745 if (ah->config.pcie_waen)
746 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
747 else
748 REG_WRITE(ah, AR_WA, ah->WARegVal);
749 }
750
751 /*
752 * Configire PCIE after Ini init. SERDES values now come from ini file
753 * This enables PCIe low power mode.
754 */
755 if (ah->config.pcieSerDesWrite) {
756 unsigned int i;
757 struct ar5416IniArray *array;
758
759 array = power_off ? &ah->iniPcieSerdes :
760 &ah->iniPcieSerdesLowPower;
761
762 for (i = 0; i < array->ia_rows; i++) {
763 REG_WRITE(ah,
764 INI_RA(array, i, 0),
765 INI_RA(array, i, 1));
766 }
767 }
768 }
769
770 /* Sets up the AR9003 hardware familiy callbacks */
ar9003_hw_attach_ops(struct ath_hw * ah)771 void ar9003_hw_attach_ops(struct ath_hw *ah)
772 {
773 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
774 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
775
776 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
777 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
778
779 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
780
781 ar9003_hw_attach_phy_ops(ah);
782 ar9003_hw_attach_calib_ops(ah);
783 ar9003_hw_attach_mac_ops(ah);
784 }
785