1 /*
2 * Copyright (C) Michel D�nzer <michdaen@iiic.ethz.ch>
3 *
4 * APUS PCI routines.
5 *
6 * Currently, only B/CVisionPPC cards (Permedia2) are supported.
7 *
8 * Thanks to Geert Uytterhoeven for the idea:
9 * Read values from given config space(s) for the first devices, -1 otherwise
10 *
11 */
12
13 #include <linux/config.h>
14 #ifdef CONFIG_AMIGA
15
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21
22 #include <asm/io.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25
26 #include "apus_pci.h"
27
28
29 /* These definitions are mostly adapted from pm2fb.c */
30
31 #undef APUS_PCI_MASTER_DEBUG
32 #ifdef APUS_PCI_MASTER_DEBUG
33 #define DPRINTK(a,b...) printk(KERN_DEBUG "apus_pci: %s: " a, __FUNCTION__ , ## b)
34 #else
35 #define DPRINTK(a,b...)
36 #endif
37
38 /*
39 * The _DEFINITIVE_ memory mapping/unmapping functions.
40 * This is due to the fact that they're changing soooo often...
41 */
42 #define DEFW() wmb()
43 #define DEFR() rmb()
44 #define DEFRW() mb()
45
46 #define DEVNO(d) ((d)>>3)
47 #define FNNO(d) ((d)&7)
48
49
50 extern unsigned long powerup_PCI_present;
51
52 static struct pci_controller *apus_hose;
53
54
pci_io_base(unsigned int bus)55 void *pci_io_base(unsigned int bus)
56 {
57 return 0;
58 }
59
60
61 #define cfg_read(val, addr, type, op) *val = op((type)(addr))
62 #define cfg_write(val, addr, type, op) op((val), (type *)(addr)); DEFW()
63 #define cfg_read_bad *val = ~0;
64 #define cfg_write_bad ;
65 #define cfg_read_val(val) *val
66 #define cfg_write_val(val) val
67
68 #define APUS_PCI_OP(rw, size, type, op, mask) \
69 int \
70 apus_pcibios_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
71 { \
72 int fnno = FNNO(dev->devfn); \
73 int devno = DEVNO(dev->devfn); \
74 \
75 if (dev->bus->number > 0 || devno != 1) { \
76 cfg_##rw##_bad; \
77 return PCIBIOS_DEVICE_NOT_FOUND; \
78 } \
79 /* base address + function offset + offset ^ endianness conversion */ \
80 cfg_##rw(val, apus_hose->cfg_data + (fnno<<5) + (offset ^ mask), \
81 type, op); \
82 \
83 DPRINTK(#op " b: 0x%x, d: 0x%x, f: 0x%x, o: 0x%x, v: 0x%x\n", \
84 dev->bus->number, dev->devfn>>3, dev->devfn&7, \
85 offset, cfg_##rw##_val(val)); \
86 return PCIBIOS_SUCCESSFUL; \
87 }
88
89 APUS_PCI_OP(read, byte, u8 *, readb, 3)
90 APUS_PCI_OP(read, word, u16 *, readw, 2)
91 APUS_PCI_OP(read, dword, u32 *, readl, 0)
92 APUS_PCI_OP(write, byte, u8, writeb, 3)
93 APUS_PCI_OP(write, word, u16, writew, 2)
94 APUS_PCI_OP(write, dword, u32, writel, 0)
95
96
97 static struct pci_ops apus_pci_ops = {
98 apus_pcibios_read_config_byte,
99 apus_pcibios_read_config_word,
100 apus_pcibios_read_config_dword,
101 apus_pcibios_write_config_byte,
102 apus_pcibios_write_config_word,
103 apus_pcibios_write_config_dword
104 };
105
106 static struct resource pci_mem = { "B/CVisionPPC PCI mem", CVPPC_FB_APERTURE_ONE, CVPPC_PCI_CONFIG, IORESOURCE_MEM };
107
108 void __init
apus_pcibios_fixup(void)109 apus_pcibios_fixup(void)
110 {
111 /* struct pci_dev *dev = pci_find_slot(0, 1<<3);
112 unsigned int reg, val, offset;*/
113
114 /* FIXME: interrupt? */
115 /*dev->interrupt = xxx;*/
116
117 request_resource(&iomem_resource, &pci_mem);
118 printk("%s: PCI mem resource requested\n", __FUNCTION__);
119 }
120
apus_pcibios_fixup_bus(struct pci_bus * bus)121 static void __init apus_pcibios_fixup_bus(struct pci_bus *bus)
122 {
123 bus->resource[1] = &pci_mem;
124 }
125
126
127 /*
128 * This is from pm2fb.c again
129 *
130 * Check if PCI (B/CVisionPPC) is available, initialize it and set up
131 * the pcibios_* pointers
132 */
133
134
135 void __init
apus_setup_pci_ptrs(void)136 apus_setup_pci_ptrs(void)
137 {
138 if (!powerup_PCI_present) {
139 DPRINTK("no PCI bridge detected\n");
140 return;
141 }
142 DPRINTK("Phase5 B/CVisionPPC PCI bridge detected.\n");
143
144 apus_hose = pcibios_alloc_controller();
145 if (!apus_hose) {
146 printk("apus_pci: Can't allocate PCI controller structure\n");
147 return;
148 }
149
150 if (!(apus_hose->cfg_data = ioremap(CVPPC_PCI_CONFIG, 256))) {
151 printk("apus_pci: unable to map PCI config region\n");
152 return;
153 }
154
155 if (!(apus_hose->cfg_addr = ioremap(CSPPC_PCI_BRIDGE, 256))) {
156 printk("apus_pci: unable to map PCI bridge\n");
157 return;
158 }
159
160 writel(CSPPCF_BRIDGE_BIG_ENDIAN, apus_hose->cfg_addr + CSPPC_BRIDGE_ENDIAN);
161 DEFW();
162
163 writel(CVPPC_REGS_REGION, apus_hose->cfg_data+ PCI_BASE_ADDRESS_0);
164 DEFW();
165 writel(CVPPC_FB_APERTURE_ONE, apus_hose->cfg_data + PCI_BASE_ADDRESS_1);
166 DEFW();
167 writel(CVPPC_FB_APERTURE_TWO, apus_hose->cfg_data + PCI_BASE_ADDRESS_2);
168 DEFW();
169 writel(CVPPC_ROM_ADDRESS, apus_hose->cfg_data + PCI_ROM_ADDRESS);
170 DEFW();
171
172 writel(0xef000000 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
173 PCI_COMMAND_MASTER, apus_hose->cfg_data + PCI_COMMAND);
174 DEFW();
175
176 apus_hose->first_busno = 0;
177 apus_hose->last_busno = 0;
178 apus_hose->ops = &apus_pci_ops;
179 ppc_md.pcibios_fixup = apus_pcibios_fixup;
180 ppc_md.pcibios_fixup_bus = apus_pcibios_fixup_bus;
181
182 return;
183 }
184
185 #endif /* CONFIG_AMIGA */
186