1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
4 */
5 #include <linux/kernel.h>
6 #include <linux/init.h>
7 #include <linux/syscore_ops.h>
8 #include <linux/amba/bus.h>
9 #include <linux/io.h>
10 #include <linux/irqchip.h>
11 #include <linux/of_irq.h>
12 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/termios.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/regmap.h>
17
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20
21 #include "integrator-hardware.h"
22 #include "integrator-cm.h"
23 #include "integrator.h"
24
25 /* Regmap to the AP system controller */
26 static struct regmap *ap_syscon_map;
27
28 /*
29 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
30 * is the (PA >> 12).
31 *
32 * Setup a VA for the Integrator interrupt controller (for header #0,
33 * just for now).
34 */
35 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
36
37 /*
38 * Logical Physical
39 * f1400000 14000000 Interrupt controller
40 * f1600000 16000000 UART 0
41 */
42
43 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
44 {
45 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
46 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
47 .length = SZ_4K,
48 .type = MT_DEVICE
49 }, {
50 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
51 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
52 .length = SZ_4K,
53 .type = MT_DEVICE
54 }
55 };
56
ap_map_io(void)57 static void __init ap_map_io(void)
58 {
59 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
60 }
61
62 #ifdef CONFIG_PM
63 static unsigned long ic_irq_enable;
64
irq_suspend(void)65 static int irq_suspend(void)
66 {
67 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
68 return 0;
69 }
70
irq_resume(void)71 static void irq_resume(void)
72 {
73 /* disable all irq sources */
74 cm_clear_irqs();
75 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
76 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
77
78 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
79 }
80 #else
81 #define irq_suspend NULL
82 #define irq_resume NULL
83 #endif
84
85 static struct syscore_ops irq_syscore_ops = {
86 .suspend = irq_suspend,
87 .resume = irq_resume,
88 };
89
irq_syscore_init(void)90 static int __init irq_syscore_init(void)
91 {
92 register_syscore_ops(&irq_syscore_ops);
93
94 return 0;
95 }
96
97 device_initcall(irq_syscore_init);
98
99 /*
100 * For the PL010 found in the Integrator/AP some of the UART control is
101 * implemented in the system controller and accessed using a callback
102 * from the driver.
103 */
integrator_uart_set_mctrl(struct amba_device * dev,void __iomem * base,unsigned int mctrl)104 static void integrator_uart_set_mctrl(struct amba_device *dev,
105 void __iomem *base, unsigned int mctrl)
106 {
107 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
108 u32 phybase = dev->res.start;
109 int ret;
110
111 if (phybase == INTEGRATOR_UART0_BASE) {
112 /* UART0 */
113 rts_mask = 1 << 4;
114 dtr_mask = 1 << 5;
115 } else {
116 /* UART1 */
117 rts_mask = 1 << 6;
118 dtr_mask = 1 << 7;
119 }
120
121 if (mctrl & TIOCM_RTS)
122 ctrlc |= rts_mask;
123 else
124 ctrls |= rts_mask;
125
126 if (mctrl & TIOCM_DTR)
127 ctrlc |= dtr_mask;
128 else
129 ctrls |= dtr_mask;
130
131 ret = regmap_write(ap_syscon_map,
132 INTEGRATOR_SC_CTRLS_OFFSET,
133 ctrls);
134 if (ret)
135 pr_err("MODEM: unable to write PL010 UART CTRLS\n");
136
137 ret = regmap_write(ap_syscon_map,
138 INTEGRATOR_SC_CTRLC_OFFSET,
139 ctrlc);
140 if (ret)
141 pr_err("MODEM: unable to write PL010 UART CRTLC\n");
142 }
143
144 struct amba_pl010_data ap_uart_data = {
145 .set_mctrl = integrator_uart_set_mctrl,
146 };
147
ap_init_irq_of(void)148 static void __init ap_init_irq_of(void)
149 {
150 cm_init();
151 irqchip_init();
152 }
153
154 /* For the Device Tree, add in the UART callbacks as AUXDATA */
155 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
156 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
157 "uart0", &ap_uart_data),
158 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
159 "uart1", &ap_uart_data),
160 { /* sentinel */ },
161 };
162
163 static const struct of_device_id ap_syscon_match[] = {
164 { .compatible = "arm,integrator-ap-syscon"},
165 { },
166 };
167
ap_init_of(void)168 static void __init ap_init_of(void)
169 {
170 struct device_node *syscon;
171
172 of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
173
174 syscon = of_find_matching_node(NULL, ap_syscon_match);
175 if (!syscon)
176 return;
177 ap_syscon_map = syscon_node_to_regmap(syscon);
178 if (IS_ERR(ap_syscon_map)) {
179 pr_crit("could not find Integrator/AP system controller\n");
180 return;
181 }
182 }
183
184 static const char * ap_dt_board_compat[] = {
185 "arm,integrator-ap",
186 NULL,
187 };
188
189 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
190 .reserve = integrator_reserve,
191 .map_io = ap_map_io,
192 .init_irq = ap_init_irq_of,
193 .init_machine = ap_init_of,
194 .dt_compat = ap_dt_board_compat,
195 MACHINE_END
196