1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  *
23  */
24 #include <linux/list.h>
25 #include "amdgpu.h"
26 #include "amdgpu_xgmi.h"
27 #include "amdgpu_ras.h"
28 #include "soc15.h"
29 #include "df/df_3_6_offset.h"
30 #include "xgmi/xgmi_4_0_0_smn.h"
31 #include "xgmi/xgmi_4_0_0_sh_mask.h"
32 #include "wafl/wafl2_4_0_0_smn.h"
33 #include "wafl/wafl2_4_0_0_sh_mask.h"
34 
35 #include "amdgpu_reset.h"
36 
37 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c
38 #define smnPCS_GOPX1_PCS_ERROR_STATUS    0x12200210
39 
40 static DEFINE_MUTEX(xgmi_mutex);
41 
42 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE		4
43 
44 static LIST_HEAD(xgmi_hive_list);
45 
46 static const int xgmi_pcs_err_status_reg_vg20[] = {
47 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
48 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
49 };
50 
51 static const int wafl_pcs_err_status_reg_vg20[] = {
52 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
53 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
54 };
55 
56 static const int xgmi_pcs_err_status_reg_arct[] = {
57 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
58 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
59 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
60 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
61 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
62 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
63 };
64 
65 /* same as vg20*/
66 static const int wafl_pcs_err_status_reg_arct[] = {
67 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
68 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
69 };
70 
71 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = {
72 	smnPCS_XGMI3X16_PCS_ERROR_STATUS,
73 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000,
74 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000,
75 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000,
76 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000,
77 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000,
78 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000,
79 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000
80 };
81 
82 static const int walf_pcs_err_status_reg_aldebaran[] = {
83 	smnPCS_GOPX1_PCS_ERROR_STATUS,
84 	smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000
85 };
86 
87 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
88 	{"XGMI PCS DataLossErr",
89 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
90 	{"XGMI PCS TrainingErr",
91 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
92 	{"XGMI PCS CRCErr",
93 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
94 	{"XGMI PCS BERExceededErr",
95 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
96 	{"XGMI PCS TxMetaDataErr",
97 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
98 	{"XGMI PCS ReplayBufParityErr",
99 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
100 	{"XGMI PCS DataParityErr",
101 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
102 	{"XGMI PCS ReplayFifoOverflowErr",
103 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
104 	{"XGMI PCS ReplayFifoUnderflowErr",
105 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
106 	{"XGMI PCS ElasticFifoOverflowErr",
107 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
108 	{"XGMI PCS DeskewErr",
109 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
110 	{"XGMI PCS DataStartupLimitErr",
111 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
112 	{"XGMI PCS FCInitTimeoutErr",
113 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
114 	{"XGMI PCS RecoveryTimeoutErr",
115 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
116 	{"XGMI PCS ReadySerialTimeoutErr",
117 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
118 	{"XGMI PCS ReadySerialAttemptErr",
119 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
120 	{"XGMI PCS RecoveryAttemptErr",
121 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
122 	{"XGMI PCS RecoveryRelockAttemptErr",
123 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
124 };
125 
126 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
127 	{"WAFL PCS DataLossErr",
128 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
129 	{"WAFL PCS TrainingErr",
130 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
131 	{"WAFL PCS CRCErr",
132 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
133 	{"WAFL PCS BERExceededErr",
134 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
135 	{"WAFL PCS TxMetaDataErr",
136 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
137 	{"WAFL PCS ReplayBufParityErr",
138 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
139 	{"WAFL PCS DataParityErr",
140 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
141 	{"WAFL PCS ReplayFifoOverflowErr",
142 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
143 	{"WAFL PCS ReplayFifoUnderflowErr",
144 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
145 	{"WAFL PCS ElasticFifoOverflowErr",
146 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
147 	{"WAFL PCS DeskewErr",
148 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
149 	{"WAFL PCS DataStartupLimitErr",
150 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
151 	{"WAFL PCS FCInitTimeoutErr",
152 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
153 	{"WAFL PCS RecoveryTimeoutErr",
154 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
155 	{"WAFL PCS ReadySerialTimeoutErr",
156 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
157 	{"WAFL PCS ReadySerialAttemptErr",
158 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
159 	{"WAFL PCS RecoveryAttemptErr",
160 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
161 	{"WAFL PCS RecoveryRelockAttemptErr",
162 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
163 };
164 
165 /**
166  * DOC: AMDGPU XGMI Support
167  *
168  * XGMI is a high speed interconnect that joins multiple GPU cards
169  * into a homogeneous memory space that is organized by a collective
170  * hive ID and individual node IDs, both of which are 64-bit numbers.
171  *
172  * The file xgmi_device_id contains the unique per GPU device ID and
173  * is stored in the /sys/class/drm/card${cardno}/device/ directory.
174  *
175  * Inside the device directory a sub-directory 'xgmi_hive_info' is
176  * created which contains the hive ID and the list of nodes.
177  *
178  * The hive ID is stored in:
179  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
180  *
181  * The node information is stored in numbered directories:
182  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
183  *
184  * Each device has their own xgmi_hive_info direction with a mirror
185  * set of node sub-directories.
186  *
187  * The XGMI memory space is built by contiguously adding the power of
188  * two padded VRAM space from each node to each other.
189  *
190  */
191 
192 static struct attribute amdgpu_xgmi_hive_id = {
193 	.name = "xgmi_hive_id",
194 	.mode = S_IRUGO
195 };
196 
197 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
198 	&amdgpu_xgmi_hive_id,
199 	NULL
200 };
201 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive);
202 
amdgpu_xgmi_show_attrs(struct kobject * kobj,struct attribute * attr,char * buf)203 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
204 	struct attribute *attr, char *buf)
205 {
206 	struct amdgpu_hive_info *hive = container_of(
207 		kobj, struct amdgpu_hive_info, kobj);
208 
209 	if (attr == &amdgpu_xgmi_hive_id)
210 		return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
211 
212 	return 0;
213 }
214 
amdgpu_xgmi_hive_release(struct kobject * kobj)215 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
216 {
217 	struct amdgpu_hive_info *hive = container_of(
218 		kobj, struct amdgpu_hive_info, kobj);
219 
220 	amdgpu_reset_put_reset_domain(hive->reset_domain);
221 	hive->reset_domain = NULL;
222 
223 	mutex_destroy(&hive->hive_lock);
224 	kfree(hive);
225 }
226 
227 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
228 	.show = amdgpu_xgmi_show_attrs,
229 };
230 
231 struct kobj_type amdgpu_xgmi_hive_type = {
232 	.release = amdgpu_xgmi_hive_release,
233 	.sysfs_ops = &amdgpu_xgmi_hive_ops,
234 	.default_groups = amdgpu_xgmi_hive_groups,
235 };
236 
amdgpu_xgmi_show_device_id(struct device * dev,struct device_attribute * attr,char * buf)237 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
238 				     struct device_attribute *attr,
239 				     char *buf)
240 {
241 	struct drm_device *ddev = dev_get_drvdata(dev);
242 	struct amdgpu_device *adev = drm_to_adev(ddev);
243 
244 	return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id);
245 
246 }
247 
248 #define AMDGPU_XGMI_SET_FICAA(o)	((o) | 0x456801)
amdgpu_xgmi_show_error(struct device * dev,struct device_attribute * attr,char * buf)249 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
250 				      struct device_attribute *attr,
251 				      char *buf)
252 {
253 	struct drm_device *ddev = dev_get_drvdata(dev);
254 	struct amdgpu_device *adev = drm_to_adev(ddev);
255 	uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
256 	uint64_t fica_out;
257 	unsigned int error_count = 0;
258 
259 	ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
260 	ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
261 
262 	if ((!adev->df.funcs) ||
263 	    (!adev->df.funcs->get_fica) ||
264 	    (!adev->df.funcs->set_fica))
265 		return -EINVAL;
266 
267 	fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
268 	if (fica_out != 0x1f)
269 		pr_err("xGMI error counters not enabled!\n");
270 
271 	fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
272 
273 	if ((fica_out & 0xffff) == 2)
274 		error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
275 
276 	adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
277 
278 	return sysfs_emit(buf, "%u\n", error_count);
279 }
280 
281 
282 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
283 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
284 
amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)285 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
286 					 struct amdgpu_hive_info *hive)
287 {
288 	int ret = 0;
289 	char node[10] = { 0 };
290 
291 	/* Create xgmi device id file */
292 	ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
293 	if (ret) {
294 		dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
295 		return ret;
296 	}
297 
298 	/* Create xgmi error file */
299 	ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
300 	if (ret)
301 		pr_err("failed to create xgmi_error\n");
302 
303 
304 	/* Create sysfs link to hive info folder on the first device */
305 	if (hive->kobj.parent != (&adev->dev->kobj)) {
306 		ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
307 					"xgmi_hive_info");
308 		if (ret) {
309 			dev_err(adev->dev, "XGMI: Failed to create link to hive info");
310 			goto remove_file;
311 		}
312 	}
313 
314 	sprintf(node, "node%d", atomic_read(&hive->number_devices));
315 	/* Create sysfs link form the hive folder to yourself */
316 	ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
317 	if (ret) {
318 		dev_err(adev->dev, "XGMI: Failed to create link from hive info");
319 		goto remove_link;
320 	}
321 
322 	goto success;
323 
324 
325 remove_link:
326 	sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
327 
328 remove_file:
329 	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
330 
331 success:
332 	return ret;
333 }
334 
amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)335 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
336 					  struct amdgpu_hive_info *hive)
337 {
338 	char node[10];
339 	memset(node, 0, sizeof(node));
340 
341 	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
342 	device_remove_file(adev->dev, &dev_attr_xgmi_error);
343 
344 	if (hive->kobj.parent != (&adev->dev->kobj))
345 		sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
346 
347 	sprintf(node, "node%d", atomic_read(&hive->number_devices));
348 	sysfs_remove_link(&hive->kobj, node);
349 
350 }
351 
352 
353 
amdgpu_get_xgmi_hive(struct amdgpu_device * adev)354 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
355 {
356 	struct amdgpu_hive_info *hive = NULL;
357 	int ret;
358 
359 	if (!adev->gmc.xgmi.hive_id)
360 		return NULL;
361 
362 	if (adev->hive) {
363 		kobject_get(&adev->hive->kobj);
364 		return adev->hive;
365 	}
366 
367 	mutex_lock(&xgmi_mutex);
368 
369 	list_for_each_entry(hive, &xgmi_hive_list, node)  {
370 		if (hive->hive_id == adev->gmc.xgmi.hive_id)
371 			goto pro_end;
372 	}
373 
374 	hive = kzalloc(sizeof(*hive), GFP_KERNEL);
375 	if (!hive) {
376 		dev_err(adev->dev, "XGMI: allocation failed\n");
377 		hive = NULL;
378 		goto pro_end;
379 	}
380 
381 	/* initialize new hive if not exist */
382 	ret = kobject_init_and_add(&hive->kobj,
383 			&amdgpu_xgmi_hive_type,
384 			&adev->dev->kobj,
385 			"%s", "xgmi_hive_info");
386 	if (ret) {
387 		dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
388 		kobject_put(&hive->kobj);
389 		hive = NULL;
390 		goto pro_end;
391 	}
392 
393 	/**
394 	 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV,
395 	 * Host driver decide how to reset the GPU either through FLR or chain reset.
396 	 * Guest side will get individual notifications from the host for the FLR
397 	 * if necessary.
398 	 */
399 	if (!amdgpu_sriov_vf(adev)) {
400 	/**
401 	 * Avoid recreating reset domain when hive is reconstructed for the case
402 	 * of reset the devices in the XGMI hive during probe for passthrough GPU
403 	 * See https://www.spinics.net/lists/amd-gfx/msg58836.html
404 	 */
405 		if (adev->reset_domain->type != XGMI_HIVE) {
406 			hive->reset_domain =
407 				amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive");
408 			if (!hive->reset_domain) {
409 				dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n");
410 				ret = -ENOMEM;
411 				kobject_put(&hive->kobj);
412 				hive = NULL;
413 				goto pro_end;
414 			}
415 		} else {
416 			amdgpu_reset_get_reset_domain(adev->reset_domain);
417 			hive->reset_domain = adev->reset_domain;
418 		}
419 	}
420 
421 	hive->hive_id = adev->gmc.xgmi.hive_id;
422 	INIT_LIST_HEAD(&hive->device_list);
423 	INIT_LIST_HEAD(&hive->node);
424 	mutex_init(&hive->hive_lock);
425 	atomic_set(&hive->number_devices, 0);
426 	task_barrier_init(&hive->tb);
427 	hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
428 	hive->hi_req_gpu = NULL;
429 
430 	/*
431 	 * hive pstate on boot is high in vega20 so we have to go to low
432 	 * pstate on after boot.
433 	 */
434 	hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
435 	list_add_tail(&hive->node, &xgmi_hive_list);
436 
437 pro_end:
438 	if (hive)
439 		kobject_get(&hive->kobj);
440 	mutex_unlock(&xgmi_mutex);
441 	return hive;
442 }
443 
amdgpu_put_xgmi_hive(struct amdgpu_hive_info * hive)444 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
445 {
446 	if (hive)
447 		kobject_put(&hive->kobj);
448 }
449 
amdgpu_xgmi_set_pstate(struct amdgpu_device * adev,int pstate)450 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
451 {
452 	int ret = 0;
453 	struct amdgpu_hive_info *hive;
454 	struct amdgpu_device *request_adev;
455 	bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
456 	bool init_low;
457 
458 	hive = amdgpu_get_xgmi_hive(adev);
459 	if (!hive)
460 		return 0;
461 
462 	request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev;
463 	init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
464 	amdgpu_put_xgmi_hive(hive);
465 	/* fw bug so temporarily disable pstate switching */
466 	return 0;
467 
468 	if (!hive || adev->asic_type != CHIP_VEGA20)
469 		return 0;
470 
471 	mutex_lock(&hive->hive_lock);
472 
473 	if (is_hi_req)
474 		hive->hi_req_count++;
475 	else
476 		hive->hi_req_count--;
477 
478 	/*
479 	 * Vega20 only needs single peer to request pstate high for the hive to
480 	 * go high but all peers must request pstate low for the hive to go low
481 	 */
482 	if (hive->pstate == pstate ||
483 			(!is_hi_req && hive->hi_req_count && !init_low))
484 		goto out;
485 
486 	dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
487 
488 	ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
489 	if (ret) {
490 		dev_err(request_adev->dev,
491 			"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
492 			request_adev->gmc.xgmi.node_id,
493 			request_adev->gmc.xgmi.hive_id, ret);
494 		goto out;
495 	}
496 
497 	if (init_low)
498 		hive->pstate = hive->hi_req_count ?
499 					hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
500 	else {
501 		hive->pstate = pstate;
502 		hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
503 							adev : NULL;
504 	}
505 out:
506 	mutex_unlock(&hive->hive_lock);
507 	return ret;
508 }
509 
amdgpu_xgmi_update_topology(struct amdgpu_hive_info * hive,struct amdgpu_device * adev)510 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
511 {
512 	int ret;
513 
514 	if (amdgpu_sriov_vf(adev))
515 		return 0;
516 
517 	/* Each psp need to set the latest topology */
518 	ret = psp_xgmi_set_topology_info(&adev->psp,
519 					 atomic_read(&hive->number_devices),
520 					 &adev->psp.xgmi_context.top_info);
521 	if (ret)
522 		dev_err(adev->dev,
523 			"XGMI: Set topology failure on device %llx, hive %llx, ret %d",
524 			adev->gmc.xgmi.node_id,
525 			adev->gmc.xgmi.hive_id, ret);
526 
527 	return ret;
528 }
529 
530 
531 /*
532  * NOTE psp_xgmi_node_info.num_hops layout is as follows:
533  * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved)
534  * num_hops[5:3] = reserved
535  * num_hops[2:0] = number of hops
536  */
amdgpu_xgmi_get_hops_count(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)537 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
538 		struct amdgpu_device *peer_adev)
539 {
540 	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
541 	uint8_t num_hops_mask = 0x7;
542 	int i;
543 
544 	for (i = 0 ; i < top->num_nodes; ++i)
545 		if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
546 			return top->nodes[i].num_hops & num_hops_mask;
547 	return	-EINVAL;
548 }
549 
amdgpu_xgmi_get_num_links(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)550 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
551 		struct amdgpu_device *peer_adev)
552 {
553 	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
554 	int i;
555 
556 	for (i = 0 ; i < top->num_nodes; ++i)
557 		if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
558 			return top->nodes[i].num_links;
559 	return	-EINVAL;
560 }
561 
562 /*
563  * Devices that support extended data require the entire hive to initialize with
564  * the shared memory buffer flag set.
565  *
566  * Hive locks and conditions apply - see amdgpu_xgmi_add_device
567  */
amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info * hive,bool set_extended_data)568 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive,
569 							bool set_extended_data)
570 {
571 	struct amdgpu_device *tmp_adev;
572 	int ret;
573 
574 	list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
575 		ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false);
576 		if (ret) {
577 			dev_err(tmp_adev->dev,
578 				"XGMI: Failed to initialize xgmi session for data partition %i\n",
579 				set_extended_data);
580 			return ret;
581 		}
582 
583 	}
584 
585 	return 0;
586 }
587 
amdgpu_xgmi_add_device(struct amdgpu_device * adev)588 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
589 {
590 	struct psp_xgmi_topology_info *top_info;
591 	struct amdgpu_hive_info *hive;
592 	struct amdgpu_xgmi	*entry;
593 	struct amdgpu_device *tmp_adev = NULL;
594 
595 	int count = 0, ret = 0;
596 
597 	if (!adev->gmc.xgmi.supported)
598 		return 0;
599 
600 	if (!adev->gmc.xgmi.pending_reset &&
601 	    amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
602 		ret = psp_xgmi_initialize(&adev->psp, false, true);
603 		if (ret) {
604 			dev_err(adev->dev,
605 				"XGMI: Failed to initialize xgmi session\n");
606 			return ret;
607 		}
608 
609 		ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
610 		if (ret) {
611 			dev_err(adev->dev,
612 				"XGMI: Failed to get hive id\n");
613 			return ret;
614 		}
615 
616 		ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
617 		if (ret) {
618 			dev_err(adev->dev,
619 				"XGMI: Failed to get node id\n");
620 			return ret;
621 		}
622 	} else {
623 		adev->gmc.xgmi.hive_id = 16;
624 		adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
625 	}
626 
627 	hive = amdgpu_get_xgmi_hive(adev);
628 	if (!hive) {
629 		ret = -EINVAL;
630 		dev_err(adev->dev,
631 			"XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
632 			adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
633 		goto exit;
634 	}
635 	mutex_lock(&hive->hive_lock);
636 
637 	top_info = &adev->psp.xgmi_context.top_info;
638 
639 	list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
640 	list_for_each_entry(entry, &hive->device_list, head)
641 		top_info->nodes[count++].node_id = entry->node_id;
642 	top_info->num_nodes = count;
643 	atomic_set(&hive->number_devices, count);
644 
645 	task_barrier_add_task(&hive->tb);
646 
647 	if (!adev->gmc.xgmi.pending_reset &&
648 	    amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
649 		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
650 			/* update node list for other device in the hive */
651 			if (tmp_adev != adev) {
652 				top_info = &tmp_adev->psp.xgmi_context.top_info;
653 				top_info->nodes[count - 1].node_id =
654 					adev->gmc.xgmi.node_id;
655 				top_info->num_nodes = count;
656 			}
657 			ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
658 			if (ret)
659 				goto exit_unlock;
660 		}
661 
662 		/* get latest topology info for each device from psp */
663 		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
664 			ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
665 					&tmp_adev->psp.xgmi_context.top_info, false);
666 			if (ret) {
667 				dev_err(tmp_adev->dev,
668 					"XGMI: Get topology failure on device %llx, hive %llx, ret %d",
669 					tmp_adev->gmc.xgmi.node_id,
670 					tmp_adev->gmc.xgmi.hive_id, ret);
671 				/* To do : continue with some node failed or disable the whole hive */
672 				goto exit_unlock;
673 			}
674 		}
675 
676 		/* get topology again for hives that support extended data */
677 		if (adev->psp.xgmi_context.supports_extended_data) {
678 
679 			/* initialize the hive to get extended data.  */
680 			ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true);
681 			if (ret)
682 				goto exit_unlock;
683 
684 			/* get the extended data. */
685 			list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
686 				ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
687 						&tmp_adev->psp.xgmi_context.top_info, true);
688 				if (ret) {
689 					dev_err(tmp_adev->dev,
690 						"XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d",
691 						tmp_adev->gmc.xgmi.node_id,
692 						tmp_adev->gmc.xgmi.hive_id, ret);
693 					goto exit_unlock;
694 				}
695 			}
696 
697 			/* initialize the hive to get non-extended data for the next round. */
698 			ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false);
699 			if (ret)
700 				goto exit_unlock;
701 
702 		}
703 	}
704 
705 	if (!ret && !adev->gmc.xgmi.pending_reset)
706 		ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
707 
708 exit_unlock:
709 	mutex_unlock(&hive->hive_lock);
710 exit:
711 	if (!ret) {
712 		adev->hive = hive;
713 		dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
714 			 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
715 	} else {
716 		amdgpu_put_xgmi_hive(hive);
717 		dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
718 			adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
719 			ret);
720 	}
721 
722 	return ret;
723 }
724 
amdgpu_xgmi_remove_device(struct amdgpu_device * adev)725 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
726 {
727 	struct amdgpu_hive_info *hive = adev->hive;
728 
729 	if (!adev->gmc.xgmi.supported)
730 		return -EINVAL;
731 
732 	if (!hive)
733 		return -EINVAL;
734 
735 	mutex_lock(&hive->hive_lock);
736 	task_barrier_rem_task(&hive->tb);
737 	amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
738 	if (hive->hi_req_gpu == adev)
739 		hive->hi_req_gpu = NULL;
740 	list_del(&adev->gmc.xgmi.head);
741 	mutex_unlock(&hive->hive_lock);
742 
743 	amdgpu_put_xgmi_hive(hive);
744 	adev->hive = NULL;
745 
746 	if (atomic_dec_return(&hive->number_devices) == 0) {
747 		/* Remove the hive from global hive list */
748 		mutex_lock(&xgmi_mutex);
749 		list_del(&hive->node);
750 		mutex_unlock(&xgmi_mutex);
751 
752 		amdgpu_put_xgmi_hive(hive);
753 	}
754 
755 	return 0;
756 }
757 
amdgpu_xgmi_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)758 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
759 {
760 	if (!adev->gmc.xgmi.supported ||
761 	    adev->gmc.xgmi.num_physical_nodes == 0)
762 		return 0;
763 
764 	adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
765 
766 	return amdgpu_ras_block_late_init(adev, ras_block);
767 }
768 
amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device * adev,uint64_t addr)769 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
770 					   uint64_t addr)
771 {
772 	struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
773 	return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
774 }
775 
pcs_clear_status(struct amdgpu_device * adev,uint32_t pcs_status_reg)776 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
777 {
778 	WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
779 	WREG32_PCIE(pcs_status_reg, 0);
780 }
781 
amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device * adev)782 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
783 {
784 	uint32_t i;
785 
786 	switch (adev->asic_type) {
787 	case CHIP_ARCTURUS:
788 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
789 			pcs_clear_status(adev,
790 					 xgmi_pcs_err_status_reg_arct[i]);
791 		break;
792 	case CHIP_VEGA20:
793 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
794 			pcs_clear_status(adev,
795 					 xgmi_pcs_err_status_reg_vg20[i]);
796 		break;
797 	case CHIP_ALDEBARAN:
798 		for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++)
799 			pcs_clear_status(adev,
800 					 xgmi3x16_pcs_err_status_reg_aldebaran[i]);
801 		for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++)
802 			pcs_clear_status(adev,
803 					 walf_pcs_err_status_reg_aldebaran[i]);
804 		break;
805 	default:
806 		break;
807 	}
808 }
809 
amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device * adev,uint32_t value,uint32_t * ue_count,uint32_t * ce_count,bool is_xgmi_pcs)810 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
811 					      uint32_t value,
812 					      uint32_t *ue_count,
813 					      uint32_t *ce_count,
814 					      bool is_xgmi_pcs)
815 {
816 	int i;
817 	int ue_cnt;
818 
819 	if (is_xgmi_pcs) {
820 		/* query xgmi pcs error status,
821 		 * only ue is supported */
822 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) {
823 			ue_cnt = (value &
824 				  xgmi_pcs_ras_fields[i].pcs_err_mask) >>
825 				  xgmi_pcs_ras_fields[i].pcs_err_shift;
826 			if (ue_cnt) {
827 				dev_info(adev->dev, "%s detected\n",
828 					 xgmi_pcs_ras_fields[i].err_name);
829 				*ue_count += ue_cnt;
830 			}
831 		}
832 	} else {
833 		/* query wafl pcs error status,
834 		 * only ue is supported */
835 		for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) {
836 			ue_cnt = (value &
837 				  wafl_pcs_ras_fields[i].pcs_err_mask) >>
838 				  wafl_pcs_ras_fields[i].pcs_err_shift;
839 			if (ue_cnt) {
840 				dev_info(adev->dev, "%s detected\n",
841 					 wafl_pcs_ras_fields[i].err_name);
842 				*ue_count += ue_cnt;
843 			}
844 		}
845 	}
846 
847 	return 0;
848 }
849 
amdgpu_xgmi_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)850 static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
851 					     void *ras_error_status)
852 {
853 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
854 	int i;
855 	uint32_t data;
856 	uint32_t ue_cnt = 0, ce_cnt = 0;
857 
858 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
859 		return ;
860 
861 	err_data->ue_count = 0;
862 	err_data->ce_count = 0;
863 
864 	switch (adev->asic_type) {
865 	case CHIP_ARCTURUS:
866 		/* check xgmi pcs error */
867 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
868 			data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
869 			if (data)
870 				amdgpu_xgmi_query_pcs_error_status(adev,
871 						data, &ue_cnt, &ce_cnt, true);
872 		}
873 		/* check wafl pcs error */
874 		for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
875 			data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
876 			if (data)
877 				amdgpu_xgmi_query_pcs_error_status(adev,
878 						data, &ue_cnt, &ce_cnt, false);
879 		}
880 		break;
881 	case CHIP_VEGA20:
882 		/* check xgmi pcs error */
883 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
884 			data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
885 			if (data)
886 				amdgpu_xgmi_query_pcs_error_status(adev,
887 						data, &ue_cnt, &ce_cnt, true);
888 		}
889 		/* check wafl pcs error */
890 		for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
891 			data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
892 			if (data)
893 				amdgpu_xgmi_query_pcs_error_status(adev,
894 						data, &ue_cnt, &ce_cnt, false);
895 		}
896 		break;
897 	case CHIP_ALDEBARAN:
898 		/* check xgmi3x16 pcs error */
899 		for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) {
900 			data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]);
901 			if (data)
902 				amdgpu_xgmi_query_pcs_error_status(adev,
903 						data, &ue_cnt, &ce_cnt, true);
904 		}
905 		/* check wafl pcs error */
906 		for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) {
907 			data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]);
908 			if (data)
909 				amdgpu_xgmi_query_pcs_error_status(adev,
910 						data, &ue_cnt, &ce_cnt, false);
911 		}
912 		break;
913 	default:
914 		dev_warn(adev->dev, "XGMI RAS error query not supported");
915 		break;
916 	}
917 
918 	adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
919 
920 	err_data->ue_count += ue_cnt;
921 	err_data->ce_count += ce_cnt;
922 }
923 
924 /* Trigger XGMI/WAFL error */
amdgpu_ras_error_inject_xgmi(struct amdgpu_device * adev,void * inject_if)925 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,  void *inject_if)
926 {
927 	int ret = 0;
928 	struct ta_ras_trigger_error_input *block_info =
929 				(struct ta_ras_trigger_error_input *)inject_if;
930 
931 	if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
932 		dev_warn(adev->dev, "Failed to disallow df cstate");
933 
934 	if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
935 		dev_warn(adev->dev, "Failed to disallow XGMI power down");
936 
937 	ret = psp_ras_trigger_error(&adev->psp, block_info);
938 
939 	if (amdgpu_ras_intr_triggered())
940 		return ret;
941 
942 	if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
943 		dev_warn(adev->dev, "Failed to allow XGMI power down");
944 
945 	if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
946 		dev_warn(adev->dev, "Failed to allow df cstate");
947 
948 	return ret;
949 }
950 
951 struct amdgpu_ras_block_hw_ops  xgmi_ras_hw_ops = {
952 	.query_ras_error_count = amdgpu_xgmi_query_ras_error_count,
953 	.reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
954 	.ras_error_inject = amdgpu_ras_error_inject_xgmi,
955 };
956 
957 struct amdgpu_xgmi_ras xgmi_ras = {
958 	.ras_block = {
959 		.ras_comm = {
960 			.name = "xgmi_wafl",
961 			.block = AMDGPU_RAS_BLOCK__XGMI_WAFL,
962 			.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
963 		},
964 		.hw_ops = &xgmi_ras_hw_ops,
965 		.ras_late_init = amdgpu_xgmi_ras_late_init,
966 	},
967 };
968