1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  *
23  */
24 #include <linux/list.h>
25 #include "amdgpu.h"
26 #include "amdgpu_xgmi.h"
27 #include "amdgpu_ras.h"
28 #include "soc15.h"
29 #include "df/df_3_6_offset.h"
30 #include "xgmi/xgmi_4_0_0_smn.h"
31 #include "xgmi/xgmi_4_0_0_sh_mask.h"
32 #include "xgmi/xgmi_6_1_0_sh_mask.h"
33 #include "wafl/wafl2_4_0_0_smn.h"
34 #include "wafl/wafl2_4_0_0_sh_mask.h"
35 
36 #include "amdgpu_reset.h"
37 
38 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c
39 #define smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK   0x11a00218
40 #define smnPCS_GOPX1_PCS_ERROR_STATUS    0x12200210
41 #define smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK      0x12200218
42 
43 static DEFINE_MUTEX(xgmi_mutex);
44 
45 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE		4
46 
47 static LIST_HEAD(xgmi_hive_list);
48 
49 static const int xgmi_pcs_err_status_reg_vg20[] = {
50 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
51 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
52 };
53 
54 static const int wafl_pcs_err_status_reg_vg20[] = {
55 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
56 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
57 };
58 
59 static const int xgmi_pcs_err_status_reg_arct[] = {
60 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
61 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
62 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
63 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
64 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
65 	smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
66 };
67 
68 /* same as vg20*/
69 static const int wafl_pcs_err_status_reg_arct[] = {
70 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
71 	smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
72 };
73 
74 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = {
75 	smnPCS_XGMI3X16_PCS_ERROR_STATUS,
76 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000,
77 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000,
78 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000,
79 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000,
80 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000,
81 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000,
82 	smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000
83 };
84 
85 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[] = {
86 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK,
87 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000,
88 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x200000,
89 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x300000,
90 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x400000,
91 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x500000,
92 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x600000,
93 	smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x700000
94 };
95 
96 static const int walf_pcs_err_status_reg_aldebaran[] = {
97 	smnPCS_GOPX1_PCS_ERROR_STATUS,
98 	smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000
99 };
100 
101 static const int walf_pcs_err_noncorrectable_mask_reg_aldebaran[] = {
102 	smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK,
103 	smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000
104 };
105 
106 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
107 	{"XGMI PCS DataLossErr",
108 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
109 	{"XGMI PCS TrainingErr",
110 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
111 	{"XGMI PCS CRCErr",
112 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
113 	{"XGMI PCS BERExceededErr",
114 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
115 	{"XGMI PCS TxMetaDataErr",
116 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
117 	{"XGMI PCS ReplayBufParityErr",
118 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
119 	{"XGMI PCS DataParityErr",
120 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
121 	{"XGMI PCS ReplayFifoOverflowErr",
122 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
123 	{"XGMI PCS ReplayFifoUnderflowErr",
124 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
125 	{"XGMI PCS ElasticFifoOverflowErr",
126 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
127 	{"XGMI PCS DeskewErr",
128 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
129 	{"XGMI PCS DataStartupLimitErr",
130 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
131 	{"XGMI PCS FCInitTimeoutErr",
132 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
133 	{"XGMI PCS RecoveryTimeoutErr",
134 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
135 	{"XGMI PCS ReadySerialTimeoutErr",
136 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
137 	{"XGMI PCS ReadySerialAttemptErr",
138 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
139 	{"XGMI PCS RecoveryAttemptErr",
140 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
141 	{"XGMI PCS RecoveryRelockAttemptErr",
142 	 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
143 };
144 
145 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
146 	{"WAFL PCS DataLossErr",
147 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
148 	{"WAFL PCS TrainingErr",
149 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
150 	{"WAFL PCS CRCErr",
151 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
152 	{"WAFL PCS BERExceededErr",
153 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
154 	{"WAFL PCS TxMetaDataErr",
155 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
156 	{"WAFL PCS ReplayBufParityErr",
157 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
158 	{"WAFL PCS DataParityErr",
159 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
160 	{"WAFL PCS ReplayFifoOverflowErr",
161 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
162 	{"WAFL PCS ReplayFifoUnderflowErr",
163 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
164 	{"WAFL PCS ElasticFifoOverflowErr",
165 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
166 	{"WAFL PCS DeskewErr",
167 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
168 	{"WAFL PCS DataStartupLimitErr",
169 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
170 	{"WAFL PCS FCInitTimeoutErr",
171 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
172 	{"WAFL PCS RecoveryTimeoutErr",
173 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
174 	{"WAFL PCS ReadySerialTimeoutErr",
175 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
176 	{"WAFL PCS ReadySerialAttemptErr",
177 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
178 	{"WAFL PCS RecoveryAttemptErr",
179 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
180 	{"WAFL PCS RecoveryRelockAttemptErr",
181 	 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
182 };
183 
184 static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = {
185 	{"XGMI3X16 PCS DataLossErr",
186 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataLossErr)},
187 	{"XGMI3X16 PCS TrainingErr",
188 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TrainingErr)},
189 	{"XGMI3X16 PCS FlowCtrlAckErr",
190 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlAckErr)},
191 	{"XGMI3X16 PCS RxFifoUnderflowErr",
192 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoUnderflowErr)},
193 	{"XGMI3X16 PCS RxFifoOverflowErr",
194 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoOverflowErr)},
195 	{"XGMI3X16 PCS CRCErr",
196 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, CRCErr)},
197 	{"XGMI3X16 PCS BERExceededErr",
198 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, BERExceededErr)},
199 	{"XGMI3X16 PCS TxVcidDataErr",
200 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxVcidDataErr)},
201 	{"XGMI3X16 PCS ReplayBufParityErr",
202 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayBufParityErr)},
203 	{"XGMI3X16 PCS DataParityErr",
204 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataParityErr)},
205 	{"XGMI3X16 PCS ReplayFifoOverflowErr",
206 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
207 	{"XGMI3X16 PCS ReplayFifoUnderflowErr",
208 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
209 	{"XGMI3X16 PCS ElasticFifoOverflowErr",
210 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
211 	{"XGMI3X16 PCS DeskewErr",
212 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DeskewErr)},
213 	{"XGMI3X16 PCS FlowCtrlCRCErr",
214 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlCRCErr)},
215 	{"XGMI3X16 PCS DataStartupLimitErr",
216 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataStartupLimitErr)},
217 	{"XGMI3X16 PCS FCInitTimeoutErr",
218 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
219 	{"XGMI3X16 PCS RecoveryTimeoutErr",
220 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
221 	{"XGMI3X16 PCS ReadySerialTimeoutErr",
222 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
223 	{"XGMI3X16 PCS ReadySerialAttemptErr",
224 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
225 	{"XGMI3X16 PCS RecoveryAttemptErr",
226 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
227 	{"XGMI3X16 PCS RecoveryRelockAttemptErr",
228 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
229 	{"XGMI3X16 PCS ReplayAttemptErr",
230 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayAttemptErr)},
231 	{"XGMI3X16 PCS SyncHdrErr",
232 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, SyncHdrErr)},
233 	{"XGMI3X16 PCS TxReplayTimeoutErr",
234 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxReplayTimeoutErr)},
235 	{"XGMI3X16 PCS RxReplayTimeoutErr",
236 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxReplayTimeoutErr)},
237 	{"XGMI3X16 PCS LinkSubTxTimeoutErr",
238 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubTxTimeoutErr)},
239 	{"XGMI3X16 PCS LinkSubRxTimeoutErr",
240 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubRxTimeoutErr)},
241 	{"XGMI3X16 PCS RxCMDPktErr",
242 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxCMDPktErr)},
243 };
244 
245 /**
246  * DOC: AMDGPU XGMI Support
247  *
248  * XGMI is a high speed interconnect that joins multiple GPU cards
249  * into a homogeneous memory space that is organized by a collective
250  * hive ID and individual node IDs, both of which are 64-bit numbers.
251  *
252  * The file xgmi_device_id contains the unique per GPU device ID and
253  * is stored in the /sys/class/drm/card${cardno}/device/ directory.
254  *
255  * Inside the device directory a sub-directory 'xgmi_hive_info' is
256  * created which contains the hive ID and the list of nodes.
257  *
258  * The hive ID is stored in:
259  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
260  *
261  * The node information is stored in numbered directories:
262  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
263  *
264  * Each device has their own xgmi_hive_info direction with a mirror
265  * set of node sub-directories.
266  *
267  * The XGMI memory space is built by contiguously adding the power of
268  * two padded VRAM space from each node to each other.
269  *
270  */
271 
272 static struct attribute amdgpu_xgmi_hive_id = {
273 	.name = "xgmi_hive_id",
274 	.mode = S_IRUGO
275 };
276 
277 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
278 	&amdgpu_xgmi_hive_id,
279 	NULL
280 };
281 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive);
282 
amdgpu_xgmi_show_attrs(struct kobject * kobj,struct attribute * attr,char * buf)283 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
284 	struct attribute *attr, char *buf)
285 {
286 	struct amdgpu_hive_info *hive = container_of(
287 		kobj, struct amdgpu_hive_info, kobj);
288 
289 	if (attr == &amdgpu_xgmi_hive_id)
290 		return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
291 
292 	return 0;
293 }
294 
amdgpu_xgmi_hive_release(struct kobject * kobj)295 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
296 {
297 	struct amdgpu_hive_info *hive = container_of(
298 		kobj, struct amdgpu_hive_info, kobj);
299 
300 	amdgpu_reset_put_reset_domain(hive->reset_domain);
301 	hive->reset_domain = NULL;
302 
303 	mutex_destroy(&hive->hive_lock);
304 	kfree(hive);
305 }
306 
307 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
308 	.show = amdgpu_xgmi_show_attrs,
309 };
310 
311 static const struct kobj_type amdgpu_xgmi_hive_type = {
312 	.release = amdgpu_xgmi_hive_release,
313 	.sysfs_ops = &amdgpu_xgmi_hive_ops,
314 	.default_groups = amdgpu_xgmi_hive_groups,
315 };
316 
amdgpu_xgmi_show_device_id(struct device * dev,struct device_attribute * attr,char * buf)317 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
318 				     struct device_attribute *attr,
319 				     char *buf)
320 {
321 	struct drm_device *ddev = dev_get_drvdata(dev);
322 	struct amdgpu_device *adev = drm_to_adev(ddev);
323 
324 	return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id);
325 
326 }
327 
amdgpu_xgmi_show_num_hops(struct device * dev,struct device_attribute * attr,char * buf)328 static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev,
329 					struct device_attribute *attr,
330 					char *buf)
331 {
332 	struct drm_device *ddev = dev_get_drvdata(dev);
333 	struct amdgpu_device *adev = drm_to_adev(ddev);
334 	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
335 	int i;
336 
337 	for (i = 0; i < top->num_nodes; i++)
338 		sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops);
339 
340 	return sysfs_emit(buf, "%s\n", buf);
341 }
342 
amdgpu_xgmi_show_num_links(struct device * dev,struct device_attribute * attr,char * buf)343 static ssize_t amdgpu_xgmi_show_num_links(struct device *dev,
344 					struct device_attribute *attr,
345 					char *buf)
346 {
347 	struct drm_device *ddev = dev_get_drvdata(dev);
348 	struct amdgpu_device *adev = drm_to_adev(ddev);
349 	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
350 	int i;
351 
352 	for (i = 0; i < top->num_nodes; i++)
353 		sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links);
354 
355 	return sysfs_emit(buf, "%s\n", buf);
356 }
357 
358 #define AMDGPU_XGMI_SET_FICAA(o)	((o) | 0x456801)
amdgpu_xgmi_show_error(struct device * dev,struct device_attribute * attr,char * buf)359 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
360 				      struct device_attribute *attr,
361 				      char *buf)
362 {
363 	struct drm_device *ddev = dev_get_drvdata(dev);
364 	struct amdgpu_device *adev = drm_to_adev(ddev);
365 	uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
366 	uint64_t fica_out;
367 	unsigned int error_count = 0;
368 
369 	ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
370 	ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
371 
372 	if ((!adev->df.funcs) ||
373 	    (!adev->df.funcs->get_fica) ||
374 	    (!adev->df.funcs->set_fica))
375 		return -EINVAL;
376 
377 	fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
378 	if (fica_out != 0x1f)
379 		pr_err("xGMI error counters not enabled!\n");
380 
381 	fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
382 
383 	if ((fica_out & 0xffff) == 2)
384 		error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
385 
386 	adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
387 
388 	return sysfs_emit(buf, "%u\n", error_count);
389 }
390 
391 
392 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
393 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
394 static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL);
395 static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL);
396 
amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)397 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
398 					 struct amdgpu_hive_info *hive)
399 {
400 	int ret = 0;
401 	char node[10] = { 0 };
402 
403 	/* Create xgmi device id file */
404 	ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
405 	if (ret) {
406 		dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
407 		return ret;
408 	}
409 
410 	/* Create xgmi error file */
411 	ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
412 	if (ret)
413 		pr_err("failed to create xgmi_error\n");
414 
415 	/* Create xgmi num hops file */
416 	ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops);
417 	if (ret)
418 		pr_err("failed to create xgmi_num_hops\n");
419 
420 	/* Create xgmi num links file */
421 	ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links);
422 	if (ret)
423 		pr_err("failed to create xgmi_num_links\n");
424 
425 	/* Create sysfs link to hive info folder on the first device */
426 	if (hive->kobj.parent != (&adev->dev->kobj)) {
427 		ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
428 					"xgmi_hive_info");
429 		if (ret) {
430 			dev_err(adev->dev, "XGMI: Failed to create link to hive info");
431 			goto remove_file;
432 		}
433 	}
434 
435 	sprintf(node, "node%d", atomic_read(&hive->number_devices));
436 	/* Create sysfs link form the hive folder to yourself */
437 	ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
438 	if (ret) {
439 		dev_err(adev->dev, "XGMI: Failed to create link from hive info");
440 		goto remove_link;
441 	}
442 
443 	goto success;
444 
445 
446 remove_link:
447 	sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
448 
449 remove_file:
450 	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
451 	device_remove_file(adev->dev, &dev_attr_xgmi_error);
452 	device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
453 	device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
454 
455 success:
456 	return ret;
457 }
458 
amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)459 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
460 					  struct amdgpu_hive_info *hive)
461 {
462 	char node[10];
463 	memset(node, 0, sizeof(node));
464 
465 	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
466 	device_remove_file(adev->dev, &dev_attr_xgmi_error);
467 	device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
468 	device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
469 
470 	if (hive->kobj.parent != (&adev->dev->kobj))
471 		sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
472 
473 	sprintf(node, "node%d", atomic_read(&hive->number_devices));
474 	sysfs_remove_link(&hive->kobj, node);
475 
476 }
477 
478 
479 
amdgpu_get_xgmi_hive(struct amdgpu_device * adev)480 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
481 {
482 	struct amdgpu_hive_info *hive = NULL;
483 	int ret;
484 
485 	if (!adev->gmc.xgmi.hive_id)
486 		return NULL;
487 
488 	if (adev->hive) {
489 		kobject_get(&adev->hive->kobj);
490 		return adev->hive;
491 	}
492 
493 	mutex_lock(&xgmi_mutex);
494 
495 	list_for_each_entry(hive, &xgmi_hive_list, node)  {
496 		if (hive->hive_id == adev->gmc.xgmi.hive_id)
497 			goto pro_end;
498 	}
499 
500 	hive = kzalloc(sizeof(*hive), GFP_KERNEL);
501 	if (!hive) {
502 		dev_err(adev->dev, "XGMI: allocation failed\n");
503 		ret = -ENOMEM;
504 		hive = NULL;
505 		goto pro_end;
506 	}
507 
508 	/* initialize new hive if not exist */
509 	ret = kobject_init_and_add(&hive->kobj,
510 			&amdgpu_xgmi_hive_type,
511 			&adev->dev->kobj,
512 			"%s", "xgmi_hive_info");
513 	if (ret) {
514 		dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
515 		kobject_put(&hive->kobj);
516 		hive = NULL;
517 		goto pro_end;
518 	}
519 
520 	/**
521 	 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV,
522 	 * Host driver decide how to reset the GPU either through FLR or chain reset.
523 	 * Guest side will get individual notifications from the host for the FLR
524 	 * if necessary.
525 	 */
526 	if (!amdgpu_sriov_vf(adev)) {
527 	/**
528 	 * Avoid recreating reset domain when hive is reconstructed for the case
529 	 * of reset the devices in the XGMI hive during probe for passthrough GPU
530 	 * See https://www.spinics.net/lists/amd-gfx/msg58836.html
531 	 */
532 		if (adev->reset_domain->type != XGMI_HIVE) {
533 			hive->reset_domain =
534 				amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive");
535 			if (!hive->reset_domain) {
536 				dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n");
537 				ret = -ENOMEM;
538 				kobject_put(&hive->kobj);
539 				hive = NULL;
540 				goto pro_end;
541 			}
542 		} else {
543 			amdgpu_reset_get_reset_domain(adev->reset_domain);
544 			hive->reset_domain = adev->reset_domain;
545 		}
546 	}
547 
548 	hive->hive_id = adev->gmc.xgmi.hive_id;
549 	INIT_LIST_HEAD(&hive->device_list);
550 	INIT_LIST_HEAD(&hive->node);
551 	mutex_init(&hive->hive_lock);
552 	atomic_set(&hive->number_devices, 0);
553 	task_barrier_init(&hive->tb);
554 	hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
555 	hive->hi_req_gpu = NULL;
556 
557 	/*
558 	 * hive pstate on boot is high in vega20 so we have to go to low
559 	 * pstate on after boot.
560 	 */
561 	hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
562 	list_add_tail(&hive->node, &xgmi_hive_list);
563 
564 pro_end:
565 	if (hive)
566 		kobject_get(&hive->kobj);
567 	mutex_unlock(&xgmi_mutex);
568 	return hive;
569 }
570 
amdgpu_put_xgmi_hive(struct amdgpu_hive_info * hive)571 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
572 {
573 	if (hive)
574 		kobject_put(&hive->kobj);
575 }
576 
amdgpu_xgmi_set_pstate(struct amdgpu_device * adev,int pstate)577 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
578 {
579 	int ret = 0;
580 	struct amdgpu_hive_info *hive;
581 	struct amdgpu_device *request_adev;
582 	bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
583 	bool init_low;
584 
585 	hive = amdgpu_get_xgmi_hive(adev);
586 	if (!hive)
587 		return 0;
588 
589 	request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev;
590 	init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
591 	amdgpu_put_xgmi_hive(hive);
592 	/* fw bug so temporarily disable pstate switching */
593 	return 0;
594 
595 	if (!hive || adev->asic_type != CHIP_VEGA20)
596 		return 0;
597 
598 	mutex_lock(&hive->hive_lock);
599 
600 	if (is_hi_req)
601 		hive->hi_req_count++;
602 	else
603 		hive->hi_req_count--;
604 
605 	/*
606 	 * Vega20 only needs single peer to request pstate high for the hive to
607 	 * go high but all peers must request pstate low for the hive to go low
608 	 */
609 	if (hive->pstate == pstate ||
610 			(!is_hi_req && hive->hi_req_count && !init_low))
611 		goto out;
612 
613 	dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
614 
615 	ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
616 	if (ret) {
617 		dev_err(request_adev->dev,
618 			"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
619 			request_adev->gmc.xgmi.node_id,
620 			request_adev->gmc.xgmi.hive_id, ret);
621 		goto out;
622 	}
623 
624 	if (init_low)
625 		hive->pstate = hive->hi_req_count ?
626 					hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
627 	else {
628 		hive->pstate = pstate;
629 		hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
630 							adev : NULL;
631 	}
632 out:
633 	mutex_unlock(&hive->hive_lock);
634 	return ret;
635 }
636 
amdgpu_xgmi_update_topology(struct amdgpu_hive_info * hive,struct amdgpu_device * adev)637 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
638 {
639 	int ret;
640 
641 	if (amdgpu_sriov_vf(adev))
642 		return 0;
643 
644 	/* Each psp need to set the latest topology */
645 	ret = psp_xgmi_set_topology_info(&adev->psp,
646 					 atomic_read(&hive->number_devices),
647 					 &adev->psp.xgmi_context.top_info);
648 	if (ret)
649 		dev_err(adev->dev,
650 			"XGMI: Set topology failure on device %llx, hive %llx, ret %d",
651 			adev->gmc.xgmi.node_id,
652 			adev->gmc.xgmi.hive_id, ret);
653 
654 	return ret;
655 }
656 
657 
658 /*
659  * NOTE psp_xgmi_node_info.num_hops layout is as follows:
660  * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved)
661  * num_hops[5:3] = reserved
662  * num_hops[2:0] = number of hops
663  */
amdgpu_xgmi_get_hops_count(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)664 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
665 		struct amdgpu_device *peer_adev)
666 {
667 	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
668 	uint8_t num_hops_mask = 0x7;
669 	int i;
670 
671 	for (i = 0 ; i < top->num_nodes; ++i)
672 		if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
673 			return top->nodes[i].num_hops & num_hops_mask;
674 	return	-EINVAL;
675 }
676 
amdgpu_xgmi_get_num_links(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)677 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
678 		struct amdgpu_device *peer_adev)
679 {
680 	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
681 	int i;
682 
683 	for (i = 0 ; i < top->num_nodes; ++i)
684 		if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
685 			return top->nodes[i].num_links;
686 	return	-EINVAL;
687 }
688 
689 /*
690  * Devices that support extended data require the entire hive to initialize with
691  * the shared memory buffer flag set.
692  *
693  * Hive locks and conditions apply - see amdgpu_xgmi_add_device
694  */
amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info * hive,bool set_extended_data)695 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive,
696 							bool set_extended_data)
697 {
698 	struct amdgpu_device *tmp_adev;
699 	int ret;
700 
701 	list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
702 		ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false);
703 		if (ret) {
704 			dev_err(tmp_adev->dev,
705 				"XGMI: Failed to initialize xgmi session for data partition %i\n",
706 				set_extended_data);
707 			return ret;
708 		}
709 
710 	}
711 
712 	return 0;
713 }
714 
amdgpu_xgmi_add_device(struct amdgpu_device * adev)715 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
716 {
717 	struct psp_xgmi_topology_info *top_info;
718 	struct amdgpu_hive_info *hive;
719 	struct amdgpu_xgmi	*entry;
720 	struct amdgpu_device *tmp_adev = NULL;
721 
722 	int count = 0, ret = 0;
723 
724 	if (!adev->gmc.xgmi.supported)
725 		return 0;
726 
727 	if (!adev->gmc.xgmi.pending_reset &&
728 	    amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
729 		ret = psp_xgmi_initialize(&adev->psp, false, true);
730 		if (ret) {
731 			dev_err(adev->dev,
732 				"XGMI: Failed to initialize xgmi session\n");
733 			return ret;
734 		}
735 
736 		ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
737 		if (ret) {
738 			dev_err(adev->dev,
739 				"XGMI: Failed to get hive id\n");
740 			return ret;
741 		}
742 
743 		ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
744 		if (ret) {
745 			dev_err(adev->dev,
746 				"XGMI: Failed to get node id\n");
747 			return ret;
748 		}
749 	} else {
750 		adev->gmc.xgmi.hive_id = 16;
751 		adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
752 	}
753 
754 	hive = amdgpu_get_xgmi_hive(adev);
755 	if (!hive) {
756 		ret = -EINVAL;
757 		dev_err(adev->dev,
758 			"XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
759 			adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
760 		goto exit;
761 	}
762 	mutex_lock(&hive->hive_lock);
763 
764 	top_info = &adev->psp.xgmi_context.top_info;
765 
766 	list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
767 	list_for_each_entry(entry, &hive->device_list, head)
768 		top_info->nodes[count++].node_id = entry->node_id;
769 	top_info->num_nodes = count;
770 	atomic_set(&hive->number_devices, count);
771 
772 	task_barrier_add_task(&hive->tb);
773 
774 	if (!adev->gmc.xgmi.pending_reset &&
775 	    amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
776 		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
777 			/* update node list for other device in the hive */
778 			if (tmp_adev != adev) {
779 				top_info = &tmp_adev->psp.xgmi_context.top_info;
780 				top_info->nodes[count - 1].node_id =
781 					adev->gmc.xgmi.node_id;
782 				top_info->num_nodes = count;
783 			}
784 			ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
785 			if (ret)
786 				goto exit_unlock;
787 		}
788 
789 		/* get latest topology info for each device from psp */
790 		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
791 			ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
792 					&tmp_adev->psp.xgmi_context.top_info, false);
793 			if (ret) {
794 				dev_err(tmp_adev->dev,
795 					"XGMI: Get topology failure on device %llx, hive %llx, ret %d",
796 					tmp_adev->gmc.xgmi.node_id,
797 					tmp_adev->gmc.xgmi.hive_id, ret);
798 				/* To do : continue with some node failed or disable the whole hive */
799 				goto exit_unlock;
800 			}
801 		}
802 
803 		/* get topology again for hives that support extended data */
804 		if (adev->psp.xgmi_context.supports_extended_data) {
805 
806 			/* initialize the hive to get extended data.  */
807 			ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true);
808 			if (ret)
809 				goto exit_unlock;
810 
811 			/* get the extended data. */
812 			list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
813 				ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
814 						&tmp_adev->psp.xgmi_context.top_info, true);
815 				if (ret) {
816 					dev_err(tmp_adev->dev,
817 						"XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d",
818 						tmp_adev->gmc.xgmi.node_id,
819 						tmp_adev->gmc.xgmi.hive_id, ret);
820 					goto exit_unlock;
821 				}
822 			}
823 
824 			/* initialize the hive to get non-extended data for the next round. */
825 			ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false);
826 			if (ret)
827 				goto exit_unlock;
828 
829 		}
830 	}
831 
832 	if (!ret && !adev->gmc.xgmi.pending_reset)
833 		ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
834 
835 exit_unlock:
836 	mutex_unlock(&hive->hive_lock);
837 exit:
838 	if (!ret) {
839 		adev->hive = hive;
840 		dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
841 			 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
842 	} else {
843 		amdgpu_put_xgmi_hive(hive);
844 		dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
845 			adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
846 			ret);
847 	}
848 
849 	return ret;
850 }
851 
amdgpu_xgmi_remove_device(struct amdgpu_device * adev)852 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
853 {
854 	struct amdgpu_hive_info *hive = adev->hive;
855 
856 	if (!adev->gmc.xgmi.supported)
857 		return -EINVAL;
858 
859 	if (!hive)
860 		return -EINVAL;
861 
862 	mutex_lock(&hive->hive_lock);
863 	task_barrier_rem_task(&hive->tb);
864 	amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
865 	if (hive->hi_req_gpu == adev)
866 		hive->hi_req_gpu = NULL;
867 	list_del(&adev->gmc.xgmi.head);
868 	mutex_unlock(&hive->hive_lock);
869 
870 	amdgpu_put_xgmi_hive(hive);
871 	adev->hive = NULL;
872 
873 	if (atomic_dec_return(&hive->number_devices) == 0) {
874 		/* Remove the hive from global hive list */
875 		mutex_lock(&xgmi_mutex);
876 		list_del(&hive->node);
877 		mutex_unlock(&xgmi_mutex);
878 
879 		amdgpu_put_xgmi_hive(hive);
880 	}
881 
882 	return 0;
883 }
884 
amdgpu_xgmi_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)885 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
886 {
887 	if (!adev->gmc.xgmi.supported ||
888 	    adev->gmc.xgmi.num_physical_nodes == 0)
889 		return 0;
890 
891 	adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
892 
893 	return amdgpu_ras_block_late_init(adev, ras_block);
894 }
895 
amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device * adev,uint64_t addr)896 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
897 					   uint64_t addr)
898 {
899 	struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
900 	return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
901 }
902 
pcs_clear_status(struct amdgpu_device * adev,uint32_t pcs_status_reg)903 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
904 {
905 	WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
906 	WREG32_PCIE(pcs_status_reg, 0);
907 }
908 
amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device * adev)909 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
910 {
911 	uint32_t i;
912 
913 	switch (adev->asic_type) {
914 	case CHIP_ARCTURUS:
915 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
916 			pcs_clear_status(adev,
917 					 xgmi_pcs_err_status_reg_arct[i]);
918 		break;
919 	case CHIP_VEGA20:
920 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
921 			pcs_clear_status(adev,
922 					 xgmi_pcs_err_status_reg_vg20[i]);
923 		break;
924 	case CHIP_ALDEBARAN:
925 		for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++)
926 			pcs_clear_status(adev,
927 					 xgmi3x16_pcs_err_status_reg_aldebaran[i]);
928 		for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++)
929 			pcs_clear_status(adev,
930 					 walf_pcs_err_status_reg_aldebaran[i]);
931 		break;
932 	default:
933 		break;
934 	}
935 }
936 
amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device * adev,uint32_t value,uint32_t mask_value,uint32_t * ue_count,uint32_t * ce_count,bool is_xgmi_pcs,bool check_mask)937 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
938 					      uint32_t value,
939 						  uint32_t mask_value,
940 					      uint32_t *ue_count,
941 					      uint32_t *ce_count,
942 					      bool is_xgmi_pcs,
943 						  bool check_mask)
944 {
945 	int i;
946 	int ue_cnt = 0;
947 	const struct amdgpu_pcs_ras_field *pcs_ras_fields = NULL;
948 	uint32_t field_array_size = 0;
949 
950 	if (is_xgmi_pcs) {
951 		if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) {
952 			pcs_ras_fields = &xgmi3x16_pcs_ras_fields[0];
953 			field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields);
954 		} else {
955 			pcs_ras_fields = &xgmi_pcs_ras_fields[0];
956 			field_array_size = ARRAY_SIZE(xgmi_pcs_ras_fields);
957 		}
958 	} else {
959 		pcs_ras_fields = &wafl_pcs_ras_fields[0];
960 		field_array_size = ARRAY_SIZE(wafl_pcs_ras_fields);
961 	}
962 
963 	if (check_mask)
964 		value = value & ~mask_value;
965 
966 	/* query xgmi/walf pcs error status,
967 	 * only ue is supported */
968 	for (i = 0; value && i < field_array_size; i++) {
969 		ue_cnt = (value &
970 				pcs_ras_fields[i].pcs_err_mask) >>
971 				pcs_ras_fields[i].pcs_err_shift;
972 		if (ue_cnt) {
973 			dev_info(adev->dev, "%s detected\n",
974 				 pcs_ras_fields[i].err_name);
975 			*ue_count += ue_cnt;
976 		}
977 
978 		/* reset bit value if the bit is checked */
979 		value &= ~(pcs_ras_fields[i].pcs_err_mask);
980 	}
981 
982 	return 0;
983 }
984 
amdgpu_xgmi_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)985 static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
986 					     void *ras_error_status)
987 {
988 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
989 	int i;
990 	uint32_t data, mask_data = 0;
991 	uint32_t ue_cnt = 0, ce_cnt = 0;
992 
993 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
994 		return ;
995 
996 	err_data->ue_count = 0;
997 	err_data->ce_count = 0;
998 
999 	switch (adev->asic_type) {
1000 	case CHIP_ARCTURUS:
1001 		/* check xgmi pcs error */
1002 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
1003 			data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
1004 			if (data)
1005 				amdgpu_xgmi_query_pcs_error_status(adev, data,
1006 						mask_data, &ue_cnt, &ce_cnt, true, false);
1007 		}
1008 		/* check wafl pcs error */
1009 		for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
1010 			data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
1011 			if (data)
1012 				amdgpu_xgmi_query_pcs_error_status(adev, data,
1013 						mask_data, &ue_cnt, &ce_cnt, false, false);
1014 		}
1015 		break;
1016 	case CHIP_VEGA20:
1017 		/* check xgmi pcs error */
1018 		for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
1019 			data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
1020 			if (data)
1021 				amdgpu_xgmi_query_pcs_error_status(adev, data,
1022 						mask_data, &ue_cnt, &ce_cnt, true, false);
1023 		}
1024 		/* check wafl pcs error */
1025 		for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
1026 			data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
1027 			if (data)
1028 				amdgpu_xgmi_query_pcs_error_status(adev, data,
1029 						mask_data, &ue_cnt, &ce_cnt, false, false);
1030 		}
1031 		break;
1032 	case CHIP_ALDEBARAN:
1033 		/* check xgmi3x16 pcs error */
1034 		for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) {
1035 			data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]);
1036 			mask_data =
1037 				RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
1038 			if (data)
1039 				amdgpu_xgmi_query_pcs_error_status(adev, data,
1040 						mask_data, &ue_cnt, &ce_cnt, true, true);
1041 		}
1042 		/* check wafl pcs error */
1043 		for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) {
1044 			data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]);
1045 			mask_data =
1046 				RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
1047 			if (data)
1048 				amdgpu_xgmi_query_pcs_error_status(adev, data,
1049 						mask_data, &ue_cnt, &ce_cnt, false, true);
1050 		}
1051 		break;
1052 	default:
1053 		dev_warn(adev->dev, "XGMI RAS error query not supported");
1054 		break;
1055 	}
1056 
1057 	adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1058 
1059 	err_data->ue_count += ue_cnt;
1060 	err_data->ce_count += ce_cnt;
1061 }
1062 
1063 /* Trigger XGMI/WAFL error */
amdgpu_ras_error_inject_xgmi(struct amdgpu_device * adev,void * inject_if,uint32_t instance_mask)1064 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
1065 			void *inject_if, uint32_t instance_mask)
1066 {
1067 	int ret = 0;
1068 	struct ta_ras_trigger_error_input *block_info =
1069 				(struct ta_ras_trigger_error_input *)inject_if;
1070 
1071 	if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
1072 		dev_warn(adev->dev, "Failed to disallow df cstate");
1073 
1074 	if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
1075 		dev_warn(adev->dev, "Failed to disallow XGMI power down");
1076 
1077 	ret = psp_ras_trigger_error(&adev->psp, block_info, instance_mask);
1078 
1079 	if (amdgpu_ras_intr_triggered())
1080 		return ret;
1081 
1082 	if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
1083 		dev_warn(adev->dev, "Failed to allow XGMI power down");
1084 
1085 	if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
1086 		dev_warn(adev->dev, "Failed to allow df cstate");
1087 
1088 	return ret;
1089 }
1090 
1091 struct amdgpu_ras_block_hw_ops  xgmi_ras_hw_ops = {
1092 	.query_ras_error_count = amdgpu_xgmi_query_ras_error_count,
1093 	.reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
1094 	.ras_error_inject = amdgpu_ras_error_inject_xgmi,
1095 };
1096 
1097 struct amdgpu_xgmi_ras xgmi_ras = {
1098 	.ras_block = {
1099 		.hw_ops = &xgmi_ras_hw_ops,
1100 		.ras_late_init = amdgpu_xgmi_ras_late_init,
1101 	},
1102 };
1103 
amdgpu_xgmi_ras_sw_init(struct amdgpu_device * adev)1104 int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev)
1105 {
1106 	int err;
1107 	struct amdgpu_xgmi_ras *ras;
1108 
1109 	if (!adev->gmc.xgmi.ras)
1110 		return 0;
1111 
1112 	ras = adev->gmc.xgmi.ras;
1113 	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1114 	if (err) {
1115 		dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n");
1116 		return err;
1117 	}
1118 
1119 	strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl");
1120 	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
1121 	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1122 	adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm;
1123 
1124 	return 0;
1125 }
1126