1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include <linux/firmware.h>
28 #include <linux/module.h>
29 #include <linux/dmi.h>
30 #include <linux/pci.h>
31 #include <linux/debugfs.h>
32 #include <drm/drm_drv.h>
33
34 #include "amdgpu.h"
35 #include "amdgpu_pm.h"
36 #include "amdgpu_vcn.h"
37 #include "soc15d.h"
38
39 /* Firmware Names */
40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin"
53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin"
58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin"
59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin"
60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin"
61
62 MODULE_FIRMWARE(FIRMWARE_RAVEN);
63 MODULE_FIRMWARE(FIRMWARE_PICASSO);
64 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
65 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
66 MODULE_FIRMWARE(FIRMWARE_RENOIR);
67 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
68 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
69 MODULE_FIRMWARE(FIRMWARE_NAVI10);
70 MODULE_FIRMWARE(FIRMWARE_NAVI14);
71 MODULE_FIRMWARE(FIRMWARE_NAVI12);
72 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
73 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
74 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
75 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
76 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
77 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
78 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
80 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
81 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3);
82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
83
84 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
85
amdgpu_vcn_early_init(struct amdgpu_device * adev)86 int amdgpu_vcn_early_init(struct amdgpu_device *adev)
87 {
88 char ucode_prefix[30];
89 char fw_name[40];
90 int r;
91
92 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
93 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
94 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name);
95 if (r)
96 amdgpu_ucode_release(&adev->vcn.fw);
97
98 return r;
99 }
100
amdgpu_vcn_sw_init(struct amdgpu_device * adev)101 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
102 {
103 unsigned long bo_size;
104 const struct common_firmware_header *hdr;
105 unsigned char fw_check;
106 unsigned int fw_shared_size, log_offset;
107 int i, r;
108
109 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
110 mutex_init(&adev->vcn.vcn_pg_lock);
111 mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
112 atomic_set(&adev->vcn.total_submission_cnt, 0);
113 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
114 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
115
116 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
117 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
118 adev->vcn.indirect_sram = true;
119
120 /*
121 * Some Steam Deck's BIOS versions are incompatible with the
122 * indirect SRAM mode, leading to amdgpu being unable to get
123 * properly probed (and even potentially crashing the kernel).
124 * Hence, check for these versions here - notice this is
125 * restricted to Vangogh (Deck's APU).
126 */
127 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 2)) {
128 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
129
130 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) ||
131 !strncmp("F7A0114", bios_ver, 7))) {
132 adev->vcn.indirect_sram = false;
133 dev_info(adev->dev,
134 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);
135 }
136 }
137
138 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
139 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
140
141 /* Bit 20-23, it is encode major and non-zero for new naming convention.
142 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
143 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
144 * is zero in old naming convention, this field is always zero so far.
145 * These four bits are used to tell which naming convention is present.
146 */
147 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
148 if (fw_check) {
149 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
150
151 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
152 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
153 enc_major = fw_check;
154 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
155 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
156 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
157 enc_major, enc_minor, dec_ver, vep, fw_rev);
158 } else {
159 unsigned int version_major, version_minor, family_id;
160
161 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
162 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
163 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
164 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
165 version_major, version_minor, family_id);
166 }
167
168 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
169 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
170 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
171
172 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) {
173 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
174 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
175 } else {
176 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
177 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
178 }
179
180 bo_size += fw_shared_size;
181
182 if (amdgpu_vcnfw_log)
183 bo_size += AMDGPU_VCNFW_LOG_SIZE;
184
185 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
186 if (adev->vcn.harvest_config & (1 << i))
187 continue;
188
189 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
190 AMDGPU_GEM_DOMAIN_VRAM |
191 AMDGPU_GEM_DOMAIN_GTT,
192 &adev->vcn.inst[i].vcpu_bo,
193 &adev->vcn.inst[i].gpu_addr,
194 &adev->vcn.inst[i].cpu_addr);
195 if (r) {
196 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
197 return r;
198 }
199
200 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
201 bo_size - fw_shared_size;
202 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
203 bo_size - fw_shared_size;
204
205 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
206
207 if (amdgpu_vcnfw_log) {
208 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
209 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
210 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
211 }
212
213 if (adev->vcn.indirect_sram) {
214 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
215 AMDGPU_GEM_DOMAIN_VRAM |
216 AMDGPU_GEM_DOMAIN_GTT,
217 &adev->vcn.inst[i].dpg_sram_bo,
218 &adev->vcn.inst[i].dpg_sram_gpu_addr,
219 &adev->vcn.inst[i].dpg_sram_cpu_addr);
220 if (r) {
221 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
222 return r;
223 }
224 }
225 }
226
227 return 0;
228 }
229
amdgpu_vcn_sw_fini(struct amdgpu_device * adev)230 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
231 {
232 int i, j;
233
234 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
235 if (adev->vcn.harvest_config & (1 << j))
236 continue;
237
238 amdgpu_bo_free_kernel(
239 &adev->vcn.inst[j].dpg_sram_bo,
240 &adev->vcn.inst[j].dpg_sram_gpu_addr,
241 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
242
243 kvfree(adev->vcn.inst[j].saved_bo);
244
245 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
246 &adev->vcn.inst[j].gpu_addr,
247 (void **)&adev->vcn.inst[j].cpu_addr);
248
249 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
250
251 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
252 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
253 }
254
255 amdgpu_ucode_release(&adev->vcn.fw);
256 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
257 mutex_destroy(&adev->vcn.vcn_pg_lock);
258
259 return 0;
260 }
261
262 /* from vcn4 and above, only unified queue is used */
amdgpu_vcn_using_unified_queue(struct amdgpu_ring * ring)263 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
264 {
265 struct amdgpu_device *adev = ring->adev;
266 bool ret = false;
267
268 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
269 ret = true;
270
271 return ret;
272 }
273
amdgpu_vcn_is_disabled_vcn(struct amdgpu_device * adev,enum vcn_ring_type type,uint32_t vcn_instance)274 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
275 {
276 bool ret = false;
277 int vcn_config = adev->vcn.vcn_config[vcn_instance];
278
279 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))
280 ret = true;
281 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK))
282 ret = true;
283 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK))
284 ret = true;
285
286 return ret;
287 }
288
amdgpu_vcn_suspend(struct amdgpu_device * adev)289 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
290 {
291 unsigned int size;
292 void *ptr;
293 int i, idx;
294
295 bool in_ras_intr = amdgpu_ras_intr_triggered();
296
297 cancel_delayed_work_sync(&adev->vcn.idle_work);
298
299 /* err_event_athub will corrupt VCPU buffer, so we need to
300 * restore fw data and clear buffer in amdgpu_vcn_resume() */
301 if (in_ras_intr)
302 return 0;
303
304 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
305 if (adev->vcn.harvest_config & (1 << i))
306 continue;
307 if (adev->vcn.inst[i].vcpu_bo == NULL)
308 return 0;
309
310 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
311 ptr = adev->vcn.inst[i].cpu_addr;
312
313 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
314 if (!adev->vcn.inst[i].saved_bo)
315 return -ENOMEM;
316
317 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
318 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
319 drm_dev_exit(idx);
320 }
321 }
322 return 0;
323 }
324
amdgpu_vcn_resume(struct amdgpu_device * adev)325 int amdgpu_vcn_resume(struct amdgpu_device *adev)
326 {
327 unsigned int size;
328 void *ptr;
329 int i, idx;
330
331 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
332 if (adev->vcn.harvest_config & (1 << i))
333 continue;
334 if (adev->vcn.inst[i].vcpu_bo == NULL)
335 return -EINVAL;
336
337 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
338 ptr = adev->vcn.inst[i].cpu_addr;
339
340 if (adev->vcn.inst[i].saved_bo != NULL) {
341 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
342 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
343 drm_dev_exit(idx);
344 }
345 kvfree(adev->vcn.inst[i].saved_bo);
346 adev->vcn.inst[i].saved_bo = NULL;
347 } else {
348 const struct common_firmware_header *hdr;
349 unsigned int offset;
350
351 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
352 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
353 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
354 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
355 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
356 le32_to_cpu(hdr->ucode_size_bytes));
357 drm_dev_exit(idx);
358 }
359 size -= le32_to_cpu(hdr->ucode_size_bytes);
360 ptr += le32_to_cpu(hdr->ucode_size_bytes);
361 }
362 memset_io(ptr, 0, size);
363 }
364 }
365 return 0;
366 }
367
amdgpu_vcn_idle_work_handler(struct work_struct * work)368 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
369 {
370 struct amdgpu_device *adev =
371 container_of(work, struct amdgpu_device, vcn.idle_work.work);
372 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
373 unsigned int i, j;
374 int r = 0;
375
376 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
377 if (adev->vcn.harvest_config & (1 << j))
378 continue;
379
380 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
381 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
382
383 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
384 struct dpg_pause_state new_state;
385
386 if (fence[j] ||
387 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
388 new_state.fw_based = VCN_DPG_STATE__PAUSE;
389 else
390 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
391
392 adev->vcn.pause_dpg_mode(adev, j, &new_state);
393 }
394
395 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
396 fences += fence[j];
397 }
398
399 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
400 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
401 AMD_PG_STATE_GATE);
402 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
403 false);
404 if (r)
405 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
406 } else {
407 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
408 }
409 }
410
amdgpu_vcn_ring_begin_use(struct amdgpu_ring * ring)411 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
412 {
413 struct amdgpu_device *adev = ring->adev;
414 int r = 0;
415
416 atomic_inc(&adev->vcn.total_submission_cnt);
417
418 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
419 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
420 true);
421 if (r)
422 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
423 }
424
425 mutex_lock(&adev->vcn.vcn_pg_lock);
426 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
427 AMD_PG_STATE_UNGATE);
428
429 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
430 struct dpg_pause_state new_state;
431
432 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
433 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
434 new_state.fw_based = VCN_DPG_STATE__PAUSE;
435 } else {
436 unsigned int fences = 0;
437 unsigned int i;
438
439 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
440 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
441
442 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
443 new_state.fw_based = VCN_DPG_STATE__PAUSE;
444 else
445 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
446 }
447
448 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
449 }
450 mutex_unlock(&adev->vcn.vcn_pg_lock);
451 }
452
amdgpu_vcn_ring_end_use(struct amdgpu_ring * ring)453 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
454 {
455 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
456 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
457 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
458
459 atomic_dec(&ring->adev->vcn.total_submission_cnt);
460
461 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
462 }
463
amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring * ring)464 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
465 {
466 struct amdgpu_device *adev = ring->adev;
467 uint32_t tmp = 0;
468 unsigned int i;
469 int r;
470
471 /* VCN in SRIOV does not support direct register read/write */
472 if (amdgpu_sriov_vf(adev))
473 return 0;
474
475 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
476 r = amdgpu_ring_alloc(ring, 3);
477 if (r)
478 return r;
479 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
480 amdgpu_ring_write(ring, 0xDEADBEEF);
481 amdgpu_ring_commit(ring);
482 for (i = 0; i < adev->usec_timeout; i++) {
483 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
484 if (tmp == 0xDEADBEEF)
485 break;
486 udelay(1);
487 }
488
489 if (i >= adev->usec_timeout)
490 r = -ETIMEDOUT;
491
492 return r;
493 }
494
amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring * ring)495 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
496 {
497 struct amdgpu_device *adev = ring->adev;
498 uint32_t rptr;
499 unsigned int i;
500 int r;
501
502 if (amdgpu_sriov_vf(adev))
503 return 0;
504
505 r = amdgpu_ring_alloc(ring, 16);
506 if (r)
507 return r;
508
509 rptr = amdgpu_ring_get_rptr(ring);
510
511 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
512 amdgpu_ring_commit(ring);
513
514 for (i = 0; i < adev->usec_timeout; i++) {
515 if (amdgpu_ring_get_rptr(ring) != rptr)
516 break;
517 udelay(1);
518 }
519
520 if (i >= adev->usec_timeout)
521 r = -ETIMEDOUT;
522
523 return r;
524 }
525
amdgpu_vcn_dec_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)526 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
527 struct amdgpu_ib *ib_msg,
528 struct dma_fence **fence)
529 {
530 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
531 struct amdgpu_device *adev = ring->adev;
532 struct dma_fence *f = NULL;
533 struct amdgpu_job *job;
534 struct amdgpu_ib *ib;
535 int i, r;
536
537 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
538 64, AMDGPU_IB_POOL_DIRECT,
539 &job);
540 if (r)
541 goto err;
542
543 ib = &job->ibs[0];
544 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
545 ib->ptr[1] = addr;
546 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
547 ib->ptr[3] = addr >> 32;
548 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
549 ib->ptr[5] = 0;
550 for (i = 6; i < 16; i += 2) {
551 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
552 ib->ptr[i+1] = 0;
553 }
554 ib->length_dw = 16;
555
556 r = amdgpu_job_submit_direct(job, ring, &f);
557 if (r)
558 goto err_free;
559
560 amdgpu_ib_free(adev, ib_msg, f);
561
562 if (fence)
563 *fence = dma_fence_get(f);
564 dma_fence_put(f);
565
566 return 0;
567
568 err_free:
569 amdgpu_job_free(job);
570 err:
571 amdgpu_ib_free(adev, ib_msg, f);
572 return r;
573 }
574
amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)575 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
576 struct amdgpu_ib *ib)
577 {
578 struct amdgpu_device *adev = ring->adev;
579 uint32_t *msg;
580 int r, i;
581
582 memset(ib, 0, sizeof(*ib));
583 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
584 AMDGPU_IB_POOL_DIRECT,
585 ib);
586 if (r)
587 return r;
588
589 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
590 msg[0] = cpu_to_le32(0x00000028);
591 msg[1] = cpu_to_le32(0x00000038);
592 msg[2] = cpu_to_le32(0x00000001);
593 msg[3] = cpu_to_le32(0x00000000);
594 msg[4] = cpu_to_le32(handle);
595 msg[5] = cpu_to_le32(0x00000000);
596 msg[6] = cpu_to_le32(0x00000001);
597 msg[7] = cpu_to_le32(0x00000028);
598 msg[8] = cpu_to_le32(0x00000010);
599 msg[9] = cpu_to_le32(0x00000000);
600 msg[10] = cpu_to_le32(0x00000007);
601 msg[11] = cpu_to_le32(0x00000000);
602 msg[12] = cpu_to_le32(0x00000780);
603 msg[13] = cpu_to_le32(0x00000440);
604 for (i = 14; i < 1024; ++i)
605 msg[i] = cpu_to_le32(0x0);
606
607 return 0;
608 }
609
amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)610 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
611 struct amdgpu_ib *ib)
612 {
613 struct amdgpu_device *adev = ring->adev;
614 uint32_t *msg;
615 int r, i;
616
617 memset(ib, 0, sizeof(*ib));
618 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
619 AMDGPU_IB_POOL_DIRECT,
620 ib);
621 if (r)
622 return r;
623
624 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
625 msg[0] = cpu_to_le32(0x00000028);
626 msg[1] = cpu_to_le32(0x00000018);
627 msg[2] = cpu_to_le32(0x00000000);
628 msg[3] = cpu_to_le32(0x00000002);
629 msg[4] = cpu_to_le32(handle);
630 msg[5] = cpu_to_le32(0x00000000);
631 for (i = 6; i < 1024; ++i)
632 msg[i] = cpu_to_le32(0x0);
633
634 return 0;
635 }
636
amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring * ring,long timeout)637 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
638 {
639 struct dma_fence *fence = NULL;
640 struct amdgpu_ib ib;
641 long r;
642
643 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
644 if (r)
645 goto error;
646
647 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
648 if (r)
649 goto error;
650 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
651 if (r)
652 goto error;
653
654 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
655 if (r)
656 goto error;
657
658 r = dma_fence_wait_timeout(fence, false, timeout);
659 if (r == 0)
660 r = -ETIMEDOUT;
661 else if (r > 0)
662 r = 0;
663
664 dma_fence_put(fence);
665 error:
666 return r;
667 }
668
amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib * ib,uint32_t ib_pack_in_dw,bool enc)669 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
670 uint32_t ib_pack_in_dw, bool enc)
671 {
672 uint32_t *ib_checksum;
673
674 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
675 ib->ptr[ib->length_dw++] = 0x30000002;
676 ib_checksum = &ib->ptr[ib->length_dw++];
677 ib->ptr[ib->length_dw++] = ib_pack_in_dw;
678
679 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
680 ib->ptr[ib->length_dw++] = 0x30000001;
681 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
682 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
683
684 return ib_checksum;
685 }
686
amdgpu_vcn_unified_ring_ib_checksum(uint32_t ** ib_checksum,uint32_t ib_pack_in_dw)687 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
688 uint32_t ib_pack_in_dw)
689 {
690 uint32_t i;
691 uint32_t checksum = 0;
692
693 for (i = 0; i < ib_pack_in_dw; i++)
694 checksum += *(*ib_checksum + 2 + i);
695
696 **ib_checksum = checksum;
697 }
698
amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)699 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
700 struct amdgpu_ib *ib_msg,
701 struct dma_fence **fence)
702 {
703 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
704 unsigned int ib_size_dw = 64;
705 struct amdgpu_device *adev = ring->adev;
706 struct dma_fence *f = NULL;
707 struct amdgpu_job *job;
708 struct amdgpu_ib *ib;
709 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
710 bool sq = amdgpu_vcn_using_unified_queue(ring);
711 uint32_t *ib_checksum;
712 uint32_t ib_pack_in_dw;
713 int i, r;
714
715 if (sq)
716 ib_size_dw += 8;
717
718 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
719 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
720 &job);
721 if (r)
722 goto err;
723
724 ib = &job->ibs[0];
725 ib->length_dw = 0;
726
727 /* single queue headers */
728 if (sq) {
729 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
730 + 4 + 2; /* engine info + decoding ib in dw */
731 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
732 }
733
734 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
735 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
736 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
737 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
738 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
739
740 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
741 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
742 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
743
744 for (i = ib->length_dw; i < ib_size_dw; ++i)
745 ib->ptr[i] = 0x0;
746
747 if (sq)
748 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
749
750 r = amdgpu_job_submit_direct(job, ring, &f);
751 if (r)
752 goto err_free;
753
754 amdgpu_ib_free(adev, ib_msg, f);
755
756 if (fence)
757 *fence = dma_fence_get(f);
758 dma_fence_put(f);
759
760 return 0;
761
762 err_free:
763 amdgpu_job_free(job);
764 err:
765 amdgpu_ib_free(adev, ib_msg, f);
766 return r;
767 }
768
amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring * ring,long timeout)769 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
770 {
771 struct dma_fence *fence = NULL;
772 struct amdgpu_ib ib;
773 long r;
774
775 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
776 if (r)
777 goto error;
778
779 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
780 if (r)
781 goto error;
782 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
783 if (r)
784 goto error;
785
786 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
787 if (r)
788 goto error;
789
790 r = dma_fence_wait_timeout(fence, false, timeout);
791 if (r == 0)
792 r = -ETIMEDOUT;
793 else if (r > 0)
794 r = 0;
795
796 dma_fence_put(fence);
797 error:
798 return r;
799 }
800
amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring * ring)801 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
802 {
803 struct amdgpu_device *adev = ring->adev;
804 uint32_t rptr;
805 unsigned int i;
806 int r;
807
808 if (amdgpu_sriov_vf(adev))
809 return 0;
810
811 r = amdgpu_ring_alloc(ring, 16);
812 if (r)
813 return r;
814
815 rptr = amdgpu_ring_get_rptr(ring);
816
817 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
818 amdgpu_ring_commit(ring);
819
820 for (i = 0; i < adev->usec_timeout; i++) {
821 if (amdgpu_ring_get_rptr(ring) != rptr)
822 break;
823 udelay(1);
824 }
825
826 if (i >= adev->usec_timeout)
827 r = -ETIMEDOUT;
828
829 return r;
830 }
831
amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)832 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
833 struct amdgpu_ib *ib_msg,
834 struct dma_fence **fence)
835 {
836 unsigned int ib_size_dw = 16;
837 struct amdgpu_job *job;
838 struct amdgpu_ib *ib;
839 struct dma_fence *f = NULL;
840 uint32_t *ib_checksum = NULL;
841 uint64_t addr;
842 bool sq = amdgpu_vcn_using_unified_queue(ring);
843 int i, r;
844
845 if (sq)
846 ib_size_dw += 8;
847
848 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
849 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
850 &job);
851 if (r)
852 return r;
853
854 ib = &job->ibs[0];
855 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
856
857 ib->length_dw = 0;
858
859 if (sq)
860 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
861
862 ib->ptr[ib->length_dw++] = 0x00000018;
863 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
864 ib->ptr[ib->length_dw++] = handle;
865 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
866 ib->ptr[ib->length_dw++] = addr;
867 ib->ptr[ib->length_dw++] = 0x0000000b;
868
869 ib->ptr[ib->length_dw++] = 0x00000014;
870 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
871 ib->ptr[ib->length_dw++] = 0x0000001c;
872 ib->ptr[ib->length_dw++] = 0x00000000;
873 ib->ptr[ib->length_dw++] = 0x00000000;
874
875 ib->ptr[ib->length_dw++] = 0x00000008;
876 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
877
878 for (i = ib->length_dw; i < ib_size_dw; ++i)
879 ib->ptr[i] = 0x0;
880
881 if (sq)
882 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
883
884 r = amdgpu_job_submit_direct(job, ring, &f);
885 if (r)
886 goto err;
887
888 if (fence)
889 *fence = dma_fence_get(f);
890 dma_fence_put(f);
891
892 return 0;
893
894 err:
895 amdgpu_job_free(job);
896 return r;
897 }
898
amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)899 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
900 struct amdgpu_ib *ib_msg,
901 struct dma_fence **fence)
902 {
903 unsigned int ib_size_dw = 16;
904 struct amdgpu_job *job;
905 struct amdgpu_ib *ib;
906 struct dma_fence *f = NULL;
907 uint32_t *ib_checksum = NULL;
908 uint64_t addr;
909 bool sq = amdgpu_vcn_using_unified_queue(ring);
910 int i, r;
911
912 if (sq)
913 ib_size_dw += 8;
914
915 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
916 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
917 &job);
918 if (r)
919 return r;
920
921 ib = &job->ibs[0];
922 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
923
924 ib->length_dw = 0;
925
926 if (sq)
927 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
928
929 ib->ptr[ib->length_dw++] = 0x00000018;
930 ib->ptr[ib->length_dw++] = 0x00000001;
931 ib->ptr[ib->length_dw++] = handle;
932 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
933 ib->ptr[ib->length_dw++] = addr;
934 ib->ptr[ib->length_dw++] = 0x0000000b;
935
936 ib->ptr[ib->length_dw++] = 0x00000014;
937 ib->ptr[ib->length_dw++] = 0x00000002;
938 ib->ptr[ib->length_dw++] = 0x0000001c;
939 ib->ptr[ib->length_dw++] = 0x00000000;
940 ib->ptr[ib->length_dw++] = 0x00000000;
941
942 ib->ptr[ib->length_dw++] = 0x00000008;
943 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
944
945 for (i = ib->length_dw; i < ib_size_dw; ++i)
946 ib->ptr[i] = 0x0;
947
948 if (sq)
949 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
950
951 r = amdgpu_job_submit_direct(job, ring, &f);
952 if (r)
953 goto err;
954
955 if (fence)
956 *fence = dma_fence_get(f);
957 dma_fence_put(f);
958
959 return 0;
960
961 err:
962 amdgpu_job_free(job);
963 return r;
964 }
965
amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)966 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
967 {
968 struct amdgpu_device *adev = ring->adev;
969 struct dma_fence *fence = NULL;
970 struct amdgpu_ib ib;
971 long r;
972
973 memset(&ib, 0, sizeof(ib));
974 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
975 AMDGPU_IB_POOL_DIRECT,
976 &ib);
977 if (r)
978 return r;
979
980 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
981 if (r)
982 goto error;
983
984 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
985 if (r)
986 goto error;
987
988 r = dma_fence_wait_timeout(fence, false, timeout);
989 if (r == 0)
990 r = -ETIMEDOUT;
991 else if (r > 0)
992 r = 0;
993
994 error:
995 amdgpu_ib_free(adev, &ib, fence);
996 dma_fence_put(fence);
997
998 return r;
999 }
1000
amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring * ring,long timeout)1001 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1002 {
1003 struct amdgpu_device *adev = ring->adev;
1004 long r;
1005
1006 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(4, 0, 3)) {
1007 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1008 if (r)
1009 goto error;
1010 }
1011
1012 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1013
1014 error:
1015 return r;
1016 }
1017
amdgpu_vcn_get_enc_ring_prio(int ring)1018 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1019 {
1020 switch (ring) {
1021 case 0:
1022 return AMDGPU_RING_PRIO_0;
1023 case 1:
1024 return AMDGPU_RING_PRIO_1;
1025 case 2:
1026 return AMDGPU_RING_PRIO_2;
1027 default:
1028 return AMDGPU_RING_PRIO_0;
1029 }
1030 }
1031
amdgpu_vcn_setup_ucode(struct amdgpu_device * adev)1032 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1033 {
1034 int i;
1035 unsigned int idx;
1036
1037 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1038 const struct common_firmware_header *hdr;
1039
1040 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1041
1042 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1043 if (adev->vcn.harvest_config & (1 << i))
1044 continue;
1045 /* currently only support 2 FW instances */
1046 if (i >= 2) {
1047 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1048 break;
1049 }
1050 idx = AMDGPU_UCODE_ID_VCN + i;
1051 adev->firmware.ucode[idx].ucode_id = idx;
1052 adev->firmware.ucode[idx].fw = adev->vcn.fw;
1053 adev->firmware.fw_size +=
1054 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1055
1056 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(4, 0, 3))
1057 break;
1058 }
1059 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1060 }
1061 }
1062
1063 /*
1064 * debugfs for mapping vcn firmware log buffer.
1065 */
1066 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_vcn_fwlog_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1067 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1068 size_t size, loff_t *pos)
1069 {
1070 struct amdgpu_vcn_inst *vcn;
1071 void *log_buf;
1072 volatile struct amdgpu_vcn_fwlog *plog;
1073 unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1074 unsigned int read_num[2] = {0};
1075
1076 vcn = file_inode(f)->i_private;
1077 if (!vcn)
1078 return -ENODEV;
1079
1080 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1081 return -EFAULT;
1082
1083 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1084
1085 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1086 read_pos = plog->rptr;
1087 write_pos = plog->wptr;
1088
1089 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1090 return -EFAULT;
1091
1092 if (!size || (read_pos == write_pos))
1093 return 0;
1094
1095 if (write_pos > read_pos) {
1096 available = write_pos - read_pos;
1097 read_num[0] = min(size, (size_t)available);
1098 } else {
1099 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1100 available = read_num[0] + write_pos - plog->header_size;
1101 if (size > available)
1102 read_num[1] = write_pos - plog->header_size;
1103 else if (size > read_num[0])
1104 read_num[1] = size - read_num[0];
1105 else
1106 read_num[0] = size;
1107 }
1108
1109 for (i = 0; i < 2; i++) {
1110 if (read_num[i]) {
1111 if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1112 read_pos = plog->header_size;
1113 if (read_num[i] == copy_to_user((buf + read_bytes),
1114 (log_buf + read_pos), read_num[i]))
1115 return -EFAULT;
1116
1117 read_bytes += read_num[i];
1118 read_pos += read_num[i];
1119 }
1120 }
1121
1122 plog->rptr = read_pos;
1123 *pos += read_bytes;
1124 return read_bytes;
1125 }
1126
1127 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1128 .owner = THIS_MODULE,
1129 .read = amdgpu_debugfs_vcn_fwlog_read,
1130 .llseek = default_llseek
1131 };
1132 #endif
1133
amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device * adev,uint8_t i,struct amdgpu_vcn_inst * vcn)1134 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1135 struct amdgpu_vcn_inst *vcn)
1136 {
1137 #if defined(CONFIG_DEBUG_FS)
1138 struct drm_minor *minor = adev_to_drm(adev)->primary;
1139 struct dentry *root = minor->debugfs_root;
1140 char name[32];
1141
1142 sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1143 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn,
1144 &amdgpu_debugfs_vcnfwlog_fops,
1145 AMDGPU_VCNFW_LOG_SIZE);
1146 #endif
1147 }
1148
amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst * vcn)1149 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1150 {
1151 #if defined(CONFIG_DEBUG_FS)
1152 volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1153 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1154 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1155 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1156 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1157 + vcn->fw_shared.log_offset;
1158 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1159 fw_log->is_enabled = 1;
1160 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1161 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1162 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1163
1164 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1165 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1166 log_buf->rptr = log_buf->header_size;
1167 log_buf->wptr = log_buf->header_size;
1168 log_buf->wrapped = 0;
1169 #endif
1170 }
1171
amdgpu_vcn_process_poison_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1172 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1173 struct amdgpu_irq_src *source,
1174 struct amdgpu_iv_entry *entry)
1175 {
1176 struct ras_common_if *ras_if = adev->vcn.ras_if;
1177 struct ras_dispatch_if ih_data = {
1178 .entry = entry,
1179 };
1180
1181 if (!ras_if)
1182 return 0;
1183
1184 if (!amdgpu_sriov_vf(adev)) {
1185 ih_data.head = *ras_if;
1186 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1187 } else {
1188 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
1189 adev->virt.ops->ras_poison_handler(adev);
1190 else
1191 dev_warn(adev->dev,
1192 "No ras_poison_handler interface in SRIOV for VCN!\n");
1193 }
1194
1195 return 0;
1196 }
1197
amdgpu_vcn_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)1198 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
1199 {
1200 int r, i;
1201
1202 r = amdgpu_ras_block_late_init(adev, ras_block);
1203 if (r)
1204 return r;
1205
1206 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
1207 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1208 if (adev->vcn.harvest_config & (1 << i) ||
1209 !adev->vcn.inst[i].ras_poison_irq.funcs)
1210 continue;
1211
1212 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1213 if (r)
1214 goto late_fini;
1215 }
1216 }
1217 return 0;
1218
1219 late_fini:
1220 amdgpu_ras_block_late_fini(adev, ras_block);
1221 return r;
1222 }
1223
amdgpu_vcn_ras_sw_init(struct amdgpu_device * adev)1224 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
1225 {
1226 int err;
1227 struct amdgpu_vcn_ras *ras;
1228
1229 if (!adev->vcn.ras)
1230 return 0;
1231
1232 ras = adev->vcn.ras;
1233 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1234 if (err) {
1235 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1236 return err;
1237 }
1238
1239 strcpy(ras->ras_block.ras_comm.name, "vcn");
1240 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
1241 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
1242 adev->vcn.ras_if = &ras->ras_block.ras_comm;
1243
1244 if (!ras->ras_block.ras_late_init)
1245 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init;
1246
1247 return 0;
1248 }
1249
amdgpu_vcn_psp_update_sram(struct amdgpu_device * adev,int inst_idx,enum AMDGPU_UCODE_ID ucode_id)1250 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
1251 enum AMDGPU_UCODE_ID ucode_id)
1252 {
1253 struct amdgpu_firmware_info ucode = {
1254 .ucode_id = (ucode_id ? ucode_id :
1255 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1256 AMDGPU_UCODE_ID_VCN0_RAM)),
1257 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1258 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1259 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
1260 };
1261
1262 return psp_execute_ip_fw_load(&adev->psp, &ucode);
1263 }
1264