1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/pagemap.h>
36 #include <linux/sched/task.h>
37 #include <linux/sched/mm.h>
38 #include <linux/seq_file.h>
39 #include <linux/slab.h>
40 #include <linux/swap.h>
41 #include <linux/dma-buf.h>
42 #include <linux/sizes.h>
43 #include <linux/module.h>
44 
45 #include <drm/drm_drv.h>
46 #include <drm/ttm/ttm_bo.h>
47 #include <drm/ttm/ttm_placement.h>
48 #include <drm/ttm/ttm_range_manager.h>
49 #include <drm/ttm/ttm_tt.h>
50 
51 #include <drm/amdgpu_drm.h>
52 
53 #include "amdgpu.h"
54 #include "amdgpu_object.h"
55 #include "amdgpu_trace.h"
56 #include "amdgpu_amdkfd.h"
57 #include "amdgpu_sdma.h"
58 #include "amdgpu_ras.h"
59 #include "amdgpu_hmm.h"
60 #include "amdgpu_atomfirmware.h"
61 #include "amdgpu_res_cursor.h"
62 #include "bif/bif_4_1_d.h"
63 
64 MODULE_IMPORT_NS(DMA_BUF);
65 
66 #define AMDGPU_TTM_VRAM_MAX_DW_READ	((size_t)128)
67 
68 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
69 				   struct ttm_tt *ttm,
70 				   struct ttm_resource *bo_mem);
71 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
72 				      struct ttm_tt *ttm);
73 
amdgpu_ttm_init_on_chip(struct amdgpu_device * adev,unsigned int type,uint64_t size_in_page)74 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
75 				    unsigned int type,
76 				    uint64_t size_in_page)
77 {
78 	return ttm_range_man_init(&adev->mman.bdev, type,
79 				  false, size_in_page);
80 }
81 
82 /**
83  * amdgpu_evict_flags - Compute placement flags
84  *
85  * @bo: The buffer object to evict
86  * @placement: Possible destination(s) for evicted BO
87  *
88  * Fill in placement data when ttm_bo_evict() is called
89  */
amdgpu_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * placement)90 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
91 				struct ttm_placement *placement)
92 {
93 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
94 	struct amdgpu_bo *abo;
95 	static const struct ttm_place placements = {
96 		.fpfn = 0,
97 		.lpfn = 0,
98 		.mem_type = TTM_PL_SYSTEM,
99 		.flags = 0
100 	};
101 
102 	/* Don't handle scatter gather BOs */
103 	if (bo->type == ttm_bo_type_sg) {
104 		placement->num_placement = 0;
105 		placement->num_busy_placement = 0;
106 		return;
107 	}
108 
109 	/* Object isn't an AMDGPU object so ignore */
110 	if (!amdgpu_bo_is_amdgpu_bo(bo)) {
111 		placement->placement = &placements;
112 		placement->busy_placement = &placements;
113 		placement->num_placement = 1;
114 		placement->num_busy_placement = 1;
115 		return;
116 	}
117 
118 	abo = ttm_to_amdgpu_bo(bo);
119 	if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
120 		placement->num_placement = 0;
121 		placement->num_busy_placement = 0;
122 		return;
123 	}
124 
125 	switch (bo->resource->mem_type) {
126 	case AMDGPU_PL_GDS:
127 	case AMDGPU_PL_GWS:
128 	case AMDGPU_PL_OA:
129 	case AMDGPU_PL_DOORBELL:
130 		placement->num_placement = 0;
131 		placement->num_busy_placement = 0;
132 		return;
133 
134 	case TTM_PL_VRAM:
135 		if (!adev->mman.buffer_funcs_enabled) {
136 			/* Move to system memory */
137 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
138 		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
139 			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
140 			   amdgpu_bo_in_cpu_visible_vram(abo)) {
141 
142 			/* Try evicting to the CPU inaccessible part of VRAM
143 			 * first, but only set GTT as busy placement, so this
144 			 * BO will be evicted to GTT rather than causing other
145 			 * BOs to be evicted from VRAM
146 			 */
147 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
148 							AMDGPU_GEM_DOMAIN_GTT |
149 							AMDGPU_GEM_DOMAIN_CPU);
150 			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
151 			abo->placements[0].lpfn = 0;
152 			abo->placement.busy_placement = &abo->placements[1];
153 			abo->placement.num_busy_placement = 1;
154 		} else {
155 			/* Move to GTT memory */
156 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
157 							AMDGPU_GEM_DOMAIN_CPU);
158 		}
159 		break;
160 	case TTM_PL_TT:
161 	case AMDGPU_PL_PREEMPT:
162 	default:
163 		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
164 		break;
165 	}
166 	*placement = abo->placement;
167 }
168 
169 /**
170  * amdgpu_ttm_map_buffer - Map memory into the GART windows
171  * @bo: buffer object to map
172  * @mem: memory object to map
173  * @mm_cur: range to map
174  * @window: which GART window to use
175  * @ring: DMA ring to use for the copy
176  * @tmz: if we should setup a TMZ enabled mapping
177  * @size: in number of bytes to map, out number of bytes mapped
178  * @addr: resulting address inside the MC address space
179  *
180  * Setup one of the GART windows to access a specific piece of memory or return
181  * the physical address for local memory.
182  */
amdgpu_ttm_map_buffer(struct ttm_buffer_object * bo,struct ttm_resource * mem,struct amdgpu_res_cursor * mm_cur,unsigned int window,struct amdgpu_ring * ring,bool tmz,uint64_t * size,uint64_t * addr)183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
184 				 struct ttm_resource *mem,
185 				 struct amdgpu_res_cursor *mm_cur,
186 				 unsigned int window, struct amdgpu_ring *ring,
187 				 bool tmz, uint64_t *size, uint64_t *addr)
188 {
189 	struct amdgpu_device *adev = ring->adev;
190 	unsigned int offset, num_pages, num_dw, num_bytes;
191 	uint64_t src_addr, dst_addr;
192 	struct amdgpu_job *job;
193 	void *cpu_addr;
194 	uint64_t flags;
195 	unsigned int i;
196 	int r;
197 
198 	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
199 	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
200 
201 	if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
202 		return -EINVAL;
203 
204 	/* Map only what can't be accessed directly */
205 	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
206 		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
207 			mm_cur->start;
208 		return 0;
209 	}
210 
211 
212 	/*
213 	 * If start begins at an offset inside the page, then adjust the size
214 	 * and addr accordingly
215 	 */
216 	offset = mm_cur->start & ~PAGE_MASK;
217 
218 	num_pages = PFN_UP(*size + offset);
219 	num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
220 
221 	*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
222 
223 	*addr = adev->gmc.gart_start;
224 	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
225 		AMDGPU_GPU_PAGE_SIZE;
226 	*addr += offset;
227 
228 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
229 	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
230 
231 	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
232 				     AMDGPU_FENCE_OWNER_UNDEFINED,
233 				     num_dw * 4 + num_bytes,
234 				     AMDGPU_IB_POOL_DELAYED, &job);
235 	if (r)
236 		return r;
237 
238 	src_addr = num_dw * 4;
239 	src_addr += job->ibs[0].gpu_addr;
240 
241 	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
242 	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
243 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
244 				dst_addr, num_bytes, false);
245 
246 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
247 	WARN_ON(job->ibs[0].length_dw > num_dw);
248 
249 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
250 	if (tmz)
251 		flags |= AMDGPU_PTE_TMZ;
252 
253 	cpu_addr = &job->ibs[0].ptr[num_dw];
254 
255 	if (mem->mem_type == TTM_PL_TT) {
256 		dma_addr_t *dma_addr;
257 
258 		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
259 		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
260 	} else {
261 		dma_addr_t dma_address;
262 
263 		dma_address = mm_cur->start;
264 		dma_address += adev->vm_manager.vram_base_offset;
265 
266 		for (i = 0; i < num_pages; ++i) {
267 			amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
268 					flags, cpu_addr);
269 			dma_address += PAGE_SIZE;
270 		}
271 	}
272 
273 	dma_fence_put(amdgpu_job_submit(job));
274 	return 0;
275 }
276 
277 /**
278  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
279  * @adev: amdgpu device
280  * @src: buffer/address where to read from
281  * @dst: buffer/address where to write to
282  * @size: number of bytes to copy
283  * @tmz: if a secure copy should be used
284  * @resv: resv object to sync to
285  * @f: Returns the last fence if multiple jobs are submitted.
286  *
287  * The function copies @size bytes from {src->mem + src->offset} to
288  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
289  * move and different for a BO to BO copy.
290  *
291  */
amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device * adev,const struct amdgpu_copy_mem * src,const struct amdgpu_copy_mem * dst,uint64_t size,bool tmz,struct dma_resv * resv,struct dma_fence ** f)292 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
293 			       const struct amdgpu_copy_mem *src,
294 			       const struct amdgpu_copy_mem *dst,
295 			       uint64_t size, bool tmz,
296 			       struct dma_resv *resv,
297 			       struct dma_fence **f)
298 {
299 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
300 	struct amdgpu_res_cursor src_mm, dst_mm;
301 	struct dma_fence *fence = NULL;
302 	int r = 0;
303 
304 	if (!adev->mman.buffer_funcs_enabled) {
305 		DRM_ERROR("Trying to move memory with ring turned off.\n");
306 		return -EINVAL;
307 	}
308 
309 	amdgpu_res_first(src->mem, src->offset, size, &src_mm);
310 	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
311 
312 	mutex_lock(&adev->mman.gtt_window_lock);
313 	while (src_mm.remaining) {
314 		uint64_t from, to, cur_size;
315 		struct dma_fence *next;
316 
317 		/* Never copy more than 256MiB at once to avoid a timeout */
318 		cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
319 
320 		/* Map src to window 0 and dst to window 1. */
321 		r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
322 					  0, ring, tmz, &cur_size, &from);
323 		if (r)
324 			goto error;
325 
326 		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
327 					  1, ring, tmz, &cur_size, &to);
328 		if (r)
329 			goto error;
330 
331 		r = amdgpu_copy_buffer(ring, from, to, cur_size,
332 				       resv, &next, false, true, tmz);
333 		if (r)
334 			goto error;
335 
336 		dma_fence_put(fence);
337 		fence = next;
338 
339 		amdgpu_res_next(&src_mm, cur_size);
340 		amdgpu_res_next(&dst_mm, cur_size);
341 	}
342 error:
343 	mutex_unlock(&adev->mman.gtt_window_lock);
344 	if (f)
345 		*f = dma_fence_get(fence);
346 	dma_fence_put(fence);
347 	return r;
348 }
349 
350 /*
351  * amdgpu_move_blit - Copy an entire buffer to another buffer
352  *
353  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
354  * help move buffers to and from VRAM.
355  */
amdgpu_move_blit(struct ttm_buffer_object * bo,bool evict,struct ttm_resource * new_mem,struct ttm_resource * old_mem)356 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
357 			    bool evict,
358 			    struct ttm_resource *new_mem,
359 			    struct ttm_resource *old_mem)
360 {
361 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
362 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
363 	struct amdgpu_copy_mem src, dst;
364 	struct dma_fence *fence = NULL;
365 	int r;
366 
367 	src.bo = bo;
368 	dst.bo = bo;
369 	src.mem = old_mem;
370 	dst.mem = new_mem;
371 	src.offset = 0;
372 	dst.offset = 0;
373 
374 	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
375 				       new_mem->size,
376 				       amdgpu_bo_encrypted(abo),
377 				       bo->base.resv, &fence);
378 	if (r)
379 		goto error;
380 
381 	/* clear the space being freed */
382 	if (old_mem->mem_type == TTM_PL_VRAM &&
383 	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
384 		struct dma_fence *wipe_fence = NULL;
385 
386 		r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence,
387 					false);
388 		if (r) {
389 			goto error;
390 		} else if (wipe_fence) {
391 			dma_fence_put(fence);
392 			fence = wipe_fence;
393 		}
394 	}
395 
396 	/* Always block for VM page tables before committing the new location */
397 	if (bo->type == ttm_bo_type_kernel)
398 		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
399 	else
400 		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
401 	dma_fence_put(fence);
402 	return r;
403 
404 error:
405 	if (fence)
406 		dma_fence_wait(fence, false);
407 	dma_fence_put(fence);
408 	return r;
409 }
410 
411 /*
412  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
413  *
414  * Called by amdgpu_bo_move()
415  */
amdgpu_mem_visible(struct amdgpu_device * adev,struct ttm_resource * mem)416 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
417 			       struct ttm_resource *mem)
418 {
419 	u64 mem_size = (u64)mem->size;
420 	struct amdgpu_res_cursor cursor;
421 	u64 end;
422 
423 	if (mem->mem_type == TTM_PL_SYSTEM ||
424 	    mem->mem_type == TTM_PL_TT)
425 		return true;
426 	if (mem->mem_type != TTM_PL_VRAM)
427 		return false;
428 
429 	amdgpu_res_first(mem, 0, mem_size, &cursor);
430 	end = cursor.start + cursor.size;
431 	while (cursor.remaining) {
432 		amdgpu_res_next(&cursor, cursor.size);
433 
434 		if (!cursor.remaining)
435 			break;
436 
437 		/* ttm_resource_ioremap only supports contiguous memory */
438 		if (end != cursor.start)
439 			return false;
440 
441 		end = cursor.start + cursor.size;
442 	}
443 
444 	return end <= adev->gmc.visible_vram_size;
445 }
446 
447 /*
448  * amdgpu_bo_move - Move a buffer object to a new memory location
449  *
450  * Called by ttm_bo_handle_move_mem()
451  */
amdgpu_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_resource * new_mem,struct ttm_place * hop)452 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
453 			  struct ttm_operation_ctx *ctx,
454 			  struct ttm_resource *new_mem,
455 			  struct ttm_place *hop)
456 {
457 	struct amdgpu_device *adev;
458 	struct amdgpu_bo *abo;
459 	struct ttm_resource *old_mem = bo->resource;
460 	int r;
461 
462 	if (new_mem->mem_type == TTM_PL_TT ||
463 	    new_mem->mem_type == AMDGPU_PL_PREEMPT) {
464 		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
465 		if (r)
466 			return r;
467 	}
468 
469 	abo = ttm_to_amdgpu_bo(bo);
470 	adev = amdgpu_ttm_adev(bo->bdev);
471 
472 	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
473 			 bo->ttm == NULL)) {
474 		ttm_bo_move_null(bo, new_mem);
475 		goto out;
476 	}
477 	if (old_mem->mem_type == TTM_PL_SYSTEM &&
478 	    (new_mem->mem_type == TTM_PL_TT ||
479 	     new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
480 		ttm_bo_move_null(bo, new_mem);
481 		goto out;
482 	}
483 	if ((old_mem->mem_type == TTM_PL_TT ||
484 	     old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
485 	    new_mem->mem_type == TTM_PL_SYSTEM) {
486 		r = ttm_bo_wait_ctx(bo, ctx);
487 		if (r)
488 			return r;
489 
490 		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
491 		ttm_resource_free(bo, &bo->resource);
492 		ttm_bo_assign_mem(bo, new_mem);
493 		goto out;
494 	}
495 
496 	if (old_mem->mem_type == AMDGPU_PL_GDS ||
497 	    old_mem->mem_type == AMDGPU_PL_GWS ||
498 	    old_mem->mem_type == AMDGPU_PL_OA ||
499 	    old_mem->mem_type == AMDGPU_PL_DOORBELL ||
500 	    new_mem->mem_type == AMDGPU_PL_GDS ||
501 	    new_mem->mem_type == AMDGPU_PL_GWS ||
502 	    new_mem->mem_type == AMDGPU_PL_OA ||
503 	    new_mem->mem_type == AMDGPU_PL_DOORBELL) {
504 		/* Nothing to save here */
505 		ttm_bo_move_null(bo, new_mem);
506 		goto out;
507 	}
508 
509 	if (bo->type == ttm_bo_type_device &&
510 	    new_mem->mem_type == TTM_PL_VRAM &&
511 	    old_mem->mem_type != TTM_PL_VRAM) {
512 		/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
513 		 * accesses the BO after it's moved.
514 		 */
515 		abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
516 	}
517 
518 	if (adev->mman.buffer_funcs_enabled) {
519 		if (((old_mem->mem_type == TTM_PL_SYSTEM &&
520 		      new_mem->mem_type == TTM_PL_VRAM) ||
521 		     (old_mem->mem_type == TTM_PL_VRAM &&
522 		      new_mem->mem_type == TTM_PL_SYSTEM))) {
523 			hop->fpfn = 0;
524 			hop->lpfn = 0;
525 			hop->mem_type = TTM_PL_TT;
526 			hop->flags = TTM_PL_FLAG_TEMPORARY;
527 			return -EMULTIHOP;
528 		}
529 
530 		r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
531 	} else {
532 		r = -ENODEV;
533 	}
534 
535 	if (r) {
536 		/* Check that all memory is CPU accessible */
537 		if (!amdgpu_mem_visible(adev, old_mem) ||
538 		    !amdgpu_mem_visible(adev, new_mem)) {
539 			pr_err("Move buffer fallback to memcpy unavailable\n");
540 			return r;
541 		}
542 
543 		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
544 		if (r)
545 			return r;
546 	}
547 
548 	trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
549 out:
550 	/* update statistics */
551 	atomic64_add(bo->base.size, &adev->num_bytes_moved);
552 	amdgpu_bo_move_notify(bo, evict);
553 	return 0;
554 }
555 
556 /*
557  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
558  *
559  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
560  */
amdgpu_ttm_io_mem_reserve(struct ttm_device * bdev,struct ttm_resource * mem)561 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
562 				     struct ttm_resource *mem)
563 {
564 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
565 	size_t bus_size = (size_t)mem->size;
566 
567 	switch (mem->mem_type) {
568 	case TTM_PL_SYSTEM:
569 		/* system memory */
570 		return 0;
571 	case TTM_PL_TT:
572 	case AMDGPU_PL_PREEMPT:
573 		break;
574 	case TTM_PL_VRAM:
575 		mem->bus.offset = mem->start << PAGE_SHIFT;
576 		/* check if it's visible */
577 		if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
578 			return -EINVAL;
579 
580 		if (adev->mman.aper_base_kaddr &&
581 		    mem->placement & TTM_PL_FLAG_CONTIGUOUS)
582 			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
583 					mem->bus.offset;
584 
585 		mem->bus.offset += adev->gmc.aper_base;
586 		mem->bus.is_iomem = true;
587 		break;
588 	case AMDGPU_PL_DOORBELL:
589 		mem->bus.offset = mem->start << PAGE_SHIFT;
590 		mem->bus.offset += adev->doorbell.base;
591 		mem->bus.is_iomem = true;
592 		mem->bus.caching = ttm_uncached;
593 		break;
594 	default:
595 		return -EINVAL;
596 	}
597 	return 0;
598 }
599 
amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object * bo,unsigned long page_offset)600 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
601 					   unsigned long page_offset)
602 {
603 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
604 	struct amdgpu_res_cursor cursor;
605 
606 	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
607 			 &cursor);
608 
609 	if (bo->resource->mem_type == AMDGPU_PL_DOORBELL)
610 		return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT;
611 
612 	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
613 }
614 
615 /**
616  * amdgpu_ttm_domain_start - Returns GPU start address
617  * @adev: amdgpu device object
618  * @type: type of the memory
619  *
620  * Returns:
621  * GPU start address of a memory domain
622  */
623 
amdgpu_ttm_domain_start(struct amdgpu_device * adev,uint32_t type)624 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
625 {
626 	switch (type) {
627 	case TTM_PL_TT:
628 		return adev->gmc.gart_start;
629 	case TTM_PL_VRAM:
630 		return adev->gmc.vram_start;
631 	}
632 
633 	return 0;
634 }
635 
636 /*
637  * TTM backend functions.
638  */
639 struct amdgpu_ttm_tt {
640 	struct ttm_tt	ttm;
641 	struct drm_gem_object	*gobj;
642 	u64			offset;
643 	uint64_t		userptr;
644 	struct task_struct	*usertask;
645 	uint32_t		userflags;
646 	bool			bound;
647 	int32_t			pool_id;
648 };
649 
650 #define ttm_to_amdgpu_ttm_tt(ptr)	container_of(ptr, struct amdgpu_ttm_tt, ttm)
651 
652 #ifdef CONFIG_DRM_AMDGPU_USERPTR
653 /*
654  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
655  * memory and start HMM tracking CPU page table update
656  *
657  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
658  * once afterwards to stop HMM tracking
659  */
amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo * bo,struct page ** pages,struct hmm_range ** range)660 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
661 				 struct hmm_range **range)
662 {
663 	struct ttm_tt *ttm = bo->tbo.ttm;
664 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
665 	unsigned long start = gtt->userptr;
666 	struct vm_area_struct *vma;
667 	struct mm_struct *mm;
668 	bool readonly;
669 	int r = 0;
670 
671 	/* Make sure get_user_pages_done() can cleanup gracefully */
672 	*range = NULL;
673 
674 	mm = bo->notifier.mm;
675 	if (unlikely(!mm)) {
676 		DRM_DEBUG_DRIVER("BO is not registered?\n");
677 		return -EFAULT;
678 	}
679 
680 	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
681 		return -ESRCH;
682 
683 	mmap_read_lock(mm);
684 	vma = vma_lookup(mm, start);
685 	if (unlikely(!vma)) {
686 		r = -EFAULT;
687 		goto out_unlock;
688 	}
689 	if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
690 		vma->vm_file)) {
691 		r = -EPERM;
692 		goto out_unlock;
693 	}
694 
695 	readonly = amdgpu_ttm_tt_is_readonly(ttm);
696 	r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages,
697 				       readonly, NULL, pages, range);
698 out_unlock:
699 	mmap_read_unlock(mm);
700 	if (r)
701 		pr_debug("failed %d to get user pages 0x%lx\n", r, start);
702 
703 	mmput(mm);
704 
705 	return r;
706 }
707 
708 /* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations
709  */
amdgpu_ttm_tt_discard_user_pages(struct ttm_tt * ttm,struct hmm_range * range)710 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
711 				      struct hmm_range *range)
712 {
713 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
714 
715 	if (gtt && gtt->userptr && range)
716 		amdgpu_hmm_range_get_pages_done(range);
717 }
718 
719 /*
720  * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change
721  * Check if the pages backing this ttm range have been invalidated
722  *
723  * Returns: true if pages are still valid
724  */
amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt * ttm,struct hmm_range * range)725 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
726 				       struct hmm_range *range)
727 {
728 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
729 
730 	if (!gtt || !gtt->userptr || !range)
731 		return false;
732 
733 	DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
734 		gtt->userptr, ttm->num_pages);
735 
736 	WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
737 
738 	return !amdgpu_hmm_range_get_pages_done(range);
739 }
740 #endif
741 
742 /*
743  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
744  *
745  * Called by amdgpu_cs_list_validate(). This creates the page list
746  * that backs user memory and will ultimately be mapped into the device
747  * address space.
748  */
amdgpu_ttm_tt_set_user_pages(struct ttm_tt * ttm,struct page ** pages)749 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
750 {
751 	unsigned long i;
752 
753 	for (i = 0; i < ttm->num_pages; ++i)
754 		ttm->pages[i] = pages ? pages[i] : NULL;
755 }
756 
757 /*
758  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
759  *
760  * Called by amdgpu_ttm_backend_bind()
761  **/
amdgpu_ttm_tt_pin_userptr(struct ttm_device * bdev,struct ttm_tt * ttm)762 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
763 				     struct ttm_tt *ttm)
764 {
765 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
766 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
767 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
768 	enum dma_data_direction direction = write ?
769 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
770 	int r;
771 
772 	/* Allocate an SG array and squash pages into it */
773 	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
774 				      (u64)ttm->num_pages << PAGE_SHIFT,
775 				      GFP_KERNEL);
776 	if (r)
777 		goto release_sg;
778 
779 	/* Map SG to device */
780 	r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
781 	if (r)
782 		goto release_sg;
783 
784 	/* convert SG to linear array of pages and dma addresses */
785 	drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
786 				       ttm->num_pages);
787 
788 	return 0;
789 
790 release_sg:
791 	kfree(ttm->sg);
792 	ttm->sg = NULL;
793 	return r;
794 }
795 
796 /*
797  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
798  */
amdgpu_ttm_tt_unpin_userptr(struct ttm_device * bdev,struct ttm_tt * ttm)799 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
800 					struct ttm_tt *ttm)
801 {
802 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
803 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
804 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
805 	enum dma_data_direction direction = write ?
806 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
807 
808 	/* double check that we don't free the table twice */
809 	if (!ttm->sg || !ttm->sg->sgl)
810 		return;
811 
812 	/* unmap the pages mapped to the device */
813 	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
814 	sg_free_table(ttm->sg);
815 }
816 
817 /*
818  * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ...
819  * MQDn+CtrlStackn where n is the number of XCCs per partition.
820  * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD
821  * and uses memory type default, UC. The rest of pages_per_xcc are
822  * Ctrl stack and modify their memory type to NC.
823  */
amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device * adev,struct ttm_tt * ttm,uint64_t flags)824 static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
825 				struct ttm_tt *ttm, uint64_t flags)
826 {
827 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
828 	uint64_t total_pages = ttm->num_pages;
829 	int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
830 	uint64_t page_idx, pages_per_xcc;
831 	int i;
832 	uint64_t ctrl_flags = (flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
833 			AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
834 
835 	pages_per_xcc = total_pages;
836 	do_div(pages_per_xcc, num_xcc);
837 
838 	for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
839 		/* MQD page: use default flags */
840 		amdgpu_gart_bind(adev,
841 				gtt->offset + (page_idx << PAGE_SHIFT),
842 				1, &gtt->ttm.dma_address[page_idx], flags);
843 		/*
844 		 * Ctrl pages - modify the memory type to NC (ctrl_flags) from
845 		 * the second page of the BO onward.
846 		 */
847 		amdgpu_gart_bind(adev,
848 				gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
849 				pages_per_xcc - 1,
850 				&gtt->ttm.dma_address[page_idx + 1],
851 				ctrl_flags);
852 	}
853 }
854 
amdgpu_ttm_gart_bind(struct amdgpu_device * adev,struct ttm_buffer_object * tbo,uint64_t flags)855 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
856 				 struct ttm_buffer_object *tbo,
857 				 uint64_t flags)
858 {
859 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
860 	struct ttm_tt *ttm = tbo->ttm;
861 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
862 
863 	if (amdgpu_bo_encrypted(abo))
864 		flags |= AMDGPU_PTE_TMZ;
865 
866 	if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
867 		amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
868 	} else {
869 		amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
870 				 gtt->ttm.dma_address, flags);
871 	}
872 }
873 
874 /*
875  * amdgpu_ttm_backend_bind - Bind GTT memory
876  *
877  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
878  * This handles binding GTT memory to the device address space.
879  */
amdgpu_ttm_backend_bind(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_resource * bo_mem)880 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
881 				   struct ttm_tt *ttm,
882 				   struct ttm_resource *bo_mem)
883 {
884 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
885 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
886 	uint64_t flags;
887 	int r;
888 
889 	if (!bo_mem)
890 		return -EINVAL;
891 
892 	if (gtt->bound)
893 		return 0;
894 
895 	if (gtt->userptr) {
896 		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
897 		if (r) {
898 			DRM_ERROR("failed to pin userptr\n");
899 			return r;
900 		}
901 	} else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
902 		if (!ttm->sg) {
903 			struct dma_buf_attachment *attach;
904 			struct sg_table *sgt;
905 
906 			attach = gtt->gobj->import_attach;
907 			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
908 			if (IS_ERR(sgt))
909 				return PTR_ERR(sgt);
910 
911 			ttm->sg = sgt;
912 		}
913 
914 		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
915 					       ttm->num_pages);
916 	}
917 
918 	if (!ttm->num_pages) {
919 		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
920 		     ttm->num_pages, bo_mem, ttm);
921 	}
922 
923 	if (bo_mem->mem_type != TTM_PL_TT ||
924 	    !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
925 		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
926 		return 0;
927 	}
928 
929 	/* compute PTE flags relevant to this BO memory */
930 	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
931 
932 	/* bind pages into GART page tables */
933 	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
934 	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
935 			 gtt->ttm.dma_address, flags);
936 	gtt->bound = true;
937 	return 0;
938 }
939 
940 /*
941  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
942  * through AGP or GART aperture.
943  *
944  * If bo is accessible through AGP aperture, then use AGP aperture
945  * to access bo; otherwise allocate logical space in GART aperture
946  * and map bo to GART aperture.
947  */
amdgpu_ttm_alloc_gart(struct ttm_buffer_object * bo)948 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
949 {
950 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
951 	struct ttm_operation_ctx ctx = { false, false };
952 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
953 	struct ttm_placement placement;
954 	struct ttm_place placements;
955 	struct ttm_resource *tmp;
956 	uint64_t addr, flags;
957 	int r;
958 
959 	if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
960 		return 0;
961 
962 	addr = amdgpu_gmc_agp_addr(bo);
963 	if (addr != AMDGPU_BO_INVALID_OFFSET) {
964 		bo->resource->start = addr >> PAGE_SHIFT;
965 		return 0;
966 	}
967 
968 	/* allocate GART space */
969 	placement.num_placement = 1;
970 	placement.placement = &placements;
971 	placement.num_busy_placement = 1;
972 	placement.busy_placement = &placements;
973 	placements.fpfn = 0;
974 	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
975 	placements.mem_type = TTM_PL_TT;
976 	placements.flags = bo->resource->placement;
977 
978 	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
979 	if (unlikely(r))
980 		return r;
981 
982 	/* compute PTE flags for this buffer object */
983 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
984 
985 	/* Bind pages */
986 	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
987 	amdgpu_ttm_gart_bind(adev, bo, flags);
988 	amdgpu_gart_invalidate_tlb(adev);
989 	ttm_resource_free(bo, &bo->resource);
990 	ttm_bo_assign_mem(bo, tmp);
991 
992 	return 0;
993 }
994 
995 /*
996  * amdgpu_ttm_recover_gart - Rebind GTT pages
997  *
998  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
999  * rebind GTT pages during a GPU reset.
1000  */
amdgpu_ttm_recover_gart(struct ttm_buffer_object * tbo)1001 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1002 {
1003 	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1004 	uint64_t flags;
1005 
1006 	if (!tbo->ttm)
1007 		return;
1008 
1009 	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1010 	amdgpu_ttm_gart_bind(adev, tbo, flags);
1011 }
1012 
1013 /*
1014  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1015  *
1016  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1017  * ttm_tt_destroy().
1018  */
amdgpu_ttm_backend_unbind(struct ttm_device * bdev,struct ttm_tt * ttm)1019 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1020 				      struct ttm_tt *ttm)
1021 {
1022 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1023 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1024 
1025 	/* if the pages have userptr pinning then clear that first */
1026 	if (gtt->userptr) {
1027 		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1028 	} else if (ttm->sg && gtt->gobj->import_attach) {
1029 		struct dma_buf_attachment *attach;
1030 
1031 		attach = gtt->gobj->import_attach;
1032 		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1033 		ttm->sg = NULL;
1034 	}
1035 
1036 	if (!gtt->bound)
1037 		return;
1038 
1039 	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1040 		return;
1041 
1042 	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1043 	amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1044 	gtt->bound = false;
1045 }
1046 
amdgpu_ttm_backend_destroy(struct ttm_device * bdev,struct ttm_tt * ttm)1047 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1048 				       struct ttm_tt *ttm)
1049 {
1050 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1051 
1052 	if (gtt->usertask)
1053 		put_task_struct(gtt->usertask);
1054 
1055 	ttm_tt_fini(&gtt->ttm);
1056 	kfree(gtt);
1057 }
1058 
1059 /**
1060  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1061  *
1062  * @bo: The buffer object to create a GTT ttm_tt object around
1063  * @page_flags: Page flags to be added to the ttm_tt object
1064  *
1065  * Called by ttm_tt_create().
1066  */
amdgpu_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)1067 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1068 					   uint32_t page_flags)
1069 {
1070 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1071 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1072 	struct amdgpu_ttm_tt *gtt;
1073 	enum ttm_caching caching;
1074 
1075 	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1076 	if (!gtt)
1077 		return NULL;
1078 
1079 	gtt->gobj = &bo->base;
1080 	if (adev->gmc.mem_partitions && abo->xcp_id >= 0)
1081 		gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
1082 	else
1083 		gtt->pool_id = abo->xcp_id;
1084 
1085 	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1086 		caching = ttm_write_combined;
1087 	else
1088 		caching = ttm_cached;
1089 
1090 	/* allocate space for the uninitialized page entries */
1091 	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1092 		kfree(gtt);
1093 		return NULL;
1094 	}
1095 	return &gtt->ttm;
1096 }
1097 
1098 /*
1099  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1100  *
1101  * Map the pages of a ttm_tt object to an address space visible
1102  * to the underlying device.
1103  */
amdgpu_ttm_tt_populate(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)1104 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1105 				  struct ttm_tt *ttm,
1106 				  struct ttm_operation_ctx *ctx)
1107 {
1108 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1109 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1110 	struct ttm_pool *pool;
1111 	pgoff_t i;
1112 	int ret;
1113 
1114 	/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1115 	if (gtt->userptr) {
1116 		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1117 		if (!ttm->sg)
1118 			return -ENOMEM;
1119 		return 0;
1120 	}
1121 
1122 	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1123 		return 0;
1124 
1125 	if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1126 		pool = &adev->mman.ttm_pools[gtt->pool_id];
1127 	else
1128 		pool = &adev->mman.bdev.pool;
1129 	ret = ttm_pool_alloc(pool, ttm, ctx);
1130 	if (ret)
1131 		return ret;
1132 
1133 	for (i = 0; i < ttm->num_pages; ++i)
1134 		ttm->pages[i]->mapping = bdev->dev_mapping;
1135 
1136 	return 0;
1137 }
1138 
1139 /*
1140  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1141  *
1142  * Unmaps pages of a ttm_tt object from the device address space and
1143  * unpopulates the page array backing it.
1144  */
amdgpu_ttm_tt_unpopulate(struct ttm_device * bdev,struct ttm_tt * ttm)1145 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1146 				     struct ttm_tt *ttm)
1147 {
1148 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1149 	struct amdgpu_device *adev;
1150 	struct ttm_pool *pool;
1151 	pgoff_t i;
1152 
1153 	amdgpu_ttm_backend_unbind(bdev, ttm);
1154 
1155 	if (gtt->userptr) {
1156 		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1157 		kfree(ttm->sg);
1158 		ttm->sg = NULL;
1159 		return;
1160 	}
1161 
1162 	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1163 		return;
1164 
1165 	for (i = 0; i < ttm->num_pages; ++i)
1166 		ttm->pages[i]->mapping = NULL;
1167 
1168 	adev = amdgpu_ttm_adev(bdev);
1169 
1170 	if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1171 		pool = &adev->mman.ttm_pools[gtt->pool_id];
1172 	else
1173 		pool = &adev->mman.bdev.pool;
1174 
1175 	return ttm_pool_free(pool, ttm);
1176 }
1177 
1178 /**
1179  * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1180  * task
1181  *
1182  * @tbo: The ttm_buffer_object that contains the userptr
1183  * @user_addr:  The returned value
1184  */
amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object * tbo,uint64_t * user_addr)1185 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1186 			      uint64_t *user_addr)
1187 {
1188 	struct amdgpu_ttm_tt *gtt;
1189 
1190 	if (!tbo->ttm)
1191 		return -EINVAL;
1192 
1193 	gtt = (void *)tbo->ttm;
1194 	*user_addr = gtt->userptr;
1195 	return 0;
1196 }
1197 
1198 /**
1199  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1200  * task
1201  *
1202  * @bo: The ttm_buffer_object to bind this userptr to
1203  * @addr:  The address in the current tasks VM space to use
1204  * @flags: Requirements of userptr object.
1205  *
1206  * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to
1207  * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to
1208  * initialize GPU VM for a KFD process.
1209  */
amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object * bo,uint64_t addr,uint32_t flags)1210 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1211 			      uint64_t addr, uint32_t flags)
1212 {
1213 	struct amdgpu_ttm_tt *gtt;
1214 
1215 	if (!bo->ttm) {
1216 		/* TODO: We want a separate TTM object type for userptrs */
1217 		bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1218 		if (bo->ttm == NULL)
1219 			return -ENOMEM;
1220 	}
1221 
1222 	/* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1223 	bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1224 
1225 	gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1226 	gtt->userptr = addr;
1227 	gtt->userflags = flags;
1228 
1229 	if (gtt->usertask)
1230 		put_task_struct(gtt->usertask);
1231 	gtt->usertask = current->group_leader;
1232 	get_task_struct(gtt->usertask);
1233 
1234 	return 0;
1235 }
1236 
1237 /*
1238  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1239  */
amdgpu_ttm_tt_get_usermm(struct ttm_tt * ttm)1240 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1241 {
1242 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1243 
1244 	if (gtt == NULL)
1245 		return NULL;
1246 
1247 	if (gtt->usertask == NULL)
1248 		return NULL;
1249 
1250 	return gtt->usertask->mm;
1251 }
1252 
1253 /*
1254  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1255  * address range for the current task.
1256  *
1257  */
amdgpu_ttm_tt_affect_userptr(struct ttm_tt * ttm,unsigned long start,unsigned long end,unsigned long * userptr)1258 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1259 				  unsigned long end, unsigned long *userptr)
1260 {
1261 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1262 	unsigned long size;
1263 
1264 	if (gtt == NULL || !gtt->userptr)
1265 		return false;
1266 
1267 	/* Return false if no part of the ttm_tt object lies within
1268 	 * the range
1269 	 */
1270 	size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1271 	if (gtt->userptr > end || gtt->userptr + size <= start)
1272 		return false;
1273 
1274 	if (userptr)
1275 		*userptr = gtt->userptr;
1276 	return true;
1277 }
1278 
1279 /*
1280  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1281  */
amdgpu_ttm_tt_is_userptr(struct ttm_tt * ttm)1282 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1283 {
1284 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1285 
1286 	if (gtt == NULL || !gtt->userptr)
1287 		return false;
1288 
1289 	return true;
1290 }
1291 
1292 /*
1293  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1294  */
amdgpu_ttm_tt_is_readonly(struct ttm_tt * ttm)1295 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1296 {
1297 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1298 
1299 	if (gtt == NULL)
1300 		return false;
1301 
1302 	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1303 }
1304 
1305 /**
1306  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1307  *
1308  * @ttm: The ttm_tt object to compute the flags for
1309  * @mem: The memory registry backing this ttm_tt object
1310  *
1311  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1312  */
amdgpu_ttm_tt_pde_flags(struct ttm_tt * ttm,struct ttm_resource * mem)1313 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1314 {
1315 	uint64_t flags = 0;
1316 
1317 	if (mem && mem->mem_type != TTM_PL_SYSTEM)
1318 		flags |= AMDGPU_PTE_VALID;
1319 
1320 	if (mem && (mem->mem_type == TTM_PL_TT ||
1321 		    mem->mem_type == AMDGPU_PL_DOORBELL ||
1322 		    mem->mem_type == AMDGPU_PL_PREEMPT)) {
1323 		flags |= AMDGPU_PTE_SYSTEM;
1324 
1325 		if (ttm->caching == ttm_cached)
1326 			flags |= AMDGPU_PTE_SNOOPED;
1327 	}
1328 
1329 	if (mem && mem->mem_type == TTM_PL_VRAM &&
1330 			mem->bus.caching == ttm_cached)
1331 		flags |= AMDGPU_PTE_SNOOPED;
1332 
1333 	return flags;
1334 }
1335 
1336 /**
1337  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1338  *
1339  * @adev: amdgpu_device pointer
1340  * @ttm: The ttm_tt object to compute the flags for
1341  * @mem: The memory registry backing this ttm_tt object
1342  *
1343  * Figure out the flags to use for a VM PTE (Page Table Entry).
1344  */
amdgpu_ttm_tt_pte_flags(struct amdgpu_device * adev,struct ttm_tt * ttm,struct ttm_resource * mem)1345 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1346 				 struct ttm_resource *mem)
1347 {
1348 	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1349 
1350 	flags |= adev->gart.gart_pte_flags;
1351 	flags |= AMDGPU_PTE_READABLE;
1352 
1353 	if (!amdgpu_ttm_tt_is_readonly(ttm))
1354 		flags |= AMDGPU_PTE_WRITEABLE;
1355 
1356 	return flags;
1357 }
1358 
1359 /*
1360  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1361  * object.
1362  *
1363  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1364  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1365  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1366  * used to clean out a memory space.
1367  */
amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object * bo,const struct ttm_place * place)1368 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1369 					    const struct ttm_place *place)
1370 {
1371 	struct dma_resv_iter resv_cursor;
1372 	struct dma_fence *f;
1373 
1374 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1375 		return ttm_bo_eviction_valuable(bo, place);
1376 
1377 	/* Swapout? */
1378 	if (bo->resource->mem_type == TTM_PL_SYSTEM)
1379 		return true;
1380 
1381 	if (bo->type == ttm_bo_type_kernel &&
1382 	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1383 		return false;
1384 
1385 	/* If bo is a KFD BO, check if the bo belongs to the current process.
1386 	 * If true, then return false as any KFD process needs all its BOs to
1387 	 * be resident to run successfully
1388 	 */
1389 	dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1390 				DMA_RESV_USAGE_BOOKKEEP, f) {
1391 		if (amdkfd_fence_check_mm(f, current->mm))
1392 			return false;
1393 	}
1394 
1395 	/* Preemptible BOs don't own system resources managed by the
1396 	 * driver (pages, VRAM, GART space). They point to resources
1397 	 * owned by someone else (e.g. pageable memory in user mode
1398 	 * or a DMABuf). They are used in a preemptible context so we
1399 	 * can guarantee no deadlocks and good QoS in case of MMU
1400 	 * notifiers or DMABuf move notifiers from the resource owner.
1401 	 */
1402 	if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1403 		return false;
1404 
1405 	if (bo->resource->mem_type == TTM_PL_TT &&
1406 	    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1407 		return false;
1408 
1409 	return ttm_bo_eviction_valuable(bo, place);
1410 }
1411 
amdgpu_ttm_vram_mm_access(struct amdgpu_device * adev,loff_t pos,void * buf,size_t size,bool write)1412 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1413 				      void *buf, size_t size, bool write)
1414 {
1415 	while (size) {
1416 		uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1417 		uint64_t bytes = 4 - (pos & 0x3);
1418 		uint32_t shift = (pos & 0x3) * 8;
1419 		uint32_t mask = 0xffffffff << shift;
1420 		uint32_t value = 0;
1421 
1422 		if (size < bytes) {
1423 			mask &= 0xffffffff >> (bytes - size) * 8;
1424 			bytes = size;
1425 		}
1426 
1427 		if (mask != 0xffffffff) {
1428 			amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1429 			if (write) {
1430 				value &= ~mask;
1431 				value |= (*(uint32_t *)buf << shift) & mask;
1432 				amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1433 			} else {
1434 				value = (value & mask) >> shift;
1435 				memcpy(buf, &value, bytes);
1436 			}
1437 		} else {
1438 			amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1439 		}
1440 
1441 		pos += bytes;
1442 		buf += bytes;
1443 		size -= bytes;
1444 	}
1445 }
1446 
amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object * bo,unsigned long offset,void * buf,int len,int write)1447 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1448 					unsigned long offset, void *buf,
1449 					int len, int write)
1450 {
1451 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1452 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1453 	struct amdgpu_res_cursor src_mm;
1454 	struct amdgpu_job *job;
1455 	struct dma_fence *fence;
1456 	uint64_t src_addr, dst_addr;
1457 	unsigned int num_dw;
1458 	int r, idx;
1459 
1460 	if (len != PAGE_SIZE)
1461 		return -EINVAL;
1462 
1463 	if (!adev->mman.sdma_access_ptr)
1464 		return -EACCES;
1465 
1466 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1467 		return -ENODEV;
1468 
1469 	if (write)
1470 		memcpy(adev->mman.sdma_access_ptr, buf, len);
1471 
1472 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1473 	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
1474 				     AMDGPU_FENCE_OWNER_UNDEFINED,
1475 				     num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1476 				     &job);
1477 	if (r)
1478 		goto out;
1479 
1480 	amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1481 	src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) +
1482 		src_mm.start;
1483 	dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1484 	if (write)
1485 		swap(src_addr, dst_addr);
1486 
1487 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
1488 				PAGE_SIZE, false);
1489 
1490 	amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1491 	WARN_ON(job->ibs[0].length_dw > num_dw);
1492 
1493 	fence = amdgpu_job_submit(job);
1494 
1495 	if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1496 		r = -ETIMEDOUT;
1497 	dma_fence_put(fence);
1498 
1499 	if (!(r || write))
1500 		memcpy(buf, adev->mman.sdma_access_ptr, len);
1501 out:
1502 	drm_dev_exit(idx);
1503 	return r;
1504 }
1505 
1506 /**
1507  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1508  *
1509  * @bo:  The buffer object to read/write
1510  * @offset:  Offset into buffer object
1511  * @buf:  Secondary buffer to write/read from
1512  * @len: Length in bytes of access
1513  * @write:  true if writing
1514  *
1515  * This is used to access VRAM that backs a buffer object via MMIO
1516  * access for debugging purposes.
1517  */
amdgpu_ttm_access_memory(struct ttm_buffer_object * bo,unsigned long offset,void * buf,int len,int write)1518 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1519 				    unsigned long offset, void *buf, int len,
1520 				    int write)
1521 {
1522 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1523 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1524 	struct amdgpu_res_cursor cursor;
1525 	int ret = 0;
1526 
1527 	if (bo->resource->mem_type != TTM_PL_VRAM)
1528 		return -EIO;
1529 
1530 	if (amdgpu_device_has_timeouts_enabled(adev) &&
1531 			!amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1532 		return len;
1533 
1534 	amdgpu_res_first(bo->resource, offset, len, &cursor);
1535 	while (cursor.remaining) {
1536 		size_t count, size = cursor.size;
1537 		loff_t pos = cursor.start;
1538 
1539 		count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1540 		size -= count;
1541 		if (size) {
1542 			/* using MM to access rest vram and handle un-aligned address */
1543 			pos += count;
1544 			buf += count;
1545 			amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1546 		}
1547 
1548 		ret += cursor.size;
1549 		buf += cursor.size;
1550 		amdgpu_res_next(&cursor, cursor.size);
1551 	}
1552 
1553 	return ret;
1554 }
1555 
1556 static void
amdgpu_bo_delete_mem_notify(struct ttm_buffer_object * bo)1557 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1558 {
1559 	amdgpu_bo_move_notify(bo, false);
1560 }
1561 
1562 static struct ttm_device_funcs amdgpu_bo_driver = {
1563 	.ttm_tt_create = &amdgpu_ttm_tt_create,
1564 	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
1565 	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1566 	.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1567 	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1568 	.evict_flags = &amdgpu_evict_flags,
1569 	.move = &amdgpu_bo_move,
1570 	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1571 	.release_notify = &amdgpu_bo_release_notify,
1572 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1573 	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1574 	.access_memory = &amdgpu_ttm_access_memory,
1575 };
1576 
1577 /*
1578  * Firmware Reservation functions
1579  */
1580 /**
1581  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1582  *
1583  * @adev: amdgpu_device pointer
1584  *
1585  * free fw reserved vram if it has been reserved.
1586  */
amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device * adev)1587 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1588 {
1589 	amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1590 		NULL, &adev->mman.fw_vram_usage_va);
1591 }
1592 
1593 /*
1594  * Driver Reservation functions
1595  */
1596 /**
1597  * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
1598  *
1599  * @adev: amdgpu_device pointer
1600  *
1601  * free drv reserved vram if it has been reserved.
1602  */
amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device * adev)1603 static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
1604 {
1605 	amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
1606 						  NULL,
1607 						  &adev->mman.drv_vram_usage_va);
1608 }
1609 
1610 /**
1611  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1612  *
1613  * @adev: amdgpu_device pointer
1614  *
1615  * create bo vram reservation from fw.
1616  */
amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device * adev)1617 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1618 {
1619 	uint64_t vram_size = adev->gmc.visible_vram_size;
1620 
1621 	adev->mman.fw_vram_usage_va = NULL;
1622 	adev->mman.fw_vram_usage_reserved_bo = NULL;
1623 
1624 	if (adev->mman.fw_vram_usage_size == 0 ||
1625 	    adev->mman.fw_vram_usage_size > vram_size)
1626 		return 0;
1627 
1628 	return amdgpu_bo_create_kernel_at(adev,
1629 					  adev->mman.fw_vram_usage_start_offset,
1630 					  adev->mman.fw_vram_usage_size,
1631 					  &adev->mman.fw_vram_usage_reserved_bo,
1632 					  &adev->mman.fw_vram_usage_va);
1633 }
1634 
1635 /**
1636  * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
1637  *
1638  * @adev: amdgpu_device pointer
1639  *
1640  * create bo vram reservation from drv.
1641  */
amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device * adev)1642 static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
1643 {
1644 	u64 vram_size = adev->gmc.visible_vram_size;
1645 
1646 	adev->mman.drv_vram_usage_va = NULL;
1647 	adev->mman.drv_vram_usage_reserved_bo = NULL;
1648 
1649 	if (adev->mman.drv_vram_usage_size == 0 ||
1650 	    adev->mman.drv_vram_usage_size > vram_size)
1651 		return 0;
1652 
1653 	return amdgpu_bo_create_kernel_at(adev,
1654 					  adev->mman.drv_vram_usage_start_offset,
1655 					  adev->mman.drv_vram_usage_size,
1656 					  &adev->mman.drv_vram_usage_reserved_bo,
1657 					  &adev->mman.drv_vram_usage_va);
1658 }
1659 
1660 /*
1661  * Memoy training reservation functions
1662  */
1663 
1664 /**
1665  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1666  *
1667  * @adev: amdgpu_device pointer
1668  *
1669  * free memory training reserved vram if it has been reserved.
1670  */
amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device * adev)1671 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1672 {
1673 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1674 
1675 	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1676 	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1677 	ctx->c2p_bo = NULL;
1678 
1679 	return 0;
1680 }
1681 
amdgpu_ttm_training_data_block_init(struct amdgpu_device * adev,uint32_t reserve_size)1682 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev,
1683 						uint32_t reserve_size)
1684 {
1685 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1686 
1687 	memset(ctx, 0, sizeof(*ctx));
1688 
1689 	ctx->c2p_train_data_offset =
1690 		ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M);
1691 	ctx->p2c_train_data_offset =
1692 		(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1693 	ctx->train_data_size =
1694 		GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1695 
1696 	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1697 			ctx->train_data_size,
1698 			ctx->p2c_train_data_offset,
1699 			ctx->c2p_train_data_offset);
1700 }
1701 
1702 /*
1703  * reserve TMR memory at the top of VRAM which holds
1704  * IP Discovery data and is protected by PSP.
1705  */
amdgpu_ttm_reserve_tmr(struct amdgpu_device * adev)1706 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1707 {
1708 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1709 	bool mem_train_support = false;
1710 	uint32_t reserve_size = 0;
1711 	int ret;
1712 
1713 	if (adev->bios && !amdgpu_sriov_vf(adev)) {
1714 		if (amdgpu_atomfirmware_mem_training_supported(adev))
1715 			mem_train_support = true;
1716 		else
1717 			DRM_DEBUG("memory training does not support!\n");
1718 	}
1719 
1720 	/*
1721 	 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1722 	 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1723 	 *
1724 	 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1725 	 * discovery data and G6 memory training data respectively
1726 	 */
1727 	if (adev->bios)
1728 		reserve_size =
1729 			amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1730 
1731 	if (!adev->bios && adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
1732 		reserve_size = max(reserve_size, (uint32_t)280 << 20);
1733 	else if (!reserve_size)
1734 		reserve_size = DISCOVERY_TMR_OFFSET;
1735 
1736 	if (mem_train_support) {
1737 		/* reserve vram for mem train according to TMR location */
1738 		amdgpu_ttm_training_data_block_init(adev, reserve_size);
1739 		ret = amdgpu_bo_create_kernel_at(adev,
1740 						 ctx->c2p_train_data_offset,
1741 						 ctx->train_data_size,
1742 						 &ctx->c2p_bo,
1743 						 NULL);
1744 		if (ret) {
1745 			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1746 			amdgpu_ttm_training_reserve_vram_fini(adev);
1747 			return ret;
1748 		}
1749 		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1750 	}
1751 
1752 	if (!adev->gmc.is_app_apu) {
1753 		ret = amdgpu_bo_create_kernel_at(
1754 			adev, adev->gmc.real_vram_size - reserve_size,
1755 			reserve_size, &adev->mman.fw_reserved_memory, NULL);
1756 		if (ret) {
1757 			DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1758 			amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory,
1759 					      NULL, NULL);
1760 			return ret;
1761 		}
1762 	} else {
1763 		DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n");
1764 	}
1765 
1766 	return 0;
1767 }
1768 
amdgpu_ttm_pools_init(struct amdgpu_device * adev)1769 static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)
1770 {
1771 	int i;
1772 
1773 	if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions)
1774 		return 0;
1775 
1776 	adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions,
1777 				       sizeof(*adev->mman.ttm_pools),
1778 				       GFP_KERNEL);
1779 	if (!adev->mman.ttm_pools)
1780 		return -ENOMEM;
1781 
1782 	for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
1783 		ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev,
1784 			      adev->gmc.mem_partitions[i].numa.node,
1785 			      false, false);
1786 	}
1787 	return 0;
1788 }
1789 
amdgpu_ttm_pools_fini(struct amdgpu_device * adev)1790 static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev)
1791 {
1792 	int i;
1793 
1794 	if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools)
1795 		return;
1796 
1797 	for (i = 0; i < adev->gmc.num_mem_partitions; i++)
1798 		ttm_pool_fini(&adev->mman.ttm_pools[i]);
1799 
1800 	kfree(adev->mman.ttm_pools);
1801 	adev->mman.ttm_pools = NULL;
1802 }
1803 
1804 /*
1805  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1806  * gtt/vram related fields.
1807  *
1808  * This initializes all of the memory space pools that the TTM layer
1809  * will need such as the GTT space (system memory mapped to the device),
1810  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1811  * can be mapped per VMID.
1812  */
amdgpu_ttm_init(struct amdgpu_device * adev)1813 int amdgpu_ttm_init(struct amdgpu_device *adev)
1814 {
1815 	uint64_t gtt_size;
1816 	int r;
1817 
1818 	mutex_init(&adev->mman.gtt_window_lock);
1819 
1820 	/* No others user of address space so set it to 0 */
1821 	r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1822 			       adev_to_drm(adev)->anon_inode->i_mapping,
1823 			       adev_to_drm(adev)->vma_offset_manager,
1824 			       adev->need_swiotlb,
1825 			       dma_addressing_limited(adev->dev));
1826 	if (r) {
1827 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1828 		return r;
1829 	}
1830 
1831 	r = amdgpu_ttm_pools_init(adev);
1832 	if (r) {
1833 		DRM_ERROR("failed to init ttm pools(%d).\n", r);
1834 		return r;
1835 	}
1836 	adev->mman.initialized = true;
1837 
1838 	/* Initialize VRAM pool with all of VRAM divided into pages */
1839 	r = amdgpu_vram_mgr_init(adev);
1840 	if (r) {
1841 		DRM_ERROR("Failed initializing VRAM heap.\n");
1842 		return r;
1843 	}
1844 
1845 	/* Change the size here instead of the init above so only lpfn is affected */
1846 	amdgpu_ttm_set_buffer_funcs_status(adev, false);
1847 #ifdef CONFIG_64BIT
1848 #ifdef CONFIG_X86
1849 	if (adev->gmc.xgmi.connected_to_cpu)
1850 		adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1851 				adev->gmc.visible_vram_size);
1852 
1853 	else if (adev->gmc.is_app_apu)
1854 		DRM_DEBUG_DRIVER(
1855 			"No need to ioremap when real vram size is 0\n");
1856 	else
1857 #endif
1858 		adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1859 				adev->gmc.visible_vram_size);
1860 #endif
1861 
1862 	/*
1863 	 *The reserved vram for firmware must be pinned to the specified
1864 	 *place on the VRAM, so reserve it early.
1865 	 */
1866 	r = amdgpu_ttm_fw_reserve_vram_init(adev);
1867 	if (r)
1868 		return r;
1869 
1870 	/*
1871 	 *The reserved vram for driver must be pinned to the specified
1872 	 *place on the VRAM, so reserve it early.
1873 	 */
1874 	r = amdgpu_ttm_drv_reserve_vram_init(adev);
1875 	if (r)
1876 		return r;
1877 
1878 	/*
1879 	 * only NAVI10 and onwards ASIC support for IP discovery.
1880 	 * If IP discovery enabled, a block of memory should be
1881 	 * reserved for IP discovey.
1882 	 */
1883 	if (adev->mman.discovery_bin) {
1884 		r = amdgpu_ttm_reserve_tmr(adev);
1885 		if (r)
1886 			return r;
1887 	}
1888 
1889 	/* allocate memory as required for VGA
1890 	 * This is used for VGA emulation and pre-OS scanout buffers to
1891 	 * avoid display artifacts while transitioning between pre-OS
1892 	 * and driver.
1893 	 */
1894 	if (!adev->gmc.is_app_apu) {
1895 		r = amdgpu_bo_create_kernel_at(adev, 0,
1896 					       adev->mman.stolen_vga_size,
1897 					       &adev->mman.stolen_vga_memory,
1898 					       NULL);
1899 		if (r)
1900 			return r;
1901 
1902 		r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1903 					       adev->mman.stolen_extended_size,
1904 					       &adev->mman.stolen_extended_memory,
1905 					       NULL);
1906 
1907 		if (r)
1908 			return r;
1909 
1910 		r = amdgpu_bo_create_kernel_at(adev,
1911 					       adev->mman.stolen_reserved_offset,
1912 					       adev->mman.stolen_reserved_size,
1913 					       &adev->mman.stolen_reserved_memory,
1914 					       NULL);
1915 		if (r)
1916 			return r;
1917 	} else {
1918 		DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n");
1919 	}
1920 
1921 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1922 		 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024)));
1923 
1924 	/* Compute GTT size, either based on TTM limit
1925 	 * or whatever the user passed on module init.
1926 	 */
1927 	if (amdgpu_gtt_size == -1)
1928 		gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT;
1929 	else
1930 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1931 
1932 	/* Initialize GTT memory pool */
1933 	r = amdgpu_gtt_mgr_init(adev, gtt_size);
1934 	if (r) {
1935 		DRM_ERROR("Failed initializing GTT heap.\n");
1936 		return r;
1937 	}
1938 	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1939 		 (unsigned int)(gtt_size / (1024 * 1024)));
1940 
1941 	/* Initiailize doorbell pool on PCI BAR */
1942 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE);
1943 	if (r) {
1944 		DRM_ERROR("Failed initializing doorbell heap.\n");
1945 		return r;
1946 	}
1947 
1948 	/* Create a boorbell page for kernel usages */
1949 	r = amdgpu_doorbell_create_kernel_doorbells(adev);
1950 	if (r) {
1951 		DRM_ERROR("Failed to initialize kernel doorbells.\n");
1952 		return r;
1953 	}
1954 
1955 	/* Initialize preemptible memory pool */
1956 	r = amdgpu_preempt_mgr_init(adev);
1957 	if (r) {
1958 		DRM_ERROR("Failed initializing PREEMPT heap.\n");
1959 		return r;
1960 	}
1961 
1962 	/* Initialize various on-chip memory pools */
1963 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1964 	if (r) {
1965 		DRM_ERROR("Failed initializing GDS heap.\n");
1966 		return r;
1967 	}
1968 
1969 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1970 	if (r) {
1971 		DRM_ERROR("Failed initializing gws heap.\n");
1972 		return r;
1973 	}
1974 
1975 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1976 	if (r) {
1977 		DRM_ERROR("Failed initializing oa heap.\n");
1978 		return r;
1979 	}
1980 	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1981 				AMDGPU_GEM_DOMAIN_GTT,
1982 				&adev->mman.sdma_access_bo, NULL,
1983 				&adev->mman.sdma_access_ptr))
1984 		DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1985 
1986 	return 0;
1987 }
1988 
1989 /*
1990  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1991  */
amdgpu_ttm_fini(struct amdgpu_device * adev)1992 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1993 {
1994 	int idx;
1995 
1996 	if (!adev->mman.initialized)
1997 		return;
1998 
1999 	amdgpu_ttm_pools_fini(adev);
2000 
2001 	amdgpu_ttm_training_reserve_vram_fini(adev);
2002 	/* return the stolen vga memory back to VRAM */
2003 	if (!adev->gmc.is_app_apu) {
2004 		amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2005 		amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2006 		/* return the FW reserved memory back to VRAM */
2007 		amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL,
2008 				      NULL);
2009 		if (adev->mman.stolen_reserved_size)
2010 			amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
2011 					      NULL, NULL);
2012 	}
2013 	amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
2014 					&adev->mman.sdma_access_ptr);
2015 	amdgpu_ttm_fw_reserve_vram_fini(adev);
2016 	amdgpu_ttm_drv_reserve_vram_fini(adev);
2017 
2018 	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
2019 
2020 		if (adev->mman.aper_base_kaddr)
2021 			iounmap(adev->mman.aper_base_kaddr);
2022 		adev->mman.aper_base_kaddr = NULL;
2023 
2024 		drm_dev_exit(idx);
2025 	}
2026 
2027 	amdgpu_vram_mgr_fini(adev);
2028 	amdgpu_gtt_mgr_fini(adev);
2029 	amdgpu_preempt_mgr_fini(adev);
2030 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2031 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2032 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2033 	ttm_device_fini(&adev->mman.bdev);
2034 	adev->mman.initialized = false;
2035 	DRM_INFO("amdgpu: ttm finalized\n");
2036 }
2037 
2038 /**
2039  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2040  *
2041  * @adev: amdgpu_device pointer
2042  * @enable: true when we can use buffer functions.
2043  *
2044  * Enable/disable use of buffer functions during suspend/resume. This should
2045  * only be called at bootup or when userspace isn't running.
2046  */
amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device * adev,bool enable)2047 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2048 {
2049 	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2050 	uint64_t size;
2051 	int r;
2052 
2053 	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2054 	    adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
2055 		return;
2056 
2057 	if (enable) {
2058 		struct amdgpu_ring *ring;
2059 		struct drm_gpu_scheduler *sched;
2060 
2061 		ring = adev->mman.buffer_funcs_ring;
2062 		sched = &ring->sched;
2063 		r = drm_sched_entity_init(&adev->mman.high_pr,
2064 					  DRM_SCHED_PRIORITY_KERNEL, &sched,
2065 					  1, NULL);
2066 		if (r) {
2067 			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2068 				  r);
2069 			return;
2070 		}
2071 
2072 		r = drm_sched_entity_init(&adev->mman.low_pr,
2073 					  DRM_SCHED_PRIORITY_NORMAL, &sched,
2074 					  1, NULL);
2075 		if (r) {
2076 			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2077 				  r);
2078 			goto error_free_entity;
2079 		}
2080 	} else {
2081 		drm_sched_entity_destroy(&adev->mman.high_pr);
2082 		drm_sched_entity_destroy(&adev->mman.low_pr);
2083 		dma_fence_put(man->move);
2084 		man->move = NULL;
2085 	}
2086 
2087 	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
2088 	if (enable)
2089 		size = adev->gmc.real_vram_size;
2090 	else
2091 		size = adev->gmc.visible_vram_size;
2092 	man->size = size;
2093 	adev->mman.buffer_funcs_enabled = enable;
2094 
2095 	return;
2096 
2097 error_free_entity:
2098 	drm_sched_entity_destroy(&adev->mman.high_pr);
2099 }
2100 
amdgpu_ttm_prepare_job(struct amdgpu_device * adev,bool direct_submit,unsigned int num_dw,struct dma_resv * resv,bool vm_needs_flush,struct amdgpu_job ** job,bool delayed)2101 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
2102 				  bool direct_submit,
2103 				  unsigned int num_dw,
2104 				  struct dma_resv *resv,
2105 				  bool vm_needs_flush,
2106 				  struct amdgpu_job **job,
2107 				  bool delayed)
2108 {
2109 	enum amdgpu_ib_pool_type pool = direct_submit ?
2110 		AMDGPU_IB_POOL_DIRECT :
2111 		AMDGPU_IB_POOL_DELAYED;
2112 	int r;
2113 	struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
2114 						    &adev->mman.high_pr;
2115 	r = amdgpu_job_alloc_with_ib(adev, entity,
2116 				     AMDGPU_FENCE_OWNER_UNDEFINED,
2117 				     num_dw * 4, pool, job);
2118 	if (r)
2119 		return r;
2120 
2121 	if (vm_needs_flush) {
2122 		(*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
2123 							adev->gmc.pdb0_bo :
2124 							adev->gart.bo);
2125 		(*job)->vm_needs_flush = true;
2126 	}
2127 	if (!resv)
2128 		return 0;
2129 
2130 	return drm_sched_job_add_resv_dependencies(&(*job)->base, resv,
2131 						   DMA_RESV_USAGE_BOOKKEEP);
2132 }
2133 
amdgpu_copy_buffer(struct amdgpu_ring * ring,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,struct dma_resv * resv,struct dma_fence ** fence,bool direct_submit,bool vm_needs_flush,bool tmz)2134 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2135 		       uint64_t dst_offset, uint32_t byte_count,
2136 		       struct dma_resv *resv,
2137 		       struct dma_fence **fence, bool direct_submit,
2138 		       bool vm_needs_flush, bool tmz)
2139 {
2140 	struct amdgpu_device *adev = ring->adev;
2141 	unsigned int num_loops, num_dw;
2142 	struct amdgpu_job *job;
2143 	uint32_t max_bytes;
2144 	unsigned int i;
2145 	int r;
2146 
2147 	if (!direct_submit && !ring->sched.ready) {
2148 		DRM_ERROR("Trying to move memory with ring turned off.\n");
2149 		return -EINVAL;
2150 	}
2151 
2152 	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2153 	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2154 	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2155 	r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2156 				   resv, vm_needs_flush, &job, false);
2157 	if (r)
2158 		return r;
2159 
2160 	for (i = 0; i < num_loops; i++) {
2161 		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2162 
2163 		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2164 					dst_offset, cur_size_in_bytes, tmz);
2165 
2166 		src_offset += cur_size_in_bytes;
2167 		dst_offset += cur_size_in_bytes;
2168 		byte_count -= cur_size_in_bytes;
2169 	}
2170 
2171 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2172 	WARN_ON(job->ibs[0].length_dw > num_dw);
2173 	if (direct_submit)
2174 		r = amdgpu_job_submit_direct(job, ring, fence);
2175 	else
2176 		*fence = amdgpu_job_submit(job);
2177 	if (r)
2178 		goto error_free;
2179 
2180 	return r;
2181 
2182 error_free:
2183 	amdgpu_job_free(job);
2184 	DRM_ERROR("Error scheduling IBs (%d)\n", r);
2185 	return r;
2186 }
2187 
amdgpu_ttm_fill_mem(struct amdgpu_ring * ring,uint32_t src_data,uint64_t dst_addr,uint32_t byte_count,struct dma_resv * resv,struct dma_fence ** fence,bool vm_needs_flush,bool delayed)2188 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2189 			       uint64_t dst_addr, uint32_t byte_count,
2190 			       struct dma_resv *resv,
2191 			       struct dma_fence **fence,
2192 			       bool vm_needs_flush, bool delayed)
2193 {
2194 	struct amdgpu_device *adev = ring->adev;
2195 	unsigned int num_loops, num_dw;
2196 	struct amdgpu_job *job;
2197 	uint32_t max_bytes;
2198 	unsigned int i;
2199 	int r;
2200 
2201 	max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2202 	num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2203 	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2204 	r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2205 				   &job, delayed);
2206 	if (r)
2207 		return r;
2208 
2209 	for (i = 0; i < num_loops; i++) {
2210 		uint32_t cur_size = min(byte_count, max_bytes);
2211 
2212 		amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2213 					cur_size);
2214 
2215 		dst_addr += cur_size;
2216 		byte_count -= cur_size;
2217 	}
2218 
2219 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2220 	WARN_ON(job->ibs[0].length_dw > num_dw);
2221 	*fence = amdgpu_job_submit(job);
2222 	return 0;
2223 }
2224 
amdgpu_fill_buffer(struct amdgpu_bo * bo,uint32_t src_data,struct dma_resv * resv,struct dma_fence ** f,bool delayed)2225 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2226 			uint32_t src_data,
2227 			struct dma_resv *resv,
2228 			struct dma_fence **f,
2229 			bool delayed)
2230 {
2231 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2232 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2233 	struct dma_fence *fence = NULL;
2234 	struct amdgpu_res_cursor dst;
2235 	int r;
2236 
2237 	if (!adev->mman.buffer_funcs_enabled) {
2238 		DRM_ERROR("Trying to clear memory with ring turned off.\n");
2239 		return -EINVAL;
2240 	}
2241 
2242 	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2243 
2244 	mutex_lock(&adev->mman.gtt_window_lock);
2245 	while (dst.remaining) {
2246 		struct dma_fence *next;
2247 		uint64_t cur_size, to;
2248 
2249 		/* Never fill more than 256MiB at once to avoid timeouts */
2250 		cur_size = min(dst.size, 256ULL << 20);
2251 
2252 		r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2253 					  1, ring, false, &cur_size, &to);
2254 		if (r)
2255 			goto error;
2256 
2257 		r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2258 					&next, true, delayed);
2259 		if (r)
2260 			goto error;
2261 
2262 		dma_fence_put(fence);
2263 		fence = next;
2264 
2265 		amdgpu_res_next(&dst, cur_size);
2266 	}
2267 error:
2268 	mutex_unlock(&adev->mman.gtt_window_lock);
2269 	if (f)
2270 		*f = dma_fence_get(fence);
2271 	dma_fence_put(fence);
2272 	return r;
2273 }
2274 
2275 /**
2276  * amdgpu_ttm_evict_resources - evict memory buffers
2277  * @adev: amdgpu device object
2278  * @mem_type: evicted BO's memory type
2279  *
2280  * Evicts all @mem_type buffers on the lru list of the memory type.
2281  *
2282  * Returns:
2283  * 0 for success or a negative error code on failure.
2284  */
amdgpu_ttm_evict_resources(struct amdgpu_device * adev,int mem_type)2285 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2286 {
2287 	struct ttm_resource_manager *man;
2288 
2289 	switch (mem_type) {
2290 	case TTM_PL_VRAM:
2291 	case TTM_PL_TT:
2292 	case AMDGPU_PL_GWS:
2293 	case AMDGPU_PL_GDS:
2294 	case AMDGPU_PL_OA:
2295 		man = ttm_manager_type(&adev->mman.bdev, mem_type);
2296 		break;
2297 	default:
2298 		DRM_ERROR("Trying to evict invalid memory type\n");
2299 		return -EINVAL;
2300 	}
2301 
2302 	return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2303 }
2304 
2305 #if defined(CONFIG_DEBUG_FS)
2306 
amdgpu_ttm_page_pool_show(struct seq_file * m,void * unused)2307 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2308 {
2309 	struct amdgpu_device *adev = m->private;
2310 
2311 	return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2312 }
2313 
2314 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2315 
2316 /*
2317  * amdgpu_ttm_vram_read - Linear read access to VRAM
2318  *
2319  * Accesses VRAM via MMIO for debugging purposes.
2320  */
amdgpu_ttm_vram_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2321 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2322 				    size_t size, loff_t *pos)
2323 {
2324 	struct amdgpu_device *adev = file_inode(f)->i_private;
2325 	ssize_t result = 0;
2326 
2327 	if (size & 0x3 || *pos & 0x3)
2328 		return -EINVAL;
2329 
2330 	if (*pos >= adev->gmc.mc_vram_size)
2331 		return -ENXIO;
2332 
2333 	size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2334 	while (size) {
2335 		size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2336 		uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2337 
2338 		amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2339 		if (copy_to_user(buf, value, bytes))
2340 			return -EFAULT;
2341 
2342 		result += bytes;
2343 		buf += bytes;
2344 		*pos += bytes;
2345 		size -= bytes;
2346 	}
2347 
2348 	return result;
2349 }
2350 
2351 /*
2352  * amdgpu_ttm_vram_write - Linear write access to VRAM
2353  *
2354  * Accesses VRAM via MMIO for debugging purposes.
2355  */
amdgpu_ttm_vram_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2356 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2357 				    size_t size, loff_t *pos)
2358 {
2359 	struct amdgpu_device *adev = file_inode(f)->i_private;
2360 	ssize_t result = 0;
2361 	int r;
2362 
2363 	if (size & 0x3 || *pos & 0x3)
2364 		return -EINVAL;
2365 
2366 	if (*pos >= adev->gmc.mc_vram_size)
2367 		return -ENXIO;
2368 
2369 	while (size) {
2370 		uint32_t value;
2371 
2372 		if (*pos >= adev->gmc.mc_vram_size)
2373 			return result;
2374 
2375 		r = get_user(value, (uint32_t *)buf);
2376 		if (r)
2377 			return r;
2378 
2379 		amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2380 
2381 		result += 4;
2382 		buf += 4;
2383 		*pos += 4;
2384 		size -= 4;
2385 	}
2386 
2387 	return result;
2388 }
2389 
2390 static const struct file_operations amdgpu_ttm_vram_fops = {
2391 	.owner = THIS_MODULE,
2392 	.read = amdgpu_ttm_vram_read,
2393 	.write = amdgpu_ttm_vram_write,
2394 	.llseek = default_llseek,
2395 };
2396 
2397 /*
2398  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2399  *
2400  * This function is used to read memory that has been mapped to the
2401  * GPU and the known addresses are not physical addresses but instead
2402  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2403  */
amdgpu_iomem_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2404 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2405 				 size_t size, loff_t *pos)
2406 {
2407 	struct amdgpu_device *adev = file_inode(f)->i_private;
2408 	struct iommu_domain *dom;
2409 	ssize_t result = 0;
2410 	int r;
2411 
2412 	/* retrieve the IOMMU domain if any for this device */
2413 	dom = iommu_get_domain_for_dev(adev->dev);
2414 
2415 	while (size) {
2416 		phys_addr_t addr = *pos & PAGE_MASK;
2417 		loff_t off = *pos & ~PAGE_MASK;
2418 		size_t bytes = PAGE_SIZE - off;
2419 		unsigned long pfn;
2420 		struct page *p;
2421 		void *ptr;
2422 
2423 		bytes = min(bytes, size);
2424 
2425 		/* Translate the bus address to a physical address.  If
2426 		 * the domain is NULL it means there is no IOMMU active
2427 		 * and the address translation is the identity
2428 		 */
2429 		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2430 
2431 		pfn = addr >> PAGE_SHIFT;
2432 		if (!pfn_valid(pfn))
2433 			return -EPERM;
2434 
2435 		p = pfn_to_page(pfn);
2436 		if (p->mapping != adev->mman.bdev.dev_mapping)
2437 			return -EPERM;
2438 
2439 		ptr = kmap_local_page(p);
2440 		r = copy_to_user(buf, ptr + off, bytes);
2441 		kunmap_local(ptr);
2442 		if (r)
2443 			return -EFAULT;
2444 
2445 		size -= bytes;
2446 		*pos += bytes;
2447 		result += bytes;
2448 	}
2449 
2450 	return result;
2451 }
2452 
2453 /*
2454  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2455  *
2456  * This function is used to write memory that has been mapped to the
2457  * GPU and the known addresses are not physical addresses but instead
2458  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2459  */
amdgpu_iomem_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2460 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2461 				 size_t size, loff_t *pos)
2462 {
2463 	struct amdgpu_device *adev = file_inode(f)->i_private;
2464 	struct iommu_domain *dom;
2465 	ssize_t result = 0;
2466 	int r;
2467 
2468 	dom = iommu_get_domain_for_dev(adev->dev);
2469 
2470 	while (size) {
2471 		phys_addr_t addr = *pos & PAGE_MASK;
2472 		loff_t off = *pos & ~PAGE_MASK;
2473 		size_t bytes = PAGE_SIZE - off;
2474 		unsigned long pfn;
2475 		struct page *p;
2476 		void *ptr;
2477 
2478 		bytes = min(bytes, size);
2479 
2480 		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2481 
2482 		pfn = addr >> PAGE_SHIFT;
2483 		if (!pfn_valid(pfn))
2484 			return -EPERM;
2485 
2486 		p = pfn_to_page(pfn);
2487 		if (p->mapping != adev->mman.bdev.dev_mapping)
2488 			return -EPERM;
2489 
2490 		ptr = kmap_local_page(p);
2491 		r = copy_from_user(ptr + off, buf, bytes);
2492 		kunmap_local(ptr);
2493 		if (r)
2494 			return -EFAULT;
2495 
2496 		size -= bytes;
2497 		*pos += bytes;
2498 		result += bytes;
2499 	}
2500 
2501 	return result;
2502 }
2503 
2504 static const struct file_operations amdgpu_ttm_iomem_fops = {
2505 	.owner = THIS_MODULE,
2506 	.read = amdgpu_iomem_read,
2507 	.write = amdgpu_iomem_write,
2508 	.llseek = default_llseek
2509 };
2510 
2511 #endif
2512 
amdgpu_ttm_debugfs_init(struct amdgpu_device * adev)2513 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2514 {
2515 #if defined(CONFIG_DEBUG_FS)
2516 	struct drm_minor *minor = adev_to_drm(adev)->primary;
2517 	struct dentry *root = minor->debugfs_root;
2518 
2519 	debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2520 				 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2521 	debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2522 			    &amdgpu_ttm_iomem_fops);
2523 	debugfs_create_file("ttm_page_pool", 0444, root, adev,
2524 			    &amdgpu_ttm_page_pool_fops);
2525 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2526 							     TTM_PL_VRAM),
2527 					    root, "amdgpu_vram_mm");
2528 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2529 							     TTM_PL_TT),
2530 					    root, "amdgpu_gtt_mm");
2531 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2532 							     AMDGPU_PL_GDS),
2533 					    root, "amdgpu_gds_mm");
2534 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2535 							     AMDGPU_PL_GWS),
2536 					    root, "amdgpu_gws_mm");
2537 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2538 							     AMDGPU_PL_OA),
2539 					    root, "amdgpu_oa_mm");
2540 
2541 #endif
2542 }
2543