1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu_ras_eeprom.h"
25 #include "amdgpu.h"
26 #include "amdgpu_ras.h"
27 #include <linux/bits.h>
28 #include "atom.h"
29 #include "amdgpu_eeprom.h"
30 #include "amdgpu_atomfirmware.h"
31 #include <linux/debugfs.h>
32 #include <linux/uaccess.h>
33
34 #include "amdgpu_reset.h"
35
36 #define EEPROM_I2C_MADDR_VEGA20 0x0
37 #define EEPROM_I2C_MADDR_ARCTURUS 0x40000
38 #define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0
39 #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
40 #define EEPROM_I2C_MADDR_ALDEBARAN 0x0
41 #define EEPROM_I2C_MADDR_SMU_13_0_0 (0x54UL << 16)
42
43 /*
44 * The 2 macros bellow represent the actual size in bytes that
45 * those entities occupy in the EEPROM memory.
46 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
47 * uses uint64 to store 6b fields such as retired_page.
48 */
49 #define RAS_TABLE_HEADER_SIZE 20
50 #define RAS_TABLE_RECORD_SIZE 24
51
52 /* Table hdr is 'AMDR' */
53 #define RAS_TABLE_HDR_VAL 0x414d4452
54 #define RAS_TABLE_VER 0x00010000
55
56 /* Bad GPU tag ‘BADG’ */
57 #define RAS_TABLE_HDR_BAD 0x42414447
58
59 /* Assume 2-Mbit size EEPROM and take up the whole space. */
60 #define RAS_TBL_SIZE_BYTES (256 * 1024)
61 #define RAS_TABLE_START 0
62 #define RAS_HDR_START RAS_TABLE_START
63 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
64 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
65 / RAS_TABLE_RECORD_SIZE)
66
67 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
68 * offset off of RAS_TABLE_START. That is, this is something you can
69 * add to control->i2c_address, and then tell I2C layer to read
70 * from/write to there. _N is the so called absolute index,
71 * because it starts right after the table header.
72 */
73 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
74 (_N) * RAS_TABLE_RECORD_SIZE)
75
76 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
77 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
78
79 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
80 * of "fri", return the absolute record index off of the end of
81 * the table header.
82 */
83 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
84 (_C)->ras_max_record_count)
85
86 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
87 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
88
89 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
90
__is_ras_eeprom_supported(struct amdgpu_device * adev)91 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
92 {
93 return adev->asic_type == CHIP_VEGA20 ||
94 adev->asic_type == CHIP_ARCTURUS ||
95 adev->asic_type == CHIP_SIENNA_CICHLID ||
96 adev->asic_type == CHIP_ALDEBARAN;
97 }
98
__get_eeprom_i2c_addr_arct(struct amdgpu_device * adev,struct amdgpu_ras_eeprom_control * control)99 static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
100 struct amdgpu_ras_eeprom_control *control)
101 {
102 struct atom_context *atom_ctx = adev->mode_info.atom_context;
103
104 if (!control || !atom_ctx)
105 return false;
106
107 if (strnstr(atom_ctx->vbios_version,
108 "D342",
109 sizeof(atom_ctx->vbios_version)))
110 control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342;
111 else
112 control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
113
114 return true;
115 }
116
__get_eeprom_i2c_addr(struct amdgpu_device * adev,struct amdgpu_ras_eeprom_control * control)117 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
118 struct amdgpu_ras_eeprom_control *control)
119 {
120 u8 i2c_addr;
121
122 if (!control)
123 return false;
124
125 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
126 /* The address given by VBIOS is an 8-bit, wire-format
127 * address, i.e. the most significant byte.
128 *
129 * Normalize it to a 19-bit EEPROM address. Remove the
130 * device type identifier and make it a 7-bit address;
131 * then make it a 19-bit EEPROM address. See top of
132 * amdgpu_eeprom.c.
133 */
134 i2c_addr = (i2c_addr & 0x0F) >> 1;
135 control->i2c_address = ((u32) i2c_addr) << 16;
136
137 return true;
138 }
139
140 switch (adev->asic_type) {
141 case CHIP_VEGA20:
142 control->i2c_address = EEPROM_I2C_MADDR_VEGA20;
143 break;
144
145 case CHIP_ARCTURUS:
146 return __get_eeprom_i2c_addr_arct(adev, control);
147
148 case CHIP_SIENNA_CICHLID:
149 control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID;
150 break;
151
152 case CHIP_ALDEBARAN:
153 control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;
154 break;
155
156 default:
157 return false;
158 }
159
160 switch (adev->ip_versions[MP1_HWIP][0]) {
161 case IP_VERSION(13, 0, 0):
162 control->i2c_address = EEPROM_I2C_MADDR_SMU_13_0_0;
163 break;
164
165 default:
166 break;
167 }
168
169 return true;
170 }
171
172 static void
__encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)173 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
174 unsigned char *buf)
175 {
176 u32 *pp = (uint32_t *)buf;
177
178 pp[0] = cpu_to_le32(hdr->header);
179 pp[1] = cpu_to_le32(hdr->version);
180 pp[2] = cpu_to_le32(hdr->first_rec_offset);
181 pp[3] = cpu_to_le32(hdr->tbl_size);
182 pp[4] = cpu_to_le32(hdr->checksum);
183 }
184
185 static void
__decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)186 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
187 unsigned char *buf)
188 {
189 u32 *pp = (uint32_t *)buf;
190
191 hdr->header = le32_to_cpu(pp[0]);
192 hdr->version = le32_to_cpu(pp[1]);
193 hdr->first_rec_offset = le32_to_cpu(pp[2]);
194 hdr->tbl_size = le32_to_cpu(pp[3]);
195 hdr->checksum = le32_to_cpu(pp[4]);
196 }
197
__write_table_header(struct amdgpu_ras_eeprom_control * control)198 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
199 {
200 u8 buf[RAS_TABLE_HEADER_SIZE];
201 struct amdgpu_device *adev = to_amdgpu_device(control);
202 int res;
203
204 memset(buf, 0, sizeof(buf));
205 __encode_table_header_to_buf(&control->tbl_hdr, buf);
206
207 /* i2c may be unstable in gpu reset */
208 down_read(&adev->reset_domain->sem);
209 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
210 control->i2c_address +
211 control->ras_header_offset,
212 buf, RAS_TABLE_HEADER_SIZE);
213 up_read(&adev->reset_domain->sem);
214
215 if (res < 0) {
216 DRM_ERROR("Failed to write EEPROM table header:%d", res);
217 } else if (res < RAS_TABLE_HEADER_SIZE) {
218 DRM_ERROR("Short write:%d out of %d\n",
219 res, RAS_TABLE_HEADER_SIZE);
220 res = -EIO;
221 } else {
222 res = 0;
223 }
224
225 return res;
226 }
227
__calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control * control)228 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
229 {
230 int ii;
231 u8 *pp, csum;
232 size_t sz;
233
234 /* Header checksum, skip checksum field in the calculation */
235 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
236 pp = (u8 *) &control->tbl_hdr;
237 csum = 0;
238 for (ii = 0; ii < sz; ii++, pp++)
239 csum += *pp;
240
241 return csum;
242 }
243
amdgpu_ras_eeprom_correct_header_tag(struct amdgpu_ras_eeprom_control * control,uint32_t header)244 static int amdgpu_ras_eeprom_correct_header_tag(
245 struct amdgpu_ras_eeprom_control *control,
246 uint32_t header)
247 {
248 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
249 u8 *hh;
250 int res;
251 u8 csum;
252
253 csum = -hdr->checksum;
254
255 hh = (void *) &hdr->header;
256 csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
257 hh = (void *) &header;
258 csum += hh[0] + hh[1] + hh[2] + hh[3];
259 csum = -csum;
260 mutex_lock(&control->ras_tbl_mutex);
261 hdr->header = header;
262 hdr->checksum = csum;
263 res = __write_table_header(control);
264 mutex_unlock(&control->ras_tbl_mutex);
265
266 return res;
267 }
268
269 /**
270 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
271 * @control: pointer to control structure
272 *
273 * Reset the contents of the header of the RAS EEPROM table.
274 * Return 0 on success, -errno on error.
275 */
amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control * control)276 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
277 {
278 struct amdgpu_device *adev = to_amdgpu_device(control);
279 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
280 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
281 u8 csum;
282 int res;
283
284 mutex_lock(&control->ras_tbl_mutex);
285
286 hdr->header = RAS_TABLE_HDR_VAL;
287 hdr->version = RAS_TABLE_VER;
288 hdr->first_rec_offset = RAS_RECORD_START;
289 hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
290
291 csum = __calc_hdr_byte_sum(control);
292 csum = -csum;
293 hdr->checksum = csum;
294 res = __write_table_header(control);
295
296 control->ras_num_recs = 0;
297 control->ras_fri = 0;
298
299 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);
300
301 control->bad_channel_bitmap = 0;
302 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);
303 con->update_channel_flag = false;
304
305 amdgpu_ras_debugfs_set_ret_size(control);
306
307 mutex_unlock(&control->ras_tbl_mutex);
308
309 return res;
310 }
311
312 static void
__encode_table_record_to_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)313 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
314 struct eeprom_table_record *record,
315 unsigned char *buf)
316 {
317 __le64 tmp = 0;
318 int i = 0;
319
320 /* Next are all record fields according to EEPROM page spec in LE foramt */
321 buf[i++] = record->err_type;
322
323 buf[i++] = record->bank;
324
325 tmp = cpu_to_le64(record->ts);
326 memcpy(buf + i, &tmp, 8);
327 i += 8;
328
329 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
330 memcpy(buf + i, &tmp, 6);
331 i += 6;
332
333 buf[i++] = record->mem_channel;
334 buf[i++] = record->mcumc_id;
335
336 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
337 memcpy(buf + i, &tmp, 6);
338 }
339
340 static void
__decode_table_record_from_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)341 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
342 struct eeprom_table_record *record,
343 unsigned char *buf)
344 {
345 __le64 tmp = 0;
346 int i = 0;
347
348 /* Next are all record fields according to EEPROM page spec in LE foramt */
349 record->err_type = buf[i++];
350
351 record->bank = buf[i++];
352
353 memcpy(&tmp, buf + i, 8);
354 record->ts = le64_to_cpu(tmp);
355 i += 8;
356
357 memcpy(&tmp, buf + i, 6);
358 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
359 i += 6;
360
361 record->mem_channel = buf[i++];
362 record->mcumc_id = buf[i++];
363
364 memcpy(&tmp, buf + i, 6);
365 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
366 }
367
amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device * adev)368 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
369 {
370 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
371
372 if (!__is_ras_eeprom_supported(adev))
373 return false;
374
375 /* skip check eeprom table for VEGA20 Gaming */
376 if (!con)
377 return false;
378 else
379 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
380 return false;
381
382 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
383 dev_warn(adev->dev, "This GPU is in BAD status.");
384 dev_warn(adev->dev, "Please retire it or set a larger "
385 "threshold value when reloading driver.\n");
386 return true;
387 }
388
389 return false;
390 }
391
392 /**
393 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
394 * @control: pointer to control structure
395 * @buf: pointer to buffer containing data to write
396 * @fri: start writing at this index
397 * @num: number of records to write
398 *
399 * The caller must hold the table mutex in @control.
400 * Return 0 on success, -errno otherwise.
401 */
__amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)402 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
403 u8 *buf, const u32 fri, const u32 num)
404 {
405 struct amdgpu_device *adev = to_amdgpu_device(control);
406 u32 buf_size;
407 int res;
408
409 /* i2c may be unstable in gpu reset */
410 down_read(&adev->reset_domain->sem);
411 buf_size = num * RAS_TABLE_RECORD_SIZE;
412 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
413 control->i2c_address +
414 RAS_INDEX_TO_OFFSET(control, fri),
415 buf, buf_size);
416 up_read(&adev->reset_domain->sem);
417 if (res < 0) {
418 DRM_ERROR("Writing %d EEPROM table records error:%d",
419 num, res);
420 } else if (res < buf_size) {
421 /* Short write, return error.
422 */
423 DRM_ERROR("Wrote %d records out of %d",
424 res / RAS_TABLE_RECORD_SIZE, num);
425 res = -EIO;
426 } else {
427 res = 0;
428 }
429
430 return res;
431 }
432
433 static int
amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)434 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
435 struct eeprom_table_record *record,
436 const u32 num)
437 {
438 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
439 u32 a, b, i;
440 u8 *buf, *pp;
441 int res;
442
443 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
444 if (!buf)
445 return -ENOMEM;
446
447 /* Encode all of them in one go.
448 */
449 pp = buf;
450 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
451 __encode_table_record_to_buf(control, &record[i], pp);
452
453 /* update bad channel bitmap */
454 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
455 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
456 con->update_channel_flag = true;
457 }
458 }
459
460 /* a, first record index to write into.
461 * b, last record index to write into.
462 * a = first index to read (fri) + number of records in the table,
463 * b = a + @num - 1.
464 * Let N = control->ras_max_num_record_count, then we have,
465 * case 0: 0 <= a <= b < N,
466 * just append @num records starting at a;
467 * case 1: 0 <= a < N <= b,
468 * append (N - a) records starting at a, and
469 * append the remainder, b % N + 1, starting at 0.
470 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
471 * case 2a: 0 <= a <= b < N
472 * append num records starting at a; and fix fri if b overwrote it,
473 * and since a <= b, if b overwrote it then a must've also,
474 * and if b didn't overwrite it, then a didn't also.
475 * case 2b: 0 <= b < a < N
476 * write num records starting at a, which wraps around 0=N
477 * and overwrite fri unconditionally. Now from case 2a,
478 * this means that b eclipsed fri to overwrite it and wrap
479 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
480 * set fri = b + 1 (mod N).
481 * Now, since fri is updated in every case, except the trivial case 0,
482 * the number of records present in the table after writing, is,
483 * num_recs - 1 = b - fri (mod N), and we take the positive value,
484 * by adding an arbitrary multiple of N before taking the modulo N
485 * as shown below.
486 */
487 a = control->ras_fri + control->ras_num_recs;
488 b = a + num - 1;
489 if (b < control->ras_max_record_count) {
490 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
491 } else if (a < control->ras_max_record_count) {
492 u32 g0, g1;
493
494 g0 = control->ras_max_record_count - a;
495 g1 = b % control->ras_max_record_count + 1;
496 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
497 if (res)
498 goto Out;
499 res = __amdgpu_ras_eeprom_write(control,
500 buf + g0 * RAS_TABLE_RECORD_SIZE,
501 0, g1);
502 if (res)
503 goto Out;
504 if (g1 > control->ras_fri)
505 control->ras_fri = g1 % control->ras_max_record_count;
506 } else {
507 a %= control->ras_max_record_count;
508 b %= control->ras_max_record_count;
509
510 if (a <= b) {
511 /* Note that, b - a + 1 = num. */
512 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
513 if (res)
514 goto Out;
515 if (b >= control->ras_fri)
516 control->ras_fri = (b + 1) % control->ras_max_record_count;
517 } else {
518 u32 g0, g1;
519
520 /* b < a, which means, we write from
521 * a to the end of the table, and from
522 * the start of the table to b.
523 */
524 g0 = control->ras_max_record_count - a;
525 g1 = b + 1;
526 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
527 if (res)
528 goto Out;
529 res = __amdgpu_ras_eeprom_write(control,
530 buf + g0 * RAS_TABLE_RECORD_SIZE,
531 0, g1);
532 if (res)
533 goto Out;
534 control->ras_fri = g1 % control->ras_max_record_count;
535 }
536 }
537 control->ras_num_recs = 1 + (control->ras_max_record_count + b
538 - control->ras_fri)
539 % control->ras_max_record_count;
540 Out:
541 kfree(buf);
542 return res;
543 }
544
545 static int
amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control * control)546 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
547 {
548 struct amdgpu_device *adev = to_amdgpu_device(control);
549 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
550 u8 *buf, *pp, csum;
551 u32 buf_size;
552 int res;
553
554 /* Modify the header if it exceeds.
555 */
556 if (amdgpu_bad_page_threshold != 0 &&
557 control->ras_num_recs >= ras->bad_page_cnt_threshold) {
558 dev_warn(adev->dev,
559 "Saved bad pages %d reaches threshold value %d\n",
560 control->ras_num_recs, ras->bad_page_cnt_threshold);
561 control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
562 }
563
564 control->tbl_hdr.version = RAS_TABLE_VER;
565 control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri);
566 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
567 control->tbl_hdr.checksum = 0;
568
569 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
570 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
571 if (!buf) {
572 DRM_ERROR("allocating memory for table of size %d bytes failed\n",
573 control->tbl_hdr.tbl_size);
574 res = -ENOMEM;
575 goto Out;
576 }
577
578 down_read(&adev->reset_domain->sem);
579 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
580 control->i2c_address +
581 control->ras_record_offset,
582 buf, buf_size);
583 up_read(&adev->reset_domain->sem);
584 if (res < 0) {
585 DRM_ERROR("EEPROM failed reading records:%d\n",
586 res);
587 goto Out;
588 } else if (res < buf_size) {
589 DRM_ERROR("EEPROM read %d out of %d bytes\n",
590 res, buf_size);
591 res = -EIO;
592 goto Out;
593 }
594
595 /* Recalc the checksum.
596 */
597 csum = 0;
598 for (pp = buf; pp < buf + buf_size; pp++)
599 csum += *pp;
600
601 csum += __calc_hdr_byte_sum(control);
602 /* avoid sign extension when assigning to "checksum" */
603 csum = -csum;
604 control->tbl_hdr.checksum = csum;
605 res = __write_table_header(control);
606 Out:
607 kfree(buf);
608 return res;
609 }
610
611 /**
612 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
613 * @control: pointer to control structure
614 * @record: array of records to append
615 * @num: number of records in @record array
616 *
617 * Append @num records to the table, calculate the checksum and write
618 * the table back to EEPROM. The maximum number of records that
619 * can be appended is between 1 and control->ras_max_record_count,
620 * regardless of how many records are already stored in the table.
621 *
622 * Return 0 on success or if EEPROM is not supported, -errno on error.
623 */
amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)624 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
625 struct eeprom_table_record *record,
626 const u32 num)
627 {
628 struct amdgpu_device *adev = to_amdgpu_device(control);
629 int res;
630
631 if (!__is_ras_eeprom_supported(adev))
632 return 0;
633
634 if (num == 0) {
635 DRM_ERROR("will not append 0 records\n");
636 return -EINVAL;
637 } else if (num > control->ras_max_record_count) {
638 DRM_ERROR("cannot append %d records than the size of table %d\n",
639 num, control->ras_max_record_count);
640 return -EINVAL;
641 }
642
643 mutex_lock(&control->ras_tbl_mutex);
644
645 res = amdgpu_ras_eeprom_append_table(control, record, num);
646 if (!res)
647 res = amdgpu_ras_eeprom_update_header(control);
648 if (!res)
649 amdgpu_ras_debugfs_set_ret_size(control);
650
651 mutex_unlock(&control->ras_tbl_mutex);
652 return res;
653 }
654
655 /**
656 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
657 * @control: pointer to control structure
658 * @buf: pointer to buffer to read into
659 * @fri: first record index, start reading at this index, absolute index
660 * @num: number of records to read
661 *
662 * The caller must hold the table mutex in @control.
663 * Return 0 on success, -errno otherwise.
664 */
__amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)665 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
666 u8 *buf, const u32 fri, const u32 num)
667 {
668 struct amdgpu_device *adev = to_amdgpu_device(control);
669 u32 buf_size;
670 int res;
671
672 /* i2c may be unstable in gpu reset */
673 down_read(&adev->reset_domain->sem);
674 buf_size = num * RAS_TABLE_RECORD_SIZE;
675 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
676 control->i2c_address +
677 RAS_INDEX_TO_OFFSET(control, fri),
678 buf, buf_size);
679 up_read(&adev->reset_domain->sem);
680 if (res < 0) {
681 DRM_ERROR("Reading %d EEPROM table records error:%d",
682 num, res);
683 } else if (res < buf_size) {
684 /* Short read, return error.
685 */
686 DRM_ERROR("Read %d records out of %d",
687 res / RAS_TABLE_RECORD_SIZE, num);
688 res = -EIO;
689 } else {
690 res = 0;
691 }
692
693 return res;
694 }
695
696 /**
697 * amdgpu_ras_eeprom_read -- read EEPROM
698 * @control: pointer to control structure
699 * @record: array of records to read into
700 * @num: number of records in @record
701 *
702 * Reads num records from the RAS table in EEPROM and
703 * writes the data into @record array.
704 *
705 * Returns 0 on success, -errno on error.
706 */
amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)707 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
708 struct eeprom_table_record *record,
709 const u32 num)
710 {
711 struct amdgpu_device *adev = to_amdgpu_device(control);
712 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
713 int i, res;
714 u8 *buf, *pp;
715 u32 g0, g1;
716
717 if (!__is_ras_eeprom_supported(adev))
718 return 0;
719
720 if (num == 0) {
721 DRM_ERROR("will not read 0 records\n");
722 return -EINVAL;
723 } else if (num > control->ras_num_recs) {
724 DRM_ERROR("too many records to read:%d available:%d\n",
725 num, control->ras_num_recs);
726 return -EINVAL;
727 }
728
729 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
730 if (!buf)
731 return -ENOMEM;
732
733 /* Determine how many records to read, from the first record
734 * index, fri, to the end of the table, and from the beginning
735 * of the table, such that the total number of records is
736 * @num, and we handle wrap around when fri > 0 and
737 * fri + num > RAS_MAX_RECORD_COUNT.
738 *
739 * First we compute the index of the last element
740 * which would be fetched from each region,
741 * g0 is in [fri, fri + num - 1], and
742 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
743 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
744 * the last element to fetch, we set g0 to _the number_
745 * of elements to fetch, @num, since we know that the last
746 * indexed to be fetched does not exceed the table.
747 *
748 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
749 * we set g0 to the number of elements to read
750 * until the end of the table, and g1 to the number of
751 * elements to read from the beginning of the table.
752 */
753 g0 = control->ras_fri + num - 1;
754 g1 = g0 % control->ras_max_record_count;
755 if (g0 < control->ras_max_record_count) {
756 g0 = num;
757 g1 = 0;
758 } else {
759 g0 = control->ras_max_record_count - control->ras_fri;
760 g1 += 1;
761 }
762
763 mutex_lock(&control->ras_tbl_mutex);
764 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
765 if (res)
766 goto Out;
767 if (g1) {
768 res = __amdgpu_ras_eeprom_read(control,
769 buf + g0 * RAS_TABLE_RECORD_SIZE,
770 0, g1);
771 if (res)
772 goto Out;
773 }
774
775 res = 0;
776
777 /* Read up everything? Then transform.
778 */
779 pp = buf;
780 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
781 __decode_table_record_from_buf(control, &record[i], pp);
782
783 /* update bad channel bitmap */
784 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
785 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
786 con->update_channel_flag = true;
787 }
788 }
789 Out:
790 kfree(buf);
791 mutex_unlock(&control->ras_tbl_mutex);
792
793 return res;
794 }
795
amdgpu_ras_eeprom_max_record_count(void)796 uint32_t amdgpu_ras_eeprom_max_record_count(void)
797 {
798 return RAS_MAX_RECORD_COUNT;
799 }
800
801 static ssize_t
amdgpu_ras_debugfs_eeprom_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)802 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
803 size_t size, loff_t *pos)
804 {
805 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
806 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
807 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
808 u8 data[50];
809 int res;
810
811 if (!size)
812 return size;
813
814 if (!ras || !control) {
815 res = snprintf(data, sizeof(data), "Not supported\n");
816 } else {
817 res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
818 RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
819 }
820
821 if (*pos >= res)
822 return 0;
823
824 res -= *pos;
825 res = min_t(size_t, res, size);
826
827 if (copy_to_user(buf, &data[*pos], res))
828 return -EFAULT;
829
830 *pos += res;
831
832 return res;
833 }
834
835 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
836 .owner = THIS_MODULE,
837 .read = amdgpu_ras_debugfs_eeprom_size_read,
838 .write = NULL,
839 .llseek = default_llseek,
840 };
841
842 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
843 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
844 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
845 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
846 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
847 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
848
849 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
850 "ignore",
851 "re",
852 "ue",
853 };
854
amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control * control)855 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
856 {
857 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
858 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
859 }
860
amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control * control)861 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
862 {
863 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
864 eeprom_control);
865 struct dentry *de = ras->de_ras_eeprom_table;
866
867 if (de)
868 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
869 }
870
amdgpu_ras_debugfs_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)871 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
872 size_t size, loff_t *pos)
873 {
874 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
875 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
876 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
877 const size_t orig_size = size;
878 int res = -EFAULT;
879 size_t data_len;
880
881 mutex_lock(&control->ras_tbl_mutex);
882
883 /* We want *pos - data_len > 0, which means there's
884 * bytes to be printed from data.
885 */
886 data_len = strlen(tbl_hdr_str);
887 if (*pos < data_len) {
888 data_len -= *pos;
889 data_len = min_t(size_t, data_len, size);
890 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
891 goto Out;
892 buf += data_len;
893 size -= data_len;
894 *pos += data_len;
895 }
896
897 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
898 if (*pos < data_len && size > 0) {
899 u8 data[tbl_hdr_fmt_size + 1];
900 loff_t lpos;
901
902 snprintf(data, sizeof(data), tbl_hdr_fmt,
903 control->tbl_hdr.header,
904 control->tbl_hdr.version,
905 control->tbl_hdr.first_rec_offset,
906 control->tbl_hdr.tbl_size,
907 control->tbl_hdr.checksum);
908
909 data_len -= *pos;
910 data_len = min_t(size_t, data_len, size);
911 lpos = *pos - strlen(tbl_hdr_str);
912 if (copy_to_user(buf, &data[lpos], data_len))
913 goto Out;
914 buf += data_len;
915 size -= data_len;
916 *pos += data_len;
917 }
918
919 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
920 if (*pos < data_len && size > 0) {
921 loff_t lpos;
922
923 data_len -= *pos;
924 data_len = min_t(size_t, data_len, size);
925 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
926 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
927 goto Out;
928 buf += data_len;
929 size -= data_len;
930 *pos += data_len;
931 }
932
933 data_len = amdgpu_ras_debugfs_table_size(control);
934 if (*pos < data_len && size > 0) {
935 u8 dare[RAS_TABLE_RECORD_SIZE];
936 u8 data[rec_hdr_fmt_size + 1];
937 struct eeprom_table_record record;
938 int s, r;
939
940 /* Find the starting record index
941 */
942 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
943 strlen(rec_hdr_str);
944 s = s / rec_hdr_fmt_size;
945 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
946 strlen(rec_hdr_str);
947 r = r % rec_hdr_fmt_size;
948
949 for ( ; size > 0 && s < control->ras_num_recs; s++) {
950 u32 ai = RAS_RI_TO_AI(control, s);
951 /* Read a single record
952 */
953 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
954 if (res)
955 goto Out;
956 __decode_table_record_from_buf(control, &record, dare);
957 snprintf(data, sizeof(data), rec_hdr_fmt,
958 s,
959 RAS_INDEX_TO_OFFSET(control, ai),
960 record_err_type_str[record.err_type],
961 record.bank,
962 record.ts,
963 record.offset,
964 record.mem_channel,
965 record.mcumc_id,
966 record.retired_page);
967
968 data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
969 if (copy_to_user(buf, &data[r], data_len)) {
970 res = -EFAULT;
971 goto Out;
972 }
973 buf += data_len;
974 size -= data_len;
975 *pos += data_len;
976 r = 0;
977 }
978 }
979 res = 0;
980 Out:
981 mutex_unlock(&control->ras_tbl_mutex);
982 return res < 0 ? res : orig_size - size;
983 }
984
985 static ssize_t
amdgpu_ras_debugfs_eeprom_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)986 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
987 size_t size, loff_t *pos)
988 {
989 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
990 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
991 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
992 u8 data[81];
993 int res;
994
995 if (!size)
996 return size;
997
998 if (!ras || !control) {
999 res = snprintf(data, sizeof(data), "Not supported\n");
1000 if (*pos >= res)
1001 return 0;
1002
1003 res -= *pos;
1004 res = min_t(size_t, res, size);
1005
1006 if (copy_to_user(buf, &data[*pos], res))
1007 return -EFAULT;
1008
1009 *pos += res;
1010
1011 return res;
1012 } else {
1013 return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
1014 }
1015 }
1016
1017 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
1018 .owner = THIS_MODULE,
1019 .read = amdgpu_ras_debugfs_eeprom_table_read,
1020 .write = NULL,
1021 .llseek = default_llseek,
1022 };
1023
1024 /**
1025 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
1026 * @control: pointer to control structure
1027 *
1028 * Check the checksum of the stored in EEPROM RAS table.
1029 *
1030 * Return 0 if the checksum is correct,
1031 * positive if it is not correct, and
1032 * -errno on I/O error.
1033 */
__verify_ras_table_checksum(struct amdgpu_ras_eeprom_control * control)1034 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
1035 {
1036 struct amdgpu_device *adev = to_amdgpu_device(control);
1037 int buf_size, res;
1038 u8 csum, *buf, *pp;
1039
1040 buf_size = RAS_TABLE_HEADER_SIZE +
1041 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1042 buf = kzalloc(buf_size, GFP_KERNEL);
1043 if (!buf) {
1044 DRM_ERROR("Out of memory checking RAS table checksum.\n");
1045 return -ENOMEM;
1046 }
1047
1048 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1049 control->i2c_address +
1050 control->ras_header_offset,
1051 buf, buf_size);
1052 if (res < buf_size) {
1053 DRM_ERROR("Partial read for checksum, res:%d\n", res);
1054 /* On partial reads, return -EIO.
1055 */
1056 if (res >= 0)
1057 res = -EIO;
1058 goto Out;
1059 }
1060
1061 csum = 0;
1062 for (pp = buf; pp < buf + buf_size; pp++)
1063 csum += *pp;
1064 Out:
1065 kfree(buf);
1066 return res < 0 ? res : csum;
1067 }
1068
amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control * control,bool * exceed_err_limit)1069 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
1070 bool *exceed_err_limit)
1071 {
1072 struct amdgpu_device *adev = to_amdgpu_device(control);
1073 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1074 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1075 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1076 int res;
1077
1078 *exceed_err_limit = false;
1079
1080 if (!__is_ras_eeprom_supported(adev))
1081 return 0;
1082
1083 /* Verify i2c adapter is initialized */
1084 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1085 return -ENOENT;
1086
1087 if (!__get_eeprom_i2c_addr(adev, control))
1088 return -EINVAL;
1089
1090 control->ras_header_offset = RAS_HDR_START;
1091 control->ras_record_offset = RAS_RECORD_START;
1092 control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1093 mutex_init(&control->ras_tbl_mutex);
1094
1095 /* Read the table header from EEPROM address */
1096 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1097 control->i2c_address + control->ras_header_offset,
1098 buf, RAS_TABLE_HEADER_SIZE);
1099 if (res < RAS_TABLE_HEADER_SIZE) {
1100 DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
1101 return res >= 0 ? -EIO : res;
1102 }
1103
1104 __decode_table_header_from_buf(hdr, buf);
1105
1106 control->ras_num_recs = RAS_NUM_RECS(hdr);
1107 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1108
1109 if (hdr->header == RAS_TABLE_HDR_VAL) {
1110 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
1111 control->ras_num_recs);
1112 res = __verify_ras_table_checksum(control);
1113 if (res)
1114 DRM_ERROR("RAS table incorrect checksum or error:%d\n",
1115 res);
1116
1117 /* Warn if we are at 90% of the threshold or above
1118 */
1119 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold)
1120 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d",
1121 control->ras_num_recs,
1122 ras->bad_page_cnt_threshold);
1123 } else if (hdr->header == RAS_TABLE_HDR_BAD &&
1124 amdgpu_bad_page_threshold != 0) {
1125 res = __verify_ras_table_checksum(control);
1126 if (res)
1127 DRM_ERROR("RAS Table incorrect checksum or error:%d\n",
1128 res);
1129 if (ras->bad_page_cnt_threshold > control->ras_num_recs) {
1130 /* This means that, the threshold was increased since
1131 * the last time the system was booted, and now,
1132 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1133 * so that at least one more record can be saved,
1134 * before the page count threshold is reached.
1135 */
1136 dev_info(adev->dev,
1137 "records:%d threshold:%d, resetting "
1138 "RAS table header signature",
1139 control->ras_num_recs,
1140 ras->bad_page_cnt_threshold);
1141 res = amdgpu_ras_eeprom_correct_header_tag(control,
1142 RAS_TABLE_HDR_VAL);
1143 } else {
1144 dev_err(adev->dev, "RAS records:%d exceed threshold:%d",
1145 control->ras_num_recs, ras->bad_page_cnt_threshold);
1146 if (amdgpu_bad_page_threshold == -2) {
1147 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -2.");
1148 res = 0;
1149 } else {
1150 *exceed_err_limit = true;
1151 dev_err(adev->dev,
1152 "RAS records:%d exceed threshold:%d, "
1153 "GPU will not be initialized. Replace this GPU or increase the threshold",
1154 control->ras_num_recs, ras->bad_page_cnt_threshold);
1155 }
1156 }
1157 } else {
1158 DRM_INFO("Creating a new EEPROM table");
1159
1160 res = amdgpu_ras_eeprom_reset_table(control);
1161 }
1162
1163 return res < 0 ? res : 0;
1164 }
1165