1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  *
23  */
24 #include <linux/kthread.h>
25 #include <linux/wait.h>
26 #include <linux/sched.h>
27 
28 #include <drm/drm_drv.h>
29 
30 #include "amdgpu.h"
31 #include "amdgpu_trace.h"
32 #include "amdgpu_reset.h"
33 
amdgpu_job_timedout(struct drm_sched_job * s_job)34 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
35 {
36 	struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
37 	struct amdgpu_job *job = to_amdgpu_job(s_job);
38 	struct amdgpu_task_info ti;
39 	struct amdgpu_device *adev = ring->adev;
40 	int idx;
41 	int r;
42 
43 	if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
44 		DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
45 			 __func__, s_job->sched->name);
46 
47 		/* Effectively the job is aborted as the device is gone */
48 		return DRM_GPU_SCHED_STAT_ENODEV;
49 	}
50 
51 	memset(&ti, 0, sizeof(struct amdgpu_task_info));
52 	adev->job_hang = true;
53 
54 	if (amdgpu_gpu_recovery &&
55 	    amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
56 		DRM_ERROR("ring %s timeout, but soft recovered\n",
57 			  s_job->sched->name);
58 		goto exit;
59 	}
60 
61 	amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
62 	DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
63 		  job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
64 		  ring->fence_drv.sync_seq);
65 	DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
66 		  ti.process_name, ti.tgid, ti.task_name, ti.pid);
67 
68 	if (amdgpu_device_should_recover_gpu(ring->adev)) {
69 		struct amdgpu_reset_context reset_context;
70 		memset(&reset_context, 0, sizeof(reset_context));
71 
72 		reset_context.method = AMD_RESET_METHOD_NONE;
73 		reset_context.reset_req_dev = adev;
74 		clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
75 
76 		r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
77 		if (r)
78 			DRM_ERROR("GPU Recovery Failed: %d\n", r);
79 	} else {
80 		drm_sched_suspend_timeout(&ring->sched);
81 		if (amdgpu_sriov_vf(adev))
82 			adev->virt.tdr_debug = true;
83 	}
84 
85 exit:
86 	adev->job_hang = false;
87 	drm_dev_exit(idx);
88 	return DRM_GPU_SCHED_STAT_NOMINAL;
89 }
90 
amdgpu_job_alloc(struct amdgpu_device * adev,unsigned num_ibs,struct amdgpu_job ** job,struct amdgpu_vm * vm)91 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
92 		     struct amdgpu_job **job, struct amdgpu_vm *vm)
93 {
94 	if (num_ibs == 0)
95 		return -EINVAL;
96 
97 	*job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL);
98 	if (!*job)
99 		return -ENOMEM;
100 
101 	/*
102 	 * Initialize the scheduler to at least some ring so that we always
103 	 * have a pointer to adev.
104 	 */
105 	(*job)->base.sched = &adev->rings[0]->sched;
106 	(*job)->vm = vm;
107 
108 	amdgpu_sync_create(&(*job)->sync);
109 	amdgpu_sync_create(&(*job)->sched_sync);
110 	(*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
111 	(*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
112 
113 	return 0;
114 }
115 
amdgpu_job_alloc_with_ib(struct amdgpu_device * adev,unsigned size,enum amdgpu_ib_pool_type pool_type,struct amdgpu_job ** job)116 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
117 		enum amdgpu_ib_pool_type pool_type,
118 		struct amdgpu_job **job)
119 {
120 	int r;
121 
122 	r = amdgpu_job_alloc(adev, 1, job, NULL);
123 	if (r)
124 		return r;
125 
126 	(*job)->num_ibs = 1;
127 	r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
128 	if (r)
129 		kfree(*job);
130 
131 	return r;
132 }
133 
amdgpu_job_set_resources(struct amdgpu_job * job,struct amdgpu_bo * gds,struct amdgpu_bo * gws,struct amdgpu_bo * oa)134 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
135 			      struct amdgpu_bo *gws, struct amdgpu_bo *oa)
136 {
137 	if (gds) {
138 		job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
139 		job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
140 	}
141 	if (gws) {
142 		job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
143 		job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
144 	}
145 	if (oa) {
146 		job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
147 		job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
148 	}
149 }
150 
amdgpu_job_free_resources(struct amdgpu_job * job)151 void amdgpu_job_free_resources(struct amdgpu_job *job)
152 {
153 	struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
154 	struct dma_fence *f;
155 	unsigned i;
156 
157 	/* Check if any fences where initialized */
158 	if (job->base.s_fence && job->base.s_fence->finished.ops)
159 		f = &job->base.s_fence->finished;
160 	else if (job->hw_fence.ops)
161 		f = &job->hw_fence;
162 	else
163 		f = NULL;
164 
165 	for (i = 0; i < job->num_ibs; ++i)
166 		amdgpu_ib_free(ring->adev, &job->ibs[i], f);
167 }
168 
amdgpu_job_free_cb(struct drm_sched_job * s_job)169 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
170 {
171 	struct amdgpu_job *job = to_amdgpu_job(s_job);
172 
173 	drm_sched_job_cleanup(s_job);
174 
175 	amdgpu_sync_free(&job->sync);
176 	amdgpu_sync_free(&job->sched_sync);
177 
178 	/* only put the hw fence if has embedded fence */
179 	if (!job->hw_fence.ops)
180 		kfree(job);
181 	else
182 		dma_fence_put(&job->hw_fence);
183 }
184 
amdgpu_job_set_gang_leader(struct amdgpu_job * job,struct amdgpu_job * leader)185 void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
186 				struct amdgpu_job *leader)
187 {
188 	struct dma_fence *fence = &leader->base.s_fence->scheduled;
189 
190 	WARN_ON(job->gang_submit);
191 
192 	/*
193 	 * Don't add a reference when we are the gang leader to avoid circle
194 	 * dependency.
195 	 */
196 	if (job != leader)
197 		dma_fence_get(fence);
198 	job->gang_submit = fence;
199 }
200 
amdgpu_job_free(struct amdgpu_job * job)201 void amdgpu_job_free(struct amdgpu_job *job)
202 {
203 	amdgpu_job_free_resources(job);
204 	amdgpu_sync_free(&job->sync);
205 	amdgpu_sync_free(&job->sched_sync);
206 	if (job->gang_submit != &job->base.s_fence->scheduled)
207 		dma_fence_put(job->gang_submit);
208 
209 	if (!job->hw_fence.ops)
210 		kfree(job);
211 	else
212 		dma_fence_put(&job->hw_fence);
213 }
214 
amdgpu_job_submit(struct amdgpu_job * job,struct drm_sched_entity * entity,void * owner,struct dma_fence ** f)215 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
216 		      void *owner, struct dma_fence **f)
217 {
218 	int r;
219 
220 	if (!f)
221 		return -EINVAL;
222 
223 	r = drm_sched_job_init(&job->base, entity, owner);
224 	if (r)
225 		return r;
226 
227 	drm_sched_job_arm(&job->base);
228 
229 	*f = dma_fence_get(&job->base.s_fence->finished);
230 	amdgpu_job_free_resources(job);
231 	drm_sched_entity_push_job(&job->base);
232 
233 	return 0;
234 }
235 
amdgpu_job_submit_direct(struct amdgpu_job * job,struct amdgpu_ring * ring,struct dma_fence ** fence)236 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
237 			     struct dma_fence **fence)
238 {
239 	int r;
240 
241 	job->base.sched = &ring->sched;
242 	r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence);
243 
244 	if (r)
245 		return r;
246 
247 	amdgpu_job_free(job);
248 	return 0;
249 }
250 
amdgpu_job_dependency(struct drm_sched_job * sched_job,struct drm_sched_entity * s_entity)251 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
252 					       struct drm_sched_entity *s_entity)
253 {
254 	struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
255 	struct amdgpu_job *job = to_amdgpu_job(sched_job);
256 	struct amdgpu_vm *vm = job->vm;
257 	struct dma_fence *fence;
258 	int r;
259 
260 	fence = amdgpu_sync_get_fence(&job->sync);
261 	if (fence && drm_sched_dependency_optimized(fence, s_entity)) {
262 		r = amdgpu_sync_fence(&job->sched_sync, fence);
263 		if (r)
264 			DRM_ERROR("Error adding fence (%d)\n", r);
265 	}
266 
267 	if (!fence && job->gang_submit)
268 		fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
269 
270 	while (fence == NULL && vm && !job->vmid) {
271 		r = amdgpu_vmid_grab(vm, ring, &job->sync,
272 				     &job->base.s_fence->finished,
273 				     job);
274 		if (r)
275 			DRM_ERROR("Error getting VM ID (%d)\n", r);
276 
277 		fence = amdgpu_sync_get_fence(&job->sync);
278 	}
279 
280 	return fence;
281 }
282 
amdgpu_job_run(struct drm_sched_job * sched_job)283 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
284 {
285 	struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
286 	struct amdgpu_device *adev = ring->adev;
287 	struct dma_fence *fence = NULL, *finished;
288 	struct amdgpu_job *job;
289 	int r = 0;
290 
291 	job = to_amdgpu_job(sched_job);
292 	finished = &job->base.s_fence->finished;
293 
294 	BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
295 
296 	trace_amdgpu_sched_run_job(job);
297 
298 	/* Skip job if VRAM is lost and never resubmit gangs */
299 	if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter) ||
300 	    (job->job_run_counter && job->gang_submit))
301 		dma_fence_set_error(finished, -ECANCELED);
302 
303 	if (finished->error < 0) {
304 		DRM_INFO("Skip scheduling IBs!\n");
305 	} else {
306 		r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
307 				       &fence);
308 		if (r)
309 			DRM_ERROR("Error scheduling IBs (%d)\n", r);
310 	}
311 
312 	job->job_run_counter++;
313 	amdgpu_job_free_resources(job);
314 
315 	fence = r ? ERR_PTR(r) : fence;
316 	return fence;
317 }
318 
319 #define to_drm_sched_job(sched_job)		\
320 		container_of((sched_job), struct drm_sched_job, queue_node)
321 
amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler * sched)322 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
323 {
324 	struct drm_sched_job *s_job;
325 	struct drm_sched_entity *s_entity = NULL;
326 	int i;
327 
328 	/* Signal all jobs not yet scheduled */
329 	for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
330 		struct drm_sched_rq *rq = &sched->sched_rq[i];
331 		spin_lock(&rq->lock);
332 		list_for_each_entry(s_entity, &rq->entities, list) {
333 			while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
334 				struct drm_sched_fence *s_fence = s_job->s_fence;
335 
336 				dma_fence_signal(&s_fence->scheduled);
337 				dma_fence_set_error(&s_fence->finished, -EHWPOISON);
338 				dma_fence_signal(&s_fence->finished);
339 			}
340 		}
341 		spin_unlock(&rq->lock);
342 	}
343 
344 	/* Signal all jobs already scheduled to HW */
345 	list_for_each_entry(s_job, &sched->pending_list, list) {
346 		struct drm_sched_fence *s_fence = s_job->s_fence;
347 
348 		dma_fence_set_error(&s_fence->finished, -EHWPOISON);
349 		dma_fence_signal(&s_fence->finished);
350 	}
351 }
352 
353 const struct drm_sched_backend_ops amdgpu_sched_ops = {
354 	.dependency = amdgpu_job_dependency,
355 	.run_job = amdgpu_job_run,
356 	.timedout_job = amdgpu_job_timedout,
357 	.free_job = amdgpu_job_free_cb
358 };
359