1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28 
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_crtc.h"
33 #include "amdgpu_dm_plane.h"
34 #include "amdgpu_dm_trace.h"
35 #include "amdgpu_dm_debugfs.h"
36 
dm_crtc_handle_vblank(struct amdgpu_crtc * acrtc)37 void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
38 {
39 	struct drm_crtc *crtc = &acrtc->base;
40 	struct drm_device *dev = crtc->dev;
41 	unsigned long flags;
42 
43 	drm_crtc_handle_vblank(crtc);
44 
45 	spin_lock_irqsave(&dev->event_lock, flags);
46 
47 	/* Send completion event for cursor-only commits */
48 	if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
49 		drm_crtc_send_vblank_event(crtc, acrtc->event);
50 		drm_crtc_vblank_put(crtc);
51 		acrtc->event = NULL;
52 	}
53 
54 	spin_unlock_irqrestore(&dev->event_lock, flags);
55 }
56 
modeset_required(struct drm_crtc_state * crtc_state,struct dc_stream_state * new_stream,struct dc_stream_state * old_stream)57 bool modeset_required(struct drm_crtc_state *crtc_state,
58 			     struct dc_stream_state *new_stream,
59 			     struct dc_stream_state *old_stream)
60 {
61 	return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
62 }
63 
amdgpu_dm_vrr_active_irq(struct amdgpu_crtc * acrtc)64 bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
65 
66 {
67 	return acrtc->dm_irq_params.freesync_config.state ==
68 		       VRR_STATE_ACTIVE_VARIABLE ||
69 	       acrtc->dm_irq_params.freesync_config.state ==
70 		       VRR_STATE_ACTIVE_FIXED;
71 }
72 
dm_set_vupdate_irq(struct drm_crtc * crtc,bool enable)73 int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
74 {
75 	enum dc_irq_source irq_source;
76 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
77 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
78 	int rc;
79 
80 	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
81 
82 	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
83 
84 	DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
85 		      acrtc->crtc_id, enable ? "en" : "dis", rc);
86 	return rc;
87 }
88 
amdgpu_dm_vrr_active(struct dm_crtc_state * dm_state)89 bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
90 {
91 	return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
92 	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
93 }
94 
vblank_control_worker(struct work_struct * work)95 static void vblank_control_worker(struct work_struct *work)
96 {
97 	struct vblank_control_work *vblank_work =
98 		container_of(work, struct vblank_control_work, work);
99 	struct amdgpu_display_manager *dm = vblank_work->dm;
100 
101 	mutex_lock(&dm->dc_lock);
102 
103 	if (vblank_work->enable)
104 		dm->active_vblank_irq_count++;
105 	else if (dm->active_vblank_irq_count)
106 		dm->active_vblank_irq_count--;
107 
108 	dc_allow_idle_optimizations(
109 		dm->dc, dm->active_vblank_irq_count == 0 ? true : false);
110 
111 	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
112 
113 	/*
114 	 * Control PSR based on vblank requirements from OS
115 	 *
116 	 * If panel supports PSR SU, there's no need to disable PSR when OS is
117 	 * submitting fast atomic commits (we infer this by whether the OS
118 	 * requests vblank events). Fast atomic commits will simply trigger a
119 	 * full-frame-update (FFU); a specific case of selective-update (SU)
120 	 * where the SU region is the full hactive*vactive region. See
121 	 * fill_dc_dirty_rects().
122 	 */
123 	if (vblank_work->stream && vblank_work->stream->link) {
124 		if (vblank_work->enable) {
125 			if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
126 			    vblank_work->stream->link->psr_settings.psr_allow_active)
127 				amdgpu_dm_psr_disable(vblank_work->stream);
128 		} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
129 			   !vblank_work->stream->link->psr_settings.psr_allow_active &&
130 			   vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
131 			amdgpu_dm_psr_enable(vblank_work->stream);
132 		}
133 	}
134 
135 	mutex_unlock(&dm->dc_lock);
136 
137 	dc_stream_release(vblank_work->stream);
138 
139 	kfree(vblank_work);
140 }
141 
dm_set_vblank(struct drm_crtc * crtc,bool enable)142 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
143 {
144 	enum dc_irq_source irq_source;
145 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
146 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
147 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
148 	struct amdgpu_display_manager *dm = &adev->dm;
149 	struct vblank_control_work *work;
150 	int rc = 0;
151 
152 	if (enable) {
153 		/* vblank irq on -> Only need vupdate irq in vrr mode */
154 		if (amdgpu_dm_vrr_active(acrtc_state))
155 			rc = dm_set_vupdate_irq(crtc, true);
156 	} else {
157 		/* vblank irq off -> vupdate irq off */
158 		rc = dm_set_vupdate_irq(crtc, false);
159 	}
160 
161 	if (rc)
162 		return rc;
163 
164 	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
165 
166 	if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
167 		return -EBUSY;
168 
169 	if (amdgpu_in_reset(adev))
170 		return 0;
171 
172 	if (dm->vblank_control_workqueue) {
173 		work = kzalloc(sizeof(*work), GFP_ATOMIC);
174 		if (!work)
175 			return -ENOMEM;
176 
177 		INIT_WORK(&work->work, vblank_control_worker);
178 		work->dm = dm;
179 		work->acrtc = acrtc;
180 		work->enable = enable;
181 
182 		if (acrtc_state->stream) {
183 			dc_stream_retain(acrtc_state->stream);
184 			work->stream = acrtc_state->stream;
185 		}
186 
187 		queue_work(dm->vblank_control_workqueue, &work->work);
188 	}
189 
190 	return 0;
191 }
192 
dm_enable_vblank(struct drm_crtc * crtc)193 int dm_enable_vblank(struct drm_crtc *crtc)
194 {
195 	return dm_set_vblank(crtc, true);
196 }
197 
dm_disable_vblank(struct drm_crtc * crtc)198 void dm_disable_vblank(struct drm_crtc *crtc)
199 {
200 	dm_set_vblank(crtc, false);
201 }
202 
dm_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)203 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
204 				  struct drm_crtc_state *state)
205 {
206 	struct dm_crtc_state *cur = to_dm_crtc_state(state);
207 
208 	/* TODO Destroy dc_stream objects are stream object is flattened */
209 	if (cur->stream)
210 		dc_stream_release(cur->stream);
211 
212 
213 	__drm_atomic_helper_crtc_destroy_state(state);
214 
215 
216 	kfree(state);
217 }
218 
dm_crtc_duplicate_state(struct drm_crtc * crtc)219 static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
220 {
221 	struct dm_crtc_state *state, *cur;
222 
223 	cur = to_dm_crtc_state(crtc->state);
224 
225 	if (WARN_ON(!crtc->state))
226 		return NULL;
227 
228 	state = kzalloc(sizeof(*state), GFP_KERNEL);
229 	if (!state)
230 		return NULL;
231 
232 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
233 
234 	if (cur->stream) {
235 		state->stream = cur->stream;
236 		dc_stream_retain(state->stream);
237 	}
238 
239 	state->active_planes = cur->active_planes;
240 	state->vrr_infopacket = cur->vrr_infopacket;
241 	state->abm_level = cur->abm_level;
242 	state->vrr_supported = cur->vrr_supported;
243 	state->freesync_config = cur->freesync_config;
244 	state->cm_has_degamma = cur->cm_has_degamma;
245 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
246 	state->crc_skip_count = cur->crc_skip_count;
247 	state->mpo_requested = cur->mpo_requested;
248 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
249 
250 	return &state->base;
251 }
252 
amdgpu_dm_crtc_destroy(struct drm_crtc * crtc)253 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
254 {
255 	drm_crtc_cleanup(crtc);
256 	kfree(crtc);
257 }
258 
dm_crtc_reset_state(struct drm_crtc * crtc)259 static void dm_crtc_reset_state(struct drm_crtc *crtc)
260 {
261 	struct dm_crtc_state *state;
262 
263 	if (crtc->state)
264 		dm_crtc_destroy_state(crtc, crtc->state);
265 
266 	state = kzalloc(sizeof(*state), GFP_KERNEL);
267 	if (WARN_ON(!state))
268 		return;
269 
270 	__drm_atomic_helper_crtc_reset(crtc, &state->base);
271 }
272 
273 #ifdef CONFIG_DEBUG_FS
amdgpu_dm_crtc_late_register(struct drm_crtc * crtc)274 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
275 {
276 	crtc_debugfs_init(crtc);
277 
278 	return 0;
279 }
280 #endif
281 
282 /* Implemented only the options currently available for the driver */
283 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
284 	.reset = dm_crtc_reset_state,
285 	.destroy = amdgpu_dm_crtc_destroy,
286 	.set_config = drm_atomic_helper_set_config,
287 	.page_flip = drm_atomic_helper_page_flip,
288 	.atomic_duplicate_state = dm_crtc_duplicate_state,
289 	.atomic_destroy_state = dm_crtc_destroy_state,
290 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
291 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
292 	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
293 	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
294 	.enable_vblank = dm_enable_vblank,
295 	.disable_vblank = dm_disable_vblank,
296 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
297 #if defined(CONFIG_DEBUG_FS)
298 	.late_register = amdgpu_dm_crtc_late_register,
299 #endif
300 };
301 
dm_crtc_helper_disable(struct drm_crtc * crtc)302 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
303 {
304 }
305 
count_crtc_active_planes(struct drm_crtc_state * new_crtc_state)306 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
307 {
308 	struct drm_atomic_state *state = new_crtc_state->state;
309 	struct drm_plane *plane;
310 	int num_active = 0;
311 
312 	drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
313 		struct drm_plane_state *new_plane_state;
314 
315 		/* Cursor planes are "fake". */
316 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
317 			continue;
318 
319 		new_plane_state = drm_atomic_get_new_plane_state(state, plane);
320 
321 		if (!new_plane_state) {
322 			/*
323 			 * The plane is enable on the CRTC and hasn't changed
324 			 * state. This means that it previously passed
325 			 * validation and is therefore enabled.
326 			 */
327 			num_active += 1;
328 			continue;
329 		}
330 
331 		/* We need a framebuffer to be considered enabled. */
332 		num_active += (new_plane_state->fb != NULL);
333 	}
334 
335 	return num_active;
336 }
337 
dm_update_crtc_active_planes(struct drm_crtc * crtc,struct drm_crtc_state * new_crtc_state)338 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
339 					 struct drm_crtc_state *new_crtc_state)
340 {
341 	struct dm_crtc_state *dm_new_crtc_state =
342 		to_dm_crtc_state(new_crtc_state);
343 
344 	dm_new_crtc_state->active_planes = 0;
345 
346 	if (!dm_new_crtc_state->stream)
347 		return;
348 
349 	dm_new_crtc_state->active_planes =
350 		count_crtc_active_planes(new_crtc_state);
351 }
352 
dm_crtc_helper_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)353 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
354 				      const struct drm_display_mode *mode,
355 				      struct drm_display_mode *adjusted_mode)
356 {
357 	return true;
358 }
359 
dm_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)360 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
361 				      struct drm_atomic_state *state)
362 {
363 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
364 										crtc);
365 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
366 	struct dc *dc = adev->dm.dc;
367 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
368 	int ret = -EINVAL;
369 
370 	trace_amdgpu_dm_crtc_atomic_check(crtc_state);
371 
372 	dm_update_crtc_active_planes(crtc, crtc_state);
373 
374 	if (WARN_ON(unlikely(!dm_crtc_state->stream &&
375 			modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
376 		return ret;
377 	}
378 
379 	/*
380 	 * We require the primary plane to be enabled whenever the CRTC is, otherwise
381 	 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
382 	 * planes are disabled, which is not supported by the hardware. And there is legacy
383 	 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
384 	 */
385 	if (crtc_state->enable &&
386 		!(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
387 		DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
388 		return -EINVAL;
389 	}
390 
391 	/* In some use cases, like reset, no stream is attached */
392 	if (!dm_crtc_state->stream)
393 		return 0;
394 
395 	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
396 		return 0;
397 
398 	DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
399 	return ret;
400 }
401 
402 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
403 	.disable = dm_crtc_helper_disable,
404 	.atomic_check = dm_crtc_helper_atomic_check,
405 	.mode_fixup = dm_crtc_helper_mode_fixup,
406 	.get_scanout_position = amdgpu_crtc_get_scanout_position,
407 };
408 
amdgpu_dm_crtc_init(struct amdgpu_display_manager * dm,struct drm_plane * plane,uint32_t crtc_index)409 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
410 			       struct drm_plane *plane,
411 			       uint32_t crtc_index)
412 {
413 	struct amdgpu_crtc *acrtc = NULL;
414 	struct drm_plane *cursor_plane;
415 	bool is_dcn;
416 	int res = -ENOMEM;
417 
418 	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
419 	if (!cursor_plane)
420 		goto fail;
421 
422 	cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
423 	res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
424 
425 	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
426 	if (!acrtc)
427 		goto fail;
428 
429 	res = drm_crtc_init_with_planes(
430 			dm->ddev,
431 			&acrtc->base,
432 			plane,
433 			cursor_plane,
434 			&amdgpu_dm_crtc_funcs, NULL);
435 
436 	if (res)
437 		goto fail;
438 
439 	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
440 
441 	/* Create (reset) the plane state */
442 	if (acrtc->base.funcs->reset)
443 		acrtc->base.funcs->reset(&acrtc->base);
444 
445 	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
446 	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
447 
448 	acrtc->crtc_id = crtc_index;
449 	acrtc->base.enabled = false;
450 	acrtc->otg_inst = -1;
451 
452 	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
453 
454 	/* Don't enable DRM CRTC degamma property for DCE since it doesn't
455 	 * support programmable degamma anywhere.
456 	 */
457 	is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
458 	drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
459 				   true, MAX_COLOR_LUT_ENTRIES);
460 
461 	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
462 
463 	return 0;
464 
465 fail:
466 	kfree(acrtc);
467 	kfree(cursor_plane);
468 	return res;
469 }
470 
471