1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include <linux/firmware.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/debugfs.h>
31 #include <drm/drm_drv.h>
32
33 #include "amdgpu.h"
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vcn.h"
36 #include "soc15d.h"
37
38 /* Firmware Names */
39 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
40 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
41 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
42 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
43 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
44 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
45 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
46 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
47 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
48 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
49 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
50 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
51 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin"
52 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
53 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
54 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
55 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
56 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin"
57 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin"
58 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin"
59
60 MODULE_FIRMWARE(FIRMWARE_RAVEN);
61 MODULE_FIRMWARE(FIRMWARE_PICASSO);
62 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
63 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
64 MODULE_FIRMWARE(FIRMWARE_RENOIR);
65 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
66 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
67 MODULE_FIRMWARE(FIRMWARE_NAVI10);
68 MODULE_FIRMWARE(FIRMWARE_NAVI14);
69 MODULE_FIRMWARE(FIRMWARE_NAVI12);
70 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
71 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
72 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
73 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
74 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
75 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
76 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
77 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
78 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
80
81 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
82
amdgpu_vcn_sw_init(struct amdgpu_device * adev)83 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
84 {
85 unsigned long bo_size;
86 const char *fw_name;
87 const struct common_firmware_header *hdr;
88 unsigned char fw_check;
89 unsigned int fw_shared_size, log_offset;
90 int i, r;
91
92 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
93 mutex_init(&adev->vcn.vcn_pg_lock);
94 mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
95 atomic_set(&adev->vcn.total_submission_cnt, 0);
96 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
97 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
98
99 switch (adev->ip_versions[UVD_HWIP][0]) {
100 case IP_VERSION(1, 0, 0):
101 case IP_VERSION(1, 0, 1):
102 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
103 fw_name = FIRMWARE_RAVEN2;
104 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
105 fw_name = FIRMWARE_PICASSO;
106 else
107 fw_name = FIRMWARE_RAVEN;
108 break;
109 case IP_VERSION(2, 5, 0):
110 fw_name = FIRMWARE_ARCTURUS;
111 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
112 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
113 adev->vcn.indirect_sram = true;
114 break;
115 case IP_VERSION(2, 2, 0):
116 if (adev->apu_flags & AMD_APU_IS_RENOIR)
117 fw_name = FIRMWARE_RENOIR;
118 else
119 fw_name = FIRMWARE_GREEN_SARDINE;
120
121 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
122 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
123 adev->vcn.indirect_sram = true;
124 break;
125 case IP_VERSION(2, 6, 0):
126 fw_name = FIRMWARE_ALDEBARAN;
127 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
128 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
129 adev->vcn.indirect_sram = true;
130 break;
131 case IP_VERSION(2, 0, 0):
132 fw_name = FIRMWARE_NAVI10;
133 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
134 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
135 adev->vcn.indirect_sram = true;
136 break;
137 case IP_VERSION(2, 0, 2):
138 if (adev->asic_type == CHIP_NAVI12)
139 fw_name = FIRMWARE_NAVI12;
140 else
141 fw_name = FIRMWARE_NAVI14;
142 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
143 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
144 adev->vcn.indirect_sram = true;
145 break;
146 case IP_VERSION(3, 0, 0):
147 case IP_VERSION(3, 0, 64):
148 case IP_VERSION(3, 0, 192):
149 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
150 fw_name = FIRMWARE_SIENNA_CICHLID;
151 else
152 fw_name = FIRMWARE_NAVY_FLOUNDER;
153 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
154 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
155 adev->vcn.indirect_sram = true;
156 break;
157 case IP_VERSION(3, 0, 2):
158 fw_name = FIRMWARE_VANGOGH;
159 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
160 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
161 adev->vcn.indirect_sram = true;
162 break;
163 case IP_VERSION(3, 0, 16):
164 fw_name = FIRMWARE_DIMGREY_CAVEFISH;
165 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
166 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
167 adev->vcn.indirect_sram = true;
168 break;
169 case IP_VERSION(3, 0, 33):
170 fw_name = FIRMWARE_BEIGE_GOBY;
171 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
172 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
173 adev->vcn.indirect_sram = true;
174 break;
175 case IP_VERSION(3, 1, 1):
176 fw_name = FIRMWARE_YELLOW_CARP;
177 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
178 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
179 adev->vcn.indirect_sram = true;
180 break;
181 case IP_VERSION(3, 1, 2):
182 fw_name = FIRMWARE_VCN_3_1_2;
183 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
184 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
185 adev->vcn.indirect_sram = true;
186 break;
187 case IP_VERSION(4, 0, 0):
188 fw_name = FIRMWARE_VCN4_0_0;
189 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
190 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
191 adev->vcn.indirect_sram = true;
192 break;
193 case IP_VERSION(4, 0, 2):
194 fw_name = FIRMWARE_VCN4_0_2;
195 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
196 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
197 adev->vcn.indirect_sram = true;
198 break;
199 case IP_VERSION(4, 0, 4):
200 fw_name = FIRMWARE_VCN4_0_4;
201 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
202 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
203 adev->vcn.indirect_sram = true;
204 break;
205 default:
206 return -EINVAL;
207 }
208
209 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
210 if (r) {
211 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
212 fw_name);
213 return r;
214 }
215
216 r = amdgpu_ucode_validate(adev->vcn.fw);
217 if (r) {
218 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
219 fw_name);
220 release_firmware(adev->vcn.fw);
221 adev->vcn.fw = NULL;
222 return r;
223 }
224
225 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
226 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
227
228 /* Bit 20-23, it is encode major and non-zero for new naming convention.
229 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
230 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
231 * is zero in old naming convention, this field is always zero so far.
232 * These four bits are used to tell which naming convention is present.
233 */
234 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
235 if (fw_check) {
236 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
237
238 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
239 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
240 enc_major = fw_check;
241 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
242 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
243 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
244 enc_major, enc_minor, dec_ver, vep, fw_rev);
245 } else {
246 unsigned int version_major, version_minor, family_id;
247
248 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
249 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
250 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
251 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
252 version_major, version_minor, family_id);
253 }
254
255 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
256 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
257 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
258
259 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){
260 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
261 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
262 } else {
263 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
264 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
265 }
266
267 bo_size += fw_shared_size;
268
269 if (amdgpu_vcnfw_log)
270 bo_size += AMDGPU_VCNFW_LOG_SIZE;
271
272 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
273 if (adev->vcn.harvest_config & (1 << i))
274 continue;
275
276 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
277 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
278 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
279 if (r) {
280 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
281 return r;
282 }
283
284 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
285 bo_size - fw_shared_size;
286 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
287 bo_size - fw_shared_size;
288
289 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
290
291 if (amdgpu_vcnfw_log) {
292 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
293 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
294 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
295 }
296
297 if (adev->vcn.indirect_sram) {
298 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
299 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
300 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
301 if (r) {
302 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
303 return r;
304 }
305 }
306 }
307
308 return 0;
309 }
310
amdgpu_vcn_sw_fini(struct amdgpu_device * adev)311 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
312 {
313 int i, j;
314
315 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
316 if (adev->vcn.harvest_config & (1 << j))
317 continue;
318
319 if (adev->vcn.indirect_sram) {
320 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
321 &adev->vcn.inst[j].dpg_sram_gpu_addr,
322 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
323 }
324 kvfree(adev->vcn.inst[j].saved_bo);
325
326 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
327 &adev->vcn.inst[j].gpu_addr,
328 (void **)&adev->vcn.inst[j].cpu_addr);
329
330 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
331
332 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
333 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
334 }
335
336 release_firmware(adev->vcn.fw);
337 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
338 mutex_destroy(&adev->vcn.vcn_pg_lock);
339
340 return 0;
341 }
342
343 /* from vcn4 and above, only unified queue is used */
amdgpu_vcn_using_unified_queue(struct amdgpu_ring * ring)344 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
345 {
346 struct amdgpu_device *adev = ring->adev;
347 bool ret = false;
348
349 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
350 ret = true;
351
352 return ret;
353 }
354
amdgpu_vcn_is_disabled_vcn(struct amdgpu_device * adev,enum vcn_ring_type type,uint32_t vcn_instance)355 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
356 {
357 bool ret = false;
358 int vcn_config = adev->vcn.vcn_config[vcn_instance];
359
360 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
361 ret = true;
362 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) {
363 ret = true;
364 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
365 ret = true;
366 }
367
368 return ret;
369 }
370
amdgpu_vcn_suspend(struct amdgpu_device * adev)371 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
372 {
373 unsigned size;
374 void *ptr;
375 int i, idx;
376
377 cancel_delayed_work_sync(&adev->vcn.idle_work);
378
379 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
380 if (adev->vcn.harvest_config & (1 << i))
381 continue;
382 if (adev->vcn.inst[i].vcpu_bo == NULL)
383 return 0;
384
385 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
386 ptr = adev->vcn.inst[i].cpu_addr;
387
388 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
389 if (!adev->vcn.inst[i].saved_bo)
390 return -ENOMEM;
391
392 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
393 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
394 drm_dev_exit(idx);
395 }
396 }
397 return 0;
398 }
399
amdgpu_vcn_resume(struct amdgpu_device * adev)400 int amdgpu_vcn_resume(struct amdgpu_device *adev)
401 {
402 unsigned size;
403 void *ptr;
404 int i, idx;
405
406 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
407 if (adev->vcn.harvest_config & (1 << i))
408 continue;
409 if (adev->vcn.inst[i].vcpu_bo == NULL)
410 return -EINVAL;
411
412 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
413 ptr = adev->vcn.inst[i].cpu_addr;
414
415 if (adev->vcn.inst[i].saved_bo != NULL) {
416 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
417 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
418 drm_dev_exit(idx);
419 }
420 kvfree(adev->vcn.inst[i].saved_bo);
421 adev->vcn.inst[i].saved_bo = NULL;
422 } else {
423 const struct common_firmware_header *hdr;
424 unsigned offset;
425
426 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
427 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
428 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
429 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
430 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
431 le32_to_cpu(hdr->ucode_size_bytes));
432 drm_dev_exit(idx);
433 }
434 size -= le32_to_cpu(hdr->ucode_size_bytes);
435 ptr += le32_to_cpu(hdr->ucode_size_bytes);
436 }
437 memset_io(ptr, 0, size);
438 }
439 }
440 return 0;
441 }
442
amdgpu_vcn_idle_work_handler(struct work_struct * work)443 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
444 {
445 struct amdgpu_device *adev =
446 container_of(work, struct amdgpu_device, vcn.idle_work.work);
447 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
448 unsigned int i, j;
449 int r = 0;
450
451 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
452 if (adev->vcn.harvest_config & (1 << j))
453 continue;
454
455 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
456 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
457 }
458
459 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
460 struct dpg_pause_state new_state;
461
462 if (fence[j] ||
463 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
464 new_state.fw_based = VCN_DPG_STATE__PAUSE;
465 else
466 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
467
468 adev->vcn.pause_dpg_mode(adev, j, &new_state);
469 }
470
471 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
472 fences += fence[j];
473 }
474
475 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
476 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
477 AMD_PG_STATE_GATE);
478 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
479 false);
480 if (r)
481 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
482 } else {
483 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
484 }
485 }
486
amdgpu_vcn_ring_begin_use(struct amdgpu_ring * ring)487 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
488 {
489 struct amdgpu_device *adev = ring->adev;
490 int r = 0;
491
492 atomic_inc(&adev->vcn.total_submission_cnt);
493
494 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
495 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
496 true);
497 if (r)
498 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
499 }
500
501 mutex_lock(&adev->vcn.vcn_pg_lock);
502 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
503 AMD_PG_STATE_UNGATE);
504
505 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
506 struct dpg_pause_state new_state;
507
508 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
509 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
510 new_state.fw_based = VCN_DPG_STATE__PAUSE;
511 } else {
512 unsigned int fences = 0;
513 unsigned int i;
514
515 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
516 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
517
518 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
519 new_state.fw_based = VCN_DPG_STATE__PAUSE;
520 else
521 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
522 }
523
524 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
525 }
526 mutex_unlock(&adev->vcn.vcn_pg_lock);
527 }
528
amdgpu_vcn_ring_end_use(struct amdgpu_ring * ring)529 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
530 {
531 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
532 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
533 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
534
535 atomic_dec(&ring->adev->vcn.total_submission_cnt);
536
537 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
538 }
539
amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring * ring)540 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
541 {
542 struct amdgpu_device *adev = ring->adev;
543 uint32_t tmp = 0;
544 unsigned i;
545 int r;
546
547 /* VCN in SRIOV does not support direct register read/write */
548 if (amdgpu_sriov_vf(adev))
549 return 0;
550
551 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
552 r = amdgpu_ring_alloc(ring, 3);
553 if (r)
554 return r;
555 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
556 amdgpu_ring_write(ring, 0xDEADBEEF);
557 amdgpu_ring_commit(ring);
558 for (i = 0; i < adev->usec_timeout; i++) {
559 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
560 if (tmp == 0xDEADBEEF)
561 break;
562 udelay(1);
563 }
564
565 if (i >= adev->usec_timeout)
566 r = -ETIMEDOUT;
567
568 return r;
569 }
570
amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring * ring)571 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
572 {
573 struct amdgpu_device *adev = ring->adev;
574 uint32_t rptr;
575 unsigned int i;
576 int r;
577
578 if (amdgpu_sriov_vf(adev))
579 return 0;
580
581 r = amdgpu_ring_alloc(ring, 16);
582 if (r)
583 return r;
584
585 rptr = amdgpu_ring_get_rptr(ring);
586
587 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
588 amdgpu_ring_commit(ring);
589
590 for (i = 0; i < adev->usec_timeout; i++) {
591 if (amdgpu_ring_get_rptr(ring) != rptr)
592 break;
593 udelay(1);
594 }
595
596 if (i >= adev->usec_timeout)
597 r = -ETIMEDOUT;
598
599 return r;
600 }
601
amdgpu_vcn_dec_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)602 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
603 struct amdgpu_ib *ib_msg,
604 struct dma_fence **fence)
605 {
606 struct amdgpu_device *adev = ring->adev;
607 struct dma_fence *f = NULL;
608 struct amdgpu_job *job;
609 struct amdgpu_ib *ib;
610 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
611 int i, r;
612
613 r = amdgpu_job_alloc_with_ib(adev, 64,
614 AMDGPU_IB_POOL_DIRECT, &job);
615 if (r)
616 goto err;
617
618 ib = &job->ibs[0];
619 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
620 ib->ptr[1] = addr;
621 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
622 ib->ptr[3] = addr >> 32;
623 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
624 ib->ptr[5] = 0;
625 for (i = 6; i < 16; i += 2) {
626 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
627 ib->ptr[i+1] = 0;
628 }
629 ib->length_dw = 16;
630
631 r = amdgpu_job_submit_direct(job, ring, &f);
632 if (r)
633 goto err_free;
634
635 amdgpu_ib_free(adev, ib_msg, f);
636
637 if (fence)
638 *fence = dma_fence_get(f);
639 dma_fence_put(f);
640
641 return 0;
642
643 err_free:
644 amdgpu_job_free(job);
645 err:
646 amdgpu_ib_free(adev, ib_msg, f);
647 return r;
648 }
649
amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)650 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
651 struct amdgpu_ib *ib)
652 {
653 struct amdgpu_device *adev = ring->adev;
654 uint32_t *msg;
655 int r, i;
656
657 memset(ib, 0, sizeof(*ib));
658 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
659 AMDGPU_IB_POOL_DIRECT,
660 ib);
661 if (r)
662 return r;
663
664 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
665 msg[0] = cpu_to_le32(0x00000028);
666 msg[1] = cpu_to_le32(0x00000038);
667 msg[2] = cpu_to_le32(0x00000001);
668 msg[3] = cpu_to_le32(0x00000000);
669 msg[4] = cpu_to_le32(handle);
670 msg[5] = cpu_to_le32(0x00000000);
671 msg[6] = cpu_to_le32(0x00000001);
672 msg[7] = cpu_to_le32(0x00000028);
673 msg[8] = cpu_to_le32(0x00000010);
674 msg[9] = cpu_to_le32(0x00000000);
675 msg[10] = cpu_to_le32(0x00000007);
676 msg[11] = cpu_to_le32(0x00000000);
677 msg[12] = cpu_to_le32(0x00000780);
678 msg[13] = cpu_to_le32(0x00000440);
679 for (i = 14; i < 1024; ++i)
680 msg[i] = cpu_to_le32(0x0);
681
682 return 0;
683 }
684
amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)685 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
686 struct amdgpu_ib *ib)
687 {
688 struct amdgpu_device *adev = ring->adev;
689 uint32_t *msg;
690 int r, i;
691
692 memset(ib, 0, sizeof(*ib));
693 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
694 AMDGPU_IB_POOL_DIRECT,
695 ib);
696 if (r)
697 return r;
698
699 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
700 msg[0] = cpu_to_le32(0x00000028);
701 msg[1] = cpu_to_le32(0x00000018);
702 msg[2] = cpu_to_le32(0x00000000);
703 msg[3] = cpu_to_le32(0x00000002);
704 msg[4] = cpu_to_le32(handle);
705 msg[5] = cpu_to_le32(0x00000000);
706 for (i = 6; i < 1024; ++i)
707 msg[i] = cpu_to_le32(0x0);
708
709 return 0;
710 }
711
amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring * ring,long timeout)712 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
713 {
714 struct dma_fence *fence = NULL;
715 struct amdgpu_ib ib;
716 long r;
717
718 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
719 if (r)
720 goto error;
721
722 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
723 if (r)
724 goto error;
725 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
726 if (r)
727 goto error;
728
729 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
730 if (r)
731 goto error;
732
733 r = dma_fence_wait_timeout(fence, false, timeout);
734 if (r == 0)
735 r = -ETIMEDOUT;
736 else if (r > 0)
737 r = 0;
738
739 dma_fence_put(fence);
740 error:
741 return r;
742 }
743
amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib * ib,uint32_t ib_pack_in_dw,bool enc)744 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
745 uint32_t ib_pack_in_dw, bool enc)
746 {
747 uint32_t *ib_checksum;
748
749 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
750 ib->ptr[ib->length_dw++] = 0x30000002;
751 ib_checksum = &ib->ptr[ib->length_dw++];
752 ib->ptr[ib->length_dw++] = ib_pack_in_dw;
753
754 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
755 ib->ptr[ib->length_dw++] = 0x30000001;
756 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
757 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
758
759 return ib_checksum;
760 }
761
amdgpu_vcn_unified_ring_ib_checksum(uint32_t ** ib_checksum,uint32_t ib_pack_in_dw)762 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
763 uint32_t ib_pack_in_dw)
764 {
765 uint32_t i;
766 uint32_t checksum = 0;
767
768 for (i = 0; i < ib_pack_in_dw; i++)
769 checksum += *(*ib_checksum + 2 + i);
770
771 **ib_checksum = checksum;
772 }
773
amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)774 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
775 struct amdgpu_ib *ib_msg,
776 struct dma_fence **fence)
777 {
778 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
779 unsigned int ib_size_dw = 64;
780 struct amdgpu_device *adev = ring->adev;
781 struct dma_fence *f = NULL;
782 struct amdgpu_job *job;
783 struct amdgpu_ib *ib;
784 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
785 bool sq = amdgpu_vcn_using_unified_queue(ring);
786 uint32_t *ib_checksum;
787 uint32_t ib_pack_in_dw;
788 int i, r;
789
790 if (sq)
791 ib_size_dw += 8;
792
793 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
794 AMDGPU_IB_POOL_DIRECT, &job);
795 if (r)
796 goto err;
797
798 ib = &job->ibs[0];
799 ib->length_dw = 0;
800
801 /* single queue headers */
802 if (sq) {
803 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
804 + 4 + 2; /* engine info + decoding ib in dw */
805 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
806 }
807
808 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
809 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
810 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
811 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
812 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
813
814 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
815 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
816 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
817
818 for (i = ib->length_dw; i < ib_size_dw; ++i)
819 ib->ptr[i] = 0x0;
820
821 if (sq)
822 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
823
824 r = amdgpu_job_submit_direct(job, ring, &f);
825 if (r)
826 goto err_free;
827
828 amdgpu_ib_free(adev, ib_msg, f);
829
830 if (fence)
831 *fence = dma_fence_get(f);
832 dma_fence_put(f);
833
834 return 0;
835
836 err_free:
837 amdgpu_job_free(job);
838 err:
839 amdgpu_ib_free(adev, ib_msg, f);
840 return r;
841 }
842
amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring * ring,long timeout)843 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
844 {
845 struct dma_fence *fence = NULL;
846 struct amdgpu_ib ib;
847 long r;
848
849 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
850 if (r)
851 goto error;
852
853 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
854 if (r)
855 goto error;
856 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
857 if (r)
858 goto error;
859
860 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
861 if (r)
862 goto error;
863
864 r = dma_fence_wait_timeout(fence, false, timeout);
865 if (r == 0)
866 r = -ETIMEDOUT;
867 else if (r > 0)
868 r = 0;
869
870 dma_fence_put(fence);
871 error:
872 return r;
873 }
874
amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring * ring)875 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
876 {
877 struct amdgpu_device *adev = ring->adev;
878 uint32_t rptr;
879 unsigned i;
880 int r;
881
882 if (amdgpu_sriov_vf(adev))
883 return 0;
884
885 r = amdgpu_ring_alloc(ring, 16);
886 if (r)
887 return r;
888
889 rptr = amdgpu_ring_get_rptr(ring);
890
891 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
892 amdgpu_ring_commit(ring);
893
894 for (i = 0; i < adev->usec_timeout; i++) {
895 if (amdgpu_ring_get_rptr(ring) != rptr)
896 break;
897 udelay(1);
898 }
899
900 if (i >= adev->usec_timeout)
901 r = -ETIMEDOUT;
902
903 return r;
904 }
905
amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)906 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
907 struct amdgpu_ib *ib_msg,
908 struct dma_fence **fence)
909 {
910 unsigned int ib_size_dw = 16;
911 struct amdgpu_job *job;
912 struct amdgpu_ib *ib;
913 struct dma_fence *f = NULL;
914 uint32_t *ib_checksum = NULL;
915 uint64_t addr;
916 bool sq = amdgpu_vcn_using_unified_queue(ring);
917 int i, r;
918
919 if (sq)
920 ib_size_dw += 8;
921
922 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
923 AMDGPU_IB_POOL_DIRECT, &job);
924 if (r)
925 return r;
926
927 ib = &job->ibs[0];
928 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
929
930 ib->length_dw = 0;
931
932 if (sq)
933 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
934
935 ib->ptr[ib->length_dw++] = 0x00000018;
936 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
937 ib->ptr[ib->length_dw++] = handle;
938 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
939 ib->ptr[ib->length_dw++] = addr;
940 ib->ptr[ib->length_dw++] = 0x0000000b;
941
942 ib->ptr[ib->length_dw++] = 0x00000014;
943 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
944 ib->ptr[ib->length_dw++] = 0x0000001c;
945 ib->ptr[ib->length_dw++] = 0x00000000;
946 ib->ptr[ib->length_dw++] = 0x00000000;
947
948 ib->ptr[ib->length_dw++] = 0x00000008;
949 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
950
951 for (i = ib->length_dw; i < ib_size_dw; ++i)
952 ib->ptr[i] = 0x0;
953
954 if (sq)
955 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
956
957 r = amdgpu_job_submit_direct(job, ring, &f);
958 if (r)
959 goto err;
960
961 if (fence)
962 *fence = dma_fence_get(f);
963 dma_fence_put(f);
964
965 return 0;
966
967 err:
968 amdgpu_job_free(job);
969 return r;
970 }
971
amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)972 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
973 struct amdgpu_ib *ib_msg,
974 struct dma_fence **fence)
975 {
976 unsigned int ib_size_dw = 16;
977 struct amdgpu_job *job;
978 struct amdgpu_ib *ib;
979 struct dma_fence *f = NULL;
980 uint32_t *ib_checksum = NULL;
981 uint64_t addr;
982 bool sq = amdgpu_vcn_using_unified_queue(ring);
983 int i, r;
984
985 if (sq)
986 ib_size_dw += 8;
987
988 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
989 AMDGPU_IB_POOL_DIRECT, &job);
990 if (r)
991 return r;
992
993 ib = &job->ibs[0];
994 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
995
996 ib->length_dw = 0;
997
998 if (sq)
999 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
1000
1001 ib->ptr[ib->length_dw++] = 0x00000018;
1002 ib->ptr[ib->length_dw++] = 0x00000001;
1003 ib->ptr[ib->length_dw++] = handle;
1004 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1005 ib->ptr[ib->length_dw++] = addr;
1006 ib->ptr[ib->length_dw++] = 0x0000000b;
1007
1008 ib->ptr[ib->length_dw++] = 0x00000014;
1009 ib->ptr[ib->length_dw++] = 0x00000002;
1010 ib->ptr[ib->length_dw++] = 0x0000001c;
1011 ib->ptr[ib->length_dw++] = 0x00000000;
1012 ib->ptr[ib->length_dw++] = 0x00000000;
1013
1014 ib->ptr[ib->length_dw++] = 0x00000008;
1015 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
1016
1017 for (i = ib->length_dw; i < ib_size_dw; ++i)
1018 ib->ptr[i] = 0x0;
1019
1020 if (sq)
1021 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
1022
1023 r = amdgpu_job_submit_direct(job, ring, &f);
1024 if (r)
1025 goto err;
1026
1027 if (fence)
1028 *fence = dma_fence_get(f);
1029 dma_fence_put(f);
1030
1031 return 0;
1032
1033 err:
1034 amdgpu_job_free(job);
1035 return r;
1036 }
1037
amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)1038 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1039 {
1040 struct amdgpu_device *adev = ring->adev;
1041 struct dma_fence *fence = NULL;
1042 struct amdgpu_ib ib;
1043 long r;
1044
1045 memset(&ib, 0, sizeof(ib));
1046 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
1047 AMDGPU_IB_POOL_DIRECT,
1048 &ib);
1049 if (r)
1050 return r;
1051
1052 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
1053 if (r)
1054 goto error;
1055
1056 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
1057 if (r)
1058 goto error;
1059
1060 r = dma_fence_wait_timeout(fence, false, timeout);
1061 if (r == 0)
1062 r = -ETIMEDOUT;
1063 else if (r > 0)
1064 r = 0;
1065
1066 error:
1067 amdgpu_ib_free(adev, &ib, fence);
1068 dma_fence_put(fence);
1069
1070 return r;
1071 }
1072
amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring * ring,long timeout)1073 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1074 {
1075 long r;
1076
1077 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1078 if (r)
1079 goto error;
1080
1081 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1082
1083 error:
1084 return r;
1085 }
1086
amdgpu_vcn_get_enc_ring_prio(int ring)1087 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1088 {
1089 switch(ring) {
1090 case 0:
1091 return AMDGPU_RING_PRIO_0;
1092 case 1:
1093 return AMDGPU_RING_PRIO_1;
1094 case 2:
1095 return AMDGPU_RING_PRIO_2;
1096 default:
1097 return AMDGPU_RING_PRIO_0;
1098 }
1099 }
1100
amdgpu_vcn_setup_ucode(struct amdgpu_device * adev)1101 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1102 {
1103 int i;
1104 unsigned int idx;
1105
1106 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1107 const struct common_firmware_header *hdr;
1108 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1109
1110 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1111 if (adev->vcn.harvest_config & (1 << i))
1112 continue;
1113 /* currently only support 2 FW instances */
1114 if (i >= 2) {
1115 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1116 break;
1117 }
1118 idx = AMDGPU_UCODE_ID_VCN + i;
1119 adev->firmware.ucode[idx].ucode_id = idx;
1120 adev->firmware.ucode[idx].fw = adev->vcn.fw;
1121 adev->firmware.fw_size +=
1122 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1123 }
1124 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1125 }
1126 }
1127
1128 /*
1129 * debugfs for mapping vcn firmware log buffer.
1130 */
1131 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_vcn_fwlog_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1132 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1133 size_t size, loff_t *pos)
1134 {
1135 struct amdgpu_vcn_inst *vcn;
1136 void *log_buf;
1137 volatile struct amdgpu_vcn_fwlog *plog;
1138 unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1139 unsigned int read_num[2] = {0};
1140
1141 vcn = file_inode(f)->i_private;
1142 if (!vcn)
1143 return -ENODEV;
1144
1145 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1146 return -EFAULT;
1147
1148 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1149
1150 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1151 read_pos = plog->rptr;
1152 write_pos = plog->wptr;
1153
1154 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1155 return -EFAULT;
1156
1157 if (!size || (read_pos == write_pos))
1158 return 0;
1159
1160 if (write_pos > read_pos) {
1161 available = write_pos - read_pos;
1162 read_num[0] = min(size, (size_t)available);
1163 } else {
1164 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1165 available = read_num[0] + write_pos - plog->header_size;
1166 if (size > available)
1167 read_num[1] = write_pos - plog->header_size;
1168 else if (size > read_num[0])
1169 read_num[1] = size - read_num[0];
1170 else
1171 read_num[0] = size;
1172 }
1173
1174 for (i = 0; i < 2; i++) {
1175 if (read_num[i]) {
1176 if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1177 read_pos = plog->header_size;
1178 if (read_num[i] == copy_to_user((buf + read_bytes),
1179 (log_buf + read_pos), read_num[i]))
1180 return -EFAULT;
1181
1182 read_bytes += read_num[i];
1183 read_pos += read_num[i];
1184 }
1185 }
1186
1187 plog->rptr = read_pos;
1188 *pos += read_bytes;
1189 return read_bytes;
1190 }
1191
1192 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1193 .owner = THIS_MODULE,
1194 .read = amdgpu_debugfs_vcn_fwlog_read,
1195 .llseek = default_llseek
1196 };
1197 #endif
1198
amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device * adev,uint8_t i,struct amdgpu_vcn_inst * vcn)1199 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1200 struct amdgpu_vcn_inst *vcn)
1201 {
1202 #if defined(CONFIG_DEBUG_FS)
1203 struct drm_minor *minor = adev_to_drm(adev)->primary;
1204 struct dentry *root = minor->debugfs_root;
1205 char name[32];
1206
1207 sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1208 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn,
1209 &amdgpu_debugfs_vcnfwlog_fops,
1210 AMDGPU_VCNFW_LOG_SIZE);
1211 #endif
1212 }
1213
amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst * vcn)1214 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1215 {
1216 #if defined(CONFIG_DEBUG_FS)
1217 volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1218 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1219 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1220 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1221 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1222 + vcn->fw_shared.log_offset;
1223 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1224 fw_log->is_enabled = 1;
1225 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1226 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1227 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1228
1229 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1230 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1231 log_buf->rptr = log_buf->header_size;
1232 log_buf->wptr = log_buf->header_size;
1233 log_buf->wrapped = 0;
1234 #endif
1235 }
1236
amdgpu_vcn_process_poison_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1237 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1238 struct amdgpu_irq_src *source,
1239 struct amdgpu_iv_entry *entry)
1240 {
1241 struct ras_common_if *ras_if = adev->vcn.ras_if;
1242 struct ras_dispatch_if ih_data = {
1243 .entry = entry,
1244 };
1245
1246 if (!ras_if)
1247 return 0;
1248
1249 ih_data.head = *ras_if;
1250 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1251
1252 return 0;
1253 }
1254