1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
35 
36 #include <drm/drm_drv.h>
37 #include <drm/amdgpu_drm.h>
38 #include <drm/drm_cache.h>
39 #include "amdgpu.h"
40 #include "amdgpu_trace.h"
41 #include "amdgpu_amdkfd.h"
42 
43 /**
44  * DOC: amdgpu_object
45  *
46  * This defines the interfaces to operate on an &amdgpu_bo buffer object which
47  * represents memory used by driver (VRAM, system memory, etc.). The driver
48  * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
49  * to create/destroy/set buffer object which are then managed by the kernel TTM
50  * memory manager.
51  * The interfaces are also used internally by kernel clients, including gfx,
52  * uvd, etc. for kernel managed allocations used by the GPU.
53  *
54  */
55 
amdgpu_bo_destroy(struct ttm_buffer_object * tbo)56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
57 {
58 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
59 
60 	amdgpu_bo_kunmap(bo);
61 
62 	if (bo->tbo.base.import_attach)
63 		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
64 	drm_gem_object_release(&bo->tbo.base);
65 	amdgpu_bo_unref(&bo->parent);
66 	kvfree(bo);
67 }
68 
amdgpu_bo_user_destroy(struct ttm_buffer_object * tbo)69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
70 {
71 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
72 	struct amdgpu_bo_user *ubo;
73 
74 	ubo = to_amdgpu_bo_user(bo);
75 	kfree(ubo->metadata);
76 	amdgpu_bo_destroy(tbo);
77 }
78 
amdgpu_bo_vm_destroy(struct ttm_buffer_object * tbo)79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
80 {
81 	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
82 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
83 	struct amdgpu_bo_vm *vmbo;
84 
85 	vmbo = to_amdgpu_bo_vm(bo);
86 	/* in case amdgpu_device_recover_vram got NULL of bo->parent */
87 	if (!list_empty(&vmbo->shadow_list)) {
88 		mutex_lock(&adev->shadow_list_lock);
89 		list_del_init(&vmbo->shadow_list);
90 		mutex_unlock(&adev->shadow_list_lock);
91 	}
92 
93 	amdgpu_bo_destroy(tbo);
94 }
95 
96 /**
97  * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
98  * @bo: buffer object to be checked
99  *
100  * Uses destroy function associated with the object to determine if this is
101  * an &amdgpu_bo.
102  *
103  * Returns:
104  * true if the object belongs to &amdgpu_bo, false if not.
105  */
amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object * bo)106 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
107 {
108 	if (bo->destroy == &amdgpu_bo_destroy ||
109 	    bo->destroy == &amdgpu_bo_user_destroy ||
110 	    bo->destroy == &amdgpu_bo_vm_destroy)
111 		return true;
112 
113 	return false;
114 }
115 
116 /**
117  * amdgpu_bo_placement_from_domain - set buffer's placement
118  * @abo: &amdgpu_bo buffer object whose placement is to be set
119  * @domain: requested domain
120  *
121  * Sets buffer's placement according to requested domain and the buffer's
122  * flags.
123  */
amdgpu_bo_placement_from_domain(struct amdgpu_bo * abo,u32 domain)124 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
125 {
126 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
127 	struct ttm_placement *placement = &abo->placement;
128 	struct ttm_place *places = abo->placements;
129 	u64 flags = abo->flags;
130 	u32 c = 0;
131 
132 	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
133 		unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
134 
135 		places[c].fpfn = 0;
136 		places[c].lpfn = 0;
137 		places[c].mem_type = TTM_PL_VRAM;
138 		places[c].flags = 0;
139 
140 		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
141 			places[c].lpfn = visible_pfn;
142 		else
143 			places[c].flags |= TTM_PL_FLAG_TOPDOWN;
144 
145 		if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
146 			places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
147 		c++;
148 	}
149 
150 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
151 		places[c].fpfn = 0;
152 		places[c].lpfn = 0;
153 		places[c].mem_type =
154 			abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
155 			AMDGPU_PL_PREEMPT : TTM_PL_TT;
156 		places[c].flags = 0;
157 		c++;
158 	}
159 
160 	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
161 		places[c].fpfn = 0;
162 		places[c].lpfn = 0;
163 		places[c].mem_type = TTM_PL_SYSTEM;
164 		places[c].flags = 0;
165 		c++;
166 	}
167 
168 	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
169 		places[c].fpfn = 0;
170 		places[c].lpfn = 0;
171 		places[c].mem_type = AMDGPU_PL_GDS;
172 		places[c].flags = 0;
173 		c++;
174 	}
175 
176 	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
177 		places[c].fpfn = 0;
178 		places[c].lpfn = 0;
179 		places[c].mem_type = AMDGPU_PL_GWS;
180 		places[c].flags = 0;
181 		c++;
182 	}
183 
184 	if (domain & AMDGPU_GEM_DOMAIN_OA) {
185 		places[c].fpfn = 0;
186 		places[c].lpfn = 0;
187 		places[c].mem_type = AMDGPU_PL_OA;
188 		places[c].flags = 0;
189 		c++;
190 	}
191 
192 	if (!c) {
193 		places[c].fpfn = 0;
194 		places[c].lpfn = 0;
195 		places[c].mem_type = TTM_PL_SYSTEM;
196 		places[c].flags = 0;
197 		c++;
198 	}
199 
200 	BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
201 
202 	placement->num_placement = c;
203 	placement->placement = places;
204 
205 	placement->num_busy_placement = c;
206 	placement->busy_placement = places;
207 }
208 
209 /**
210  * amdgpu_bo_create_reserved - create reserved BO for kernel use
211  *
212  * @adev: amdgpu device object
213  * @size: size for the new BO
214  * @align: alignment for the new BO
215  * @domain: where to place it
216  * @bo_ptr: used to initialize BOs in structures
217  * @gpu_addr: GPU addr of the pinned BO
218  * @cpu_addr: optional CPU address mapping
219  *
220  * Allocates and pins a BO for kernel internal use, and returns it still
221  * reserved.
222  *
223  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
224  *
225  * Returns:
226  * 0 on success, negative error code otherwise.
227  */
amdgpu_bo_create_reserved(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
229 			      unsigned long size, int align,
230 			      u32 domain, struct amdgpu_bo **bo_ptr,
231 			      u64 *gpu_addr, void **cpu_addr)
232 {
233 	struct amdgpu_bo_param bp;
234 	bool free = false;
235 	int r;
236 
237 	if (!size) {
238 		amdgpu_bo_unref(bo_ptr);
239 		return 0;
240 	}
241 
242 	memset(&bp, 0, sizeof(bp));
243 	bp.size = size;
244 	bp.byte_align = align;
245 	bp.domain = domain;
246 	bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
247 		: AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
248 	bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
249 	bp.type = ttm_bo_type_kernel;
250 	bp.resv = NULL;
251 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
252 
253 	if (!*bo_ptr) {
254 		r = amdgpu_bo_create(adev, &bp, bo_ptr);
255 		if (r) {
256 			dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
257 				r);
258 			return r;
259 		}
260 		free = true;
261 	}
262 
263 	r = amdgpu_bo_reserve(*bo_ptr, false);
264 	if (r) {
265 		dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
266 		goto error_free;
267 	}
268 
269 	r = amdgpu_bo_pin(*bo_ptr, domain);
270 	if (r) {
271 		dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
272 		goto error_unreserve;
273 	}
274 
275 	r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
276 	if (r) {
277 		dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
278 		goto error_unpin;
279 	}
280 
281 	if (gpu_addr)
282 		*gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
283 
284 	if (cpu_addr) {
285 		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
286 		if (r) {
287 			dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
288 			goto error_unpin;
289 		}
290 	}
291 
292 	return 0;
293 
294 error_unpin:
295 	amdgpu_bo_unpin(*bo_ptr);
296 error_unreserve:
297 	amdgpu_bo_unreserve(*bo_ptr);
298 
299 error_free:
300 	if (free)
301 		amdgpu_bo_unref(bo_ptr);
302 
303 	return r;
304 }
305 
306 /**
307  * amdgpu_bo_create_kernel - create BO for kernel use
308  *
309  * @adev: amdgpu device object
310  * @size: size for the new BO
311  * @align: alignment for the new BO
312  * @domain: where to place it
313  * @bo_ptr:  used to initialize BOs in structures
314  * @gpu_addr: GPU addr of the pinned BO
315  * @cpu_addr: optional CPU address mapping
316  *
317  * Allocates and pins a BO for kernel internal use.
318  *
319  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
320  *
321  * Returns:
322  * 0 on success, negative error code otherwise.
323  */
amdgpu_bo_create_kernel(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)324 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
325 			    unsigned long size, int align,
326 			    u32 domain, struct amdgpu_bo **bo_ptr,
327 			    u64 *gpu_addr, void **cpu_addr)
328 {
329 	int r;
330 
331 	r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
332 				      gpu_addr, cpu_addr);
333 
334 	if (r)
335 		return r;
336 
337 	if (*bo_ptr)
338 		amdgpu_bo_unreserve(*bo_ptr);
339 
340 	return 0;
341 }
342 
343 /**
344  * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
345  *
346  * @adev: amdgpu device object
347  * @offset: offset of the BO
348  * @size: size of the BO
349  * @domain: where to place it
350  * @bo_ptr:  used to initialize BOs in structures
351  * @cpu_addr: optional CPU address mapping
352  *
353  * Creates a kernel BO at a specific offset in the address space of the domain.
354  *
355  * Returns:
356  * 0 on success, negative error code otherwise.
357  */
amdgpu_bo_create_kernel_at(struct amdgpu_device * adev,uint64_t offset,uint64_t size,uint32_t domain,struct amdgpu_bo ** bo_ptr,void ** cpu_addr)358 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
359 			       uint64_t offset, uint64_t size, uint32_t domain,
360 			       struct amdgpu_bo **bo_ptr, void **cpu_addr)
361 {
362 	struct ttm_operation_ctx ctx = { false, false };
363 	unsigned int i;
364 	int r;
365 
366 	offset &= PAGE_MASK;
367 	size = ALIGN(size, PAGE_SIZE);
368 
369 	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
370 				      NULL, cpu_addr);
371 	if (r)
372 		return r;
373 
374 	if ((*bo_ptr) == NULL)
375 		return 0;
376 
377 	/*
378 	 * Remove the original mem node and create a new one at the request
379 	 * position.
380 	 */
381 	if (cpu_addr)
382 		amdgpu_bo_kunmap(*bo_ptr);
383 
384 	ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
385 
386 	for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
387 		(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
388 		(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
389 	}
390 	r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
391 			     &(*bo_ptr)->tbo.resource, &ctx);
392 	if (r)
393 		goto error;
394 
395 	if (cpu_addr) {
396 		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
397 		if (r)
398 			goto error;
399 	}
400 
401 	amdgpu_bo_unreserve(*bo_ptr);
402 	return 0;
403 
404 error:
405 	amdgpu_bo_unreserve(*bo_ptr);
406 	amdgpu_bo_unref(bo_ptr);
407 	return r;
408 }
409 
410 /**
411  * amdgpu_bo_free_kernel - free BO for kernel use
412  *
413  * @bo: amdgpu BO to free
414  * @gpu_addr: pointer to where the BO's GPU memory space address was stored
415  * @cpu_addr: pointer to where the BO's CPU memory space address was stored
416  *
417  * unmaps and unpin a BO for kernel internal use.
418  */
amdgpu_bo_free_kernel(struct amdgpu_bo ** bo,u64 * gpu_addr,void ** cpu_addr)419 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
420 			   void **cpu_addr)
421 {
422 	if (*bo == NULL)
423 		return;
424 
425 	if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
426 		if (cpu_addr)
427 			amdgpu_bo_kunmap(*bo);
428 
429 		amdgpu_bo_unpin(*bo);
430 		amdgpu_bo_unreserve(*bo);
431 	}
432 	amdgpu_bo_unref(bo);
433 
434 	if (gpu_addr)
435 		*gpu_addr = 0;
436 
437 	if (cpu_addr)
438 		*cpu_addr = NULL;
439 }
440 
441 /* Validate bo size is bit bigger then the request domain */
amdgpu_bo_validate_size(struct amdgpu_device * adev,unsigned long size,u32 domain)442 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
443 					  unsigned long size, u32 domain)
444 {
445 	struct ttm_resource_manager *man = NULL;
446 
447 	/*
448 	 * If GTT is part of requested domains the check must succeed to
449 	 * allow fall back to GTT.
450 	 */
451 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
452 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
453 
454 		if (man && size < man->size)
455 			return true;
456 		else if (!man)
457 			WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized");
458 		goto fail;
459 	} else if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
460 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
461 
462 		if (man && size < man->size)
463 			return true;
464 		goto fail;
465 	}
466 
467 	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
468 	return true;
469 
470 fail:
471 	if (man)
472 		DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
473 			  man->size);
474 	return false;
475 }
476 
amdgpu_bo_support_uswc(u64 bo_flags)477 bool amdgpu_bo_support_uswc(u64 bo_flags)
478 {
479 
480 #ifdef CONFIG_X86_32
481 	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
482 	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
483 	 */
484 	return false;
485 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
486 	/* Don't try to enable write-combining when it can't work, or things
487 	 * may be slow
488 	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
489 	 */
490 
491 #ifndef CONFIG_COMPILE_TEST
492 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
493 	 thanks to write-combining
494 #endif
495 
496 	if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
497 		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
498 			      "better performance thanks to write-combining\n");
499 	return false;
500 #else
501 	/* For architectures that don't support WC memory,
502 	 * mask out the WC flag from the BO
503 	 */
504 	if (!drm_arch_can_wc_memory())
505 		return false;
506 
507 	return true;
508 #endif
509 }
510 
511 /**
512  * amdgpu_bo_create - create an &amdgpu_bo buffer object
513  * @adev: amdgpu device object
514  * @bp: parameters to be used for the buffer object
515  * @bo_ptr: pointer to the buffer object pointer
516  *
517  * Creates an &amdgpu_bo buffer object.
518  *
519  * Returns:
520  * 0 for success or a negative error code on failure.
521  */
amdgpu_bo_create(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo ** bo_ptr)522 int amdgpu_bo_create(struct amdgpu_device *adev,
523 			       struct amdgpu_bo_param *bp,
524 			       struct amdgpu_bo **bo_ptr)
525 {
526 	struct ttm_operation_ctx ctx = {
527 		.interruptible = (bp->type != ttm_bo_type_kernel),
528 		.no_wait_gpu = bp->no_wait_gpu,
529 		/* We opt to avoid OOM on system pages allocations */
530 		.gfp_retry_mayfail = true,
531 		.allow_res_evict = bp->type != ttm_bo_type_kernel,
532 		.resv = bp->resv
533 	};
534 	struct amdgpu_bo *bo;
535 	unsigned long page_align, size = bp->size;
536 	int r;
537 
538 	/* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
539 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
540 		/* GWS and OA don't need any alignment. */
541 		page_align = bp->byte_align;
542 		size <<= PAGE_SHIFT;
543 	} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
544 		/* Both size and alignment must be a multiple of 4. */
545 		page_align = ALIGN(bp->byte_align, 4);
546 		size = ALIGN(size, 4) << PAGE_SHIFT;
547 	} else {
548 		/* Memory should be aligned at least to a page size. */
549 		page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
550 		size = ALIGN(size, PAGE_SIZE);
551 	}
552 
553 	if (!amdgpu_bo_validate_size(adev, size, bp->domain))
554 		return -ENOMEM;
555 
556 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
557 
558 	*bo_ptr = NULL;
559 	bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
560 	if (bo == NULL)
561 		return -ENOMEM;
562 	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
563 	bo->vm_bo = NULL;
564 	bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
565 		bp->domain;
566 	bo->allowed_domains = bo->preferred_domains;
567 	if (bp->type != ttm_bo_type_kernel &&
568 	    !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) &&
569 	    bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
570 		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
571 
572 	bo->flags = bp->flags;
573 
574 	if (!amdgpu_bo_support_uswc(bo->flags))
575 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
576 
577 	if (adev->ras_enabled)
578 		bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
579 
580 	bo->tbo.bdev = &adev->mman.bdev;
581 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
582 			  AMDGPU_GEM_DOMAIN_GDS))
583 		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
584 	else
585 		amdgpu_bo_placement_from_domain(bo, bp->domain);
586 	if (bp->type == ttm_bo_type_kernel)
587 		bo->tbo.priority = 1;
588 
589 	if (!bp->destroy)
590 		bp->destroy = &amdgpu_bo_destroy;
591 
592 	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type,
593 				 &bo->placement, page_align, &ctx,  NULL,
594 				 bp->resv, bp->destroy);
595 	if (unlikely(r != 0))
596 		return r;
597 
598 	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
599 	    bo->tbo.resource->mem_type == TTM_PL_VRAM &&
600 	    bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
601 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
602 					     ctx.bytes_moved);
603 	else
604 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
605 
606 	if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
607 	    bo->tbo.resource->mem_type == TTM_PL_VRAM) {
608 		struct dma_fence *fence;
609 
610 		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
611 		if (unlikely(r))
612 			goto fail_unreserve;
613 
614 		dma_resv_add_fence(bo->tbo.base.resv, fence,
615 				   DMA_RESV_USAGE_KERNEL);
616 		dma_fence_put(fence);
617 	}
618 	if (!bp->resv)
619 		amdgpu_bo_unreserve(bo);
620 	*bo_ptr = bo;
621 
622 	trace_amdgpu_bo_create(bo);
623 
624 	/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
625 	if (bp->type == ttm_bo_type_device)
626 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
627 
628 	return 0;
629 
630 fail_unreserve:
631 	if (!bp->resv)
632 		dma_resv_unlock(bo->tbo.base.resv);
633 	amdgpu_bo_unref(&bo);
634 	return r;
635 }
636 
637 /**
638  * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
639  * @adev: amdgpu device object
640  * @bp: parameters to be used for the buffer object
641  * @ubo_ptr: pointer to the buffer object pointer
642  *
643  * Create a BO to be used by user application;
644  *
645  * Returns:
646  * 0 for success or a negative error code on failure.
647  */
648 
amdgpu_bo_create_user(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_user ** ubo_ptr)649 int amdgpu_bo_create_user(struct amdgpu_device *adev,
650 			  struct amdgpu_bo_param *bp,
651 			  struct amdgpu_bo_user **ubo_ptr)
652 {
653 	struct amdgpu_bo *bo_ptr;
654 	int r;
655 
656 	bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
657 	bp->destroy = &amdgpu_bo_user_destroy;
658 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
659 	if (r)
660 		return r;
661 
662 	*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
663 	return r;
664 }
665 
666 /**
667  * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
668  * @adev: amdgpu device object
669  * @bp: parameters to be used for the buffer object
670  * @vmbo_ptr: pointer to the buffer object pointer
671  *
672  * Create a BO to be for GPUVM.
673  *
674  * Returns:
675  * 0 for success or a negative error code on failure.
676  */
677 
amdgpu_bo_create_vm(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_vm ** vmbo_ptr)678 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
679 			struct amdgpu_bo_param *bp,
680 			struct amdgpu_bo_vm **vmbo_ptr)
681 {
682 	struct amdgpu_bo *bo_ptr;
683 	int r;
684 
685 	/* bo_ptr_size will be determined by the caller and it depends on
686 	 * num of amdgpu_vm_pt entries.
687 	 */
688 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
689 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
690 	if (r)
691 		return r;
692 
693 	*vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
694 	INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list);
695 	/* Set destroy callback to amdgpu_bo_vm_destroy after vmbo->shadow_list
696 	 * is initialized.
697 	 */
698 	bo_ptr->tbo.destroy = &amdgpu_bo_vm_destroy;
699 	return r;
700 }
701 
702 /**
703  * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
704  *
705  * @vmbo: BO that will be inserted into the shadow list
706  *
707  * Insert a BO to the shadow list.
708  */
amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm * vmbo)709 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)
710 {
711 	struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev);
712 
713 	mutex_lock(&adev->shadow_list_lock);
714 	list_add_tail(&vmbo->shadow_list, &adev->shadow_list);
715 	mutex_unlock(&adev->shadow_list_lock);
716 }
717 
718 /**
719  * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
720  *
721  * @shadow: &amdgpu_bo shadow to be restored
722  * @fence: dma_fence associated with the operation
723  *
724  * Copies a buffer object's shadow content back to the object.
725  * This is used for recovering a buffer from its shadow in case of a gpu
726  * reset where vram context may be lost.
727  *
728  * Returns:
729  * 0 for success or a negative error code on failure.
730  */
amdgpu_bo_restore_shadow(struct amdgpu_bo * shadow,struct dma_fence ** fence)731 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
732 
733 {
734 	struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
735 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
736 	uint64_t shadow_addr, parent_addr;
737 
738 	shadow_addr = amdgpu_bo_gpu_offset(shadow);
739 	parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
740 
741 	return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
742 				  amdgpu_bo_size(shadow), NULL, fence,
743 				  true, false, false);
744 }
745 
746 /**
747  * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
748  * @bo: &amdgpu_bo buffer object to be mapped
749  * @ptr: kernel virtual address to be returned
750  *
751  * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
752  * amdgpu_bo_kptr() to get the kernel virtual address.
753  *
754  * Returns:
755  * 0 for success or a negative error code on failure.
756  */
amdgpu_bo_kmap(struct amdgpu_bo * bo,void ** ptr)757 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
758 {
759 	void *kptr;
760 	long r;
761 
762 	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
763 		return -EPERM;
764 
765 	r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
766 				  false, MAX_SCHEDULE_TIMEOUT);
767 	if (r < 0)
768 		return r;
769 
770 	kptr = amdgpu_bo_kptr(bo);
771 	if (kptr) {
772 		if (ptr)
773 			*ptr = kptr;
774 		return 0;
775 	}
776 
777 	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);
778 	if (r)
779 		return r;
780 
781 	if (ptr)
782 		*ptr = amdgpu_bo_kptr(bo);
783 
784 	return 0;
785 }
786 
787 /**
788  * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
789  * @bo: &amdgpu_bo buffer object
790  *
791  * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
792  *
793  * Returns:
794  * the virtual address of a buffer object area.
795  */
amdgpu_bo_kptr(struct amdgpu_bo * bo)796 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
797 {
798 	bool is_iomem;
799 
800 	return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
801 }
802 
803 /**
804  * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
805  * @bo: &amdgpu_bo buffer object to be unmapped
806  *
807  * Unmaps a kernel map set up by amdgpu_bo_kmap().
808  */
amdgpu_bo_kunmap(struct amdgpu_bo * bo)809 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
810 {
811 	if (bo->kmap.bo)
812 		ttm_bo_kunmap(&bo->kmap);
813 }
814 
815 /**
816  * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
817  * @bo: &amdgpu_bo buffer object
818  *
819  * References the contained &ttm_buffer_object.
820  *
821  * Returns:
822  * a refcounted pointer to the &amdgpu_bo buffer object.
823  */
amdgpu_bo_ref(struct amdgpu_bo * bo)824 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
825 {
826 	if (bo == NULL)
827 		return NULL;
828 
829 	ttm_bo_get(&bo->tbo);
830 	return bo;
831 }
832 
833 /**
834  * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
835  * @bo: &amdgpu_bo buffer object
836  *
837  * Unreferences the contained &ttm_buffer_object and clear the pointer
838  */
amdgpu_bo_unref(struct amdgpu_bo ** bo)839 void amdgpu_bo_unref(struct amdgpu_bo **bo)
840 {
841 	struct ttm_buffer_object *tbo;
842 
843 	if ((*bo) == NULL)
844 		return;
845 
846 	tbo = &((*bo)->tbo);
847 	ttm_bo_put(tbo);
848 	*bo = NULL;
849 }
850 
851 /**
852  * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
853  * @bo: &amdgpu_bo buffer object to be pinned
854  * @domain: domain to be pinned to
855  * @min_offset: the start of requested address range
856  * @max_offset: the end of requested address range
857  *
858  * Pins the buffer object according to requested domain and address range. If
859  * the memory is unbound gart memory, binds the pages into gart table. Adjusts
860  * pin_count and pin_size accordingly.
861  *
862  * Pinning means to lock pages in memory along with keeping them at a fixed
863  * offset. It is required when a buffer can not be moved, for example, when
864  * a display buffer is being scanned out.
865  *
866  * Compared with amdgpu_bo_pin(), this function gives more flexibility on
867  * where to pin a buffer if there are specific restrictions on where a buffer
868  * must be located.
869  *
870  * Returns:
871  * 0 for success or a negative error code on failure.
872  */
amdgpu_bo_pin_restricted(struct amdgpu_bo * bo,u32 domain,u64 min_offset,u64 max_offset)873 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
874 			     u64 min_offset, u64 max_offset)
875 {
876 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
877 	struct ttm_operation_ctx ctx = { false, false };
878 	int r, i;
879 
880 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
881 		return -EPERM;
882 
883 	if (WARN_ON_ONCE(min_offset > max_offset))
884 		return -EINVAL;
885 
886 	/* Check domain to be pinned to against preferred domains */
887 	if (bo->preferred_domains & domain)
888 		domain = bo->preferred_domains & domain;
889 
890 	/* A shared bo cannot be migrated to VRAM */
891 	if (bo->tbo.base.import_attach) {
892 		if (domain & AMDGPU_GEM_DOMAIN_GTT)
893 			domain = AMDGPU_GEM_DOMAIN_GTT;
894 		else
895 			return -EINVAL;
896 	}
897 
898 	if (bo->tbo.pin_count) {
899 		uint32_t mem_type = bo->tbo.resource->mem_type;
900 		uint32_t mem_flags = bo->tbo.resource->placement;
901 
902 		if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
903 			return -EINVAL;
904 
905 		if ((mem_type == TTM_PL_VRAM) &&
906 		    (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
907 		    !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
908 			return -EINVAL;
909 
910 		ttm_bo_pin(&bo->tbo);
911 
912 		if (max_offset != 0) {
913 			u64 domain_start = amdgpu_ttm_domain_start(adev,
914 								   mem_type);
915 			WARN_ON_ONCE(max_offset <
916 				     (amdgpu_bo_gpu_offset(bo) - domain_start));
917 		}
918 
919 		return 0;
920 	}
921 
922 	/* This assumes only APU display buffers are pinned with (VRAM|GTT).
923 	 * See function amdgpu_display_supported_domains()
924 	 */
925 	domain = amdgpu_bo_get_preferred_domain(adev, domain);
926 
927 	if (bo->tbo.base.import_attach)
928 		dma_buf_pin(bo->tbo.base.import_attach);
929 
930 	/* force to pin into visible video ram */
931 	if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
932 		bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
933 	amdgpu_bo_placement_from_domain(bo, domain);
934 	for (i = 0; i < bo->placement.num_placement; i++) {
935 		unsigned fpfn, lpfn;
936 
937 		fpfn = min_offset >> PAGE_SHIFT;
938 		lpfn = max_offset >> PAGE_SHIFT;
939 
940 		if (fpfn > bo->placements[i].fpfn)
941 			bo->placements[i].fpfn = fpfn;
942 		if (!bo->placements[i].lpfn ||
943 		    (lpfn && lpfn < bo->placements[i].lpfn))
944 			bo->placements[i].lpfn = lpfn;
945 	}
946 
947 	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
948 	if (unlikely(r)) {
949 		dev_err(adev->dev, "%p pin failed\n", bo);
950 		goto error;
951 	}
952 
953 	ttm_bo_pin(&bo->tbo);
954 
955 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
956 	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
957 		atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
958 		atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
959 			     &adev->visible_pin_size);
960 	} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
961 		atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
962 	}
963 
964 error:
965 	return r;
966 }
967 
968 /**
969  * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
970  * @bo: &amdgpu_bo buffer object to be pinned
971  * @domain: domain to be pinned to
972  *
973  * A simple wrapper to amdgpu_bo_pin_restricted().
974  * Provides a simpler API for buffers that do not have any strict restrictions
975  * on where a buffer must be located.
976  *
977  * Returns:
978  * 0 for success or a negative error code on failure.
979  */
amdgpu_bo_pin(struct amdgpu_bo * bo,u32 domain)980 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
981 {
982 	bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
983 	return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
984 }
985 
986 /**
987  * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
988  * @bo: &amdgpu_bo buffer object to be unpinned
989  *
990  * Decreases the pin_count, and clears the flags if pin_count reaches 0.
991  * Changes placement and pin size accordingly.
992  *
993  * Returns:
994  * 0 for success or a negative error code on failure.
995  */
amdgpu_bo_unpin(struct amdgpu_bo * bo)996 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
997 {
998 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
999 
1000 	ttm_bo_unpin(&bo->tbo);
1001 	if (bo->tbo.pin_count)
1002 		return;
1003 
1004 	if (bo->tbo.base.import_attach)
1005 		dma_buf_unpin(bo->tbo.base.import_attach);
1006 
1007 	if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
1008 		atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
1009 		atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
1010 			     &adev->visible_pin_size);
1011 	} else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1012 		atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
1013 	}
1014 }
1015 
1016 static const char *amdgpu_vram_names[] = {
1017 	"UNKNOWN",
1018 	"GDDR1",
1019 	"DDR2",
1020 	"GDDR3",
1021 	"GDDR4",
1022 	"GDDR5",
1023 	"HBM",
1024 	"DDR3",
1025 	"DDR4",
1026 	"GDDR6",
1027 	"DDR5",
1028 	"LPDDR4",
1029 	"LPDDR5"
1030 };
1031 
1032 /**
1033  * amdgpu_bo_init - initialize memory manager
1034  * @adev: amdgpu device object
1035  *
1036  * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1037  *
1038  * Returns:
1039  * 0 for success or a negative error code on failure.
1040  */
amdgpu_bo_init(struct amdgpu_device * adev)1041 int amdgpu_bo_init(struct amdgpu_device *adev)
1042 {
1043 	/* On A+A platform, VRAM can be mapped as WB */
1044 	if (!adev->gmc.xgmi.connected_to_cpu) {
1045 		/* reserve PAT memory space to WC for VRAM */
1046 		int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1047 				adev->gmc.aper_size);
1048 
1049 		if (r) {
1050 			DRM_ERROR("Unable to set WC memtype for the aperture base\n");
1051 			return r;
1052 		}
1053 
1054 		/* Add an MTRR for the VRAM */
1055 		adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1056 				adev->gmc.aper_size);
1057 	}
1058 
1059 	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1060 		 adev->gmc.mc_vram_size >> 20,
1061 		 (unsigned long long)adev->gmc.aper_size >> 20);
1062 	DRM_INFO("RAM width %dbits %s\n",
1063 		 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1064 	return amdgpu_ttm_init(adev);
1065 }
1066 
1067 /**
1068  * amdgpu_bo_fini - tear down memory manager
1069  * @adev: amdgpu device object
1070  *
1071  * Reverses amdgpu_bo_init() to tear down memory manager.
1072  */
amdgpu_bo_fini(struct amdgpu_device * adev)1073 void amdgpu_bo_fini(struct amdgpu_device *adev)
1074 {
1075 	int idx;
1076 
1077 	amdgpu_ttm_fini(adev);
1078 
1079 	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1080 
1081 		if (!adev->gmc.xgmi.connected_to_cpu) {
1082 			arch_phys_wc_del(adev->gmc.vram_mtrr);
1083 			arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
1084 		}
1085 		drm_dev_exit(idx);
1086 	}
1087 }
1088 
1089 /**
1090  * amdgpu_bo_set_tiling_flags - set tiling flags
1091  * @bo: &amdgpu_bo buffer object
1092  * @tiling_flags: new flags
1093  *
1094  * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1095  * kernel driver to set the tiling flags on a buffer.
1096  *
1097  * Returns:
1098  * 0 for success or a negative error code on failure.
1099  */
amdgpu_bo_set_tiling_flags(struct amdgpu_bo * bo,u64 tiling_flags)1100 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1101 {
1102 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1103 	struct amdgpu_bo_user *ubo;
1104 
1105 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1106 	if (adev->family <= AMDGPU_FAMILY_CZ &&
1107 	    AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1108 		return -EINVAL;
1109 
1110 	ubo = to_amdgpu_bo_user(bo);
1111 	ubo->tiling_flags = tiling_flags;
1112 	return 0;
1113 }
1114 
1115 /**
1116  * amdgpu_bo_get_tiling_flags - get tiling flags
1117  * @bo: &amdgpu_bo buffer object
1118  * @tiling_flags: returned flags
1119  *
1120  * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1121  * set the tiling flags on a buffer.
1122  */
amdgpu_bo_get_tiling_flags(struct amdgpu_bo * bo,u64 * tiling_flags)1123 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1124 {
1125 	struct amdgpu_bo_user *ubo;
1126 
1127 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1128 	dma_resv_assert_held(bo->tbo.base.resv);
1129 	ubo = to_amdgpu_bo_user(bo);
1130 
1131 	if (tiling_flags)
1132 		*tiling_flags = ubo->tiling_flags;
1133 }
1134 
1135 /**
1136  * amdgpu_bo_set_metadata - set metadata
1137  * @bo: &amdgpu_bo buffer object
1138  * @metadata: new metadata
1139  * @metadata_size: size of the new metadata
1140  * @flags: flags of the new metadata
1141  *
1142  * Sets buffer object's metadata, its size and flags.
1143  * Used via GEM ioctl.
1144  *
1145  * Returns:
1146  * 0 for success or a negative error code on failure.
1147  */
amdgpu_bo_set_metadata(struct amdgpu_bo * bo,void * metadata,uint32_t metadata_size,uint64_t flags)1148 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
1149 			    uint32_t metadata_size, uint64_t flags)
1150 {
1151 	struct amdgpu_bo_user *ubo;
1152 	void *buffer;
1153 
1154 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1155 	ubo = to_amdgpu_bo_user(bo);
1156 	if (!metadata_size) {
1157 		if (ubo->metadata_size) {
1158 			kfree(ubo->metadata);
1159 			ubo->metadata = NULL;
1160 			ubo->metadata_size = 0;
1161 		}
1162 		return 0;
1163 	}
1164 
1165 	if (metadata == NULL)
1166 		return -EINVAL;
1167 
1168 	buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1169 	if (buffer == NULL)
1170 		return -ENOMEM;
1171 
1172 	kfree(ubo->metadata);
1173 	ubo->metadata_flags = flags;
1174 	ubo->metadata = buffer;
1175 	ubo->metadata_size = metadata_size;
1176 
1177 	return 0;
1178 }
1179 
1180 /**
1181  * amdgpu_bo_get_metadata - get metadata
1182  * @bo: &amdgpu_bo buffer object
1183  * @buffer: returned metadata
1184  * @buffer_size: size of the buffer
1185  * @metadata_size: size of the returned metadata
1186  * @flags: flags of the returned metadata
1187  *
1188  * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1189  * less than metadata_size.
1190  * Used via GEM ioctl.
1191  *
1192  * Returns:
1193  * 0 for success or a negative error code on failure.
1194  */
amdgpu_bo_get_metadata(struct amdgpu_bo * bo,void * buffer,size_t buffer_size,uint32_t * metadata_size,uint64_t * flags)1195 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1196 			   size_t buffer_size, uint32_t *metadata_size,
1197 			   uint64_t *flags)
1198 {
1199 	struct amdgpu_bo_user *ubo;
1200 
1201 	if (!buffer && !metadata_size)
1202 		return -EINVAL;
1203 
1204 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1205 	ubo = to_amdgpu_bo_user(bo);
1206 	if (metadata_size)
1207 		*metadata_size = ubo->metadata_size;
1208 
1209 	if (buffer) {
1210 		if (buffer_size < ubo->metadata_size)
1211 			return -EINVAL;
1212 
1213 		if (ubo->metadata_size)
1214 			memcpy(buffer, ubo->metadata, ubo->metadata_size);
1215 	}
1216 
1217 	if (flags)
1218 		*flags = ubo->metadata_flags;
1219 
1220 	return 0;
1221 }
1222 
1223 /**
1224  * amdgpu_bo_move_notify - notification about a memory move
1225  * @bo: pointer to a buffer object
1226  * @evict: if this move is evicting the buffer from the graphics address space
1227  * @new_mem: new information of the bufer object
1228  *
1229  * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1230  * bookkeeping.
1231  * TTM driver callback which is called when ttm moves a buffer.
1232  */
amdgpu_bo_move_notify(struct ttm_buffer_object * bo,bool evict,struct ttm_resource * new_mem)1233 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1234 			   bool evict,
1235 			   struct ttm_resource *new_mem)
1236 {
1237 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1238 	struct amdgpu_bo *abo;
1239 	struct ttm_resource *old_mem = bo->resource;
1240 
1241 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1242 		return;
1243 
1244 	abo = ttm_to_amdgpu_bo(bo);
1245 	amdgpu_vm_bo_invalidate(adev, abo, evict);
1246 
1247 	amdgpu_bo_kunmap(abo);
1248 
1249 	if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1250 	    bo->resource->mem_type != TTM_PL_SYSTEM)
1251 		dma_buf_move_notify(abo->tbo.base.dma_buf);
1252 
1253 	/* remember the eviction */
1254 	if (evict)
1255 		atomic64_inc(&adev->num_evictions);
1256 
1257 	/* update statistics */
1258 	if (!new_mem)
1259 		return;
1260 
1261 	/* move_notify is called before move happens */
1262 	trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
1263 }
1264 
amdgpu_bo_get_memory(struct amdgpu_bo * bo,uint64_t * vram_mem,uint64_t * gtt_mem,uint64_t * cpu_mem)1265 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
1266 				uint64_t *gtt_mem, uint64_t *cpu_mem)
1267 {
1268 	unsigned int domain;
1269 
1270 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1271 	switch (domain) {
1272 	case AMDGPU_GEM_DOMAIN_VRAM:
1273 		*vram_mem += amdgpu_bo_size(bo);
1274 		break;
1275 	case AMDGPU_GEM_DOMAIN_GTT:
1276 		*gtt_mem += amdgpu_bo_size(bo);
1277 		break;
1278 	case AMDGPU_GEM_DOMAIN_CPU:
1279 	default:
1280 		*cpu_mem += amdgpu_bo_size(bo);
1281 		break;
1282 	}
1283 }
1284 
1285 /**
1286  * amdgpu_bo_release_notify - notification about a BO being released
1287  * @bo: pointer to a buffer object
1288  *
1289  * Wipes VRAM buffers whose contents should not be leaked before the
1290  * memory is released.
1291  */
amdgpu_bo_release_notify(struct ttm_buffer_object * bo)1292 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1293 {
1294 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1295 	struct dma_fence *fence = NULL;
1296 	struct amdgpu_bo *abo;
1297 	int r;
1298 
1299 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1300 		return;
1301 
1302 	abo = ttm_to_amdgpu_bo(bo);
1303 
1304 	if (abo->kfd_bo)
1305 		amdgpu_amdkfd_release_notify(abo);
1306 
1307 	/* We only remove the fence if the resv has individualized. */
1308 	WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1309 			&& bo->base.resv != &bo->base._resv);
1310 	if (bo->base.resv == &bo->base._resv)
1311 		amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1312 
1313 	if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
1314 	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
1315 	    adev->in_suspend || adev->shutdown)
1316 		return;
1317 
1318 	if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
1319 		return;
1320 
1321 	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);
1322 	if (!WARN_ON(r)) {
1323 		amdgpu_bo_fence(abo, fence, false);
1324 		dma_fence_put(fence);
1325 	}
1326 
1327 	dma_resv_unlock(bo->base.resv);
1328 }
1329 
1330 /**
1331  * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1332  * @bo: pointer to a buffer object
1333  *
1334  * Notifies the driver we are taking a fault on this BO and have reserved it,
1335  * also performs bookkeeping.
1336  * TTM driver callback for dealing with vm faults.
1337  *
1338  * Returns:
1339  * 0 for success or a negative error code on failure.
1340  */
amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object * bo)1341 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1342 {
1343 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1344 	struct ttm_operation_ctx ctx = { false, false };
1345 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1346 	unsigned long offset;
1347 	int r;
1348 
1349 	/* Remember that this BO was accessed by the CPU */
1350 	abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1351 
1352 	if (bo->resource->mem_type != TTM_PL_VRAM)
1353 		return 0;
1354 
1355 	offset = bo->resource->start << PAGE_SHIFT;
1356 	if ((offset + bo->base.size) <= adev->gmc.visible_vram_size)
1357 		return 0;
1358 
1359 	/* Can't move a pinned BO to visible VRAM */
1360 	if (abo->tbo.pin_count > 0)
1361 		return VM_FAULT_SIGBUS;
1362 
1363 	/* hurrah the memory is not visible ! */
1364 	atomic64_inc(&adev->num_vram_cpu_page_faults);
1365 	amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1366 					AMDGPU_GEM_DOMAIN_GTT);
1367 
1368 	/* Avoid costly evictions; only set GTT as a busy placement */
1369 	abo->placement.num_busy_placement = 1;
1370 	abo->placement.busy_placement = &abo->placements[1];
1371 
1372 	r = ttm_bo_validate(bo, &abo->placement, &ctx);
1373 	if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1374 		return VM_FAULT_NOPAGE;
1375 	else if (unlikely(r))
1376 		return VM_FAULT_SIGBUS;
1377 
1378 	offset = bo->resource->start << PAGE_SHIFT;
1379 	/* this should never happen */
1380 	if (bo->resource->mem_type == TTM_PL_VRAM &&
1381 	    (offset + bo->base.size) > adev->gmc.visible_vram_size)
1382 		return VM_FAULT_SIGBUS;
1383 
1384 	ttm_bo_move_to_lru_tail_unlocked(bo);
1385 	return 0;
1386 }
1387 
1388 /**
1389  * amdgpu_bo_fence - add fence to buffer object
1390  *
1391  * @bo: buffer object in question
1392  * @fence: fence to add
1393  * @shared: true if fence should be added shared
1394  *
1395  */
amdgpu_bo_fence(struct amdgpu_bo * bo,struct dma_fence * fence,bool shared)1396 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1397 		     bool shared)
1398 {
1399 	struct dma_resv *resv = bo->tbo.base.resv;
1400 	int r;
1401 
1402 	r = dma_resv_reserve_fences(resv, 1);
1403 	if (r) {
1404 		/* As last resort on OOM we block for the fence */
1405 		dma_fence_wait(fence, false);
1406 		return;
1407 	}
1408 
1409 	dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ :
1410 			   DMA_RESV_USAGE_WRITE);
1411 }
1412 
1413 /**
1414  * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1415  *
1416  * @adev: amdgpu device pointer
1417  * @resv: reservation object to sync to
1418  * @sync_mode: synchronization mode
1419  * @owner: fence owner
1420  * @intr: Whether the wait is interruptible
1421  *
1422  * Extract the fences from the reservation object and waits for them to finish.
1423  *
1424  * Returns:
1425  * 0 on success, errno otherwise.
1426  */
amdgpu_bo_sync_wait_resv(struct amdgpu_device * adev,struct dma_resv * resv,enum amdgpu_sync_mode sync_mode,void * owner,bool intr)1427 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1428 			     enum amdgpu_sync_mode sync_mode, void *owner,
1429 			     bool intr)
1430 {
1431 	struct amdgpu_sync sync;
1432 	int r;
1433 
1434 	amdgpu_sync_create(&sync);
1435 	amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1436 	r = amdgpu_sync_wait(&sync, intr);
1437 	amdgpu_sync_free(&sync);
1438 	return r;
1439 }
1440 
1441 /**
1442  * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1443  * @bo: buffer object to wait for
1444  * @owner: fence owner
1445  * @intr: Whether the wait is interruptible
1446  *
1447  * Wrapper to wait for fences in a BO.
1448  * Returns:
1449  * 0 on success, errno otherwise.
1450  */
amdgpu_bo_sync_wait(struct amdgpu_bo * bo,void * owner,bool intr)1451 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1452 {
1453 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1454 
1455 	return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1456 					AMDGPU_SYNC_NE_OWNER, owner, intr);
1457 }
1458 
1459 /**
1460  * amdgpu_bo_gpu_offset - return GPU offset of bo
1461  * @bo:	amdgpu object for which we query the offset
1462  *
1463  * Note: object should either be pinned or reserved when calling this
1464  * function, it might be useful to add check for this for debugging.
1465  *
1466  * Returns:
1467  * current GPU offset of the object.
1468  */
amdgpu_bo_gpu_offset(struct amdgpu_bo * bo)1469 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1470 {
1471 	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
1472 	WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1473 		     !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1474 	WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
1475 	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
1476 		     !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1477 
1478 	return amdgpu_bo_gpu_offset_no_check(bo);
1479 }
1480 
1481 /**
1482  * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1483  * @bo:	amdgpu object for which we query the offset
1484  *
1485  * Returns:
1486  * current GPU offset of the object without raising warnings.
1487  */
amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo * bo)1488 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1489 {
1490 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1491 	uint64_t offset;
1492 
1493 	offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1494 		 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1495 
1496 	return amdgpu_gmc_sign_extend(offset);
1497 }
1498 
1499 /**
1500  * amdgpu_bo_get_preferred_domain - get preferred domain
1501  * @adev: amdgpu device object
1502  * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1503  *
1504  * Returns:
1505  * Which of the allowed domains is preferred for allocating the BO.
1506  */
amdgpu_bo_get_preferred_domain(struct amdgpu_device * adev,uint32_t domain)1507 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
1508 					    uint32_t domain)
1509 {
1510 	if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
1511 	    ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
1512 		domain = AMDGPU_GEM_DOMAIN_VRAM;
1513 		if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1514 			domain = AMDGPU_GEM_DOMAIN_GTT;
1515 	}
1516 	return domain;
1517 }
1518 
1519 #if defined(CONFIG_DEBUG_FS)
1520 #define amdgpu_bo_print_flag(m, bo, flag)		        \
1521 	do {							\
1522 		if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) {	\
1523 			seq_printf((m), " " #flag);		\
1524 		}						\
1525 	} while (0)
1526 
1527 /**
1528  * amdgpu_bo_print_info - print BO info in debugfs file
1529  *
1530  * @id: Index or Id of the BO
1531  * @bo: Requested BO for printing info
1532  * @m: debugfs file
1533  *
1534  * Print BO information in debugfs file
1535  *
1536  * Returns:
1537  * Size of the BO in bytes.
1538  */
amdgpu_bo_print_info(int id,struct amdgpu_bo * bo,struct seq_file * m)1539 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1540 {
1541 	struct dma_buf_attachment *attachment;
1542 	struct dma_buf *dma_buf;
1543 	unsigned int domain;
1544 	const char *placement;
1545 	unsigned int pin_count;
1546 	u64 size;
1547 
1548 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1549 	switch (domain) {
1550 	case AMDGPU_GEM_DOMAIN_VRAM:
1551 		placement = "VRAM";
1552 		break;
1553 	case AMDGPU_GEM_DOMAIN_GTT:
1554 		placement = " GTT";
1555 		break;
1556 	case AMDGPU_GEM_DOMAIN_CPU:
1557 	default:
1558 		placement = " CPU";
1559 		break;
1560 	}
1561 
1562 	size = amdgpu_bo_size(bo);
1563 	seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1564 			id, size, placement);
1565 
1566 	pin_count = READ_ONCE(bo->tbo.pin_count);
1567 	if (pin_count)
1568 		seq_printf(m, " pin count %d", pin_count);
1569 
1570 	dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1571 	attachment = READ_ONCE(bo->tbo.base.import_attach);
1572 
1573 	if (attachment)
1574 		seq_printf(m, " imported from %p", dma_buf);
1575 	else if (dma_buf)
1576 		seq_printf(m, " exported as %p", dma_buf);
1577 
1578 	amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1579 	amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1580 	amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1581 	amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1582 	amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1583 	amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1584 	amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
1585 
1586 	seq_puts(m, "\n");
1587 
1588 	return size;
1589 }
1590 #endif
1591