1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2014-2018 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include <linux/dma-buf.h>
24 #include <linux/list.h>
25 #include <linux/pagemap.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/task.h>
28 #include <drm/ttm/ttm_tt.h>
29 
30 #include <drm/drm_exec.h>
31 
32 #include "amdgpu_object.h"
33 #include "amdgpu_gem.h"
34 #include "amdgpu_vm.h"
35 #include "amdgpu_hmm.h"
36 #include "amdgpu_amdkfd.h"
37 #include "amdgpu_dma_buf.h"
38 #include <uapi/linux/kfd_ioctl.h>
39 #include "amdgpu_xgmi.h"
40 #include "kfd_priv.h"
41 #include "kfd_smi_events.h"
42 
43 /* Userptr restore delay, just long enough to allow consecutive VM
44  * changes to accumulate
45  */
46 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
47 
48 /*
49  * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
50  * BO chunk
51  */
52 #define VRAM_AVAILABLITY_ALIGN (1 << 21)
53 
54 /* Impose limit on how much memory KFD can use */
55 static struct {
56 	uint64_t max_system_mem_limit;
57 	uint64_t max_ttm_mem_limit;
58 	int64_t system_mem_used;
59 	int64_t ttm_mem_used;
60 	spinlock_t mem_limit_lock;
61 } kfd_mem_limit;
62 
63 static const char * const domain_bit_to_string[] = {
64 		"CPU",
65 		"GTT",
66 		"VRAM",
67 		"GDS",
68 		"GWS",
69 		"OA"
70 };
71 
72 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
73 
74 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
75 
kfd_mem_is_attached(struct amdgpu_vm * avm,struct kgd_mem * mem)76 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
77 		struct kgd_mem *mem)
78 {
79 	struct kfd_mem_attachment *entry;
80 
81 	list_for_each_entry(entry, &mem->attachments, list)
82 		if (entry->bo_va->base.vm == avm)
83 			return true;
84 
85 	return false;
86 }
87 
88 /**
89  * reuse_dmamap() - Check whether adev can share the original
90  * userptr BO
91  *
92  * If both adev and bo_adev are in direct mapping or
93  * in the same iommu group, they can share the original BO.
94  *
95  * @adev: Device to which can or cannot share the original BO
96  * @bo_adev: Device to which allocated BO belongs to
97  *
98  * Return: returns true if adev can share original userptr BO,
99  * false otherwise.
100  */
reuse_dmamap(struct amdgpu_device * adev,struct amdgpu_device * bo_adev)101 static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
102 {
103 	return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
104 			(adev->dev->iommu_group == bo_adev->dev->iommu_group);
105 }
106 
107 /* Set memory usage limits. Current, limits are
108  *  System (TTM + userptr) memory - 15/16th System RAM
109  *  TTM memory - 3/8th System RAM
110  */
amdgpu_amdkfd_gpuvm_init_mem_limits(void)111 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
112 {
113 	struct sysinfo si;
114 	uint64_t mem;
115 
116 	if (kfd_mem_limit.max_system_mem_limit)
117 		return;
118 
119 	si_meminfo(&si);
120 	mem = si.freeram - si.freehigh;
121 	mem *= si.mem_unit;
122 
123 	spin_lock_init(&kfd_mem_limit.mem_limit_lock);
124 	kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
125 	kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
126 	pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
127 		(kfd_mem_limit.max_system_mem_limit >> 20),
128 		(kfd_mem_limit.max_ttm_mem_limit >> 20));
129 }
130 
amdgpu_amdkfd_reserve_system_mem(uint64_t size)131 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
132 {
133 	kfd_mem_limit.system_mem_used += size;
134 }
135 
136 /* Estimate page table size needed to represent a given memory size
137  *
138  * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
139  * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
140  * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
141  * for 2MB pages for TLB efficiency. However, small allocations and
142  * fragmented system memory still need some 4KB pages. We choose a
143  * compromise that should work in most cases without reserving too
144  * much memory for page tables unnecessarily (factor 16K, >> 14).
145  */
146 
147 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
148 
149 /**
150  * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
151  * of buffer.
152  *
153  * @adev: Device to which allocated BO belongs to
154  * @size: Size of buffer, in bytes, encapsulated by B0. This should be
155  * equivalent to amdgpu_bo_size(BO)
156  * @alloc_flag: Flag used in allocating a BO as noted above
157  * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
158  * managed as one compute node in driver for app
159  *
160  * Return:
161  *	returns -ENOMEM in case of error, ZERO otherwise
162  */
amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device * adev,uint64_t size,u32 alloc_flag,int8_t xcp_id)163 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
164 		uint64_t size, u32 alloc_flag, int8_t xcp_id)
165 {
166 	uint64_t reserved_for_pt =
167 		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
168 	size_t system_mem_needed, ttm_mem_needed, vram_needed;
169 	int ret = 0;
170 	uint64_t vram_size = 0;
171 
172 	system_mem_needed = 0;
173 	ttm_mem_needed = 0;
174 	vram_needed = 0;
175 	if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
176 		system_mem_needed = size;
177 		ttm_mem_needed = size;
178 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
179 		/*
180 		 * Conservatively round up the allocation requirement to 2 MB
181 		 * to avoid fragmentation caused by 4K allocations in the tail
182 		 * 2M BO chunk.
183 		 */
184 		vram_needed = size;
185 		/*
186 		 * For GFX 9.4.3, get the VRAM size from XCP structs
187 		 */
188 		if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
189 			return -EINVAL;
190 
191 		vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
192 		if (adev->gmc.is_app_apu) {
193 			system_mem_needed = size;
194 			ttm_mem_needed = size;
195 		}
196 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
197 		system_mem_needed = size;
198 	} else if (!(alloc_flag &
199 				(KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
200 				 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
201 		pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
202 		return -ENOMEM;
203 	}
204 
205 	spin_lock(&kfd_mem_limit.mem_limit_lock);
206 
207 	if (kfd_mem_limit.system_mem_used + system_mem_needed >
208 	    kfd_mem_limit.max_system_mem_limit)
209 		pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
210 
211 	if ((kfd_mem_limit.system_mem_used + system_mem_needed >
212 	     kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
213 	    (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
214 	     kfd_mem_limit.max_ttm_mem_limit) ||
215 	    (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
216 	     vram_size - reserved_for_pt)) {
217 		ret = -ENOMEM;
218 		goto release;
219 	}
220 
221 	/* Update memory accounting by decreasing available system
222 	 * memory, TTM memory and GPU memory as computed above
223 	 */
224 	WARN_ONCE(vram_needed && !adev,
225 		  "adev reference can't be null when vram is used");
226 	if (adev && xcp_id >= 0) {
227 		adev->kfd.vram_used[xcp_id] += vram_needed;
228 		adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
229 				vram_needed :
230 				ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
231 	}
232 	kfd_mem_limit.system_mem_used += system_mem_needed;
233 	kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
234 
235 release:
236 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
237 	return ret;
238 }
239 
amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device * adev,uint64_t size,u32 alloc_flag,int8_t xcp_id)240 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
241 		uint64_t size, u32 alloc_flag, int8_t xcp_id)
242 {
243 	spin_lock(&kfd_mem_limit.mem_limit_lock);
244 
245 	if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
246 		kfd_mem_limit.system_mem_used -= size;
247 		kfd_mem_limit.ttm_mem_used -= size;
248 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
249 		WARN_ONCE(!adev,
250 			  "adev reference can't be null when alloc mem flags vram is set");
251 		if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
252 			goto release;
253 
254 		if (adev) {
255 			adev->kfd.vram_used[xcp_id] -= size;
256 			if (adev->gmc.is_app_apu) {
257 				adev->kfd.vram_used_aligned[xcp_id] -= size;
258 				kfd_mem_limit.system_mem_used -= size;
259 				kfd_mem_limit.ttm_mem_used -= size;
260 			} else {
261 				adev->kfd.vram_used_aligned[xcp_id] -=
262 					ALIGN(size, VRAM_AVAILABLITY_ALIGN);
263 			}
264 		}
265 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
266 		kfd_mem_limit.system_mem_used -= size;
267 	} else if (!(alloc_flag &
268 				(KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
269 				 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
270 		pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
271 		goto release;
272 	}
273 	WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
274 		  "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
275 	WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
276 		  "KFD TTM memory accounting unbalanced");
277 	WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
278 		  "KFD system memory accounting unbalanced");
279 
280 release:
281 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
282 }
283 
amdgpu_amdkfd_release_notify(struct amdgpu_bo * bo)284 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
285 {
286 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
287 	u32 alloc_flags = bo->kfd_bo->alloc_flags;
288 	u64 size = amdgpu_bo_size(bo);
289 
290 	amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
291 					  bo->xcp_id);
292 
293 	kfree(bo->kfd_bo);
294 }
295 
296 /**
297  * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
298  * about USERPTR or DOOREBELL or MMIO BO.
299  *
300  * @adev: Device for which dmamap BO is being created
301  * @mem: BO of peer device that is being DMA mapped. Provides parameters
302  *	 in building the dmamap BO
303  * @bo_out: Output parameter updated with handle of dmamap BO
304  */
305 static int
create_dmamap_sg_bo(struct amdgpu_device * adev,struct kgd_mem * mem,struct amdgpu_bo ** bo_out)306 create_dmamap_sg_bo(struct amdgpu_device *adev,
307 		 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
308 {
309 	struct drm_gem_object *gem_obj;
310 	int ret;
311 	uint64_t flags = 0;
312 
313 	ret = amdgpu_bo_reserve(mem->bo, false);
314 	if (ret)
315 		return ret;
316 
317 	if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
318 		flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
319 					AMDGPU_GEM_CREATE_UNCACHED);
320 
321 	ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
322 			AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
323 			ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
324 
325 	amdgpu_bo_unreserve(mem->bo);
326 
327 	if (ret) {
328 		pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
329 		return -EINVAL;
330 	}
331 
332 	*bo_out = gem_to_amdgpu_bo(gem_obj);
333 	(*bo_out)->parent = amdgpu_bo_ref(mem->bo);
334 	return ret;
335 }
336 
337 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
338  *  reservation object.
339  *
340  * @bo: [IN] Remove eviction fence(s) from this BO
341  * @ef: [IN] This eviction fence is removed if it
342  *  is present in the shared list.
343  *
344  * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
345  */
amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo * bo,struct amdgpu_amdkfd_fence * ef)346 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
347 					struct amdgpu_amdkfd_fence *ef)
348 {
349 	struct dma_fence *replacement;
350 
351 	if (!ef)
352 		return -EINVAL;
353 
354 	/* TODO: Instead of block before we should use the fence of the page
355 	 * table update and TLB flush here directly.
356 	 */
357 	replacement = dma_fence_get_stub();
358 	dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
359 				replacement, DMA_RESV_USAGE_BOOKKEEP);
360 	dma_fence_put(replacement);
361 	return 0;
362 }
363 
amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo * bo)364 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
365 {
366 	struct amdgpu_bo *root = bo;
367 	struct amdgpu_vm_bo_base *vm_bo;
368 	struct amdgpu_vm *vm;
369 	struct amdkfd_process_info *info;
370 	struct amdgpu_amdkfd_fence *ef;
371 	int ret;
372 
373 	/* we can always get vm_bo from root PD bo.*/
374 	while (root->parent)
375 		root = root->parent;
376 
377 	vm_bo = root->vm_bo;
378 	if (!vm_bo)
379 		return 0;
380 
381 	vm = vm_bo->vm;
382 	if (!vm)
383 		return 0;
384 
385 	info = vm->process_info;
386 	if (!info || !info->eviction_fence)
387 		return 0;
388 
389 	ef = container_of(dma_fence_get(&info->eviction_fence->base),
390 			struct amdgpu_amdkfd_fence, base);
391 
392 	BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
393 	ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
394 	dma_resv_unlock(bo->tbo.base.resv);
395 
396 	dma_fence_put(&ef->base);
397 	return ret;
398 }
399 
amdgpu_amdkfd_bo_validate(struct amdgpu_bo * bo,uint32_t domain,bool wait)400 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
401 				     bool wait)
402 {
403 	struct ttm_operation_ctx ctx = { false, false };
404 	int ret;
405 
406 	if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
407 		 "Called with userptr BO"))
408 		return -EINVAL;
409 
410 	amdgpu_bo_placement_from_domain(bo, domain);
411 
412 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
413 	if (ret)
414 		goto validate_fail;
415 	if (wait)
416 		amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
417 
418 validate_fail:
419 	return ret;
420 }
421 
amdgpu_amdkfd_validate_vm_bo(void * _unused,struct amdgpu_bo * bo)422 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
423 {
424 	return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
425 }
426 
427 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
428  *
429  * Page directories are not updated here because huge page handling
430  * during page table updates can invalidate page directory entries
431  * again. Page directories are only updated after updating page
432  * tables.
433  */
vm_validate_pt_pd_bos(struct amdgpu_vm * vm)434 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
435 {
436 	struct amdgpu_bo *pd = vm->root.bo;
437 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
438 	int ret;
439 
440 	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
441 	if (ret) {
442 		pr_err("failed to validate PT BOs\n");
443 		return ret;
444 	}
445 
446 	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
447 
448 	return 0;
449 }
450 
vm_update_pds(struct amdgpu_vm * vm,struct amdgpu_sync * sync)451 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
452 {
453 	struct amdgpu_bo *pd = vm->root.bo;
454 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
455 	int ret;
456 
457 	ret = amdgpu_vm_update_pdes(adev, vm, false);
458 	if (ret)
459 		return ret;
460 
461 	return amdgpu_sync_fence(sync, vm->last_update);
462 }
463 
get_pte_flags(struct amdgpu_device * adev,struct kgd_mem * mem)464 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
465 {
466 	uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
467 				 AMDGPU_VM_MTYPE_DEFAULT;
468 
469 	if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
470 		mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
471 	if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
472 		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
473 
474 	return amdgpu_gem_va_map_flags(adev, mapping_flags);
475 }
476 
477 /**
478  * create_sg_table() - Create an sg_table for a contiguous DMA addr range
479  * @addr: The starting address to point to
480  * @size: Size of memory area in bytes being pointed to
481  *
482  * Allocates an instance of sg_table and initializes it to point to memory
483  * area specified by input parameters. The address used to build is assumed
484  * to be DMA mapped, if needed.
485  *
486  * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
487  * because they are physically contiguous.
488  *
489  * Return: Initialized instance of SG Table or NULL
490  */
create_sg_table(uint64_t addr,uint32_t size)491 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
492 {
493 	struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
494 
495 	if (!sg)
496 		return NULL;
497 	if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
498 		kfree(sg);
499 		return NULL;
500 	}
501 	sg_dma_address(sg->sgl) = addr;
502 	sg->sgl->length = size;
503 #ifdef CONFIG_NEED_SG_DMA_LENGTH
504 	sg->sgl->dma_length = size;
505 #endif
506 	return sg;
507 }
508 
509 static int
kfd_mem_dmamap_userptr(struct kgd_mem * mem,struct kfd_mem_attachment * attachment)510 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
511 		       struct kfd_mem_attachment *attachment)
512 {
513 	enum dma_data_direction direction =
514 		mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
515 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
516 	struct ttm_operation_ctx ctx = {.interruptible = true};
517 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
518 	struct amdgpu_device *adev = attachment->adev;
519 	struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
520 	struct ttm_tt *ttm = bo->tbo.ttm;
521 	int ret;
522 
523 	if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
524 		return -EINVAL;
525 
526 	ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
527 	if (unlikely(!ttm->sg))
528 		return -ENOMEM;
529 
530 	/* Same sequence as in amdgpu_ttm_tt_pin_userptr */
531 	ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
532 					ttm->num_pages, 0,
533 					(u64)ttm->num_pages << PAGE_SHIFT,
534 					GFP_KERNEL);
535 	if (unlikely(ret))
536 		goto free_sg;
537 
538 	ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
539 	if (unlikely(ret))
540 		goto release_sg;
541 
542 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
543 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
544 	if (ret)
545 		goto unmap_sg;
546 
547 	return 0;
548 
549 unmap_sg:
550 	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
551 release_sg:
552 	pr_err("DMA map userptr failed: %d\n", ret);
553 	sg_free_table(ttm->sg);
554 free_sg:
555 	kfree(ttm->sg);
556 	ttm->sg = NULL;
557 	return ret;
558 }
559 
560 static int
kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment * attachment)561 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
562 {
563 	struct ttm_operation_ctx ctx = {.interruptible = true};
564 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
565 	int ret;
566 
567 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
568 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
569 	if (ret)
570 		return ret;
571 
572 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
573 	return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
574 }
575 
576 /**
577  * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
578  * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
579  * @attachment: Virtual address attachment of the BO on accessing device
580  *
581  * An access request from the device that owns DOORBELL does not require DMA mapping.
582  * This is because the request doesn't go through PCIe root complex i.e. it instead
583  * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
584  *
585  * In contrast, all access requests for MMIO need to be DMA mapped without regard to
586  * device ownership. This is because access requests for MMIO go through PCIe root
587  * complex.
588  *
589  * This is accomplished in two steps:
590  *   - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
591  *         in updating requesting device's page table
592  *   - Signal TTM to mark memory pointed to by requesting device's BO as GPU
593  *         accessible. This allows an update of requesting device's page table
594  *         with entries associated with DOOREBELL or MMIO memory
595  *
596  * This method is invoked in the following contexts:
597  *   - Mapping of DOORBELL or MMIO BO of same or peer device
598  *   - Validating an evicted DOOREBELL or MMIO BO on device seeking access
599  *
600  * Return: ZERO if successful, NON-ZERO otherwise
601  */
602 static int
kfd_mem_dmamap_sg_bo(struct kgd_mem * mem,struct kfd_mem_attachment * attachment)603 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
604 		     struct kfd_mem_attachment *attachment)
605 {
606 	struct ttm_operation_ctx ctx = {.interruptible = true};
607 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
608 	struct amdgpu_device *adev = attachment->adev;
609 	struct ttm_tt *ttm = bo->tbo.ttm;
610 	enum dma_data_direction dir;
611 	dma_addr_t dma_addr;
612 	bool mmio;
613 	int ret;
614 
615 	/* Expect SG Table of dmapmap BO to be NULL */
616 	mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
617 	if (unlikely(ttm->sg)) {
618 		pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
619 		return -EINVAL;
620 	}
621 
622 	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
623 			DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
624 	dma_addr = mem->bo->tbo.sg->sgl->dma_address;
625 	pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
626 	pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
627 	dma_addr = dma_map_resource(adev->dev, dma_addr,
628 			mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
629 	ret = dma_mapping_error(adev->dev, dma_addr);
630 	if (unlikely(ret))
631 		return ret;
632 	pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
633 
634 	ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
635 	if (unlikely(!ttm->sg)) {
636 		ret = -ENOMEM;
637 		goto unmap_sg;
638 	}
639 
640 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
641 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
642 	if (unlikely(ret))
643 		goto free_sg;
644 
645 	return ret;
646 
647 free_sg:
648 	sg_free_table(ttm->sg);
649 	kfree(ttm->sg);
650 	ttm->sg = NULL;
651 unmap_sg:
652 	dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
653 			   dir, DMA_ATTR_SKIP_CPU_SYNC);
654 	return ret;
655 }
656 
657 static int
kfd_mem_dmamap_attachment(struct kgd_mem * mem,struct kfd_mem_attachment * attachment)658 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
659 			  struct kfd_mem_attachment *attachment)
660 {
661 	switch (attachment->type) {
662 	case KFD_MEM_ATT_SHARED:
663 		return 0;
664 	case KFD_MEM_ATT_USERPTR:
665 		return kfd_mem_dmamap_userptr(mem, attachment);
666 	case KFD_MEM_ATT_DMABUF:
667 		return kfd_mem_dmamap_dmabuf(attachment);
668 	case KFD_MEM_ATT_SG:
669 		return kfd_mem_dmamap_sg_bo(mem, attachment);
670 	default:
671 		WARN_ON_ONCE(1);
672 	}
673 	return -EINVAL;
674 }
675 
676 static void
kfd_mem_dmaunmap_userptr(struct kgd_mem * mem,struct kfd_mem_attachment * attachment)677 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
678 			 struct kfd_mem_attachment *attachment)
679 {
680 	enum dma_data_direction direction =
681 		mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
682 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
683 	struct ttm_operation_ctx ctx = {.interruptible = false};
684 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
685 	struct amdgpu_device *adev = attachment->adev;
686 	struct ttm_tt *ttm = bo->tbo.ttm;
687 
688 	if (unlikely(!ttm->sg))
689 		return;
690 
691 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
692 	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
693 
694 	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
695 	sg_free_table(ttm->sg);
696 	kfree(ttm->sg);
697 	ttm->sg = NULL;
698 }
699 
700 static void
kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment * attachment)701 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
702 {
703 	/* This is a no-op. We don't want to trigger eviction fences when
704 	 * unmapping DMABufs. Therefore the invalidation (moving to system
705 	 * domain) is done in kfd_mem_dmamap_dmabuf.
706 	 */
707 }
708 
709 /**
710  * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
711  * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
712  * @attachment: Virtual address attachment of the BO on accessing device
713  *
714  * The method performs following steps:
715  *   - Signal TTM to mark memory pointed to by BO as GPU inaccessible
716  *   - Free SG Table that is used to encapsulate DMA mapped memory of
717  *          peer device's DOORBELL or MMIO memory
718  *
719  * This method is invoked in the following contexts:
720  *     UNMapping of DOORBELL or MMIO BO on a device having access to its memory
721  *     Eviction of DOOREBELL or MMIO BO on device having access to its memory
722  *
723  * Return: void
724  */
725 static void
kfd_mem_dmaunmap_sg_bo(struct kgd_mem * mem,struct kfd_mem_attachment * attachment)726 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
727 		       struct kfd_mem_attachment *attachment)
728 {
729 	struct ttm_operation_ctx ctx = {.interruptible = true};
730 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
731 	struct amdgpu_device *adev = attachment->adev;
732 	struct ttm_tt *ttm = bo->tbo.ttm;
733 	enum dma_data_direction dir;
734 
735 	if (unlikely(!ttm->sg)) {
736 		pr_err("SG Table of BO is UNEXPECTEDLY NULL");
737 		return;
738 	}
739 
740 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
741 	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
742 
743 	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
744 				DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
745 	dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
746 			ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
747 	sg_free_table(ttm->sg);
748 	kfree(ttm->sg);
749 	ttm->sg = NULL;
750 	bo->tbo.sg = NULL;
751 }
752 
753 static void
kfd_mem_dmaunmap_attachment(struct kgd_mem * mem,struct kfd_mem_attachment * attachment)754 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
755 			    struct kfd_mem_attachment *attachment)
756 {
757 	switch (attachment->type) {
758 	case KFD_MEM_ATT_SHARED:
759 		break;
760 	case KFD_MEM_ATT_USERPTR:
761 		kfd_mem_dmaunmap_userptr(mem, attachment);
762 		break;
763 	case KFD_MEM_ATT_DMABUF:
764 		kfd_mem_dmaunmap_dmabuf(attachment);
765 		break;
766 	case KFD_MEM_ATT_SG:
767 		kfd_mem_dmaunmap_sg_bo(mem, attachment);
768 		break;
769 	default:
770 		WARN_ON_ONCE(1);
771 	}
772 }
773 
kfd_mem_export_dmabuf(struct kgd_mem * mem)774 static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
775 {
776 	if (!mem->dmabuf) {
777 		struct dma_buf *ret = amdgpu_gem_prime_export(
778 			&mem->bo->tbo.base,
779 			mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
780 				DRM_RDWR : 0);
781 		if (IS_ERR(ret))
782 			return PTR_ERR(ret);
783 		mem->dmabuf = ret;
784 	}
785 
786 	return 0;
787 }
788 
789 static int
kfd_mem_attach_dmabuf(struct amdgpu_device * adev,struct kgd_mem * mem,struct amdgpu_bo ** bo)790 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
791 		      struct amdgpu_bo **bo)
792 {
793 	struct drm_gem_object *gobj;
794 	int ret;
795 
796 	ret = kfd_mem_export_dmabuf(mem);
797 	if (ret)
798 		return ret;
799 
800 	gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
801 	if (IS_ERR(gobj))
802 		return PTR_ERR(gobj);
803 
804 	*bo = gem_to_amdgpu_bo(gobj);
805 	(*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
806 
807 	return 0;
808 }
809 
810 /* kfd_mem_attach - Add a BO to a VM
811  *
812  * Everything that needs to bo done only once when a BO is first added
813  * to a VM. It can later be mapped and unmapped many times without
814  * repeating these steps.
815  *
816  * 0. Create BO for DMA mapping, if needed
817  * 1. Allocate and initialize BO VA entry data structure
818  * 2. Add BO to the VM
819  * 3. Determine ASIC-specific PTE flags
820  * 4. Alloc page tables and directories if needed
821  * 4a.  Validate new page tables and directories
822  */
kfd_mem_attach(struct amdgpu_device * adev,struct kgd_mem * mem,struct amdgpu_vm * vm,bool is_aql)823 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
824 		struct amdgpu_vm *vm, bool is_aql)
825 {
826 	struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
827 	unsigned long bo_size = mem->bo->tbo.base.size;
828 	uint64_t va = mem->va;
829 	struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
830 	struct amdgpu_bo *bo[2] = {NULL, NULL};
831 	bool same_hive = false;
832 	int i, ret;
833 
834 	if (!va) {
835 		pr_err("Invalid VA when adding BO to VM\n");
836 		return -EINVAL;
837 	}
838 
839 	/* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
840 	 *
841 	 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
842 	 * In contrast the access path of VRAM BOs depens upon the type of
843 	 * link that connects the peer device. Access over PCIe is allowed
844 	 * if peer device has large BAR. In contrast, access over xGMI is
845 	 * allowed for both small and large BAR configurations of peer device
846 	 */
847 	if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
848 	    ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
849 	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
850 	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
851 		if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
852 			same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
853 		if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
854 			return -EINVAL;
855 	}
856 
857 	for (i = 0; i <= is_aql; i++) {
858 		attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
859 		if (unlikely(!attachment[i])) {
860 			ret = -ENOMEM;
861 			goto unwind;
862 		}
863 
864 		pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
865 			 va + bo_size, vm);
866 
867 		if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
868 		    (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
869 			same_hive) {
870 			/* Mappings on the local GPU, or VRAM mappings in the
871 			 * local hive, or userptr mapping can reuse dma map
872 			 * address space share the original BO
873 			 */
874 			attachment[i]->type = KFD_MEM_ATT_SHARED;
875 			bo[i] = mem->bo;
876 			drm_gem_object_get(&bo[i]->tbo.base);
877 		} else if (i > 0) {
878 			/* Multiple mappings on the same GPU share the BO */
879 			attachment[i]->type = KFD_MEM_ATT_SHARED;
880 			bo[i] = bo[0];
881 			drm_gem_object_get(&bo[i]->tbo.base);
882 		} else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
883 			/* Create an SG BO to DMA-map userptrs on other GPUs */
884 			attachment[i]->type = KFD_MEM_ATT_USERPTR;
885 			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
886 			if (ret)
887 				goto unwind;
888 		/* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
889 		} else if (mem->bo->tbo.type == ttm_bo_type_sg) {
890 			WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
891 				    mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
892 				  "Handing invalid SG BO in ATTACH request");
893 			attachment[i]->type = KFD_MEM_ATT_SG;
894 			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
895 			if (ret)
896 				goto unwind;
897 		/* Enable acces to GTT and VRAM BOs of peer devices */
898 		} else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
899 			   mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
900 			attachment[i]->type = KFD_MEM_ATT_DMABUF;
901 			ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
902 			if (ret)
903 				goto unwind;
904 			pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
905 		} else {
906 			WARN_ONCE(true, "Handling invalid ATTACH request");
907 			ret = -EINVAL;
908 			goto unwind;
909 		}
910 
911 		/* Add BO to VM internal data structures */
912 		ret = amdgpu_bo_reserve(bo[i], false);
913 		if (ret) {
914 			pr_debug("Unable to reserve BO during memory attach");
915 			goto unwind;
916 		}
917 		attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
918 		amdgpu_bo_unreserve(bo[i]);
919 		if (unlikely(!attachment[i]->bo_va)) {
920 			ret = -ENOMEM;
921 			pr_err("Failed to add BO object to VM. ret == %d\n",
922 			       ret);
923 			goto unwind;
924 		}
925 		attachment[i]->va = va;
926 		attachment[i]->pte_flags = get_pte_flags(adev, mem);
927 		attachment[i]->adev = adev;
928 		list_add(&attachment[i]->list, &mem->attachments);
929 
930 		va += bo_size;
931 	}
932 
933 	return 0;
934 
935 unwind:
936 	for (; i >= 0; i--) {
937 		if (!attachment[i])
938 			continue;
939 		if (attachment[i]->bo_va) {
940 			amdgpu_bo_reserve(bo[i], true);
941 			amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
942 			amdgpu_bo_unreserve(bo[i]);
943 			list_del(&attachment[i]->list);
944 		}
945 		if (bo[i])
946 			drm_gem_object_put(&bo[i]->tbo.base);
947 		kfree(attachment[i]);
948 	}
949 	return ret;
950 }
951 
kfd_mem_detach(struct kfd_mem_attachment * attachment)952 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
953 {
954 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
955 
956 	pr_debug("\t remove VA 0x%llx in entry %p\n",
957 			attachment->va, attachment);
958 	amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
959 	drm_gem_object_put(&bo->tbo.base);
960 	list_del(&attachment->list);
961 	kfree(attachment);
962 }
963 
add_kgd_mem_to_kfd_bo_list(struct kgd_mem * mem,struct amdkfd_process_info * process_info,bool userptr)964 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
965 				struct amdkfd_process_info *process_info,
966 				bool userptr)
967 {
968 	mutex_lock(&process_info->lock);
969 	if (userptr)
970 		list_add_tail(&mem->validate_list,
971 			      &process_info->userptr_valid_list);
972 	else
973 		list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
974 	mutex_unlock(&process_info->lock);
975 }
976 
remove_kgd_mem_from_kfd_bo_list(struct kgd_mem * mem,struct amdkfd_process_info * process_info)977 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
978 		struct amdkfd_process_info *process_info)
979 {
980 	mutex_lock(&process_info->lock);
981 	list_del(&mem->validate_list);
982 	mutex_unlock(&process_info->lock);
983 }
984 
985 /* Initializes user pages. It registers the MMU notifier and validates
986  * the userptr BO in the GTT domain.
987  *
988  * The BO must already be on the userptr_valid_list. Otherwise an
989  * eviction and restore may happen that leaves the new BO unmapped
990  * with the user mode queues running.
991  *
992  * Takes the process_info->lock to protect against concurrent restore
993  * workers.
994  *
995  * Returns 0 for success, negative errno for errors.
996  */
init_user_pages(struct kgd_mem * mem,uint64_t user_addr,bool criu_resume)997 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
998 			   bool criu_resume)
999 {
1000 	struct amdkfd_process_info *process_info = mem->process_info;
1001 	struct amdgpu_bo *bo = mem->bo;
1002 	struct ttm_operation_ctx ctx = { true, false };
1003 	struct hmm_range *range;
1004 	int ret = 0;
1005 
1006 	mutex_lock(&process_info->lock);
1007 
1008 	ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1009 	if (ret) {
1010 		pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1011 		goto out;
1012 	}
1013 
1014 	ret = amdgpu_hmm_register(bo, user_addr);
1015 	if (ret) {
1016 		pr_err("%s: Failed to register MMU notifier: %d\n",
1017 		       __func__, ret);
1018 		goto out;
1019 	}
1020 
1021 	if (criu_resume) {
1022 		/*
1023 		 * During a CRIU restore operation, the userptr buffer objects
1024 		 * will be validated in the restore_userptr_work worker at a
1025 		 * later stage when it is scheduled by another ioctl called by
1026 		 * CRIU master process for the target pid for restore.
1027 		 */
1028 		mutex_lock(&process_info->notifier_lock);
1029 		mem->invalid++;
1030 		mutex_unlock(&process_info->notifier_lock);
1031 		mutex_unlock(&process_info->lock);
1032 		return 0;
1033 	}
1034 
1035 	ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1036 	if (ret) {
1037 		pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1038 		goto unregister_out;
1039 	}
1040 
1041 	ret = amdgpu_bo_reserve(bo, true);
1042 	if (ret) {
1043 		pr_err("%s: Failed to reserve BO\n", __func__);
1044 		goto release_out;
1045 	}
1046 	amdgpu_bo_placement_from_domain(bo, mem->domain);
1047 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1048 	if (ret)
1049 		pr_err("%s: failed to validate BO\n", __func__);
1050 	amdgpu_bo_unreserve(bo);
1051 
1052 release_out:
1053 	amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1054 unregister_out:
1055 	if (ret)
1056 		amdgpu_hmm_unregister(bo);
1057 out:
1058 	mutex_unlock(&process_info->lock);
1059 	return ret;
1060 }
1061 
1062 /* Reserving a BO and its page table BOs must happen atomically to
1063  * avoid deadlocks. Some operations update multiple VMs at once. Track
1064  * all the reservation info in a context structure. Optionally a sync
1065  * object can track VM updates.
1066  */
1067 struct bo_vm_reservation_context {
1068 	/* DRM execution context for the reservation */
1069 	struct drm_exec exec;
1070 	/* Number of VMs reserved */
1071 	unsigned int n_vms;
1072 	/* Pointer to sync object */
1073 	struct amdgpu_sync *sync;
1074 };
1075 
1076 enum bo_vm_match {
1077 	BO_VM_NOT_MAPPED = 0,	/* Match VMs where a BO is not mapped */
1078 	BO_VM_MAPPED,		/* Match VMs where a BO is mapped     */
1079 	BO_VM_ALL,		/* Match all VMs a BO was added to    */
1080 };
1081 
1082 /**
1083  * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1084  * @mem: KFD BO structure.
1085  * @vm: the VM to reserve.
1086  * @ctx: the struct that will be used in unreserve_bo_and_vms().
1087  */
reserve_bo_and_vm(struct kgd_mem * mem,struct amdgpu_vm * vm,struct bo_vm_reservation_context * ctx)1088 static int reserve_bo_and_vm(struct kgd_mem *mem,
1089 			      struct amdgpu_vm *vm,
1090 			      struct bo_vm_reservation_context *ctx)
1091 {
1092 	struct amdgpu_bo *bo = mem->bo;
1093 	int ret;
1094 
1095 	WARN_ON(!vm);
1096 
1097 	ctx->n_vms = 1;
1098 	ctx->sync = &mem->sync;
1099 	drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1100 	drm_exec_until_all_locked(&ctx->exec) {
1101 		ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1102 		drm_exec_retry_on_contention(&ctx->exec);
1103 		if (unlikely(ret))
1104 			goto error;
1105 
1106 		ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1107 		drm_exec_retry_on_contention(&ctx->exec);
1108 		if (unlikely(ret))
1109 			goto error;
1110 	}
1111 	return 0;
1112 
1113 error:
1114 	pr_err("Failed to reserve buffers in ttm.\n");
1115 	drm_exec_fini(&ctx->exec);
1116 	return ret;
1117 }
1118 
1119 /**
1120  * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1121  * @mem: KFD BO structure.
1122  * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1123  * is used. Otherwise, a single VM associated with the BO.
1124  * @map_type: the mapping status that will be used to filter the VMs.
1125  * @ctx: the struct that will be used in unreserve_bo_and_vms().
1126  *
1127  * Returns 0 for success, negative for failure.
1128  */
reserve_bo_and_cond_vms(struct kgd_mem * mem,struct amdgpu_vm * vm,enum bo_vm_match map_type,struct bo_vm_reservation_context * ctx)1129 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1130 				struct amdgpu_vm *vm, enum bo_vm_match map_type,
1131 				struct bo_vm_reservation_context *ctx)
1132 {
1133 	struct kfd_mem_attachment *entry;
1134 	struct amdgpu_bo *bo = mem->bo;
1135 	int ret;
1136 
1137 	ctx->sync = &mem->sync;
1138 	drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1139 	drm_exec_until_all_locked(&ctx->exec) {
1140 		ctx->n_vms = 0;
1141 		list_for_each_entry(entry, &mem->attachments, list) {
1142 			if ((vm && vm != entry->bo_va->base.vm) ||
1143 				(entry->is_mapped != map_type
1144 				&& map_type != BO_VM_ALL))
1145 				continue;
1146 
1147 			ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1148 						&ctx->exec, 2);
1149 			drm_exec_retry_on_contention(&ctx->exec);
1150 			if (unlikely(ret))
1151 				goto error;
1152 			++ctx->n_vms;
1153 		}
1154 
1155 		ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1156 		drm_exec_retry_on_contention(&ctx->exec);
1157 		if (unlikely(ret))
1158 			goto error;
1159 	}
1160 	return 0;
1161 
1162 error:
1163 	pr_err("Failed to reserve buffers in ttm.\n");
1164 	drm_exec_fini(&ctx->exec);
1165 	return ret;
1166 }
1167 
1168 /**
1169  * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1170  * @ctx: Reservation context to unreserve
1171  * @wait: Optionally wait for a sync object representing pending VM updates
1172  * @intr: Whether the wait is interruptible
1173  *
1174  * Also frees any resources allocated in
1175  * reserve_bo_and_(cond_)vm(s). Returns the status from
1176  * amdgpu_sync_wait.
1177  */
unreserve_bo_and_vms(struct bo_vm_reservation_context * ctx,bool wait,bool intr)1178 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1179 				 bool wait, bool intr)
1180 {
1181 	int ret = 0;
1182 
1183 	if (wait)
1184 		ret = amdgpu_sync_wait(ctx->sync, intr);
1185 
1186 	drm_exec_fini(&ctx->exec);
1187 	ctx->sync = NULL;
1188 	return ret;
1189 }
1190 
unmap_bo_from_gpuvm(struct kgd_mem * mem,struct kfd_mem_attachment * entry,struct amdgpu_sync * sync)1191 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1192 				struct kfd_mem_attachment *entry,
1193 				struct amdgpu_sync *sync)
1194 {
1195 	struct amdgpu_bo_va *bo_va = entry->bo_va;
1196 	struct amdgpu_device *adev = entry->adev;
1197 	struct amdgpu_vm *vm = bo_va->base.vm;
1198 
1199 	amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1200 
1201 	amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1202 
1203 	amdgpu_sync_fence(sync, bo_va->last_pt_update);
1204 
1205 	kfd_mem_dmaunmap_attachment(mem, entry);
1206 }
1207 
update_gpuvm_pte(struct kgd_mem * mem,struct kfd_mem_attachment * entry,struct amdgpu_sync * sync)1208 static int update_gpuvm_pte(struct kgd_mem *mem,
1209 			    struct kfd_mem_attachment *entry,
1210 			    struct amdgpu_sync *sync)
1211 {
1212 	struct amdgpu_bo_va *bo_va = entry->bo_va;
1213 	struct amdgpu_device *adev = entry->adev;
1214 	int ret;
1215 
1216 	ret = kfd_mem_dmamap_attachment(mem, entry);
1217 	if (ret)
1218 		return ret;
1219 
1220 	/* Update the page tables  */
1221 	ret = amdgpu_vm_bo_update(adev, bo_va, false);
1222 	if (ret) {
1223 		pr_err("amdgpu_vm_bo_update failed\n");
1224 		return ret;
1225 	}
1226 
1227 	return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1228 }
1229 
map_bo_to_gpuvm(struct kgd_mem * mem,struct kfd_mem_attachment * entry,struct amdgpu_sync * sync,bool no_update_pte)1230 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1231 			   struct kfd_mem_attachment *entry,
1232 			   struct amdgpu_sync *sync,
1233 			   bool no_update_pte)
1234 {
1235 	int ret;
1236 
1237 	/* Set virtual address for the allocation */
1238 	ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1239 			       amdgpu_bo_size(entry->bo_va->base.bo),
1240 			       entry->pte_flags);
1241 	if (ret) {
1242 		pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1243 				entry->va, ret);
1244 		return ret;
1245 	}
1246 
1247 	if (no_update_pte)
1248 		return 0;
1249 
1250 	ret = update_gpuvm_pte(mem, entry, sync);
1251 	if (ret) {
1252 		pr_err("update_gpuvm_pte() failed\n");
1253 		goto update_gpuvm_pte_failed;
1254 	}
1255 
1256 	return 0;
1257 
1258 update_gpuvm_pte_failed:
1259 	unmap_bo_from_gpuvm(mem, entry, sync);
1260 	return ret;
1261 }
1262 
process_validate_vms(struct amdkfd_process_info * process_info)1263 static int process_validate_vms(struct amdkfd_process_info *process_info)
1264 {
1265 	struct amdgpu_vm *peer_vm;
1266 	int ret;
1267 
1268 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
1269 			    vm_list_node) {
1270 		ret = vm_validate_pt_pd_bos(peer_vm);
1271 		if (ret)
1272 			return ret;
1273 	}
1274 
1275 	return 0;
1276 }
1277 
process_sync_pds_resv(struct amdkfd_process_info * process_info,struct amdgpu_sync * sync)1278 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1279 				 struct amdgpu_sync *sync)
1280 {
1281 	struct amdgpu_vm *peer_vm;
1282 	int ret;
1283 
1284 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
1285 			    vm_list_node) {
1286 		struct amdgpu_bo *pd = peer_vm->root.bo;
1287 
1288 		ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1289 				       AMDGPU_SYNC_NE_OWNER,
1290 				       AMDGPU_FENCE_OWNER_KFD);
1291 		if (ret)
1292 			return ret;
1293 	}
1294 
1295 	return 0;
1296 }
1297 
process_update_pds(struct amdkfd_process_info * process_info,struct amdgpu_sync * sync)1298 static int process_update_pds(struct amdkfd_process_info *process_info,
1299 			      struct amdgpu_sync *sync)
1300 {
1301 	struct amdgpu_vm *peer_vm;
1302 	int ret;
1303 
1304 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
1305 			    vm_list_node) {
1306 		ret = vm_update_pds(peer_vm, sync);
1307 		if (ret)
1308 			return ret;
1309 	}
1310 
1311 	return 0;
1312 }
1313 
init_kfd_vm(struct amdgpu_vm * vm,void ** process_info,struct dma_fence ** ef)1314 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1315 		       struct dma_fence **ef)
1316 {
1317 	struct amdkfd_process_info *info = NULL;
1318 	int ret;
1319 
1320 	if (!*process_info) {
1321 		info = kzalloc(sizeof(*info), GFP_KERNEL);
1322 		if (!info)
1323 			return -ENOMEM;
1324 
1325 		mutex_init(&info->lock);
1326 		mutex_init(&info->notifier_lock);
1327 		INIT_LIST_HEAD(&info->vm_list_head);
1328 		INIT_LIST_HEAD(&info->kfd_bo_list);
1329 		INIT_LIST_HEAD(&info->userptr_valid_list);
1330 		INIT_LIST_HEAD(&info->userptr_inval_list);
1331 
1332 		info->eviction_fence =
1333 			amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1334 						   current->mm,
1335 						   NULL);
1336 		if (!info->eviction_fence) {
1337 			pr_err("Failed to create eviction fence\n");
1338 			ret = -ENOMEM;
1339 			goto create_evict_fence_fail;
1340 		}
1341 
1342 		info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1343 		INIT_DELAYED_WORK(&info->restore_userptr_work,
1344 				  amdgpu_amdkfd_restore_userptr_worker);
1345 
1346 		*process_info = info;
1347 		*ef = dma_fence_get(&info->eviction_fence->base);
1348 	}
1349 
1350 	vm->process_info = *process_info;
1351 
1352 	/* Validate page directory and attach eviction fence */
1353 	ret = amdgpu_bo_reserve(vm->root.bo, true);
1354 	if (ret)
1355 		goto reserve_pd_fail;
1356 	ret = vm_validate_pt_pd_bos(vm);
1357 	if (ret) {
1358 		pr_err("validate_pt_pd_bos() failed\n");
1359 		goto validate_pd_fail;
1360 	}
1361 	ret = amdgpu_bo_sync_wait(vm->root.bo,
1362 				  AMDGPU_FENCE_OWNER_KFD, false);
1363 	if (ret)
1364 		goto wait_pd_fail;
1365 	ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1366 	if (ret)
1367 		goto reserve_shared_fail;
1368 	dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1369 			   &vm->process_info->eviction_fence->base,
1370 			   DMA_RESV_USAGE_BOOKKEEP);
1371 	amdgpu_bo_unreserve(vm->root.bo);
1372 
1373 	/* Update process info */
1374 	mutex_lock(&vm->process_info->lock);
1375 	list_add_tail(&vm->vm_list_node,
1376 			&(vm->process_info->vm_list_head));
1377 	vm->process_info->n_vms++;
1378 	mutex_unlock(&vm->process_info->lock);
1379 
1380 	return 0;
1381 
1382 reserve_shared_fail:
1383 wait_pd_fail:
1384 validate_pd_fail:
1385 	amdgpu_bo_unreserve(vm->root.bo);
1386 reserve_pd_fail:
1387 	vm->process_info = NULL;
1388 	if (info) {
1389 		/* Two fence references: one in info and one in *ef */
1390 		dma_fence_put(&info->eviction_fence->base);
1391 		dma_fence_put(*ef);
1392 		*ef = NULL;
1393 		*process_info = NULL;
1394 		put_pid(info->pid);
1395 create_evict_fence_fail:
1396 		mutex_destroy(&info->lock);
1397 		mutex_destroy(&info->notifier_lock);
1398 		kfree(info);
1399 	}
1400 	return ret;
1401 }
1402 
1403 /**
1404  * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1405  * @bo: Handle of buffer object being pinned
1406  * @domain: Domain into which BO should be pinned
1407  *
1408  *   - USERPTR BOs are UNPINNABLE and will return error
1409  *   - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1410  *     PIN count incremented. It is valid to PIN a BO multiple times
1411  *
1412  * Return: ZERO if successful in pinning, Non-Zero in case of error.
1413  */
amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo * bo,u32 domain)1414 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1415 {
1416 	int ret = 0;
1417 
1418 	ret = amdgpu_bo_reserve(bo, false);
1419 	if (unlikely(ret))
1420 		return ret;
1421 
1422 	ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1423 	if (ret)
1424 		pr_err("Error in Pinning BO to domain: %d\n", domain);
1425 
1426 	amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1427 	amdgpu_bo_unreserve(bo);
1428 
1429 	return ret;
1430 }
1431 
1432 /**
1433  * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1434  * @bo: Handle of buffer object being unpinned
1435  *
1436  *   - Is a illegal request for USERPTR BOs and is ignored
1437  *   - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1438  *     PIN count decremented. Calls to UNPIN must balance calls to PIN
1439  */
amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo * bo)1440 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1441 {
1442 	int ret = 0;
1443 
1444 	ret = amdgpu_bo_reserve(bo, false);
1445 	if (unlikely(ret))
1446 		return;
1447 
1448 	amdgpu_bo_unpin(bo);
1449 	amdgpu_bo_unreserve(bo);
1450 }
1451 
amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device * adev,struct amdgpu_vm * avm,u32 pasid)1452 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1453 				     struct amdgpu_vm *avm, u32 pasid)
1454 
1455 {
1456 	int ret;
1457 
1458 	/* Free the original amdgpu allocated pasid,
1459 	 * will be replaced with kfd allocated pasid.
1460 	 */
1461 	if (avm->pasid) {
1462 		amdgpu_pasid_free(avm->pasid);
1463 		amdgpu_vm_set_pasid(adev, avm, 0);
1464 	}
1465 
1466 	ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1467 	if (ret)
1468 		return ret;
1469 
1470 	return 0;
1471 }
1472 
amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device * adev,struct amdgpu_vm * avm,void ** process_info,struct dma_fence ** ef)1473 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1474 					   struct amdgpu_vm *avm,
1475 					   void **process_info,
1476 					   struct dma_fence **ef)
1477 {
1478 	int ret;
1479 
1480 	/* Already a compute VM? */
1481 	if (avm->process_info)
1482 		return -EINVAL;
1483 
1484 	/* Convert VM into a compute VM */
1485 	ret = amdgpu_vm_make_compute(adev, avm);
1486 	if (ret)
1487 		return ret;
1488 
1489 	/* Initialize KFD part of the VM and process info */
1490 	ret = init_kfd_vm(avm, process_info, ef);
1491 	if (ret)
1492 		return ret;
1493 
1494 	amdgpu_vm_set_task_info(avm);
1495 
1496 	return 0;
1497 }
1498 
amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device * adev,struct amdgpu_vm * vm)1499 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1500 				    struct amdgpu_vm *vm)
1501 {
1502 	struct amdkfd_process_info *process_info = vm->process_info;
1503 
1504 	if (!process_info)
1505 		return;
1506 
1507 	/* Update process info */
1508 	mutex_lock(&process_info->lock);
1509 	process_info->n_vms--;
1510 	list_del(&vm->vm_list_node);
1511 	mutex_unlock(&process_info->lock);
1512 
1513 	vm->process_info = NULL;
1514 
1515 	/* Release per-process resources when last compute VM is destroyed */
1516 	if (!process_info->n_vms) {
1517 		WARN_ON(!list_empty(&process_info->kfd_bo_list));
1518 		WARN_ON(!list_empty(&process_info->userptr_valid_list));
1519 		WARN_ON(!list_empty(&process_info->userptr_inval_list));
1520 
1521 		dma_fence_put(&process_info->eviction_fence->base);
1522 		cancel_delayed_work_sync(&process_info->restore_userptr_work);
1523 		put_pid(process_info->pid);
1524 		mutex_destroy(&process_info->lock);
1525 		mutex_destroy(&process_info->notifier_lock);
1526 		kfree(process_info);
1527 	}
1528 }
1529 
amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device * adev,void * drm_priv)1530 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1531 					    void *drm_priv)
1532 {
1533 	struct amdgpu_vm *avm;
1534 
1535 	if (WARN_ON(!adev || !drm_priv))
1536 		return;
1537 
1538 	avm = drm_priv_to_vm(drm_priv);
1539 
1540 	pr_debug("Releasing process vm %p\n", avm);
1541 
1542 	/* The original pasid of amdgpu vm has already been
1543 	 * released during making a amdgpu vm to a compute vm
1544 	 * The current pasid is managed by kfd and will be
1545 	 * released on kfd process destroy. Set amdgpu pasid
1546 	 * to 0 to avoid duplicate release.
1547 	 */
1548 	amdgpu_vm_release_compute(adev, avm);
1549 }
1550 
amdgpu_amdkfd_gpuvm_get_process_page_dir(void * drm_priv)1551 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1552 {
1553 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1554 	struct amdgpu_bo *pd = avm->root.bo;
1555 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1556 
1557 	if (adev->asic_type < CHIP_VEGA10)
1558 		return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1559 	return avm->pd_phys_addr;
1560 }
1561 
amdgpu_amdkfd_block_mmu_notifications(void * p)1562 void amdgpu_amdkfd_block_mmu_notifications(void *p)
1563 {
1564 	struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1565 
1566 	mutex_lock(&pinfo->lock);
1567 	WRITE_ONCE(pinfo->block_mmu_notifications, true);
1568 	mutex_unlock(&pinfo->lock);
1569 }
1570 
amdgpu_amdkfd_criu_resume(void * p)1571 int amdgpu_amdkfd_criu_resume(void *p)
1572 {
1573 	int ret = 0;
1574 	struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1575 
1576 	mutex_lock(&pinfo->lock);
1577 	pr_debug("scheduling work\n");
1578 	mutex_lock(&pinfo->notifier_lock);
1579 	pinfo->evicted_bos++;
1580 	mutex_unlock(&pinfo->notifier_lock);
1581 	if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1582 		ret = -EINVAL;
1583 		goto out_unlock;
1584 	}
1585 	WRITE_ONCE(pinfo->block_mmu_notifications, false);
1586 	schedule_delayed_work(&pinfo->restore_userptr_work, 0);
1587 
1588 out_unlock:
1589 	mutex_unlock(&pinfo->lock);
1590 	return ret;
1591 }
1592 
amdgpu_amdkfd_get_available_memory(struct amdgpu_device * adev,uint8_t xcp_id)1593 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1594 					  uint8_t xcp_id)
1595 {
1596 	uint64_t reserved_for_pt =
1597 		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1598 	ssize_t available;
1599 	uint64_t vram_available, system_mem_available, ttm_mem_available;
1600 
1601 	spin_lock(&kfd_mem_limit.mem_limit_lock);
1602 	vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1603 		- adev->kfd.vram_used_aligned[xcp_id]
1604 		- atomic64_read(&adev->vram_pin_size)
1605 		- reserved_for_pt;
1606 
1607 	if (adev->gmc.is_app_apu) {
1608 		system_mem_available = no_system_mem_limit ?
1609 					kfd_mem_limit.max_system_mem_limit :
1610 					kfd_mem_limit.max_system_mem_limit -
1611 					kfd_mem_limit.system_mem_used;
1612 
1613 		ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1614 				kfd_mem_limit.ttm_mem_used;
1615 
1616 		available = min3(system_mem_available, ttm_mem_available,
1617 				 vram_available);
1618 		available = ALIGN_DOWN(available, PAGE_SIZE);
1619 	} else {
1620 		available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1621 	}
1622 
1623 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
1624 
1625 	if (available < 0)
1626 		available = 0;
1627 
1628 	return available;
1629 }
1630 
amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(struct amdgpu_device * adev,uint64_t va,uint64_t size,void * drm_priv,struct kgd_mem ** mem,uint64_t * offset,uint32_t flags,bool criu_resume)1631 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1632 		struct amdgpu_device *adev, uint64_t va, uint64_t size,
1633 		void *drm_priv, struct kgd_mem **mem,
1634 		uint64_t *offset, uint32_t flags, bool criu_resume)
1635 {
1636 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1637 	struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1638 	enum ttm_bo_type bo_type = ttm_bo_type_device;
1639 	struct sg_table *sg = NULL;
1640 	uint64_t user_addr = 0;
1641 	struct amdgpu_bo *bo;
1642 	struct drm_gem_object *gobj = NULL;
1643 	u32 domain, alloc_domain;
1644 	uint64_t aligned_size;
1645 	int8_t xcp_id = -1;
1646 	u64 alloc_flags;
1647 	int ret;
1648 
1649 	/*
1650 	 * Check on which domain to allocate BO
1651 	 */
1652 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1653 		domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1654 
1655 		if (adev->gmc.is_app_apu) {
1656 			domain = AMDGPU_GEM_DOMAIN_GTT;
1657 			alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1658 			alloc_flags = 0;
1659 		} else {
1660 			alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1661 			alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1662 			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1663 		}
1664 		xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1665 					0 : fpriv->xcp_id;
1666 	} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1667 		domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1668 		alloc_flags = 0;
1669 	} else {
1670 		domain = AMDGPU_GEM_DOMAIN_GTT;
1671 		alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1672 		alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1673 
1674 		if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1675 			if (!offset || !*offset)
1676 				return -EINVAL;
1677 			user_addr = untagged_addr(*offset);
1678 		} else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1679 				    KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1680 			bo_type = ttm_bo_type_sg;
1681 			if (size > UINT_MAX)
1682 				return -EINVAL;
1683 			sg = create_sg_table(*offset, size);
1684 			if (!sg)
1685 				return -ENOMEM;
1686 		} else {
1687 			return -EINVAL;
1688 		}
1689 	}
1690 
1691 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1692 		alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1693 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1694 		alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1695 
1696 	*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1697 	if (!*mem) {
1698 		ret = -ENOMEM;
1699 		goto err;
1700 	}
1701 	INIT_LIST_HEAD(&(*mem)->attachments);
1702 	mutex_init(&(*mem)->lock);
1703 	(*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1704 
1705 	/* Workaround for AQL queue wraparound bug. Map the same
1706 	 * memory twice. That means we only actually allocate half
1707 	 * the memory.
1708 	 */
1709 	if ((*mem)->aql_queue)
1710 		size >>= 1;
1711 	aligned_size = PAGE_ALIGN(size);
1712 
1713 	(*mem)->alloc_flags = flags;
1714 
1715 	amdgpu_sync_create(&(*mem)->sync);
1716 
1717 	ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1718 					      xcp_id);
1719 	if (ret) {
1720 		pr_debug("Insufficient memory\n");
1721 		goto err_reserve_limit;
1722 	}
1723 
1724 	pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1725 		 va, (*mem)->aql_queue ? size << 1 : size,
1726 		 domain_string(alloc_domain), xcp_id);
1727 
1728 	ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1729 				       bo_type, NULL, &gobj, xcp_id + 1);
1730 	if (ret) {
1731 		pr_debug("Failed to create BO on domain %s. ret %d\n",
1732 			 domain_string(alloc_domain), ret);
1733 		goto err_bo_create;
1734 	}
1735 	ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1736 	if (ret) {
1737 		pr_debug("Failed to allow vma node access. ret %d\n", ret);
1738 		goto err_node_allow;
1739 	}
1740 	bo = gem_to_amdgpu_bo(gobj);
1741 	if (bo_type == ttm_bo_type_sg) {
1742 		bo->tbo.sg = sg;
1743 		bo->tbo.ttm->sg = sg;
1744 	}
1745 	bo->kfd_bo = *mem;
1746 	(*mem)->bo = bo;
1747 	if (user_addr)
1748 		bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1749 
1750 	(*mem)->va = va;
1751 	(*mem)->domain = domain;
1752 	(*mem)->mapped_to_gpu_memory = 0;
1753 	(*mem)->process_info = avm->process_info;
1754 
1755 	add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1756 
1757 	if (user_addr) {
1758 		pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1759 		ret = init_user_pages(*mem, user_addr, criu_resume);
1760 		if (ret)
1761 			goto allocate_init_user_pages_failed;
1762 	} else  if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1763 				KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1764 		ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1765 		if (ret) {
1766 			pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1767 			goto err_pin_bo;
1768 		}
1769 		bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1770 		bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1771 	}
1772 
1773 	if (offset)
1774 		*offset = amdgpu_bo_mmap_offset(bo);
1775 
1776 	return 0;
1777 
1778 allocate_init_user_pages_failed:
1779 err_pin_bo:
1780 	remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1781 	drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1782 err_node_allow:
1783 	/* Don't unreserve system mem limit twice */
1784 	goto err_reserve_limit;
1785 err_bo_create:
1786 	amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1787 err_reserve_limit:
1788 	mutex_destroy(&(*mem)->lock);
1789 	if (gobj)
1790 		drm_gem_object_put(gobj);
1791 	else
1792 		kfree(*mem);
1793 err:
1794 	if (sg) {
1795 		sg_free_table(sg);
1796 		kfree(sg);
1797 	}
1798 	return ret;
1799 }
1800 
amdgpu_amdkfd_gpuvm_free_memory_of_gpu(struct amdgpu_device * adev,struct kgd_mem * mem,void * drm_priv,uint64_t * size)1801 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1802 		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1803 		uint64_t *size)
1804 {
1805 	struct amdkfd_process_info *process_info = mem->process_info;
1806 	unsigned long bo_size = mem->bo->tbo.base.size;
1807 	bool use_release_notifier = (mem->bo->kfd_bo == mem);
1808 	struct kfd_mem_attachment *entry, *tmp;
1809 	struct bo_vm_reservation_context ctx;
1810 	unsigned int mapped_to_gpu_memory;
1811 	int ret;
1812 	bool is_imported = false;
1813 
1814 	mutex_lock(&mem->lock);
1815 
1816 	/* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1817 	if (mem->alloc_flags &
1818 	    (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1819 	     KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1820 		amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1821 	}
1822 
1823 	mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1824 	is_imported = mem->is_imported;
1825 	mutex_unlock(&mem->lock);
1826 	/* lock is not needed after this, since mem is unused and will
1827 	 * be freed anyway
1828 	 */
1829 
1830 	if (mapped_to_gpu_memory > 0) {
1831 		pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1832 				mem->va, bo_size);
1833 		return -EBUSY;
1834 	}
1835 
1836 	/* Make sure restore workers don't access the BO any more */
1837 	mutex_lock(&process_info->lock);
1838 	list_del(&mem->validate_list);
1839 	mutex_unlock(&process_info->lock);
1840 
1841 	/* Cleanup user pages and MMU notifiers */
1842 	if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1843 		amdgpu_hmm_unregister(mem->bo);
1844 		mutex_lock(&process_info->notifier_lock);
1845 		amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1846 		mutex_unlock(&process_info->notifier_lock);
1847 	}
1848 
1849 	ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1850 	if (unlikely(ret))
1851 		return ret;
1852 
1853 	/* The eviction fence should be removed by the last unmap.
1854 	 * TODO: Log an error condition if the bo still has the eviction fence
1855 	 * attached
1856 	 */
1857 	amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1858 					process_info->eviction_fence);
1859 	pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1860 		mem->va + bo_size * (1 + mem->aql_queue));
1861 
1862 	/* Remove from VM internal data structures */
1863 	list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
1864 		kfd_mem_detach(entry);
1865 
1866 	ret = unreserve_bo_and_vms(&ctx, false, false);
1867 
1868 	/* Free the sync object */
1869 	amdgpu_sync_free(&mem->sync);
1870 
1871 	/* If the SG is not NULL, it's one we created for a doorbell or mmio
1872 	 * remap BO. We need to free it.
1873 	 */
1874 	if (mem->bo->tbo.sg) {
1875 		sg_free_table(mem->bo->tbo.sg);
1876 		kfree(mem->bo->tbo.sg);
1877 	}
1878 
1879 	/* Update the size of the BO being freed if it was allocated from
1880 	 * VRAM and is not imported. For APP APU VRAM allocations are done
1881 	 * in GTT domain
1882 	 */
1883 	if (size) {
1884 		if (!is_imported &&
1885 		   (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1886 		   (adev->gmc.is_app_apu &&
1887 		    mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1888 			*size = bo_size;
1889 		else
1890 			*size = 0;
1891 	}
1892 
1893 	/* Free the BO*/
1894 	drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1895 	if (mem->dmabuf)
1896 		dma_buf_put(mem->dmabuf);
1897 	mutex_destroy(&mem->lock);
1898 
1899 	/* If this releases the last reference, it will end up calling
1900 	 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1901 	 * this needs to be the last call here.
1902 	 */
1903 	drm_gem_object_put(&mem->bo->tbo.base);
1904 
1905 	/*
1906 	 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1907 	 * explicitly free it here.
1908 	 */
1909 	if (!use_release_notifier)
1910 		kfree(mem);
1911 
1912 	return ret;
1913 }
1914 
amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device * adev,struct kgd_mem * mem,void * drm_priv)1915 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1916 		struct amdgpu_device *adev, struct kgd_mem *mem,
1917 		void *drm_priv)
1918 {
1919 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1920 	int ret;
1921 	struct amdgpu_bo *bo;
1922 	uint32_t domain;
1923 	struct kfd_mem_attachment *entry;
1924 	struct bo_vm_reservation_context ctx;
1925 	unsigned long bo_size;
1926 	bool is_invalid_userptr = false;
1927 
1928 	bo = mem->bo;
1929 	if (!bo) {
1930 		pr_err("Invalid BO when mapping memory to GPU\n");
1931 		return -EINVAL;
1932 	}
1933 
1934 	/* Make sure restore is not running concurrently. Since we
1935 	 * don't map invalid userptr BOs, we rely on the next restore
1936 	 * worker to do the mapping
1937 	 */
1938 	mutex_lock(&mem->process_info->lock);
1939 
1940 	/* Lock notifier lock. If we find an invalid userptr BO, we can be
1941 	 * sure that the MMU notifier is no longer running
1942 	 * concurrently and the queues are actually stopped
1943 	 */
1944 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1945 		mutex_lock(&mem->process_info->notifier_lock);
1946 		is_invalid_userptr = !!mem->invalid;
1947 		mutex_unlock(&mem->process_info->notifier_lock);
1948 	}
1949 
1950 	mutex_lock(&mem->lock);
1951 
1952 	domain = mem->domain;
1953 	bo_size = bo->tbo.base.size;
1954 
1955 	pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1956 			mem->va,
1957 			mem->va + bo_size * (1 + mem->aql_queue),
1958 			avm, domain_string(domain));
1959 
1960 	if (!kfd_mem_is_attached(avm, mem)) {
1961 		ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1962 		if (ret)
1963 			goto out;
1964 	}
1965 
1966 	ret = reserve_bo_and_vm(mem, avm, &ctx);
1967 	if (unlikely(ret))
1968 		goto out;
1969 
1970 	/* Userptr can be marked as "not invalid", but not actually be
1971 	 * validated yet (still in the system domain). In that case
1972 	 * the queues are still stopped and we can leave mapping for
1973 	 * the next restore worker
1974 	 */
1975 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1976 	    bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
1977 		is_invalid_userptr = true;
1978 
1979 	ret = vm_validate_pt_pd_bos(avm);
1980 	if (unlikely(ret))
1981 		goto out_unreserve;
1982 
1983 	if (mem->mapped_to_gpu_memory == 0 &&
1984 	    !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1985 		/* Validate BO only once. The eviction fence gets added to BO
1986 		 * the first time it is mapped. Validate will wait for all
1987 		 * background evictions to complete.
1988 		 */
1989 		ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1990 		if (ret) {
1991 			pr_debug("Validate failed\n");
1992 			goto out_unreserve;
1993 		}
1994 	}
1995 
1996 	list_for_each_entry(entry, &mem->attachments, list) {
1997 		if (entry->bo_va->base.vm != avm || entry->is_mapped)
1998 			continue;
1999 
2000 		pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2001 			 entry->va, entry->va + bo_size, entry);
2002 
2003 		ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2004 				      is_invalid_userptr);
2005 		if (ret) {
2006 			pr_err("Failed to map bo to gpuvm\n");
2007 			goto out_unreserve;
2008 		}
2009 
2010 		ret = vm_update_pds(avm, ctx.sync);
2011 		if (ret) {
2012 			pr_err("Failed to update page directories\n");
2013 			goto out_unreserve;
2014 		}
2015 
2016 		entry->is_mapped = true;
2017 		mem->mapped_to_gpu_memory++;
2018 		pr_debug("\t INC mapping count %d\n",
2019 			 mem->mapped_to_gpu_memory);
2020 	}
2021 
2022 	if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
2023 		dma_resv_add_fence(bo->tbo.base.resv,
2024 				   &avm->process_info->eviction_fence->base,
2025 				   DMA_RESV_USAGE_BOOKKEEP);
2026 	ret = unreserve_bo_and_vms(&ctx, false, false);
2027 
2028 	goto out;
2029 
2030 out_unreserve:
2031 	unreserve_bo_and_vms(&ctx, false, false);
2032 out:
2033 	mutex_unlock(&mem->process_info->lock);
2034 	mutex_unlock(&mem->lock);
2035 	return ret;
2036 }
2037 
amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(struct amdgpu_device * adev,struct kgd_mem * mem,void * drm_priv)2038 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2039 		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2040 {
2041 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2042 	struct amdkfd_process_info *process_info = avm->process_info;
2043 	unsigned long bo_size = mem->bo->tbo.base.size;
2044 	struct kfd_mem_attachment *entry;
2045 	struct bo_vm_reservation_context ctx;
2046 	int ret;
2047 
2048 	mutex_lock(&mem->lock);
2049 
2050 	ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2051 	if (unlikely(ret))
2052 		goto out;
2053 	/* If no VMs were reserved, it means the BO wasn't actually mapped */
2054 	if (ctx.n_vms == 0) {
2055 		ret = -EINVAL;
2056 		goto unreserve_out;
2057 	}
2058 
2059 	ret = vm_validate_pt_pd_bos(avm);
2060 	if (unlikely(ret))
2061 		goto unreserve_out;
2062 
2063 	pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2064 		mem->va,
2065 		mem->va + bo_size * (1 + mem->aql_queue),
2066 		avm);
2067 
2068 	list_for_each_entry(entry, &mem->attachments, list) {
2069 		if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2070 			continue;
2071 
2072 		pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2073 			 entry->va, entry->va + bo_size, entry);
2074 
2075 		unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2076 		entry->is_mapped = false;
2077 
2078 		mem->mapped_to_gpu_memory--;
2079 		pr_debug("\t DEC mapping count %d\n",
2080 			 mem->mapped_to_gpu_memory);
2081 	}
2082 
2083 	/* If BO is unmapped from all VMs, unfence it. It can be evicted if
2084 	 * required.
2085 	 */
2086 	if (mem->mapped_to_gpu_memory == 0 &&
2087 	    !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
2088 	    !mem->bo->tbo.pin_count)
2089 		amdgpu_amdkfd_remove_eviction_fence(mem->bo,
2090 						process_info->eviction_fence);
2091 
2092 unreserve_out:
2093 	unreserve_bo_and_vms(&ctx, false, false);
2094 out:
2095 	mutex_unlock(&mem->lock);
2096 	return ret;
2097 }
2098 
amdgpu_amdkfd_gpuvm_sync_memory(struct amdgpu_device * adev,struct kgd_mem * mem,bool intr)2099 int amdgpu_amdkfd_gpuvm_sync_memory(
2100 		struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2101 {
2102 	struct amdgpu_sync sync;
2103 	int ret;
2104 
2105 	amdgpu_sync_create(&sync);
2106 
2107 	mutex_lock(&mem->lock);
2108 	amdgpu_sync_clone(&mem->sync, &sync);
2109 	mutex_unlock(&mem->lock);
2110 
2111 	ret = amdgpu_sync_wait(&sync, intr);
2112 	amdgpu_sync_free(&sync);
2113 	return ret;
2114 }
2115 
2116 /**
2117  * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2118  * @adev: Device to which allocated BO belongs
2119  * @bo: Buffer object to be mapped
2120  *
2121  * Before return, bo reference count is incremented. To release the reference and unpin/
2122  * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2123  */
amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device * adev,struct amdgpu_bo * bo)2124 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
2125 {
2126 	int ret;
2127 
2128 	ret = amdgpu_bo_reserve(bo, true);
2129 	if (ret) {
2130 		pr_err("Failed to reserve bo. ret %d\n", ret);
2131 		goto err_reserve_bo_failed;
2132 	}
2133 
2134 	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2135 	if (ret) {
2136 		pr_err("Failed to pin bo. ret %d\n", ret);
2137 		goto err_pin_bo_failed;
2138 	}
2139 
2140 	ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2141 	if (ret) {
2142 		pr_err("Failed to bind bo to GART. ret %d\n", ret);
2143 		goto err_map_bo_gart_failed;
2144 	}
2145 
2146 	amdgpu_amdkfd_remove_eviction_fence(
2147 		bo, bo->vm_bo->vm->process_info->eviction_fence);
2148 
2149 	amdgpu_bo_unreserve(bo);
2150 
2151 	bo = amdgpu_bo_ref(bo);
2152 
2153 	return 0;
2154 
2155 err_map_bo_gart_failed:
2156 	amdgpu_bo_unpin(bo);
2157 err_pin_bo_failed:
2158 	amdgpu_bo_unreserve(bo);
2159 err_reserve_bo_failed:
2160 
2161 	return ret;
2162 }
2163 
2164 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2165  *
2166  * @mem: Buffer object to be mapped for CPU access
2167  * @kptr[out]: pointer in kernel CPU address space
2168  * @size[out]: size of the buffer
2169  *
2170  * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2171  * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2172  * validate_list, so the GPU mapping can be restored after a page table was
2173  * evicted.
2174  *
2175  * Return: 0 on success, error code on failure
2176  */
amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem * mem,void ** kptr,uint64_t * size)2177 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2178 					     void **kptr, uint64_t *size)
2179 {
2180 	int ret;
2181 	struct amdgpu_bo *bo = mem->bo;
2182 
2183 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2184 		pr_err("userptr can't be mapped to kernel\n");
2185 		return -EINVAL;
2186 	}
2187 
2188 	mutex_lock(&mem->process_info->lock);
2189 
2190 	ret = amdgpu_bo_reserve(bo, true);
2191 	if (ret) {
2192 		pr_err("Failed to reserve bo. ret %d\n", ret);
2193 		goto bo_reserve_failed;
2194 	}
2195 
2196 	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2197 	if (ret) {
2198 		pr_err("Failed to pin bo. ret %d\n", ret);
2199 		goto pin_failed;
2200 	}
2201 
2202 	ret = amdgpu_bo_kmap(bo, kptr);
2203 	if (ret) {
2204 		pr_err("Failed to map bo to kernel. ret %d\n", ret);
2205 		goto kmap_failed;
2206 	}
2207 
2208 	amdgpu_amdkfd_remove_eviction_fence(
2209 		bo, mem->process_info->eviction_fence);
2210 
2211 	if (size)
2212 		*size = amdgpu_bo_size(bo);
2213 
2214 	amdgpu_bo_unreserve(bo);
2215 
2216 	mutex_unlock(&mem->process_info->lock);
2217 	return 0;
2218 
2219 kmap_failed:
2220 	amdgpu_bo_unpin(bo);
2221 pin_failed:
2222 	amdgpu_bo_unreserve(bo);
2223 bo_reserve_failed:
2224 	mutex_unlock(&mem->process_info->lock);
2225 
2226 	return ret;
2227 }
2228 
2229 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2230  *
2231  * @mem: Buffer object to be unmapped for CPU access
2232  *
2233  * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2234  * eviction fence, so this function should only be used for cleanup before the
2235  * BO is destroyed.
2236  */
amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem * mem)2237 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2238 {
2239 	struct amdgpu_bo *bo = mem->bo;
2240 
2241 	amdgpu_bo_reserve(bo, true);
2242 	amdgpu_bo_kunmap(bo);
2243 	amdgpu_bo_unpin(bo);
2244 	amdgpu_bo_unreserve(bo);
2245 }
2246 
amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device * adev,struct kfd_vm_fault_info * mem)2247 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2248 					  struct kfd_vm_fault_info *mem)
2249 {
2250 	if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2251 		*mem = *adev->gmc.vm_fault_info;
2252 		mb(); /* make sure read happened */
2253 		atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2254 	}
2255 	return 0;
2256 }
2257 
amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device * adev,struct dma_buf * dma_buf,uint64_t va,void * drm_priv,struct kgd_mem ** mem,uint64_t * size,uint64_t * mmap_offset)2258 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
2259 				      struct dma_buf *dma_buf,
2260 				      uint64_t va, void *drm_priv,
2261 				      struct kgd_mem **mem, uint64_t *size,
2262 				      uint64_t *mmap_offset)
2263 {
2264 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2265 	struct drm_gem_object *obj;
2266 	struct amdgpu_bo *bo;
2267 	int ret;
2268 
2269 	obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf);
2270 	if (IS_ERR(obj))
2271 		return PTR_ERR(obj);
2272 
2273 	bo = gem_to_amdgpu_bo(obj);
2274 	if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2275 				    AMDGPU_GEM_DOMAIN_GTT))) {
2276 		/* Only VRAM and GTT BOs are supported */
2277 		ret = -EINVAL;
2278 		goto err_put_obj;
2279 	}
2280 
2281 	*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2282 	if (!*mem) {
2283 		ret = -ENOMEM;
2284 		goto err_put_obj;
2285 	}
2286 
2287 	ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2288 	if (ret)
2289 		goto err_free_mem;
2290 
2291 	if (size)
2292 		*size = amdgpu_bo_size(bo);
2293 
2294 	if (mmap_offset)
2295 		*mmap_offset = amdgpu_bo_mmap_offset(bo);
2296 
2297 	INIT_LIST_HEAD(&(*mem)->attachments);
2298 	mutex_init(&(*mem)->lock);
2299 
2300 	(*mem)->alloc_flags =
2301 		((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2302 		KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2303 		| KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2304 		| KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2305 
2306 	get_dma_buf(dma_buf);
2307 	(*mem)->dmabuf = dma_buf;
2308 	(*mem)->bo = bo;
2309 	(*mem)->va = va;
2310 	(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2311 		AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2312 
2313 	(*mem)->mapped_to_gpu_memory = 0;
2314 	(*mem)->process_info = avm->process_info;
2315 	add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2316 	amdgpu_sync_create(&(*mem)->sync);
2317 	(*mem)->is_imported = true;
2318 
2319 	return 0;
2320 
2321 err_free_mem:
2322 	kfree(*mem);
2323 err_put_obj:
2324 	drm_gem_object_put(obj);
2325 	return ret;
2326 }
2327 
amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem * mem,struct dma_buf ** dma_buf)2328 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2329 				      struct dma_buf **dma_buf)
2330 {
2331 	int ret;
2332 
2333 	mutex_lock(&mem->lock);
2334 	ret = kfd_mem_export_dmabuf(mem);
2335 	if (ret)
2336 		goto out;
2337 
2338 	get_dma_buf(mem->dmabuf);
2339 	*dma_buf = mem->dmabuf;
2340 out:
2341 	mutex_unlock(&mem->lock);
2342 	return ret;
2343 }
2344 
2345 /* Evict a userptr BO by stopping the queues if necessary
2346  *
2347  * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2348  * cannot do any memory allocations, and cannot take any locks that
2349  * are held elsewhere while allocating memory.
2350  *
2351  * It doesn't do anything to the BO itself. The real work happens in
2352  * restore, where we get updated page addresses. This function only
2353  * ensures that GPU access to the BO is stopped.
2354  */
amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier * mni,unsigned long cur_seq,struct kgd_mem * mem)2355 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2356 				unsigned long cur_seq, struct kgd_mem *mem)
2357 {
2358 	struct amdkfd_process_info *process_info = mem->process_info;
2359 	int r = 0;
2360 
2361 	/* Do not process MMU notifications during CRIU restore until
2362 	 * KFD_CRIU_OP_RESUME IOCTL is received
2363 	 */
2364 	if (READ_ONCE(process_info->block_mmu_notifications))
2365 		return 0;
2366 
2367 	mutex_lock(&process_info->notifier_lock);
2368 	mmu_interval_set_seq(mni, cur_seq);
2369 
2370 	mem->invalid++;
2371 	if (++process_info->evicted_bos == 1) {
2372 		/* First eviction, stop the queues */
2373 		r = kgd2kfd_quiesce_mm(mni->mm,
2374 				       KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2375 		if (r)
2376 			pr_err("Failed to quiesce KFD\n");
2377 		schedule_delayed_work(&process_info->restore_userptr_work,
2378 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2379 	}
2380 	mutex_unlock(&process_info->notifier_lock);
2381 
2382 	return r;
2383 }
2384 
2385 /* Update invalid userptr BOs
2386  *
2387  * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2388  * userptr_inval_list and updates user pages for all BOs that have
2389  * been invalidated since their last update.
2390  */
update_invalid_user_pages(struct amdkfd_process_info * process_info,struct mm_struct * mm)2391 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2392 				     struct mm_struct *mm)
2393 {
2394 	struct kgd_mem *mem, *tmp_mem;
2395 	struct amdgpu_bo *bo;
2396 	struct ttm_operation_ctx ctx = { false, false };
2397 	uint32_t invalid;
2398 	int ret = 0;
2399 
2400 	mutex_lock(&process_info->notifier_lock);
2401 
2402 	/* Move all invalidated BOs to the userptr_inval_list */
2403 	list_for_each_entry_safe(mem, tmp_mem,
2404 				 &process_info->userptr_valid_list,
2405 				 validate_list)
2406 		if (mem->invalid)
2407 			list_move_tail(&mem->validate_list,
2408 				       &process_info->userptr_inval_list);
2409 
2410 	/* Go through userptr_inval_list and update any invalid user_pages */
2411 	list_for_each_entry(mem, &process_info->userptr_inval_list,
2412 			    validate_list) {
2413 		invalid = mem->invalid;
2414 		if (!invalid)
2415 			/* BO hasn't been invalidated since the last
2416 			 * revalidation attempt. Keep its page list.
2417 			 */
2418 			continue;
2419 
2420 		bo = mem->bo;
2421 
2422 		amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2423 		mem->range = NULL;
2424 
2425 		/* BO reservations and getting user pages (hmm_range_fault)
2426 		 * must happen outside the notifier lock
2427 		 */
2428 		mutex_unlock(&process_info->notifier_lock);
2429 
2430 		/* Move the BO to system (CPU) domain if necessary to unmap
2431 		 * and free the SG table
2432 		 */
2433 		if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2434 			if (amdgpu_bo_reserve(bo, true))
2435 				return -EAGAIN;
2436 			amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2437 			ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2438 			amdgpu_bo_unreserve(bo);
2439 			if (ret) {
2440 				pr_err("%s: Failed to invalidate userptr BO\n",
2441 				       __func__);
2442 				return -EAGAIN;
2443 			}
2444 		}
2445 
2446 		/* Get updated user pages */
2447 		ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2448 						   &mem->range);
2449 		if (ret) {
2450 			pr_debug("Failed %d to get user pages\n", ret);
2451 
2452 			/* Return -EFAULT bad address error as success. It will
2453 			 * fail later with a VM fault if the GPU tries to access
2454 			 * it. Better than hanging indefinitely with stalled
2455 			 * user mode queues.
2456 			 *
2457 			 * Return other error -EBUSY or -ENOMEM to retry restore
2458 			 */
2459 			if (ret != -EFAULT)
2460 				return ret;
2461 
2462 			ret = 0;
2463 		}
2464 
2465 		mutex_lock(&process_info->notifier_lock);
2466 
2467 		/* Mark the BO as valid unless it was invalidated
2468 		 * again concurrently.
2469 		 */
2470 		if (mem->invalid != invalid) {
2471 			ret = -EAGAIN;
2472 			goto unlock_out;
2473 		}
2474 		 /* set mem valid if mem has hmm range associated */
2475 		if (mem->range)
2476 			mem->invalid = 0;
2477 	}
2478 
2479 unlock_out:
2480 	mutex_unlock(&process_info->notifier_lock);
2481 
2482 	return ret;
2483 }
2484 
2485 /* Validate invalid userptr BOs
2486  *
2487  * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2488  * with new page addresses and waits for the page table updates to complete.
2489  */
validate_invalid_user_pages(struct amdkfd_process_info * process_info)2490 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2491 {
2492 	struct ttm_operation_ctx ctx = { false, false };
2493 	struct amdgpu_sync sync;
2494 	struct drm_exec exec;
2495 
2496 	struct amdgpu_vm *peer_vm;
2497 	struct kgd_mem *mem, *tmp_mem;
2498 	struct amdgpu_bo *bo;
2499 	int ret;
2500 
2501 	amdgpu_sync_create(&sync);
2502 
2503 	drm_exec_init(&exec, 0);
2504 	/* Reserve all BOs and page tables for validation */
2505 	drm_exec_until_all_locked(&exec) {
2506 		/* Reserve all the page directories */
2507 		list_for_each_entry(peer_vm, &process_info->vm_list_head,
2508 				    vm_list_node) {
2509 			ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2510 			drm_exec_retry_on_contention(&exec);
2511 			if (unlikely(ret))
2512 				goto unreserve_out;
2513 		}
2514 
2515 		/* Reserve the userptr_inval_list entries to resv_list */
2516 		list_for_each_entry(mem, &process_info->userptr_inval_list,
2517 				    validate_list) {
2518 			struct drm_gem_object *gobj;
2519 
2520 			gobj = &mem->bo->tbo.base;
2521 			ret = drm_exec_prepare_obj(&exec, gobj, 1);
2522 			drm_exec_retry_on_contention(&exec);
2523 			if (unlikely(ret))
2524 				goto unreserve_out;
2525 		}
2526 	}
2527 
2528 	ret = process_validate_vms(process_info);
2529 	if (ret)
2530 		goto unreserve_out;
2531 
2532 	/* Validate BOs and update GPUVM page tables */
2533 	list_for_each_entry_safe(mem, tmp_mem,
2534 				 &process_info->userptr_inval_list,
2535 				 validate_list) {
2536 		struct kfd_mem_attachment *attachment;
2537 
2538 		bo = mem->bo;
2539 
2540 		/* Validate the BO if we got user pages */
2541 		if (bo->tbo.ttm->pages[0]) {
2542 			amdgpu_bo_placement_from_domain(bo, mem->domain);
2543 			ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2544 			if (ret) {
2545 				pr_err("%s: failed to validate BO\n", __func__);
2546 				goto unreserve_out;
2547 			}
2548 		}
2549 
2550 		/* Update mapping. If the BO was not validated
2551 		 * (because we couldn't get user pages), this will
2552 		 * clear the page table entries, which will result in
2553 		 * VM faults if the GPU tries to access the invalid
2554 		 * memory.
2555 		 */
2556 		list_for_each_entry(attachment, &mem->attachments, list) {
2557 			if (!attachment->is_mapped)
2558 				continue;
2559 
2560 			kfd_mem_dmaunmap_attachment(mem, attachment);
2561 			ret = update_gpuvm_pte(mem, attachment, &sync);
2562 			if (ret) {
2563 				pr_err("%s: update PTE failed\n", __func__);
2564 				/* make sure this gets validated again */
2565 				mutex_lock(&process_info->notifier_lock);
2566 				mem->invalid++;
2567 				mutex_unlock(&process_info->notifier_lock);
2568 				goto unreserve_out;
2569 			}
2570 		}
2571 	}
2572 
2573 	/* Update page directories */
2574 	ret = process_update_pds(process_info, &sync);
2575 
2576 unreserve_out:
2577 	drm_exec_fini(&exec);
2578 	amdgpu_sync_wait(&sync, false);
2579 	amdgpu_sync_free(&sync);
2580 
2581 	return ret;
2582 }
2583 
2584 /* Confirm that all user pages are valid while holding the notifier lock
2585  *
2586  * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2587  */
confirm_valid_user_pages_locked(struct amdkfd_process_info * process_info)2588 static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2589 {
2590 	struct kgd_mem *mem, *tmp_mem;
2591 	int ret = 0;
2592 
2593 	list_for_each_entry_safe(mem, tmp_mem,
2594 				 &process_info->userptr_inval_list,
2595 				 validate_list) {
2596 		bool valid;
2597 
2598 		/* keep mem without hmm range at userptr_inval_list */
2599 		if (!mem->range)
2600 			 continue;
2601 
2602 		/* Only check mem with hmm range associated */
2603 		valid = amdgpu_ttm_tt_get_user_pages_done(
2604 					mem->bo->tbo.ttm, mem->range);
2605 
2606 		mem->range = NULL;
2607 		if (!valid) {
2608 			WARN(!mem->invalid, "Invalid BO not marked invalid");
2609 			ret = -EAGAIN;
2610 			continue;
2611 		}
2612 
2613 		if (mem->invalid) {
2614 			WARN(1, "Valid BO is marked invalid");
2615 			ret = -EAGAIN;
2616 			continue;
2617 		}
2618 
2619 		list_move_tail(&mem->validate_list,
2620 			       &process_info->userptr_valid_list);
2621 	}
2622 
2623 	return ret;
2624 }
2625 
2626 /* Worker callback to restore evicted userptr BOs
2627  *
2628  * Tries to update and validate all userptr BOs. If successful and no
2629  * concurrent evictions happened, the queues are restarted. Otherwise,
2630  * reschedule for another attempt later.
2631  */
amdgpu_amdkfd_restore_userptr_worker(struct work_struct * work)2632 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2633 {
2634 	struct delayed_work *dwork = to_delayed_work(work);
2635 	struct amdkfd_process_info *process_info =
2636 		container_of(dwork, struct amdkfd_process_info,
2637 			     restore_userptr_work);
2638 	struct task_struct *usertask;
2639 	struct mm_struct *mm;
2640 	uint32_t evicted_bos;
2641 
2642 	mutex_lock(&process_info->notifier_lock);
2643 	evicted_bos = process_info->evicted_bos;
2644 	mutex_unlock(&process_info->notifier_lock);
2645 	if (!evicted_bos)
2646 		return;
2647 
2648 	/* Reference task and mm in case of concurrent process termination */
2649 	usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2650 	if (!usertask)
2651 		return;
2652 	mm = get_task_mm(usertask);
2653 	if (!mm) {
2654 		put_task_struct(usertask);
2655 		return;
2656 	}
2657 
2658 	mutex_lock(&process_info->lock);
2659 
2660 	if (update_invalid_user_pages(process_info, mm))
2661 		goto unlock_out;
2662 	/* userptr_inval_list can be empty if all evicted userptr BOs
2663 	 * have been freed. In that case there is nothing to validate
2664 	 * and we can just restart the queues.
2665 	 */
2666 	if (!list_empty(&process_info->userptr_inval_list)) {
2667 		if (validate_invalid_user_pages(process_info))
2668 			goto unlock_out;
2669 	}
2670 	/* Final check for concurrent evicton and atomic update. If
2671 	 * another eviction happens after successful update, it will
2672 	 * be a first eviction that calls quiesce_mm. The eviction
2673 	 * reference counting inside KFD will handle this case.
2674 	 */
2675 	mutex_lock(&process_info->notifier_lock);
2676 	if (process_info->evicted_bos != evicted_bos)
2677 		goto unlock_notifier_out;
2678 
2679 	if (confirm_valid_user_pages_locked(process_info)) {
2680 		WARN(1, "User pages unexpectedly invalid");
2681 		goto unlock_notifier_out;
2682 	}
2683 
2684 	process_info->evicted_bos = evicted_bos = 0;
2685 
2686 	if (kgd2kfd_resume_mm(mm)) {
2687 		pr_err("%s: Failed to resume KFD\n", __func__);
2688 		/* No recovery from this failure. Probably the CP is
2689 		 * hanging. No point trying again.
2690 		 */
2691 	}
2692 
2693 unlock_notifier_out:
2694 	mutex_unlock(&process_info->notifier_lock);
2695 unlock_out:
2696 	mutex_unlock(&process_info->lock);
2697 
2698 	/* If validation failed, reschedule another attempt */
2699 	if (evicted_bos) {
2700 		schedule_delayed_work(&process_info->restore_userptr_work,
2701 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2702 
2703 		kfd_smi_event_queue_restore_rescheduled(mm);
2704 	}
2705 	mmput(mm);
2706 	put_task_struct(usertask);
2707 }
2708 
2709 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2710  *   KFD process identified by process_info
2711  *
2712  * @process_info: amdkfd_process_info of the KFD process
2713  *
2714  * After memory eviction, restore thread calls this function. The function
2715  * should be called when the Process is still valid. BO restore involves -
2716  *
2717  * 1.  Release old eviction fence and create new one
2718  * 2.  Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2719  * 3   Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2720  *     BOs that need to be reserved.
2721  * 4.  Reserve all the BOs
2722  * 5.  Validate of PD and PT BOs.
2723  * 6.  Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2724  * 7.  Add fence to all PD and PT BOs.
2725  * 8.  Unreserve all BOs
2726  */
amdgpu_amdkfd_gpuvm_restore_process_bos(void * info,struct dma_fence ** ef)2727 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2728 {
2729 	struct amdkfd_process_info *process_info = info;
2730 	struct amdgpu_vm *peer_vm;
2731 	struct kgd_mem *mem;
2732 	struct amdgpu_amdkfd_fence *new_fence;
2733 	struct list_head duplicate_save;
2734 	struct amdgpu_sync sync_obj;
2735 	unsigned long failed_size = 0;
2736 	unsigned long total_size = 0;
2737 	struct drm_exec exec;
2738 	int ret;
2739 
2740 	INIT_LIST_HEAD(&duplicate_save);
2741 
2742 	mutex_lock(&process_info->lock);
2743 
2744 	drm_exec_init(&exec, 0);
2745 	drm_exec_until_all_locked(&exec) {
2746 		list_for_each_entry(peer_vm, &process_info->vm_list_head,
2747 				    vm_list_node) {
2748 			ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2749 			drm_exec_retry_on_contention(&exec);
2750 			if (unlikely(ret))
2751 				goto ttm_reserve_fail;
2752 		}
2753 
2754 		/* Reserve all BOs and page tables/directory. Add all BOs from
2755 		 * kfd_bo_list to ctx.list
2756 		 */
2757 		list_for_each_entry(mem, &process_info->kfd_bo_list,
2758 				    validate_list) {
2759 			struct drm_gem_object *gobj;
2760 
2761 			gobj = &mem->bo->tbo.base;
2762 			ret = drm_exec_prepare_obj(&exec, gobj, 1);
2763 			drm_exec_retry_on_contention(&exec);
2764 			if (unlikely(ret))
2765 				goto ttm_reserve_fail;
2766 		}
2767 	}
2768 
2769 	amdgpu_sync_create(&sync_obj);
2770 
2771 	/* Validate PDs and PTs */
2772 	ret = process_validate_vms(process_info);
2773 	if (ret)
2774 		goto validate_map_fail;
2775 
2776 	ret = process_sync_pds_resv(process_info, &sync_obj);
2777 	if (ret) {
2778 		pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2779 		goto validate_map_fail;
2780 	}
2781 
2782 	/* Validate BOs and map them to GPUVM (update VM page tables). */
2783 	list_for_each_entry(mem, &process_info->kfd_bo_list,
2784 			    validate_list) {
2785 
2786 		struct amdgpu_bo *bo = mem->bo;
2787 		uint32_t domain = mem->domain;
2788 		struct kfd_mem_attachment *attachment;
2789 		struct dma_resv_iter cursor;
2790 		struct dma_fence *fence;
2791 
2792 		total_size += amdgpu_bo_size(bo);
2793 
2794 		ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2795 		if (ret) {
2796 			pr_debug("Memory eviction: Validate BOs failed\n");
2797 			failed_size += amdgpu_bo_size(bo);
2798 			ret = amdgpu_amdkfd_bo_validate(bo,
2799 						AMDGPU_GEM_DOMAIN_GTT, false);
2800 			if (ret) {
2801 				pr_debug("Memory eviction: Try again\n");
2802 				goto validate_map_fail;
2803 			}
2804 		}
2805 		dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2806 					DMA_RESV_USAGE_KERNEL, fence) {
2807 			ret = amdgpu_sync_fence(&sync_obj, fence);
2808 			if (ret) {
2809 				pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2810 				goto validate_map_fail;
2811 			}
2812 		}
2813 		list_for_each_entry(attachment, &mem->attachments, list) {
2814 			if (!attachment->is_mapped)
2815 				continue;
2816 
2817 			if (attachment->bo_va->base.bo->tbo.pin_count)
2818 				continue;
2819 
2820 			kfd_mem_dmaunmap_attachment(mem, attachment);
2821 			ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2822 			if (ret) {
2823 				pr_debug("Memory eviction: update PTE failed. Try again\n");
2824 				goto validate_map_fail;
2825 			}
2826 		}
2827 	}
2828 
2829 	if (failed_size)
2830 		pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2831 
2832 	/* Update page directories */
2833 	ret = process_update_pds(process_info, &sync_obj);
2834 	if (ret) {
2835 		pr_debug("Memory eviction: update PDs failed. Try again\n");
2836 		goto validate_map_fail;
2837 	}
2838 
2839 	/* Wait for validate and PT updates to finish */
2840 	amdgpu_sync_wait(&sync_obj, false);
2841 
2842 	/* Release old eviction fence and create new one, because fence only
2843 	 * goes from unsignaled to signaled, fence cannot be reused.
2844 	 * Use context and mm from the old fence.
2845 	 */
2846 	new_fence = amdgpu_amdkfd_fence_create(
2847 				process_info->eviction_fence->base.context,
2848 				process_info->eviction_fence->mm,
2849 				NULL);
2850 	if (!new_fence) {
2851 		pr_err("Failed to create eviction fence\n");
2852 		ret = -ENOMEM;
2853 		goto validate_map_fail;
2854 	}
2855 	dma_fence_put(&process_info->eviction_fence->base);
2856 	process_info->eviction_fence = new_fence;
2857 	*ef = dma_fence_get(&new_fence->base);
2858 
2859 	/* Attach new eviction fence to all BOs except pinned ones */
2860 	list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
2861 		if (mem->bo->tbo.pin_count)
2862 			continue;
2863 
2864 		dma_resv_add_fence(mem->bo->tbo.base.resv,
2865 				   &process_info->eviction_fence->base,
2866 				   DMA_RESV_USAGE_BOOKKEEP);
2867 	}
2868 	/* Attach eviction fence to PD / PT BOs */
2869 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
2870 			    vm_list_node) {
2871 		struct amdgpu_bo *bo = peer_vm->root.bo;
2872 
2873 		dma_resv_add_fence(bo->tbo.base.resv,
2874 				   &process_info->eviction_fence->base,
2875 				   DMA_RESV_USAGE_BOOKKEEP);
2876 	}
2877 
2878 validate_map_fail:
2879 	amdgpu_sync_free(&sync_obj);
2880 ttm_reserve_fail:
2881 	drm_exec_fini(&exec);
2882 	mutex_unlock(&process_info->lock);
2883 	return ret;
2884 }
2885 
amdgpu_amdkfd_add_gws_to_process(void * info,void * gws,struct kgd_mem ** mem)2886 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2887 {
2888 	struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2889 	struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2890 	int ret;
2891 
2892 	if (!info || !gws)
2893 		return -EINVAL;
2894 
2895 	*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2896 	if (!*mem)
2897 		return -ENOMEM;
2898 
2899 	mutex_init(&(*mem)->lock);
2900 	INIT_LIST_HEAD(&(*mem)->attachments);
2901 	(*mem)->bo = amdgpu_bo_ref(gws_bo);
2902 	(*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2903 	(*mem)->process_info = process_info;
2904 	add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2905 	amdgpu_sync_create(&(*mem)->sync);
2906 
2907 
2908 	/* Validate gws bo the first time it is added to process */
2909 	mutex_lock(&(*mem)->process_info->lock);
2910 	ret = amdgpu_bo_reserve(gws_bo, false);
2911 	if (unlikely(ret)) {
2912 		pr_err("Reserve gws bo failed %d\n", ret);
2913 		goto bo_reservation_failure;
2914 	}
2915 
2916 	ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2917 	if (ret) {
2918 		pr_err("GWS BO validate failed %d\n", ret);
2919 		goto bo_validation_failure;
2920 	}
2921 	/* GWS resource is shared b/t amdgpu and amdkfd
2922 	 * Add process eviction fence to bo so they can
2923 	 * evict each other.
2924 	 */
2925 	ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
2926 	if (ret)
2927 		goto reserve_shared_fail;
2928 	dma_resv_add_fence(gws_bo->tbo.base.resv,
2929 			   &process_info->eviction_fence->base,
2930 			   DMA_RESV_USAGE_BOOKKEEP);
2931 	amdgpu_bo_unreserve(gws_bo);
2932 	mutex_unlock(&(*mem)->process_info->lock);
2933 
2934 	return ret;
2935 
2936 reserve_shared_fail:
2937 bo_validation_failure:
2938 	amdgpu_bo_unreserve(gws_bo);
2939 bo_reservation_failure:
2940 	mutex_unlock(&(*mem)->process_info->lock);
2941 	amdgpu_sync_free(&(*mem)->sync);
2942 	remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2943 	amdgpu_bo_unref(&gws_bo);
2944 	mutex_destroy(&(*mem)->lock);
2945 	kfree(*mem);
2946 	*mem = NULL;
2947 	return ret;
2948 }
2949 
amdgpu_amdkfd_remove_gws_from_process(void * info,void * mem)2950 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2951 {
2952 	int ret;
2953 	struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2954 	struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2955 	struct amdgpu_bo *gws_bo = kgd_mem->bo;
2956 
2957 	/* Remove BO from process's validate list so restore worker won't touch
2958 	 * it anymore
2959 	 */
2960 	remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2961 
2962 	ret = amdgpu_bo_reserve(gws_bo, false);
2963 	if (unlikely(ret)) {
2964 		pr_err("Reserve gws bo failed %d\n", ret);
2965 		//TODO add BO back to validate_list?
2966 		return ret;
2967 	}
2968 	amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2969 			process_info->eviction_fence);
2970 	amdgpu_bo_unreserve(gws_bo);
2971 	amdgpu_sync_free(&kgd_mem->sync);
2972 	amdgpu_bo_unref(&gws_bo);
2973 	mutex_destroy(&kgd_mem->lock);
2974 	kfree(mem);
2975 	return 0;
2976 }
2977 
2978 /* Returns GPU-specific tiling mode information */
amdgpu_amdkfd_get_tile_config(struct amdgpu_device * adev,struct tile_config * config)2979 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
2980 				struct tile_config *config)
2981 {
2982 	config->gb_addr_config = adev->gfx.config.gb_addr_config;
2983 	config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2984 	config->num_tile_configs =
2985 			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2986 	config->macro_tile_config_ptr =
2987 			adev->gfx.config.macrotile_mode_array;
2988 	config->num_macro_tile_configs =
2989 			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2990 
2991 	/* Those values are not set from GFX9 onwards */
2992 	config->num_banks = adev->gfx.config.num_banks;
2993 	config->num_ranks = adev->gfx.config.num_ranks;
2994 
2995 	return 0;
2996 }
2997 
amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device * adev,struct kgd_mem * mem)2998 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
2999 {
3000 	struct kfd_mem_attachment *entry;
3001 
3002 	list_for_each_entry(entry, &mem->attachments, list) {
3003 		if (entry->is_mapped && entry->adev == adev)
3004 			return true;
3005 	}
3006 	return false;
3007 }
3008 
3009 #if defined(CONFIG_DEBUG_FS)
3010 
kfd_debugfs_kfd_mem_limits(struct seq_file * m,void * data)3011 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3012 {
3013 
3014 	spin_lock(&kfd_mem_limit.mem_limit_lock);
3015 	seq_printf(m, "System mem used %lldM out of %lluM\n",
3016 		  (kfd_mem_limit.system_mem_used >> 20),
3017 		  (kfd_mem_limit.max_system_mem_limit >> 20));
3018 	seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3019 		  (kfd_mem_limit.ttm_mem_used >> 20),
3020 		  (kfd_mem_limit.max_ttm_mem_limit >> 20));
3021 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
3022 
3023 	return 0;
3024 }
3025 
3026 #endif
3027