1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AMD Platform Management Framework (PMF) Driver
4 *
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #include "pmf.h"
12
13 static struct amd_pmf_static_slider_granular config_store;
14
amd_pmf_load_defaults_sps(struct amd_pmf_dev * dev)15 static void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev)
16 {
17 struct apmf_static_slider_granular_output output;
18 int i, j, idx = 0;
19
20 memset(&config_store, 0, sizeof(config_store));
21 apmf_get_static_slider_granular(dev, &output);
22
23 for (i = 0; i < POWER_SOURCE_MAX; i++) {
24 for (j = 0; j < POWER_MODE_MAX; j++) {
25 config_store.prop[i][j].spl = output.prop[idx].spl;
26 config_store.prop[i][j].sppt = output.prop[idx].sppt;
27 config_store.prop[i][j].sppt_apu_only =
28 output.prop[idx].sppt_apu_only;
29 config_store.prop[i][j].fppt = output.prop[idx].fppt;
30 config_store.prop[i][j].stt_min = output.prop[idx].stt_min;
31 config_store.prop[i][j].stt_skin_temp[STT_TEMP_APU] =
32 output.prop[idx].stt_skin_temp[STT_TEMP_APU];
33 config_store.prop[i][j].stt_skin_temp[STT_TEMP_HS2] =
34 output.prop[idx].stt_skin_temp[STT_TEMP_HS2];
35 config_store.prop[i][j].fan_id = output.prop[idx].fan_id;
36 idx++;
37 }
38 }
39 }
40
amd_pmf_update_slider(struct amd_pmf_dev * dev,bool op,int idx,struct amd_pmf_static_slider_granular * table)41 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
42 struct amd_pmf_static_slider_granular *table)
43 {
44 int src = amd_pmf_get_power_source();
45
46 if (op == SLIDER_OP_SET) {
47 amd_pmf_send_cmd(dev, SET_SPL, false, config_store.prop[src][idx].spl, NULL);
48 amd_pmf_send_cmd(dev, SET_FPPT, false, config_store.prop[src][idx].fppt, NULL);
49 amd_pmf_send_cmd(dev, SET_SPPT, false, config_store.prop[src][idx].sppt, NULL);
50 amd_pmf_send_cmd(dev, SET_SPPT_APU_ONLY, false,
51 config_store.prop[src][idx].sppt_apu_only, NULL);
52 amd_pmf_send_cmd(dev, SET_STT_MIN_LIMIT, false,
53 config_store.prop[src][idx].stt_min, NULL);
54 amd_pmf_send_cmd(dev, SET_STT_LIMIT_APU, false,
55 config_store.prop[src][idx].stt_skin_temp[STT_TEMP_APU], NULL);
56 amd_pmf_send_cmd(dev, SET_STT_LIMIT_HS2, false,
57 config_store.prop[src][idx].stt_skin_temp[STT_TEMP_HS2], NULL);
58 } else if (op == SLIDER_OP_GET) {
59 amd_pmf_send_cmd(dev, GET_SPL, true, ARG_NONE, &table->prop[src][idx].spl);
60 amd_pmf_send_cmd(dev, GET_FPPT, true, ARG_NONE, &table->prop[src][idx].fppt);
61 amd_pmf_send_cmd(dev, GET_SPPT, true, ARG_NONE, &table->prop[src][idx].sppt);
62 amd_pmf_send_cmd(dev, GET_SPPT_APU_ONLY, true, ARG_NONE,
63 &table->prop[src][idx].sppt_apu_only);
64 amd_pmf_send_cmd(dev, GET_STT_MIN_LIMIT, true, ARG_NONE,
65 &table->prop[src][idx].stt_min);
66 amd_pmf_send_cmd(dev, GET_STT_LIMIT_APU, true, ARG_NONE,
67 (u32 *)&table->prop[src][idx].stt_skin_temp[STT_TEMP_APU]);
68 amd_pmf_send_cmd(dev, GET_STT_LIMIT_HS2, true, ARG_NONE,
69 (u32 *)&table->prop[src][idx].stt_skin_temp[STT_TEMP_HS2]);
70 }
71 }
72
amd_pmf_profile_get(struct platform_profile_handler * pprof,enum platform_profile_option * profile)73 static int amd_pmf_profile_get(struct platform_profile_handler *pprof,
74 enum platform_profile_option *profile)
75 {
76 struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof);
77
78 *profile = pmf->current_profile;
79 return 0;
80 }
81
amd_pmf_get_pprof_modes(struct amd_pmf_dev * pmf)82 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf)
83 {
84 int mode;
85
86 switch (pmf->current_profile) {
87 case PLATFORM_PROFILE_PERFORMANCE:
88 mode = POWER_MODE_PERFORMANCE;
89 break;
90 case PLATFORM_PROFILE_BALANCED:
91 mode = POWER_MODE_BALANCED_POWER;
92 break;
93 case PLATFORM_PROFILE_LOW_POWER:
94 mode = POWER_MODE_POWER_SAVER;
95 break;
96 default:
97 dev_err(pmf->dev, "Unknown Platform Profile.\n");
98 return -EOPNOTSUPP;
99 }
100
101 return mode;
102 }
103
amd_pmf_profile_set(struct platform_profile_handler * pprof,enum platform_profile_option profile)104 static int amd_pmf_profile_set(struct platform_profile_handler *pprof,
105 enum platform_profile_option profile)
106 {
107 struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof);
108 int mode;
109
110 pmf->current_profile = profile;
111 mode = amd_pmf_get_pprof_modes(pmf);
112 if (mode < 0)
113 return mode;
114
115 amd_pmf_update_slider(pmf, SLIDER_OP_SET, mode, NULL);
116 return 0;
117 }
118
amd_pmf_init_sps(struct amd_pmf_dev * dev)119 int amd_pmf_init_sps(struct amd_pmf_dev *dev)
120 {
121 int err;
122
123 dev->current_profile = PLATFORM_PROFILE_BALANCED;
124 amd_pmf_load_defaults_sps(dev);
125
126 dev->pprof.profile_get = amd_pmf_profile_get;
127 dev->pprof.profile_set = amd_pmf_profile_set;
128
129 /* Setup supported modes */
130 set_bit(PLATFORM_PROFILE_LOW_POWER, dev->pprof.choices);
131 set_bit(PLATFORM_PROFILE_BALANCED, dev->pprof.choices);
132 set_bit(PLATFORM_PROFILE_PERFORMANCE, dev->pprof.choices);
133
134 /* Create platform_profile structure and register */
135 err = platform_profile_register(&dev->pprof);
136 if (err)
137 dev_err(dev->dev, "Failed to register SPS support, this is most likely an SBIOS bug: %d\n",
138 err);
139
140 return err;
141 }
142
amd_pmf_deinit_sps(struct amd_pmf_dev * dev)143 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev)
144 {
145 platform_profile_remove();
146 }
147