1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Shared support code for AMD K8 northbridges and derivatives.
4 * Copyright 2006 Andi Kleen, SUSE Labs.
5 */
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/types.h>
10 #include <linux/slab.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/export.h>
14 #include <linux/spinlock.h>
15 #include <linux/pci_ids.h>
16 #include <asm/amd_nb.h>
17
18 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
22 #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
23 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
24 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
25 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
26 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
27 #define PCI_DEVICE_ID_AMD_1AH_M00H_ROOT 0x153a
28 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
29 #define PCI_DEVICE_ID_AMD_MI200_ROOT 0x14bb
30
31 #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
32 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
33 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
34 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
35 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
36 #define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
37 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
38 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
39 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
40 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
41 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
42 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
43 #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc
44 #define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4 0x12c4
45 #define PCI_DEVICE_ID_AMD_MI200_DF_F4 0x14d4
46
47 /* Protect the PCI config register pairs used for SMN. */
48 static DEFINE_MUTEX(smn_mutex);
49
50 static u32 *flush_words;
51
52 static const struct pci_device_id amd_root_ids[] = {
53 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
54 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
55 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
56 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
57 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
58 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
59 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
60 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_ROOT) },
63 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
64 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_ROOT) },
65 {}
66 };
67
68 #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
69
70 static const struct pci_device_id amd_nb_misc_ids[] = {
71 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
72 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
73 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
74 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
75 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
76 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
77 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
78 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
79 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
80 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
81 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
82 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
83 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
84 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
85 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
86 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
87 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
88 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
89 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
90 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
91 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
92 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
93 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
94 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
95 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) },
96 {}
97 };
98
99 static const struct pci_device_id amd_nb_link_ids[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
101 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
102 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
103 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
104 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
105 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
106 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
107 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
108 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
109 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
110 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
111 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
112 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
113 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
114 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
115 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F4) },
116 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F4) },
117 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F4) },
118 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
119 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4) },
120 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F4) },
121 {}
122 };
123
124 static const struct pci_device_id hygon_root_ids[] = {
125 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
126 {}
127 };
128
129 static const struct pci_device_id hygon_nb_misc_ids[] = {
130 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
131 {}
132 };
133
134 static const struct pci_device_id hygon_nb_link_ids[] = {
135 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
136 {}
137 };
138
139 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
140 { 0x00, 0x18, 0x20 },
141 { 0xff, 0x00, 0x20 },
142 { 0xfe, 0x00, 0x20 },
143 { }
144 };
145
146 static struct amd_northbridge_info amd_northbridges;
147
amd_nb_num(void)148 u16 amd_nb_num(void)
149 {
150 return amd_northbridges.num;
151 }
152 EXPORT_SYMBOL_GPL(amd_nb_num);
153
amd_nb_has_feature(unsigned int feature)154 bool amd_nb_has_feature(unsigned int feature)
155 {
156 return ((amd_northbridges.flags & feature) == feature);
157 }
158 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
159
node_to_amd_nb(int node)160 struct amd_northbridge *node_to_amd_nb(int node)
161 {
162 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
163 }
164 EXPORT_SYMBOL_GPL(node_to_amd_nb);
165
next_northbridge(struct pci_dev * dev,const struct pci_device_id * ids)166 static struct pci_dev *next_northbridge(struct pci_dev *dev,
167 const struct pci_device_id *ids)
168 {
169 do {
170 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
171 if (!dev)
172 break;
173 } while (!pci_match_id(ids, dev));
174 return dev;
175 }
176
__amd_smn_rw(u16 node,u32 address,u32 * value,bool write)177 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
178 {
179 struct pci_dev *root;
180 int err = -ENODEV;
181
182 if (node >= amd_northbridges.num)
183 goto out;
184
185 root = node_to_amd_nb(node)->root;
186 if (!root)
187 goto out;
188
189 mutex_lock(&smn_mutex);
190
191 err = pci_write_config_dword(root, 0x60, address);
192 if (err) {
193 pr_warn("Error programming SMN address 0x%x.\n", address);
194 goto out_unlock;
195 }
196
197 err = (write ? pci_write_config_dword(root, 0x64, *value)
198 : pci_read_config_dword(root, 0x64, value));
199 if (err)
200 pr_warn("Error %s SMN address 0x%x.\n",
201 (write ? "writing to" : "reading from"), address);
202
203 out_unlock:
204 mutex_unlock(&smn_mutex);
205
206 out:
207 return err;
208 }
209
amd_smn_read(u16 node,u32 address,u32 * value)210 int amd_smn_read(u16 node, u32 address, u32 *value)
211 {
212 return __amd_smn_rw(node, address, value, false);
213 }
214 EXPORT_SYMBOL_GPL(amd_smn_read);
215
amd_smn_write(u16 node,u32 address,u32 value)216 int amd_smn_write(u16 node, u32 address, u32 value)
217 {
218 return __amd_smn_rw(node, address, &value, true);
219 }
220 EXPORT_SYMBOL_GPL(amd_smn_write);
221
222
amd_cache_northbridges(void)223 static int amd_cache_northbridges(void)
224 {
225 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
226 const struct pci_device_id *link_ids = amd_nb_link_ids;
227 const struct pci_device_id *root_ids = amd_root_ids;
228 struct pci_dev *root, *misc, *link;
229 struct amd_northbridge *nb;
230 u16 roots_per_misc = 0;
231 u16 misc_count = 0;
232 u16 root_count = 0;
233 u16 i, j;
234
235 if (amd_northbridges.num)
236 return 0;
237
238 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
239 root_ids = hygon_root_ids;
240 misc_ids = hygon_nb_misc_ids;
241 link_ids = hygon_nb_link_ids;
242 }
243
244 misc = NULL;
245 while ((misc = next_northbridge(misc, misc_ids)))
246 misc_count++;
247
248 if (!misc_count)
249 return -ENODEV;
250
251 root = NULL;
252 while ((root = next_northbridge(root, root_ids)))
253 root_count++;
254
255 if (root_count) {
256 roots_per_misc = root_count / misc_count;
257
258 /*
259 * There should be _exactly_ N roots for each DF/SMN
260 * interface.
261 */
262 if (!roots_per_misc || (root_count % roots_per_misc)) {
263 pr_info("Unsupported AMD DF/PCI configuration found\n");
264 return -ENODEV;
265 }
266 }
267
268 nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
269 if (!nb)
270 return -ENOMEM;
271
272 amd_northbridges.nb = nb;
273 amd_northbridges.num = misc_count;
274
275 link = misc = root = NULL;
276 for (i = 0; i < amd_northbridges.num; i++) {
277 node_to_amd_nb(i)->root = root =
278 next_northbridge(root, root_ids);
279 node_to_amd_nb(i)->misc = misc =
280 next_northbridge(misc, misc_ids);
281 node_to_amd_nb(i)->link = link =
282 next_northbridge(link, link_ids);
283
284 /*
285 * If there are more PCI root devices than data fabric/
286 * system management network interfaces, then the (N)
287 * PCI roots per DF/SMN interface are functionally the
288 * same (for DF/SMN access) and N-1 are redundant. N-1
289 * PCI roots should be skipped per DF/SMN interface so
290 * the following DF/SMN interfaces get mapped to
291 * correct PCI roots.
292 */
293 for (j = 1; j < roots_per_misc; j++)
294 root = next_northbridge(root, root_ids);
295 }
296
297 if (amd_gart_present())
298 amd_northbridges.flags |= AMD_NB_GART;
299
300 /*
301 * Check for L3 cache presence.
302 */
303 if (!cpuid_edx(0x80000006))
304 return 0;
305
306 /*
307 * Some CPU families support L3 Cache Index Disable. There are some
308 * limitations because of E382 and E388 on family 0x10.
309 */
310 if (boot_cpu_data.x86 == 0x10 &&
311 boot_cpu_data.x86_model >= 0x8 &&
312 (boot_cpu_data.x86_model > 0x9 ||
313 boot_cpu_data.x86_stepping >= 0x1))
314 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
315
316 if (boot_cpu_data.x86 == 0x15)
317 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
318
319 /* L3 cache partitioning is supported on family 0x15 */
320 if (boot_cpu_data.x86 == 0x15)
321 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
322
323 return 0;
324 }
325
326 /*
327 * Ignores subdevice/subvendor but as far as I can figure out
328 * they're useless anyways
329 */
early_is_amd_nb(u32 device)330 bool __init early_is_amd_nb(u32 device)
331 {
332 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
333 const struct pci_device_id *id;
334 u32 vendor = device & 0xffff;
335
336 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
337 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
338 return false;
339
340 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
341 misc_ids = hygon_nb_misc_ids;
342
343 device >>= 16;
344 for (id = misc_ids; id->vendor; id++)
345 if (vendor == id->vendor && device == id->device)
346 return true;
347 return false;
348 }
349
amd_get_mmconfig_range(struct resource * res)350 struct resource *amd_get_mmconfig_range(struct resource *res)
351 {
352 u32 address;
353 u64 base, msr;
354 unsigned int segn_busn_bits;
355
356 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
357 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
358 return NULL;
359
360 /* assume all cpus from fam10h have mmconfig */
361 if (boot_cpu_data.x86 < 0x10)
362 return NULL;
363
364 address = MSR_FAM10H_MMIO_CONF_BASE;
365 rdmsrl(address, msr);
366
367 /* mmconfig is not enabled */
368 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
369 return NULL;
370
371 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
372
373 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
374 FAM10H_MMIO_CONF_BUSRANGE_MASK;
375
376 res->flags = IORESOURCE_MEM;
377 res->start = base;
378 res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
379 return res;
380 }
381
amd_get_subcaches(int cpu)382 int amd_get_subcaches(int cpu)
383 {
384 struct pci_dev *link = node_to_amd_nb(topology_die_id(cpu))->link;
385 unsigned int mask;
386
387 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
388 return 0;
389
390 pci_read_config_dword(link, 0x1d4, &mask);
391
392 return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
393 }
394
amd_set_subcaches(int cpu,unsigned long mask)395 int amd_set_subcaches(int cpu, unsigned long mask)
396 {
397 static unsigned int reset, ban;
398 struct amd_northbridge *nb = node_to_amd_nb(topology_die_id(cpu));
399 unsigned int reg;
400 int cuid;
401
402 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
403 return -EINVAL;
404
405 /* if necessary, collect reset state of L3 partitioning and BAN mode */
406 if (reset == 0) {
407 pci_read_config_dword(nb->link, 0x1d4, &reset);
408 pci_read_config_dword(nb->misc, 0x1b8, &ban);
409 ban &= 0x180000;
410 }
411
412 /* deactivate BAN mode if any subcaches are to be disabled */
413 if (mask != 0xf) {
414 pci_read_config_dword(nb->misc, 0x1b8, ®);
415 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
416 }
417
418 cuid = cpu_data(cpu).cpu_core_id;
419 mask <<= 4 * cuid;
420 mask |= (0xf ^ (1 << cuid)) << 26;
421
422 pci_write_config_dword(nb->link, 0x1d4, mask);
423
424 /* reset BAN mode if L3 partitioning returned to reset state */
425 pci_read_config_dword(nb->link, 0x1d4, ®);
426 if (reg == reset) {
427 pci_read_config_dword(nb->misc, 0x1b8, ®);
428 reg &= ~0x180000;
429 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
430 }
431
432 return 0;
433 }
434
amd_cache_gart(void)435 static void amd_cache_gart(void)
436 {
437 u16 i;
438
439 if (!amd_nb_has_feature(AMD_NB_GART))
440 return;
441
442 flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
443 if (!flush_words) {
444 amd_northbridges.flags &= ~AMD_NB_GART;
445 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
446 return;
447 }
448
449 for (i = 0; i != amd_northbridges.num; i++)
450 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
451 }
452
amd_flush_garts(void)453 void amd_flush_garts(void)
454 {
455 int flushed, i;
456 unsigned long flags;
457 static DEFINE_SPINLOCK(gart_lock);
458
459 if (!amd_nb_has_feature(AMD_NB_GART))
460 return;
461
462 /*
463 * Avoid races between AGP and IOMMU. In theory it's not needed
464 * but I'm not sure if the hardware won't lose flush requests
465 * when another is pending. This whole thing is so expensive anyways
466 * that it doesn't matter to serialize more. -AK
467 */
468 spin_lock_irqsave(&gart_lock, flags);
469 flushed = 0;
470 for (i = 0; i < amd_northbridges.num; i++) {
471 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
472 flush_words[i] | 1);
473 flushed++;
474 }
475 for (i = 0; i < amd_northbridges.num; i++) {
476 u32 w;
477 /* Make sure the hardware actually executed the flush*/
478 for (;;) {
479 pci_read_config_dword(node_to_amd_nb(i)->misc,
480 0x9c, &w);
481 if (!(w & 1))
482 break;
483 cpu_relax();
484 }
485 }
486 spin_unlock_irqrestore(&gart_lock, flags);
487 if (!flushed)
488 pr_notice("nothing to flush?\n");
489 }
490 EXPORT_SYMBOL_GPL(amd_flush_garts);
491
__fix_erratum_688(void * info)492 static void __fix_erratum_688(void *info)
493 {
494 #define MSR_AMD64_IC_CFG 0xC0011021
495
496 msr_set_bit(MSR_AMD64_IC_CFG, 3);
497 msr_set_bit(MSR_AMD64_IC_CFG, 14);
498 }
499
500 /* Apply erratum 688 fix so machines without a BIOS fix work. */
fix_erratum_688(void)501 static __init void fix_erratum_688(void)
502 {
503 struct pci_dev *F4;
504 u32 val;
505
506 if (boot_cpu_data.x86 != 0x14)
507 return;
508
509 if (!amd_northbridges.num)
510 return;
511
512 F4 = node_to_amd_nb(0)->link;
513 if (!F4)
514 return;
515
516 if (pci_read_config_dword(F4, 0x164, &val))
517 return;
518
519 if (val & BIT(2))
520 return;
521
522 on_each_cpu(__fix_erratum_688, NULL, 0);
523
524 pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
525 }
526
init_amd_nbs(void)527 static __init int init_amd_nbs(void)
528 {
529 amd_cache_northbridges();
530 amd_cache_gart();
531
532 fix_erratum_688();
533
534 return 0;
535 }
536
537 /* This has to go after the PCI subsystem */
538 fs_initcall(init_amd_nbs);
539