1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <asm/pci-direct.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32 #include <asm/x86_init.h>
33 #include <asm/iommu_table.h>
34
35 #include "amd_iommu_proto.h"
36 #include "amd_iommu_types.h"
37
38 /*
39 * definitions for the ACPI scanning code
40 */
41 #define IVRS_HEADER_LENGTH 48
42
43 #define ACPI_IVHD_TYPE 0x10
44 #define ACPI_IVMD_TYPE_ALL 0x20
45 #define ACPI_IVMD_TYPE 0x21
46 #define ACPI_IVMD_TYPE_RANGE 0x22
47
48 #define IVHD_DEV_ALL 0x01
49 #define IVHD_DEV_SELECT 0x02
50 #define IVHD_DEV_SELECT_RANGE_START 0x03
51 #define IVHD_DEV_RANGE_END 0x04
52 #define IVHD_DEV_ALIAS 0x42
53 #define IVHD_DEV_ALIAS_RANGE 0x43
54 #define IVHD_DEV_EXT_SELECT 0x46
55 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
56
57 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
58 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
59 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
60 #define IVHD_FLAG_ISOC_EN_MASK 0x08
61
62 #define IVMD_FLAG_EXCL_RANGE 0x08
63 #define IVMD_FLAG_UNITY_MAP 0x01
64
65 #define ACPI_DEVFLAG_INITPASS 0x01
66 #define ACPI_DEVFLAG_EXTINT 0x02
67 #define ACPI_DEVFLAG_NMI 0x04
68 #define ACPI_DEVFLAG_SYSMGT1 0x10
69 #define ACPI_DEVFLAG_SYSMGT2 0x20
70 #define ACPI_DEVFLAG_LINT0 0x40
71 #define ACPI_DEVFLAG_LINT1 0x80
72 #define ACPI_DEVFLAG_ATSDIS 0x10000000
73
74 /*
75 * ACPI table definitions
76 *
77 * These data structures are laid over the table to parse the important values
78 * out of it.
79 */
80
81 /*
82 * structure describing one IOMMU in the ACPI table. Typically followed by one
83 * or more ivhd_entrys.
84 */
85 struct ivhd_header {
86 u8 type;
87 u8 flags;
88 u16 length;
89 u16 devid;
90 u16 cap_ptr;
91 u64 mmio_phys;
92 u16 pci_seg;
93 u16 info;
94 u32 reserved;
95 } __attribute__((packed));
96
97 /*
98 * A device entry describing which devices a specific IOMMU translates and
99 * which requestor ids they use.
100 */
101 struct ivhd_entry {
102 u8 type;
103 u16 devid;
104 u8 flags;
105 u32 ext;
106 } __attribute__((packed));
107
108 /*
109 * An AMD IOMMU memory definition structure. It defines things like exclusion
110 * ranges for devices and regions that should be unity mapped.
111 */
112 struct ivmd_header {
113 u8 type;
114 u8 flags;
115 u16 length;
116 u16 devid;
117 u16 aux;
118 u64 resv;
119 u64 range_start;
120 u64 range_length;
121 } __attribute__((packed));
122
123 bool amd_iommu_dump;
124
125 static int __initdata amd_iommu_detected;
126 static bool __initdata amd_iommu_disabled;
127
128 u16 amd_iommu_last_bdf; /* largest PCI device id we have
129 to handle */
130 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
131 we find in ACPI */
132 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
133
134 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
135 system */
136
137 /* Array to assign indices to IOMMUs*/
138 struct amd_iommu *amd_iommus[MAX_IOMMUS];
139 int amd_iommus_present;
140
141 /* IOMMUs have a non-present cache? */
142 bool amd_iommu_np_cache __read_mostly;
143 bool amd_iommu_iotlb_sup __read_mostly = true;
144
145 u32 amd_iommu_max_pasids __read_mostly = ~0;
146
147 bool amd_iommu_v2_present __read_mostly;
148
149 bool amd_iommu_force_isolation __read_mostly;
150
151 /*
152 * The ACPI table parsing functions set this variable on an error
153 */
154 static int __initdata amd_iommu_init_err;
155
156 /*
157 * List of protection domains - used during resume
158 */
159 LIST_HEAD(amd_iommu_pd_list);
160 spinlock_t amd_iommu_pd_lock;
161
162 /*
163 * Pointer to the device table which is shared by all AMD IOMMUs
164 * it is indexed by the PCI device id or the HT unit id and contains
165 * information about the domain the device belongs to as well as the
166 * page table root pointer.
167 */
168 struct dev_table_entry *amd_iommu_dev_table;
169
170 /*
171 * The alias table is a driver specific data structure which contains the
172 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
173 * More than one device can share the same requestor id.
174 */
175 u16 *amd_iommu_alias_table;
176
177 /*
178 * The rlookup table is used to find the IOMMU which is responsible
179 * for a specific device. It is also indexed by the PCI device id.
180 */
181 struct amd_iommu **amd_iommu_rlookup_table;
182
183 /*
184 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
185 * to know which ones are already in use.
186 */
187 unsigned long *amd_iommu_pd_alloc_bitmap;
188
189 static u32 dev_table_size; /* size of the device table */
190 static u32 alias_table_size; /* size of the alias table */
191 static u32 rlookup_table_size; /* size if the rlookup table */
192
193 /*
194 * This function flushes all internal caches of
195 * the IOMMU used by this driver.
196 */
197 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
198
199 static int amd_iommu_enable_interrupts(void);
200
update_last_devid(u16 devid)201 static inline void update_last_devid(u16 devid)
202 {
203 if (devid > amd_iommu_last_bdf)
204 amd_iommu_last_bdf = devid;
205 }
206
tbl_size(int entry_size)207 static inline unsigned long tbl_size(int entry_size)
208 {
209 unsigned shift = PAGE_SHIFT +
210 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
211
212 return 1UL << shift;
213 }
214
215 /* Access to l1 and l2 indexed register spaces */
216
iommu_read_l1(struct amd_iommu * iommu,u16 l1,u8 address)217 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
218 {
219 u32 val;
220
221 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
222 pci_read_config_dword(iommu->dev, 0xfc, &val);
223 return val;
224 }
225
iommu_write_l1(struct amd_iommu * iommu,u16 l1,u8 address,u32 val)226 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
227 {
228 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
229 pci_write_config_dword(iommu->dev, 0xfc, val);
230 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
231 }
232
iommu_read_l2(struct amd_iommu * iommu,u8 address)233 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
234 {
235 u32 val;
236
237 pci_write_config_dword(iommu->dev, 0xf0, address);
238 pci_read_config_dword(iommu->dev, 0xf4, &val);
239 return val;
240 }
241
iommu_write_l2(struct amd_iommu * iommu,u8 address,u32 val)242 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
243 {
244 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
245 pci_write_config_dword(iommu->dev, 0xf4, val);
246 }
247
248 /****************************************************************************
249 *
250 * AMD IOMMU MMIO register space handling functions
251 *
252 * These functions are used to program the IOMMU device registers in
253 * MMIO space required for that driver.
254 *
255 ****************************************************************************/
256
257 /*
258 * This function set the exclusion range in the IOMMU. DMA accesses to the
259 * exclusion range are passed through untranslated
260 */
iommu_set_exclusion_range(struct amd_iommu * iommu)261 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
262 {
263 u64 start = iommu->exclusion_start & PAGE_MASK;
264 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
265 u64 entry;
266
267 if (!iommu->exclusion_start)
268 return;
269
270 entry = start | MMIO_EXCL_ENABLE_MASK;
271 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
272 &entry, sizeof(entry));
273
274 entry = limit;
275 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
276 &entry, sizeof(entry));
277 }
278
279 /* Programs the physical address of the device table into the IOMMU hardware */
iommu_set_device_table(struct amd_iommu * iommu)280 static void iommu_set_device_table(struct amd_iommu *iommu)
281 {
282 u64 entry;
283
284 BUG_ON(iommu->mmio_base == NULL);
285
286 entry = virt_to_phys(amd_iommu_dev_table);
287 entry |= (dev_table_size >> 12) - 1;
288 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
289 &entry, sizeof(entry));
290 }
291
292 /* Generic functions to enable/disable certain features of the IOMMU. */
iommu_feature_enable(struct amd_iommu * iommu,u8 bit)293 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
294 {
295 u32 ctrl;
296
297 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
298 ctrl |= (1 << bit);
299 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
300 }
301
iommu_feature_disable(struct amd_iommu * iommu,u8 bit)302 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
303 {
304 u32 ctrl;
305
306 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
307 ctrl &= ~(1 << bit);
308 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
309 }
310
iommu_set_inv_tlb_timeout(struct amd_iommu * iommu,int timeout)311 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
312 {
313 u32 ctrl;
314
315 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
316 ctrl &= ~CTRL_INV_TO_MASK;
317 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
318 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
319 }
320
321 /* Function to enable the hardware */
iommu_enable(struct amd_iommu * iommu)322 static void iommu_enable(struct amd_iommu *iommu)
323 {
324 static const char * const feat_str[] = {
325 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
326 "IA", "GA", "HE", "PC", NULL
327 };
328 int i;
329
330 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
331 dev_name(&iommu->dev->dev), iommu->cap_ptr);
332
333 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
334 printk(KERN_CONT " extended features: ");
335 for (i = 0; feat_str[i]; ++i)
336 if (iommu_feature(iommu, (1ULL << i)))
337 printk(KERN_CONT " %s", feat_str[i]);
338 }
339 printk(KERN_CONT "\n");
340
341 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
342 }
343
iommu_disable(struct amd_iommu * iommu)344 static void iommu_disable(struct amd_iommu *iommu)
345 {
346 /* Disable command buffer */
347 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
348
349 /* Disable event logging and event interrupts */
350 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
351 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
352
353 /* Disable IOMMU hardware itself */
354 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
355 }
356
357 /*
358 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
359 * the system has one.
360 */
iommu_map_mmio_space(u64 address)361 static u8 * __init iommu_map_mmio_space(u64 address)
362 {
363 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
364 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
365 address);
366 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
367 return NULL;
368 }
369
370 return ioremap_nocache(address, MMIO_REGION_LENGTH);
371 }
372
iommu_unmap_mmio_space(struct amd_iommu * iommu)373 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
374 {
375 if (iommu->mmio_base)
376 iounmap(iommu->mmio_base);
377 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
378 }
379
380 /****************************************************************************
381 *
382 * The functions below belong to the first pass of AMD IOMMU ACPI table
383 * parsing. In this pass we try to find out the highest device id this
384 * code has to handle. Upon this information the size of the shared data
385 * structures is determined later.
386 *
387 ****************************************************************************/
388
389 /*
390 * This function calculates the length of a given IVHD entry
391 */
ivhd_entry_length(u8 * ivhd)392 static inline int ivhd_entry_length(u8 *ivhd)
393 {
394 return 0x04 << (*ivhd >> 6);
395 }
396
397 /*
398 * This function reads the last device id the IOMMU has to handle from the PCI
399 * capability header for this IOMMU
400 */
find_last_devid_on_pci(int bus,int dev,int fn,int cap_ptr)401 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
402 {
403 u32 cap;
404
405 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
406 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
407
408 return 0;
409 }
410
411 /*
412 * After reading the highest device id from the IOMMU PCI capability header
413 * this function looks if there is a higher device id defined in the ACPI table
414 */
find_last_devid_from_ivhd(struct ivhd_header * h)415 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
416 {
417 u8 *p = (void *)h, *end = (void *)h;
418 struct ivhd_entry *dev;
419
420 p += sizeof(*h);
421 end += h->length;
422
423 find_last_devid_on_pci(PCI_BUS(h->devid),
424 PCI_SLOT(h->devid),
425 PCI_FUNC(h->devid),
426 h->cap_ptr);
427
428 while (p < end) {
429 dev = (struct ivhd_entry *)p;
430 switch (dev->type) {
431 case IVHD_DEV_SELECT:
432 case IVHD_DEV_RANGE_END:
433 case IVHD_DEV_ALIAS:
434 case IVHD_DEV_EXT_SELECT:
435 /* all the above subfield types refer to device ids */
436 update_last_devid(dev->devid);
437 break;
438 default:
439 break;
440 }
441 p += ivhd_entry_length(p);
442 }
443
444 WARN_ON(p != end);
445
446 return 0;
447 }
448
449 /*
450 * Iterate over all IVHD entries in the ACPI table and find the highest device
451 * id which we need to handle. This is the first of three functions which parse
452 * the ACPI table. So we check the checksum here.
453 */
find_last_devid_acpi(struct acpi_table_header * table)454 static int __init find_last_devid_acpi(struct acpi_table_header *table)
455 {
456 int i;
457 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
458 struct ivhd_header *h;
459
460 /*
461 * Validate checksum here so we don't need to do it when
462 * we actually parse the table
463 */
464 for (i = 0; i < table->length; ++i)
465 checksum += p[i];
466 if (checksum != 0) {
467 /* ACPI table corrupt */
468 amd_iommu_init_err = -ENODEV;
469 return 0;
470 }
471
472 p += IVRS_HEADER_LENGTH;
473
474 end += table->length;
475 while (p < end) {
476 h = (struct ivhd_header *)p;
477 switch (h->type) {
478 case ACPI_IVHD_TYPE:
479 find_last_devid_from_ivhd(h);
480 break;
481 default:
482 break;
483 }
484 p += h->length;
485 }
486 WARN_ON(p != end);
487
488 return 0;
489 }
490
491 /****************************************************************************
492 *
493 * The following functions belong the the code path which parses the ACPI table
494 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
495 * data structures, initialize the device/alias/rlookup table and also
496 * basically initialize the hardware.
497 *
498 ****************************************************************************/
499
500 /*
501 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
502 * write commands to that buffer later and the IOMMU will execute them
503 * asynchronously
504 */
alloc_command_buffer(struct amd_iommu * iommu)505 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
506 {
507 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
508 get_order(CMD_BUFFER_SIZE));
509
510 if (cmd_buf == NULL)
511 return NULL;
512
513 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
514
515 return cmd_buf;
516 }
517
518 /*
519 * This function resets the command buffer if the IOMMU stopped fetching
520 * commands from it.
521 */
amd_iommu_reset_cmd_buffer(struct amd_iommu * iommu)522 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
523 {
524 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
525
526 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
527 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
528
529 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
530 }
531
532 /*
533 * This function writes the command buffer address to the hardware and
534 * enables it.
535 */
iommu_enable_command_buffer(struct amd_iommu * iommu)536 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
537 {
538 u64 entry;
539
540 BUG_ON(iommu->cmd_buf == NULL);
541
542 entry = (u64)virt_to_phys(iommu->cmd_buf);
543 entry |= MMIO_CMD_SIZE_512;
544
545 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
546 &entry, sizeof(entry));
547
548 amd_iommu_reset_cmd_buffer(iommu);
549 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
550 }
551
free_command_buffer(struct amd_iommu * iommu)552 static void __init free_command_buffer(struct amd_iommu *iommu)
553 {
554 free_pages((unsigned long)iommu->cmd_buf,
555 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
556 }
557
558 /* allocates the memory where the IOMMU will log its events to */
alloc_event_buffer(struct amd_iommu * iommu)559 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
560 {
561 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
562 get_order(EVT_BUFFER_SIZE));
563
564 if (iommu->evt_buf == NULL)
565 return NULL;
566
567 iommu->evt_buf_size = EVT_BUFFER_SIZE;
568
569 return iommu->evt_buf;
570 }
571
iommu_enable_event_buffer(struct amd_iommu * iommu)572 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
573 {
574 u64 entry;
575
576 BUG_ON(iommu->evt_buf == NULL);
577
578 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
579
580 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
581 &entry, sizeof(entry));
582
583 /* set head and tail to zero manually */
584 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
585 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
586
587 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
588 }
589
free_event_buffer(struct amd_iommu * iommu)590 static void __init free_event_buffer(struct amd_iommu *iommu)
591 {
592 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
593 }
594
595 /* allocates the memory where the IOMMU will log its events to */
alloc_ppr_log(struct amd_iommu * iommu)596 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
597 {
598 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
599 get_order(PPR_LOG_SIZE));
600
601 if (iommu->ppr_log == NULL)
602 return NULL;
603
604 return iommu->ppr_log;
605 }
606
iommu_enable_ppr_log(struct amd_iommu * iommu)607 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
608 {
609 u64 entry;
610
611 if (iommu->ppr_log == NULL)
612 return;
613
614 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
615
616 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
617 &entry, sizeof(entry));
618
619 /* set head and tail to zero manually */
620 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
621 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
622
623 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
624 iommu_feature_enable(iommu, CONTROL_PPR_EN);
625 }
626
free_ppr_log(struct amd_iommu * iommu)627 static void __init free_ppr_log(struct amd_iommu *iommu)
628 {
629 if (iommu->ppr_log == NULL)
630 return;
631
632 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
633 }
634
iommu_enable_gt(struct amd_iommu * iommu)635 static void iommu_enable_gt(struct amd_iommu *iommu)
636 {
637 if (!iommu_feature(iommu, FEATURE_GT))
638 return;
639
640 iommu_feature_enable(iommu, CONTROL_GT_EN);
641 }
642
643 /* sets a specific bit in the device table entry. */
set_dev_entry_bit(u16 devid,u8 bit)644 static void set_dev_entry_bit(u16 devid, u8 bit)
645 {
646 int i = (bit >> 6) & 0x03;
647 int _bit = bit & 0x3f;
648
649 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
650 }
651
get_dev_entry_bit(u16 devid,u8 bit)652 static int get_dev_entry_bit(u16 devid, u8 bit)
653 {
654 int i = (bit >> 6) & 0x03;
655 int _bit = bit & 0x3f;
656
657 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
658 }
659
660
amd_iommu_apply_erratum_63(u16 devid)661 void amd_iommu_apply_erratum_63(u16 devid)
662 {
663 int sysmgt;
664
665 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
666 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
667
668 if (sysmgt == 0x01)
669 set_dev_entry_bit(devid, DEV_ENTRY_IW);
670 }
671
672 /* Writes the specific IOMMU for a device into the rlookup table */
set_iommu_for_device(struct amd_iommu * iommu,u16 devid)673 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
674 {
675 amd_iommu_rlookup_table[devid] = iommu;
676 }
677
678 /*
679 * This function takes the device specific flags read from the ACPI
680 * table and sets up the device table entry with that information
681 */
set_dev_entry_from_acpi(struct amd_iommu * iommu,u16 devid,u32 flags,u32 ext_flags)682 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
683 u16 devid, u32 flags, u32 ext_flags)
684 {
685 if (flags & ACPI_DEVFLAG_INITPASS)
686 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
687 if (flags & ACPI_DEVFLAG_EXTINT)
688 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
689 if (flags & ACPI_DEVFLAG_NMI)
690 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
691 if (flags & ACPI_DEVFLAG_SYSMGT1)
692 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
693 if (flags & ACPI_DEVFLAG_SYSMGT2)
694 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
695 if (flags & ACPI_DEVFLAG_LINT0)
696 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
697 if (flags & ACPI_DEVFLAG_LINT1)
698 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
699
700 amd_iommu_apply_erratum_63(devid);
701
702 set_iommu_for_device(iommu, devid);
703 }
704
705 /*
706 * Reads the device exclusion range from ACPI and initialize IOMMU with
707 * it
708 */
set_device_exclusion_range(u16 devid,struct ivmd_header * m)709 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
710 {
711 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
712
713 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
714 return;
715
716 if (iommu) {
717 /*
718 * We only can configure exclusion ranges per IOMMU, not
719 * per device. But we can enable the exclusion range per
720 * device. This is done here
721 */
722 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
723 iommu->exclusion_start = m->range_start;
724 iommu->exclusion_length = m->range_length;
725 }
726 }
727
728 /*
729 * This function reads some important data from the IOMMU PCI space and
730 * initializes the driver data structure with it. It reads the hardware
731 * capabilities and the first/last device entries
732 */
init_iommu_from_pci(struct amd_iommu * iommu)733 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
734 {
735 int cap_ptr = iommu->cap_ptr;
736 u32 range, misc, low, high;
737 int i, j;
738
739 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
740 &iommu->cap);
741 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
742 &range);
743 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
744 &misc);
745
746 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
747 MMIO_GET_FD(range));
748 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
749 MMIO_GET_LD(range));
750 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
751
752 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
753 amd_iommu_iotlb_sup = false;
754
755 /* read extended feature bits */
756 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
757 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
758
759 iommu->features = ((u64)high << 32) | low;
760
761 if (iommu_feature(iommu, FEATURE_GT)) {
762 int glxval;
763 u32 pasids;
764 u64 shift;
765
766 shift = iommu->features & FEATURE_PASID_MASK;
767 shift >>= FEATURE_PASID_SHIFT;
768 pasids = (1 << shift);
769
770 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
771
772 glxval = iommu->features & FEATURE_GLXVAL_MASK;
773 glxval >>= FEATURE_GLXVAL_SHIFT;
774
775 if (amd_iommu_max_glx_val == -1)
776 amd_iommu_max_glx_val = glxval;
777 else
778 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
779 }
780
781 if (iommu_feature(iommu, FEATURE_GT) &&
782 iommu_feature(iommu, FEATURE_PPR)) {
783 iommu->is_iommu_v2 = true;
784 amd_iommu_v2_present = true;
785 }
786
787 if (!is_rd890_iommu(iommu->dev))
788 return;
789
790 /*
791 * Some rd890 systems may not be fully reconfigured by the BIOS, so
792 * it's necessary for us to store this information so it can be
793 * reprogrammed on resume
794 */
795
796 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
797 &iommu->stored_addr_lo);
798 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
799 &iommu->stored_addr_hi);
800
801 /* Low bit locks writes to configuration space */
802 iommu->stored_addr_lo &= ~1;
803
804 for (i = 0; i < 6; i++)
805 for (j = 0; j < 0x12; j++)
806 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
807
808 for (i = 0; i < 0x83; i++)
809 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
810 }
811
812 /*
813 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
814 * initializes the hardware and our data structures with it.
815 */
init_iommu_from_acpi(struct amd_iommu * iommu,struct ivhd_header * h)816 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
817 struct ivhd_header *h)
818 {
819 u8 *p = (u8 *)h;
820 u8 *end = p, flags = 0;
821 u16 devid = 0, devid_start = 0, devid_to = 0;
822 u32 dev_i, ext_flags = 0;
823 bool alias = false;
824 struct ivhd_entry *e;
825
826 /*
827 * First save the recommended feature enable bits from ACPI
828 */
829 iommu->acpi_flags = h->flags;
830
831 /*
832 * Done. Now parse the device entries
833 */
834 p += sizeof(struct ivhd_header);
835 end += h->length;
836
837
838 while (p < end) {
839 e = (struct ivhd_entry *)p;
840 switch (e->type) {
841 case IVHD_DEV_ALL:
842
843 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
844 " last device %02x:%02x.%x flags: %02x\n",
845 PCI_BUS(iommu->first_device),
846 PCI_SLOT(iommu->first_device),
847 PCI_FUNC(iommu->first_device),
848 PCI_BUS(iommu->last_device),
849 PCI_SLOT(iommu->last_device),
850 PCI_FUNC(iommu->last_device),
851 e->flags);
852
853 for (dev_i = iommu->first_device;
854 dev_i <= iommu->last_device; ++dev_i)
855 set_dev_entry_from_acpi(iommu, dev_i,
856 e->flags, 0);
857 break;
858 case IVHD_DEV_SELECT:
859
860 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
861 "flags: %02x\n",
862 PCI_BUS(e->devid),
863 PCI_SLOT(e->devid),
864 PCI_FUNC(e->devid),
865 e->flags);
866
867 devid = e->devid;
868 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
869 break;
870 case IVHD_DEV_SELECT_RANGE_START:
871
872 DUMP_printk(" DEV_SELECT_RANGE_START\t "
873 "devid: %02x:%02x.%x flags: %02x\n",
874 PCI_BUS(e->devid),
875 PCI_SLOT(e->devid),
876 PCI_FUNC(e->devid),
877 e->flags);
878
879 devid_start = e->devid;
880 flags = e->flags;
881 ext_flags = 0;
882 alias = false;
883 break;
884 case IVHD_DEV_ALIAS:
885
886 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
887 "flags: %02x devid_to: %02x:%02x.%x\n",
888 PCI_BUS(e->devid),
889 PCI_SLOT(e->devid),
890 PCI_FUNC(e->devid),
891 e->flags,
892 PCI_BUS(e->ext >> 8),
893 PCI_SLOT(e->ext >> 8),
894 PCI_FUNC(e->ext >> 8));
895
896 devid = e->devid;
897 devid_to = e->ext >> 8;
898 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
899 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
900 amd_iommu_alias_table[devid] = devid_to;
901 break;
902 case IVHD_DEV_ALIAS_RANGE:
903
904 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
905 "devid: %02x:%02x.%x flags: %02x "
906 "devid_to: %02x:%02x.%x\n",
907 PCI_BUS(e->devid),
908 PCI_SLOT(e->devid),
909 PCI_FUNC(e->devid),
910 e->flags,
911 PCI_BUS(e->ext >> 8),
912 PCI_SLOT(e->ext >> 8),
913 PCI_FUNC(e->ext >> 8));
914
915 devid_start = e->devid;
916 flags = e->flags;
917 devid_to = e->ext >> 8;
918 ext_flags = 0;
919 alias = true;
920 break;
921 case IVHD_DEV_EXT_SELECT:
922
923 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
924 "flags: %02x ext: %08x\n",
925 PCI_BUS(e->devid),
926 PCI_SLOT(e->devid),
927 PCI_FUNC(e->devid),
928 e->flags, e->ext);
929
930 devid = e->devid;
931 set_dev_entry_from_acpi(iommu, devid, e->flags,
932 e->ext);
933 break;
934 case IVHD_DEV_EXT_SELECT_RANGE:
935
936 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
937 "%02x:%02x.%x flags: %02x ext: %08x\n",
938 PCI_BUS(e->devid),
939 PCI_SLOT(e->devid),
940 PCI_FUNC(e->devid),
941 e->flags, e->ext);
942
943 devid_start = e->devid;
944 flags = e->flags;
945 ext_flags = e->ext;
946 alias = false;
947 break;
948 case IVHD_DEV_RANGE_END:
949
950 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
951 PCI_BUS(e->devid),
952 PCI_SLOT(e->devid),
953 PCI_FUNC(e->devid));
954
955 devid = e->devid;
956 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
957 if (alias) {
958 amd_iommu_alias_table[dev_i] = devid_to;
959 set_dev_entry_from_acpi(iommu,
960 devid_to, flags, ext_flags);
961 }
962 set_dev_entry_from_acpi(iommu, dev_i,
963 flags, ext_flags);
964 }
965 break;
966 default:
967 break;
968 }
969
970 p += ivhd_entry_length(p);
971 }
972 }
973
974 /* Initializes the device->iommu mapping for the driver */
init_iommu_devices(struct amd_iommu * iommu)975 static int __init init_iommu_devices(struct amd_iommu *iommu)
976 {
977 u32 i;
978
979 for (i = iommu->first_device; i <= iommu->last_device; ++i)
980 set_iommu_for_device(iommu, i);
981
982 return 0;
983 }
984
free_iommu_one(struct amd_iommu * iommu)985 static void __init free_iommu_one(struct amd_iommu *iommu)
986 {
987 free_command_buffer(iommu);
988 free_event_buffer(iommu);
989 free_ppr_log(iommu);
990 iommu_unmap_mmio_space(iommu);
991 }
992
free_iommu_all(void)993 static void __init free_iommu_all(void)
994 {
995 struct amd_iommu *iommu, *next;
996
997 for_each_iommu_safe(iommu, next) {
998 list_del(&iommu->list);
999 free_iommu_one(iommu);
1000 kfree(iommu);
1001 }
1002 }
1003
1004 /*
1005 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1006 * Workaround:
1007 * BIOS should disable L2B micellaneous clock gating by setting
1008 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1009 */
amd_iommu_erratum_746_workaround(struct amd_iommu * iommu)1010 static void __init amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1011 {
1012 u32 value;
1013
1014 if ((boot_cpu_data.x86 != 0x15) ||
1015 (boot_cpu_data.x86_model < 0x10) ||
1016 (boot_cpu_data.x86_model > 0x1f))
1017 return;
1018
1019 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1020 pci_read_config_dword(iommu->dev, 0xf4, &value);
1021
1022 if (value & BIT(2))
1023 return;
1024
1025 /* Select NB indirect register 0x90 and enable writing */
1026 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1027
1028 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1029 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1030 dev_name(&iommu->dev->dev));
1031
1032 /* Clear the enable writing bit */
1033 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1034 }
1035
1036 /*
1037 * This function clues the initialization function for one IOMMU
1038 * together and also allocates the command buffer and programs the
1039 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1040 */
init_iommu_one(struct amd_iommu * iommu,struct ivhd_header * h)1041 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1042 {
1043 spin_lock_init(&iommu->lock);
1044
1045 /* Add IOMMU to internal data structures */
1046 list_add_tail(&iommu->list, &amd_iommu_list);
1047 iommu->index = amd_iommus_present++;
1048
1049 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1050 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1051 return -ENOSYS;
1052 }
1053
1054 /* Index is fine - add IOMMU to the array */
1055 amd_iommus[iommu->index] = iommu;
1056
1057 /*
1058 * Copy data from ACPI table entry to the iommu struct
1059 */
1060 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
1061 if (!iommu->dev)
1062 return 1;
1063
1064 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1065 PCI_DEVFN(0, 0));
1066
1067 iommu->cap_ptr = h->cap_ptr;
1068 iommu->pci_seg = h->pci_seg;
1069 iommu->mmio_phys = h->mmio_phys;
1070 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1071 if (!iommu->mmio_base)
1072 return -ENOMEM;
1073
1074 iommu->cmd_buf = alloc_command_buffer(iommu);
1075 if (!iommu->cmd_buf)
1076 return -ENOMEM;
1077
1078 iommu->evt_buf = alloc_event_buffer(iommu);
1079 if (!iommu->evt_buf)
1080 return -ENOMEM;
1081
1082 iommu->int_enabled = false;
1083
1084 init_iommu_from_pci(iommu);
1085 init_iommu_from_acpi(iommu, h);
1086 init_iommu_devices(iommu);
1087
1088 if (iommu_feature(iommu, FEATURE_PPR)) {
1089 iommu->ppr_log = alloc_ppr_log(iommu);
1090 if (!iommu->ppr_log)
1091 return -ENOMEM;
1092 }
1093
1094 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1095 amd_iommu_np_cache = true;
1096
1097 amd_iommu_erratum_746_workaround(iommu);
1098
1099 return pci_enable_device(iommu->dev);
1100 }
1101
1102 /*
1103 * Iterates over all IOMMU entries in the ACPI table, allocates the
1104 * IOMMU structure and initializes it with init_iommu_one()
1105 */
init_iommu_all(struct acpi_table_header * table)1106 static int __init init_iommu_all(struct acpi_table_header *table)
1107 {
1108 u8 *p = (u8 *)table, *end = (u8 *)table;
1109 struct ivhd_header *h;
1110 struct amd_iommu *iommu;
1111 int ret;
1112
1113 end += table->length;
1114 p += IVRS_HEADER_LENGTH;
1115
1116 while (p < end) {
1117 h = (struct ivhd_header *)p;
1118 switch (*p) {
1119 case ACPI_IVHD_TYPE:
1120
1121 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1122 "seg: %d flags: %01x info %04x\n",
1123 PCI_BUS(h->devid), PCI_SLOT(h->devid),
1124 PCI_FUNC(h->devid), h->cap_ptr,
1125 h->pci_seg, h->flags, h->info);
1126 DUMP_printk(" mmio-addr: %016llx\n",
1127 h->mmio_phys);
1128
1129 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1130 if (iommu == NULL) {
1131 amd_iommu_init_err = -ENOMEM;
1132 return 0;
1133 }
1134
1135 ret = init_iommu_one(iommu, h);
1136 if (ret) {
1137 amd_iommu_init_err = ret;
1138 return 0;
1139 }
1140 break;
1141 default:
1142 break;
1143 }
1144 p += h->length;
1145
1146 }
1147 WARN_ON(p != end);
1148
1149 return 0;
1150 }
1151
1152 /****************************************************************************
1153 *
1154 * The following functions initialize the MSI interrupts for all IOMMUs
1155 * in the system. Its a bit challenging because there could be multiple
1156 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1157 * pci_dev.
1158 *
1159 ****************************************************************************/
1160
iommu_setup_msi(struct amd_iommu * iommu)1161 static int iommu_setup_msi(struct amd_iommu *iommu)
1162 {
1163 int r;
1164
1165 r = pci_enable_msi(iommu->dev);
1166 if (r)
1167 return r;
1168
1169 r = request_threaded_irq(iommu->dev->irq,
1170 amd_iommu_int_handler,
1171 amd_iommu_int_thread,
1172 0, "AMD-Vi",
1173 iommu->dev);
1174
1175 if (r) {
1176 pci_disable_msi(iommu->dev);
1177 return r;
1178 }
1179
1180 iommu->int_enabled = true;
1181
1182 return 0;
1183 }
1184
iommu_init_msi(struct amd_iommu * iommu)1185 static int iommu_init_msi(struct amd_iommu *iommu)
1186 {
1187 int ret;
1188
1189 if (iommu->int_enabled)
1190 goto enable_faults;
1191
1192 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1193 ret = iommu_setup_msi(iommu);
1194 else
1195 ret = -ENODEV;
1196
1197 if (ret)
1198 return ret;
1199
1200 enable_faults:
1201 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1202
1203 if (iommu->ppr_log != NULL)
1204 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1205
1206 return 0;
1207 }
1208
1209 /****************************************************************************
1210 *
1211 * The next functions belong to the third pass of parsing the ACPI
1212 * table. In this last pass the memory mapping requirements are
1213 * gathered (like exclusion and unity mapping reanges).
1214 *
1215 ****************************************************************************/
1216
free_unity_maps(void)1217 static void __init free_unity_maps(void)
1218 {
1219 struct unity_map_entry *entry, *next;
1220
1221 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1222 list_del(&entry->list);
1223 kfree(entry);
1224 }
1225 }
1226
1227 /* called when we find an exclusion range definition in ACPI */
init_exclusion_range(struct ivmd_header * m)1228 static int __init init_exclusion_range(struct ivmd_header *m)
1229 {
1230 int i;
1231
1232 switch (m->type) {
1233 case ACPI_IVMD_TYPE:
1234 set_device_exclusion_range(m->devid, m);
1235 break;
1236 case ACPI_IVMD_TYPE_ALL:
1237 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1238 set_device_exclusion_range(i, m);
1239 break;
1240 case ACPI_IVMD_TYPE_RANGE:
1241 for (i = m->devid; i <= m->aux; ++i)
1242 set_device_exclusion_range(i, m);
1243 break;
1244 default:
1245 break;
1246 }
1247
1248 return 0;
1249 }
1250
1251 /* called for unity map ACPI definition */
init_unity_map_range(struct ivmd_header * m)1252 static int __init init_unity_map_range(struct ivmd_header *m)
1253 {
1254 struct unity_map_entry *e = 0;
1255 char *s;
1256
1257 e = kzalloc(sizeof(*e), GFP_KERNEL);
1258 if (e == NULL)
1259 return -ENOMEM;
1260
1261 switch (m->type) {
1262 default:
1263 kfree(e);
1264 return 0;
1265 case ACPI_IVMD_TYPE:
1266 s = "IVMD_TYPEi\t\t\t";
1267 e->devid_start = e->devid_end = m->devid;
1268 break;
1269 case ACPI_IVMD_TYPE_ALL:
1270 s = "IVMD_TYPE_ALL\t\t";
1271 e->devid_start = 0;
1272 e->devid_end = amd_iommu_last_bdf;
1273 break;
1274 case ACPI_IVMD_TYPE_RANGE:
1275 s = "IVMD_TYPE_RANGE\t\t";
1276 e->devid_start = m->devid;
1277 e->devid_end = m->aux;
1278 break;
1279 }
1280 e->address_start = PAGE_ALIGN(m->range_start);
1281 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1282 e->prot = m->flags >> 1;
1283
1284 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1285 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1286 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1287 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1288 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1289 e->address_start, e->address_end, m->flags);
1290
1291 list_add_tail(&e->list, &amd_iommu_unity_map);
1292
1293 return 0;
1294 }
1295
1296 /* iterates over all memory definitions we find in the ACPI table */
init_memory_definitions(struct acpi_table_header * table)1297 static int __init init_memory_definitions(struct acpi_table_header *table)
1298 {
1299 u8 *p = (u8 *)table, *end = (u8 *)table;
1300 struct ivmd_header *m;
1301
1302 end += table->length;
1303 p += IVRS_HEADER_LENGTH;
1304
1305 while (p < end) {
1306 m = (struct ivmd_header *)p;
1307 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1308 init_exclusion_range(m);
1309 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1310 init_unity_map_range(m);
1311
1312 p += m->length;
1313 }
1314
1315 return 0;
1316 }
1317
1318 /*
1319 * Init the device table to not allow DMA access for devices and
1320 * suppress all page faults
1321 */
init_device_table(void)1322 static void init_device_table(void)
1323 {
1324 u32 devid;
1325
1326 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1327 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1328 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1329 }
1330 }
1331
iommu_init_flags(struct amd_iommu * iommu)1332 static void iommu_init_flags(struct amd_iommu *iommu)
1333 {
1334 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1335 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1336 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1337
1338 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1339 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1340 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1341
1342 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1343 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1344 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1345
1346 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1347 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1348 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1349
1350 /*
1351 * make IOMMU memory accesses cache coherent
1352 */
1353 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1354
1355 /* Set IOTLB invalidation timeout to 1s */
1356 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1357 }
1358
iommu_apply_resume_quirks(struct amd_iommu * iommu)1359 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1360 {
1361 int i, j;
1362 u32 ioc_feature_control;
1363 struct pci_dev *pdev = iommu->root_pdev;
1364
1365 /* RD890 BIOSes may not have completely reconfigured the iommu */
1366 if (!is_rd890_iommu(iommu->dev) || !pdev)
1367 return;
1368
1369 /*
1370 * First, we need to ensure that the iommu is enabled. This is
1371 * controlled by a register in the northbridge
1372 */
1373
1374 /* Select Northbridge indirect register 0x75 and enable writing */
1375 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1376 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1377
1378 /* Enable the iommu */
1379 if (!(ioc_feature_control & 0x1))
1380 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1381
1382 /* Restore the iommu BAR */
1383 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1384 iommu->stored_addr_lo);
1385 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1386 iommu->stored_addr_hi);
1387
1388 /* Restore the l1 indirect regs for each of the 6 l1s */
1389 for (i = 0; i < 6; i++)
1390 for (j = 0; j < 0x12; j++)
1391 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1392
1393 /* Restore the l2 indirect regs */
1394 for (i = 0; i < 0x83; i++)
1395 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1396
1397 /* Lock PCI setup registers */
1398 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1399 iommu->stored_addr_lo | 1);
1400 }
1401
1402 /*
1403 * This function finally enables all IOMMUs found in the system after
1404 * they have been initialized
1405 */
enable_iommus(void)1406 static void enable_iommus(void)
1407 {
1408 struct amd_iommu *iommu;
1409
1410 for_each_iommu(iommu) {
1411 iommu_disable(iommu);
1412 iommu_init_flags(iommu);
1413 iommu_set_device_table(iommu);
1414 iommu_enable_command_buffer(iommu);
1415 iommu_enable_event_buffer(iommu);
1416 iommu_enable_ppr_log(iommu);
1417 iommu_enable_gt(iommu);
1418 iommu_set_exclusion_range(iommu);
1419 iommu_enable(iommu);
1420 iommu_flush_all_caches(iommu);
1421 }
1422 }
1423
disable_iommus(void)1424 static void disable_iommus(void)
1425 {
1426 struct amd_iommu *iommu;
1427
1428 for_each_iommu(iommu)
1429 iommu_disable(iommu);
1430 }
1431
1432 /*
1433 * Suspend/Resume support
1434 * disable suspend until real resume implemented
1435 */
1436
amd_iommu_resume(void)1437 static void amd_iommu_resume(void)
1438 {
1439 struct amd_iommu *iommu;
1440
1441 for_each_iommu(iommu)
1442 iommu_apply_resume_quirks(iommu);
1443
1444 /* re-load the hardware */
1445 enable_iommus();
1446
1447 amd_iommu_enable_interrupts();
1448 }
1449
amd_iommu_suspend(void)1450 static int amd_iommu_suspend(void)
1451 {
1452 /* disable IOMMUs to go out of the way for BIOS */
1453 disable_iommus();
1454
1455 return 0;
1456 }
1457
1458 static struct syscore_ops amd_iommu_syscore_ops = {
1459 .suspend = amd_iommu_suspend,
1460 .resume = amd_iommu_resume,
1461 };
1462
free_on_init_error(void)1463 static void __init free_on_init_error(void)
1464 {
1465 amd_iommu_uninit_devices();
1466
1467 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1468 get_order(MAX_DOMAIN_ID/8));
1469
1470 free_pages((unsigned long)amd_iommu_rlookup_table,
1471 get_order(rlookup_table_size));
1472
1473 free_pages((unsigned long)amd_iommu_alias_table,
1474 get_order(alias_table_size));
1475
1476 free_pages((unsigned long)amd_iommu_dev_table,
1477 get_order(dev_table_size));
1478
1479 free_iommu_all();
1480
1481 free_unity_maps();
1482
1483 #ifdef CONFIG_GART_IOMMU
1484 /*
1485 * We failed to initialize the AMD IOMMU - try fallback to GART
1486 * if possible.
1487 */
1488 gart_iommu_init();
1489
1490 #endif
1491 }
1492
1493 /*
1494 * This is the hardware init function for AMD IOMMU in the system.
1495 * This function is called either from amd_iommu_init or from the interrupt
1496 * remapping setup code.
1497 *
1498 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1499 * three times:
1500 *
1501 * 1 pass) Find the highest PCI device id the driver has to handle.
1502 * Upon this information the size of the data structures is
1503 * determined that needs to be allocated.
1504 *
1505 * 2 pass) Initialize the data structures just allocated with the
1506 * information in the ACPI table about available AMD IOMMUs
1507 * in the system. It also maps the PCI devices in the
1508 * system to specific IOMMUs
1509 *
1510 * 3 pass) After the basic data structures are allocated and
1511 * initialized we update them with information about memory
1512 * remapping requirements parsed out of the ACPI table in
1513 * this last pass.
1514 *
1515 * After everything is set up the IOMMUs are enabled and the necessary
1516 * hotplug and suspend notifiers are registered.
1517 */
amd_iommu_init_hardware(void)1518 int __init amd_iommu_init_hardware(void)
1519 {
1520 int i, ret = 0;
1521
1522 if (!amd_iommu_detected)
1523 return -ENODEV;
1524
1525 if (amd_iommu_dev_table != NULL) {
1526 /* Hardware already initialized */
1527 return 0;
1528 }
1529
1530 /*
1531 * First parse ACPI tables to find the largest Bus/Dev/Func
1532 * we need to handle. Upon this information the shared data
1533 * structures for the IOMMUs in the system will be allocated
1534 */
1535 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1536 return -ENODEV;
1537
1538 ret = amd_iommu_init_err;
1539 if (ret)
1540 goto out;
1541
1542 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1543 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1544 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1545
1546 /* Device table - directly used by all IOMMUs */
1547 ret = -ENOMEM;
1548 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1549 get_order(dev_table_size));
1550 if (amd_iommu_dev_table == NULL)
1551 goto out;
1552
1553 /*
1554 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1555 * IOMMU see for that device
1556 */
1557 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1558 get_order(alias_table_size));
1559 if (amd_iommu_alias_table == NULL)
1560 goto free;
1561
1562 /* IOMMU rlookup table - find the IOMMU for a specific device */
1563 amd_iommu_rlookup_table = (void *)__get_free_pages(
1564 GFP_KERNEL | __GFP_ZERO,
1565 get_order(rlookup_table_size));
1566 if (amd_iommu_rlookup_table == NULL)
1567 goto free;
1568
1569 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1570 GFP_KERNEL | __GFP_ZERO,
1571 get_order(MAX_DOMAIN_ID/8));
1572 if (amd_iommu_pd_alloc_bitmap == NULL)
1573 goto free;
1574
1575
1576 /*
1577 * let all alias entries point to itself
1578 */
1579 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1580 amd_iommu_alias_table[i] = i;
1581
1582 /*
1583 * never allocate domain 0 because its used as the non-allocated and
1584 * error value placeholder
1585 */
1586 amd_iommu_pd_alloc_bitmap[0] = 1;
1587
1588 spin_lock_init(&amd_iommu_pd_lock);
1589
1590 /*
1591 * now the data structures are allocated and basically initialized
1592 * start the real acpi table scan
1593 */
1594 ret = -ENODEV;
1595 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1596 goto free;
1597
1598 if (amd_iommu_init_err) {
1599 ret = amd_iommu_init_err;
1600 goto free;
1601 }
1602
1603 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1604 goto free;
1605
1606 if (amd_iommu_init_err) {
1607 ret = amd_iommu_init_err;
1608 goto free;
1609 }
1610
1611 ret = amd_iommu_init_devices();
1612 if (ret)
1613 goto free;
1614
1615 enable_iommus();
1616
1617 amd_iommu_init_notifier();
1618
1619 register_syscore_ops(&amd_iommu_syscore_ops);
1620
1621 out:
1622 return ret;
1623
1624 free:
1625 free_on_init_error();
1626
1627 return ret;
1628 }
1629
amd_iommu_enable_interrupts(void)1630 static int amd_iommu_enable_interrupts(void)
1631 {
1632 struct amd_iommu *iommu;
1633 int ret = 0;
1634
1635 for_each_iommu(iommu) {
1636 ret = iommu_init_msi(iommu);
1637 if (ret)
1638 goto out;
1639 }
1640
1641 out:
1642 return ret;
1643 }
1644
1645 /*
1646 * This is the core init function for AMD IOMMU hardware in the system.
1647 * This function is called from the generic x86 DMA layer initialization
1648 * code.
1649 *
1650 * The function calls amd_iommu_init_hardware() to setup and enable the
1651 * IOMMU hardware if this has not happened yet. After that the driver
1652 * registers for the DMA-API and for the IOMMU-API as necessary.
1653 */
amd_iommu_init(void)1654 static int __init amd_iommu_init(void)
1655 {
1656 struct amd_iommu *iommu;
1657 int ret = 0;
1658
1659 ret = amd_iommu_init_hardware();
1660 if (ret)
1661 goto out;
1662
1663 ret = amd_iommu_enable_interrupts();
1664 if (ret)
1665 goto free;
1666
1667 if (iommu_pass_through)
1668 ret = amd_iommu_init_passthrough();
1669 else
1670 ret = amd_iommu_init_dma_ops();
1671
1672 if (ret)
1673 goto free;
1674
1675 /* init the device table */
1676 init_device_table();
1677
1678 for_each_iommu(iommu)
1679 iommu_flush_all_caches(iommu);
1680
1681 amd_iommu_init_api();
1682
1683 x86_platform.iommu_shutdown = disable_iommus;
1684
1685 if (iommu_pass_through)
1686 goto out;
1687
1688 if (amd_iommu_unmap_flush)
1689 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1690 else
1691 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1692
1693 out:
1694 return ret;
1695
1696 free:
1697 disable_iommus();
1698
1699 free_on_init_error();
1700
1701 goto out;
1702 }
1703
1704 /****************************************************************************
1705 *
1706 * Early detect code. This code runs at IOMMU detection time in the DMA
1707 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1708 * IOMMUs
1709 *
1710 ****************************************************************************/
early_amd_iommu_detect(struct acpi_table_header * table)1711 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1712 {
1713 return 0;
1714 }
1715
amd_iommu_detect(void)1716 int __init amd_iommu_detect(void)
1717 {
1718 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1719 return -ENODEV;
1720
1721 if (amd_iommu_disabled)
1722 return -ENODEV;
1723
1724 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1725 iommu_detected = 1;
1726 amd_iommu_detected = 1;
1727 x86_init.iommu.iommu_init = amd_iommu_init;
1728
1729 /* Make sure ACS will be enabled */
1730 pci_request_acs();
1731 return 1;
1732 }
1733 return -ENODEV;
1734 }
1735
1736 /****************************************************************************
1737 *
1738 * Parsing functions for the AMD IOMMU specific kernel command line
1739 * options.
1740 *
1741 ****************************************************************************/
1742
parse_amd_iommu_dump(char * str)1743 static int __init parse_amd_iommu_dump(char *str)
1744 {
1745 amd_iommu_dump = true;
1746
1747 return 1;
1748 }
1749
parse_amd_iommu_options(char * str)1750 static int __init parse_amd_iommu_options(char *str)
1751 {
1752 for (; *str; ++str) {
1753 if (strncmp(str, "fullflush", 9) == 0)
1754 amd_iommu_unmap_flush = true;
1755 if (strncmp(str, "off", 3) == 0)
1756 amd_iommu_disabled = true;
1757 if (strncmp(str, "force_isolation", 15) == 0)
1758 amd_iommu_force_isolation = true;
1759 }
1760
1761 return 1;
1762 }
1763
1764 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1765 __setup("amd_iommu=", parse_amd_iommu_options);
1766
1767 IOMMU_INIT_FINISH(amd_iommu_detect,
1768 gart_iommu_hole_init,
1769 0,
1770 0);
1771
amd_iommu_v2_supported(void)1772 bool amd_iommu_v2_supported(void)
1773 {
1774 return amd_iommu_v2_present;
1775 }
1776 EXPORT_SYMBOL(amd_iommu_v2_supported);
1777