1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-map-ops.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/irqdomain.h>
32 #include <linux/percpu.h>
33 #include <linux/io-pgtable.h>
34 #include <linux/cc_platform.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
37 #include <asm/apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/proto.h>
40 #include <asm/iommu.h>
41 #include <asm/gart.h>
42 #include <asm/dma.h>
43
44 #include "amd_iommu.h"
45 #include "../irq_remapping.h"
46
47 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
48
49 #define LOOP_TIMEOUT 100000
50
51 /* IO virtual address start page frame number */
52 #define IOVA_START_PFN (1)
53 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
54
55 /* Reserved IOVA ranges */
56 #define MSI_RANGE_START (0xfee00000)
57 #define MSI_RANGE_END (0xfeefffff)
58 #define HT_RANGE_START (0xfd00000000ULL)
59 #define HT_RANGE_END (0xffffffffffULL)
60
61 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL
62
63 static DEFINE_SPINLOCK(pd_bitmap_lock);
64
65 /* List of all available dev_data structures */
66 static LLIST_HEAD(dev_data_list);
67
68 LIST_HEAD(ioapic_map);
69 LIST_HEAD(hpet_map);
70 LIST_HEAD(acpihid_map);
71
72 /*
73 * Domain for untranslated devices - only allocated
74 * if iommu=pt passed on kernel cmd line.
75 */
76 const struct iommu_ops amd_iommu_ops;
77
78 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
79 int amd_iommu_max_glx_val = -1;
80
81 /*
82 * general struct to manage commands send to an IOMMU
83 */
84 struct iommu_cmd {
85 u32 data[4];
86 };
87
88 struct kmem_cache *amd_iommu_irq_cache;
89
90 static void detach_device(struct device *dev);
91
92 /****************************************************************************
93 *
94 * Helper functions
95 *
96 ****************************************************************************/
97
get_pci_device_id(struct device * dev)98 static inline u16 get_pci_device_id(struct device *dev)
99 {
100 struct pci_dev *pdev = to_pci_dev(dev);
101
102 return pci_dev_id(pdev);
103 }
104
get_acpihid_device_id(struct device * dev,struct acpihid_map_entry ** entry)105 static inline int get_acpihid_device_id(struct device *dev,
106 struct acpihid_map_entry **entry)
107 {
108 struct acpi_device *adev = ACPI_COMPANION(dev);
109 struct acpihid_map_entry *p;
110
111 if (!adev)
112 return -ENODEV;
113
114 list_for_each_entry(p, &acpihid_map, list) {
115 if (acpi_dev_hid_uid_match(adev, p->hid,
116 p->uid[0] ? p->uid : NULL)) {
117 if (entry)
118 *entry = p;
119 return p->devid;
120 }
121 }
122 return -EINVAL;
123 }
124
get_device_id(struct device * dev)125 static inline int get_device_id(struct device *dev)
126 {
127 int devid;
128
129 if (dev_is_pci(dev))
130 devid = get_pci_device_id(dev);
131 else
132 devid = get_acpihid_device_id(dev, NULL);
133
134 return devid;
135 }
136
to_pdomain(struct iommu_domain * dom)137 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
138 {
139 return container_of(dom, struct protection_domain, domain);
140 }
141
alloc_dev_data(u16 devid)142 static struct iommu_dev_data *alloc_dev_data(u16 devid)
143 {
144 struct iommu_dev_data *dev_data;
145
146 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
147 if (!dev_data)
148 return NULL;
149
150 spin_lock_init(&dev_data->lock);
151 dev_data->devid = devid;
152 ratelimit_default_init(&dev_data->rs);
153
154 llist_add(&dev_data->dev_data_list, &dev_data_list);
155 return dev_data;
156 }
157
search_dev_data(u16 devid)158 static struct iommu_dev_data *search_dev_data(u16 devid)
159 {
160 struct iommu_dev_data *dev_data;
161 struct llist_node *node;
162
163 if (llist_empty(&dev_data_list))
164 return NULL;
165
166 node = dev_data_list.first;
167 llist_for_each_entry(dev_data, node, dev_data_list) {
168 if (dev_data->devid == devid)
169 return dev_data;
170 }
171
172 return NULL;
173 }
174
clone_alias(struct pci_dev * pdev,u16 alias,void * data)175 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
176 {
177 u16 devid = pci_dev_id(pdev);
178
179 if (devid == alias)
180 return 0;
181
182 amd_iommu_rlookup_table[alias] =
183 amd_iommu_rlookup_table[devid];
184 memcpy(amd_iommu_dev_table[alias].data,
185 amd_iommu_dev_table[devid].data,
186 sizeof(amd_iommu_dev_table[alias].data));
187
188 return 0;
189 }
190
clone_aliases(struct pci_dev * pdev)191 static void clone_aliases(struct pci_dev *pdev)
192 {
193 if (!pdev)
194 return;
195
196 /*
197 * The IVRS alias stored in the alias table may not be
198 * part of the PCI DMA aliases if it's bus differs
199 * from the original device.
200 */
201 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
202
203 pci_for_each_dma_alias(pdev, clone_alias, NULL);
204 }
205
setup_aliases(struct device * dev)206 static struct pci_dev *setup_aliases(struct device *dev)
207 {
208 struct pci_dev *pdev = to_pci_dev(dev);
209 u16 ivrs_alias;
210
211 /* For ACPI HID devices, there are no aliases */
212 if (!dev_is_pci(dev))
213 return NULL;
214
215 /*
216 * Add the IVRS alias to the pci aliases if it is on the same
217 * bus. The IVRS table may know about a quirk that we don't.
218 */
219 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
220 if (ivrs_alias != pci_dev_id(pdev) &&
221 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
222 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
223
224 clone_aliases(pdev);
225
226 return pdev;
227 }
228
find_dev_data(u16 devid)229 static struct iommu_dev_data *find_dev_data(u16 devid)
230 {
231 struct iommu_dev_data *dev_data;
232 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
233
234 dev_data = search_dev_data(devid);
235
236 if (dev_data == NULL) {
237 dev_data = alloc_dev_data(devid);
238 if (!dev_data)
239 return NULL;
240
241 if (translation_pre_enabled(iommu))
242 dev_data->defer_attach = true;
243 }
244
245 return dev_data;
246 }
247
248 /*
249 * Find or create an IOMMU group for a acpihid device.
250 */
acpihid_device_group(struct device * dev)251 static struct iommu_group *acpihid_device_group(struct device *dev)
252 {
253 struct acpihid_map_entry *p, *entry = NULL;
254 int devid;
255
256 devid = get_acpihid_device_id(dev, &entry);
257 if (devid < 0)
258 return ERR_PTR(devid);
259
260 list_for_each_entry(p, &acpihid_map, list) {
261 if ((devid == p->devid) && p->group)
262 entry->group = p->group;
263 }
264
265 if (!entry->group)
266 entry->group = generic_device_group(dev);
267 else
268 iommu_group_ref_get(entry->group);
269
270 return entry->group;
271 }
272
pci_iommuv2_capable(struct pci_dev * pdev)273 static bool pci_iommuv2_capable(struct pci_dev *pdev)
274 {
275 static const int caps[] = {
276 PCI_EXT_CAP_ID_PRI,
277 PCI_EXT_CAP_ID_PASID,
278 };
279 int i, pos;
280
281 if (!pci_ats_supported(pdev))
282 return false;
283
284 for (i = 0; i < 2; ++i) {
285 pos = pci_find_ext_capability(pdev, caps[i]);
286 if (pos == 0)
287 return false;
288 }
289
290 return true;
291 }
292
293 /*
294 * This function checks if the driver got a valid device from the caller to
295 * avoid dereferencing invalid pointers.
296 */
check_device(struct device * dev)297 static bool check_device(struct device *dev)
298 {
299 int devid;
300
301 if (!dev)
302 return false;
303
304 devid = get_device_id(dev);
305 if (devid < 0)
306 return false;
307
308 /* Out of our scope? */
309 if (devid > amd_iommu_last_bdf)
310 return false;
311
312 if (amd_iommu_rlookup_table[devid] == NULL)
313 return false;
314
315 return true;
316 }
317
iommu_init_device(struct device * dev)318 static int iommu_init_device(struct device *dev)
319 {
320 struct iommu_dev_data *dev_data;
321 int devid;
322
323 if (dev_iommu_priv_get(dev))
324 return 0;
325
326 devid = get_device_id(dev);
327 if (devid < 0)
328 return devid;
329
330 dev_data = find_dev_data(devid);
331 if (!dev_data)
332 return -ENOMEM;
333
334 dev_data->pdev = setup_aliases(dev);
335
336 /*
337 * By default we use passthrough mode for IOMMUv2 capable device.
338 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
339 * invalid address), we ignore the capability for the device so
340 * it'll be forced to go into translation mode.
341 */
342 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
343 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
344 struct amd_iommu *iommu;
345
346 iommu = amd_iommu_rlookup_table[dev_data->devid];
347 dev_data->iommu_v2 = iommu->is_iommu_v2;
348 }
349
350 dev_iommu_priv_set(dev, dev_data);
351
352 return 0;
353 }
354
iommu_ignore_device(struct device * dev)355 static void iommu_ignore_device(struct device *dev)
356 {
357 int devid;
358
359 devid = get_device_id(dev);
360 if (devid < 0)
361 return;
362
363 amd_iommu_rlookup_table[devid] = NULL;
364 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
365
366 setup_aliases(dev);
367 }
368
amd_iommu_uninit_device(struct device * dev)369 static void amd_iommu_uninit_device(struct device *dev)
370 {
371 struct iommu_dev_data *dev_data;
372
373 dev_data = dev_iommu_priv_get(dev);
374 if (!dev_data)
375 return;
376
377 if (dev_data->domain)
378 detach_device(dev);
379
380 dev_iommu_priv_set(dev, NULL);
381
382 /*
383 * We keep dev_data around for unplugged devices and reuse it when the
384 * device is re-plugged - not doing so would introduce a ton of races.
385 */
386 }
387
388 /****************************************************************************
389 *
390 * Interrupt handling functions
391 *
392 ****************************************************************************/
393
dump_dte_entry(u16 devid)394 static void dump_dte_entry(u16 devid)
395 {
396 int i;
397
398 for (i = 0; i < 4; ++i)
399 pr_err("DTE[%d]: %016llx\n", i,
400 amd_iommu_dev_table[devid].data[i]);
401 }
402
dump_command(unsigned long phys_addr)403 static void dump_command(unsigned long phys_addr)
404 {
405 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
406 int i;
407
408 for (i = 0; i < 4; ++i)
409 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
410 }
411
amd_iommu_report_rmp_hw_error(volatile u32 * event)412 static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
413 {
414 struct iommu_dev_data *dev_data = NULL;
415 int devid, vmg_tag, flags;
416 struct pci_dev *pdev;
417 u64 spa;
418
419 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
420 vmg_tag = (event[1]) & 0xFFFF;
421 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
422 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
423
424 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
425 devid & 0xff);
426 if (pdev)
427 dev_data = dev_iommu_priv_get(&pdev->dev);
428
429 if (dev_data) {
430 if (__ratelimit(&dev_data->rs)) {
431 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
432 vmg_tag, spa, flags);
433 }
434 } else {
435 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
436 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
437 vmg_tag, spa, flags);
438 }
439
440 if (pdev)
441 pci_dev_put(pdev);
442 }
443
amd_iommu_report_rmp_fault(volatile u32 * event)444 static void amd_iommu_report_rmp_fault(volatile u32 *event)
445 {
446 struct iommu_dev_data *dev_data = NULL;
447 int devid, flags_rmp, vmg_tag, flags;
448 struct pci_dev *pdev;
449 u64 gpa;
450
451 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
452 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
453 vmg_tag = (event[1]) & 0xFFFF;
454 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
455 gpa = ((u64)event[3] << 32) | event[2];
456
457 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
458 devid & 0xff);
459 if (pdev)
460 dev_data = dev_iommu_priv_get(&pdev->dev);
461
462 if (dev_data) {
463 if (__ratelimit(&dev_data->rs)) {
464 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
465 vmg_tag, gpa, flags_rmp, flags);
466 }
467 } else {
468 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
469 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
470 vmg_tag, gpa, flags_rmp, flags);
471 }
472
473 if (pdev)
474 pci_dev_put(pdev);
475 }
476
477 #define IS_IOMMU_MEM_TRANSACTION(flags) \
478 (((flags) & EVENT_FLAG_I) == 0)
479
480 #define IS_WRITE_REQUEST(flags) \
481 ((flags) & EVENT_FLAG_RW)
482
amd_iommu_report_page_fault(u16 devid,u16 domain_id,u64 address,int flags)483 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
484 u64 address, int flags)
485 {
486 struct iommu_dev_data *dev_data = NULL;
487 struct pci_dev *pdev;
488
489 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
490 devid & 0xff);
491 if (pdev)
492 dev_data = dev_iommu_priv_get(&pdev->dev);
493
494 if (dev_data) {
495 /*
496 * If this is a DMA fault (for which the I(nterrupt)
497 * bit will be unset), allow report_iommu_fault() to
498 * prevent logging it.
499 */
500 if (IS_IOMMU_MEM_TRANSACTION(flags)) {
501 if (!report_iommu_fault(&dev_data->domain->domain,
502 &pdev->dev, address,
503 IS_WRITE_REQUEST(flags) ?
504 IOMMU_FAULT_WRITE :
505 IOMMU_FAULT_READ))
506 goto out;
507 }
508
509 if (__ratelimit(&dev_data->rs)) {
510 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
511 domain_id, address, flags);
512 }
513 } else {
514 pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
515 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
516 domain_id, address, flags);
517 }
518
519 out:
520 if (pdev)
521 pci_dev_put(pdev);
522 }
523
iommu_print_event(struct amd_iommu * iommu,void * __evt)524 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
525 {
526 struct device *dev = iommu->iommu.dev;
527 int type, devid, flags, tag;
528 volatile u32 *event = __evt;
529 int count = 0;
530 u64 address;
531 u32 pasid;
532
533 retry:
534 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
535 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
536 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
537 (event[1] & EVENT_DOMID_MASK_LO);
538 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
539 address = (u64)(((u64)event[3]) << 32) | event[2];
540
541 if (type == 0) {
542 /* Did we hit the erratum? */
543 if (++count == LOOP_TIMEOUT) {
544 pr_err("No event written to event log\n");
545 return;
546 }
547 udelay(1);
548 goto retry;
549 }
550
551 if (type == EVENT_TYPE_IO_FAULT) {
552 amd_iommu_report_page_fault(devid, pasid, address, flags);
553 return;
554 }
555
556 switch (type) {
557 case EVENT_TYPE_ILL_DEV:
558 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
559 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
560 pasid, address, flags);
561 dump_dte_entry(devid);
562 break;
563 case EVENT_TYPE_DEV_TAB_ERR:
564 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
565 "address=0x%llx flags=0x%04x]\n",
566 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
567 address, flags);
568 break;
569 case EVENT_TYPE_PAGE_TAB_ERR:
570 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
571 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
572 pasid, address, flags);
573 break;
574 case EVENT_TYPE_ILL_CMD:
575 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
576 dump_command(address);
577 break;
578 case EVENT_TYPE_CMD_HARD_ERR:
579 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
580 address, flags);
581 break;
582 case EVENT_TYPE_IOTLB_INV_TO:
583 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
584 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
585 address);
586 break;
587 case EVENT_TYPE_INV_DEV_REQ:
588 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
590 pasid, address, flags);
591 break;
592 case EVENT_TYPE_RMP_FAULT:
593 amd_iommu_report_rmp_fault(event);
594 break;
595 case EVENT_TYPE_RMP_HW_ERR:
596 amd_iommu_report_rmp_hw_error(event);
597 break;
598 case EVENT_TYPE_INV_PPR_REQ:
599 pasid = PPR_PASID(*((u64 *)__evt));
600 tag = event[1] & 0x03FF;
601 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
602 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
603 pasid, address, flags, tag);
604 break;
605 default:
606 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
607 event[0], event[1], event[2], event[3]);
608 }
609
610 memset(__evt, 0, 4 * sizeof(u32));
611 }
612
iommu_poll_events(struct amd_iommu * iommu)613 static void iommu_poll_events(struct amd_iommu *iommu)
614 {
615 u32 head, tail;
616
617 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
618 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
619
620 while (head != tail) {
621 iommu_print_event(iommu, iommu->evt_buf + head);
622 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
623 }
624
625 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
626 }
627
iommu_handle_ppr_entry(struct amd_iommu * iommu,u64 * raw)628 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
629 {
630 struct amd_iommu_fault fault;
631
632 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
633 pr_err_ratelimited("Unknown PPR request received\n");
634 return;
635 }
636
637 fault.address = raw[1];
638 fault.pasid = PPR_PASID(raw[0]);
639 fault.device_id = PPR_DEVID(raw[0]);
640 fault.tag = PPR_TAG(raw[0]);
641 fault.flags = PPR_FLAGS(raw[0]);
642
643 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
644 }
645
iommu_poll_ppr_log(struct amd_iommu * iommu)646 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
647 {
648 u32 head, tail;
649
650 if (iommu->ppr_log == NULL)
651 return;
652
653 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
654 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
655
656 while (head != tail) {
657 volatile u64 *raw;
658 u64 entry[2];
659 int i;
660
661 raw = (u64 *)(iommu->ppr_log + head);
662
663 /*
664 * Hardware bug: Interrupt may arrive before the entry is
665 * written to memory. If this happens we need to wait for the
666 * entry to arrive.
667 */
668 for (i = 0; i < LOOP_TIMEOUT; ++i) {
669 if (PPR_REQ_TYPE(raw[0]) != 0)
670 break;
671 udelay(1);
672 }
673
674 /* Avoid memcpy function-call overhead */
675 entry[0] = raw[0];
676 entry[1] = raw[1];
677
678 /*
679 * To detect the hardware bug we need to clear the entry
680 * back to zero.
681 */
682 raw[0] = raw[1] = 0UL;
683
684 /* Update head pointer of hardware ring-buffer */
685 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
686 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
687
688 /* Handle PPR entry */
689 iommu_handle_ppr_entry(iommu, entry);
690
691 /* Refresh ring-buffer information */
692 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
693 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
694 }
695 }
696
697 #ifdef CONFIG_IRQ_REMAP
698 static int (*iommu_ga_log_notifier)(u32);
699
amd_iommu_register_ga_log_notifier(int (* notifier)(u32))700 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
701 {
702 iommu_ga_log_notifier = notifier;
703
704 return 0;
705 }
706 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
707
iommu_poll_ga_log(struct amd_iommu * iommu)708 static void iommu_poll_ga_log(struct amd_iommu *iommu)
709 {
710 u32 head, tail, cnt = 0;
711
712 if (iommu->ga_log == NULL)
713 return;
714
715 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
716 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
717
718 while (head != tail) {
719 volatile u64 *raw;
720 u64 log_entry;
721
722 raw = (u64 *)(iommu->ga_log + head);
723 cnt++;
724
725 /* Avoid memcpy function-call overhead */
726 log_entry = *raw;
727
728 /* Update head pointer of hardware ring-buffer */
729 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
730 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
731
732 /* Handle GA entry */
733 switch (GA_REQ_TYPE(log_entry)) {
734 case GA_GUEST_NR:
735 if (!iommu_ga_log_notifier)
736 break;
737
738 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
739 __func__, GA_DEVID(log_entry),
740 GA_TAG(log_entry));
741
742 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
743 pr_err("GA log notifier failed.\n");
744 break;
745 default:
746 break;
747 }
748 }
749 }
750
751 static void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)752 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
753 {
754 if (!irq_remapping_enabled || !dev_is_pci(dev) ||
755 pci_dev_has_special_msi_domain(to_pci_dev(dev)))
756 return;
757
758 dev_set_msi_domain(dev, iommu->msi_domain);
759 }
760
761 #else /* CONFIG_IRQ_REMAP */
762 static inline void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)763 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
764 #endif /* !CONFIG_IRQ_REMAP */
765
766 #define AMD_IOMMU_INT_MASK \
767 (MMIO_STATUS_EVT_OVERFLOW_INT_MASK | \
768 MMIO_STATUS_EVT_INT_MASK | \
769 MMIO_STATUS_PPR_INT_MASK | \
770 MMIO_STATUS_GALOG_INT_MASK)
771
amd_iommu_int_thread(int irq,void * data)772 irqreturn_t amd_iommu_int_thread(int irq, void *data)
773 {
774 struct amd_iommu *iommu = (struct amd_iommu *) data;
775 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
776
777 while (status & AMD_IOMMU_INT_MASK) {
778 /* Enable interrupt sources again */
779 writel(AMD_IOMMU_INT_MASK,
780 iommu->mmio_base + MMIO_STATUS_OFFSET);
781
782 if (status & MMIO_STATUS_EVT_INT_MASK) {
783 pr_devel("Processing IOMMU Event Log\n");
784 iommu_poll_events(iommu);
785 }
786
787 if (status & MMIO_STATUS_PPR_INT_MASK) {
788 pr_devel("Processing IOMMU PPR Log\n");
789 iommu_poll_ppr_log(iommu);
790 }
791
792 #ifdef CONFIG_IRQ_REMAP
793 if (status & MMIO_STATUS_GALOG_INT_MASK) {
794 pr_devel("Processing IOMMU GA Log\n");
795 iommu_poll_ga_log(iommu);
796 }
797 #endif
798
799 if (status & MMIO_STATUS_EVT_OVERFLOW_INT_MASK) {
800 pr_info_ratelimited("IOMMU event log overflow\n");
801 amd_iommu_restart_event_logging(iommu);
802 }
803
804 /*
805 * Hardware bug: ERBT1312
806 * When re-enabling interrupt (by writing 1
807 * to clear the bit), the hardware might also try to set
808 * the interrupt bit in the event status register.
809 * In this scenario, the bit will be set, and disable
810 * subsequent interrupts.
811 *
812 * Workaround: The IOMMU driver should read back the
813 * status register and check if the interrupt bits are cleared.
814 * If not, driver will need to go through the interrupt handler
815 * again and re-clear the bits
816 */
817 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
818 }
819 return IRQ_HANDLED;
820 }
821
amd_iommu_int_handler(int irq,void * data)822 irqreturn_t amd_iommu_int_handler(int irq, void *data)
823 {
824 return IRQ_WAKE_THREAD;
825 }
826
827 /****************************************************************************
828 *
829 * IOMMU command queuing functions
830 *
831 ****************************************************************************/
832
wait_on_sem(struct amd_iommu * iommu,u64 data)833 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
834 {
835 int i = 0;
836
837 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
838 udelay(1);
839 i += 1;
840 }
841
842 if (i == LOOP_TIMEOUT) {
843 pr_alert("Completion-Wait loop timed out\n");
844 return -EIO;
845 }
846
847 return 0;
848 }
849
copy_cmd_to_buffer(struct amd_iommu * iommu,struct iommu_cmd * cmd)850 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
851 struct iommu_cmd *cmd)
852 {
853 u8 *target;
854 u32 tail;
855
856 /* Copy command to buffer */
857 tail = iommu->cmd_buf_tail;
858 target = iommu->cmd_buf + tail;
859 memcpy(target, cmd, sizeof(*cmd));
860
861 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
862 iommu->cmd_buf_tail = tail;
863
864 /* Tell the IOMMU about it */
865 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
866 }
867
build_completion_wait(struct iommu_cmd * cmd,struct amd_iommu * iommu,u64 data)868 static void build_completion_wait(struct iommu_cmd *cmd,
869 struct amd_iommu *iommu,
870 u64 data)
871 {
872 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
873
874 memset(cmd, 0, sizeof(*cmd));
875 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
876 cmd->data[1] = upper_32_bits(paddr);
877 cmd->data[2] = lower_32_bits(data);
878 cmd->data[3] = upper_32_bits(data);
879 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
880 }
881
build_inv_dte(struct iommu_cmd * cmd,u16 devid)882 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
883 {
884 memset(cmd, 0, sizeof(*cmd));
885 cmd->data[0] = devid;
886 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
887 }
888
889 /*
890 * Builds an invalidation address which is suitable for one page or multiple
891 * pages. Sets the size bit (S) as needed is more than one page is flushed.
892 */
build_inv_address(u64 address,size_t size)893 static inline u64 build_inv_address(u64 address, size_t size)
894 {
895 u64 pages, end, msb_diff;
896
897 pages = iommu_num_pages(address, size, PAGE_SIZE);
898
899 if (pages == 1)
900 return address & PAGE_MASK;
901
902 end = address + size - 1;
903
904 /*
905 * msb_diff would hold the index of the most significant bit that
906 * flipped between the start and end.
907 */
908 msb_diff = fls64(end ^ address) - 1;
909
910 /*
911 * Bits 63:52 are sign extended. If for some reason bit 51 is different
912 * between the start and the end, invalidate everything.
913 */
914 if (unlikely(msb_diff > 51)) {
915 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
916 } else {
917 /*
918 * The msb-bit must be clear on the address. Just set all the
919 * lower bits.
920 */
921 address |= (1ull << msb_diff) - 1;
922 }
923
924 /* Clear bits 11:0 */
925 address &= PAGE_MASK;
926
927 /* Set the size bit - we flush more than one 4kb page */
928 return address | CMD_INV_IOMMU_PAGES_SIZE_MASK;
929 }
930
build_inv_iommu_pages(struct iommu_cmd * cmd,u64 address,size_t size,u16 domid,int pde)931 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
932 size_t size, u16 domid, int pde)
933 {
934 u64 inv_address = build_inv_address(address, size);
935
936 memset(cmd, 0, sizeof(*cmd));
937 cmd->data[1] |= domid;
938 cmd->data[2] = lower_32_bits(inv_address);
939 cmd->data[3] = upper_32_bits(inv_address);
940 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
941 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
942 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
943 }
944
build_inv_iotlb_pages(struct iommu_cmd * cmd,u16 devid,int qdep,u64 address,size_t size)945 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
946 u64 address, size_t size)
947 {
948 u64 inv_address = build_inv_address(address, size);
949
950 memset(cmd, 0, sizeof(*cmd));
951 cmd->data[0] = devid;
952 cmd->data[0] |= (qdep & 0xff) << 24;
953 cmd->data[1] = devid;
954 cmd->data[2] = lower_32_bits(inv_address);
955 cmd->data[3] = upper_32_bits(inv_address);
956 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
957 }
958
build_inv_iommu_pasid(struct iommu_cmd * cmd,u16 domid,u32 pasid,u64 address,bool size)959 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
960 u64 address, bool size)
961 {
962 memset(cmd, 0, sizeof(*cmd));
963
964 address &= ~(0xfffULL);
965
966 cmd->data[0] = pasid;
967 cmd->data[1] = domid;
968 cmd->data[2] = lower_32_bits(address);
969 cmd->data[3] = upper_32_bits(address);
970 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
972 if (size)
973 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
974 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
975 }
976
build_inv_iotlb_pasid(struct iommu_cmd * cmd,u16 devid,u32 pasid,int qdep,u64 address,bool size)977 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
978 int qdep, u64 address, bool size)
979 {
980 memset(cmd, 0, sizeof(*cmd));
981
982 address &= ~(0xfffULL);
983
984 cmd->data[0] = devid;
985 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
986 cmd->data[0] |= (qdep & 0xff) << 24;
987 cmd->data[1] = devid;
988 cmd->data[1] |= (pasid & 0xff) << 16;
989 cmd->data[2] = lower_32_bits(address);
990 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
991 cmd->data[3] = upper_32_bits(address);
992 if (size)
993 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
994 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
995 }
996
build_complete_ppr(struct iommu_cmd * cmd,u16 devid,u32 pasid,int status,int tag,bool gn)997 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
998 int status, int tag, bool gn)
999 {
1000 memset(cmd, 0, sizeof(*cmd));
1001
1002 cmd->data[0] = devid;
1003 if (gn) {
1004 cmd->data[1] = pasid;
1005 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1006 }
1007 cmd->data[3] = tag & 0x1ff;
1008 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1009
1010 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1011 }
1012
build_inv_all(struct iommu_cmd * cmd)1013 static void build_inv_all(struct iommu_cmd *cmd)
1014 {
1015 memset(cmd, 0, sizeof(*cmd));
1016 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1017 }
1018
build_inv_irt(struct iommu_cmd * cmd,u16 devid)1019 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1020 {
1021 memset(cmd, 0, sizeof(*cmd));
1022 cmd->data[0] = devid;
1023 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1024 }
1025
1026 /*
1027 * Writes the command to the IOMMUs command buffer and informs the
1028 * hardware about the new command.
1029 */
__iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1030 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1031 struct iommu_cmd *cmd,
1032 bool sync)
1033 {
1034 unsigned int count = 0;
1035 u32 left, next_tail;
1036
1037 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1038 again:
1039 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1040
1041 if (left <= 0x20) {
1042 /* Skip udelay() the first time around */
1043 if (count++) {
1044 if (count == LOOP_TIMEOUT) {
1045 pr_err("Command buffer timeout\n");
1046 return -EIO;
1047 }
1048
1049 udelay(1);
1050 }
1051
1052 /* Update head and recheck remaining space */
1053 iommu->cmd_buf_head = readl(iommu->mmio_base +
1054 MMIO_CMD_HEAD_OFFSET);
1055
1056 goto again;
1057 }
1058
1059 copy_cmd_to_buffer(iommu, cmd);
1060
1061 /* Do we need to make sure all commands are processed? */
1062 iommu->need_sync = sync;
1063
1064 return 0;
1065 }
1066
iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1067 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1068 struct iommu_cmd *cmd,
1069 bool sync)
1070 {
1071 unsigned long flags;
1072 int ret;
1073
1074 raw_spin_lock_irqsave(&iommu->lock, flags);
1075 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1076 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1077
1078 return ret;
1079 }
1080
iommu_queue_command(struct amd_iommu * iommu,struct iommu_cmd * cmd)1081 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1082 {
1083 return iommu_queue_command_sync(iommu, cmd, true);
1084 }
1085
1086 /*
1087 * This function queues a completion wait command into the command
1088 * buffer of an IOMMU
1089 */
iommu_completion_wait(struct amd_iommu * iommu)1090 static int iommu_completion_wait(struct amd_iommu *iommu)
1091 {
1092 struct iommu_cmd cmd;
1093 unsigned long flags;
1094 int ret;
1095 u64 data;
1096
1097 if (!iommu->need_sync)
1098 return 0;
1099
1100 raw_spin_lock_irqsave(&iommu->lock, flags);
1101
1102 data = ++iommu->cmd_sem_val;
1103 build_completion_wait(&cmd, iommu, data);
1104
1105 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1106 if (ret)
1107 goto out_unlock;
1108
1109 ret = wait_on_sem(iommu, data);
1110
1111 out_unlock:
1112 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1113
1114 return ret;
1115 }
1116
iommu_flush_dte(struct amd_iommu * iommu,u16 devid)1117 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1118 {
1119 struct iommu_cmd cmd;
1120
1121 build_inv_dte(&cmd, devid);
1122
1123 return iommu_queue_command(iommu, &cmd);
1124 }
1125
amd_iommu_flush_dte_all(struct amd_iommu * iommu)1126 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1127 {
1128 u32 devid;
1129
1130 for (devid = 0; devid <= 0xffff; ++devid)
1131 iommu_flush_dte(iommu, devid);
1132
1133 iommu_completion_wait(iommu);
1134 }
1135
1136 /*
1137 * This function uses heavy locking and may disable irqs for some time. But
1138 * this is no issue because it is only called during resume.
1139 */
amd_iommu_flush_tlb_all(struct amd_iommu * iommu)1140 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1141 {
1142 u32 dom_id;
1143
1144 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1145 struct iommu_cmd cmd;
1146 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1147 dom_id, 1);
1148 iommu_queue_command(iommu, &cmd);
1149 }
1150
1151 iommu_completion_wait(iommu);
1152 }
1153
amd_iommu_flush_tlb_domid(struct amd_iommu * iommu,u32 dom_id)1154 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1155 {
1156 struct iommu_cmd cmd;
1157
1158 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1159 dom_id, 1);
1160 iommu_queue_command(iommu, &cmd);
1161
1162 iommu_completion_wait(iommu);
1163 }
1164
amd_iommu_flush_all(struct amd_iommu * iommu)1165 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1166 {
1167 struct iommu_cmd cmd;
1168
1169 build_inv_all(&cmd);
1170
1171 iommu_queue_command(iommu, &cmd);
1172 iommu_completion_wait(iommu);
1173 }
1174
iommu_flush_irt(struct amd_iommu * iommu,u16 devid)1175 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1176 {
1177 struct iommu_cmd cmd;
1178
1179 build_inv_irt(&cmd, devid);
1180
1181 iommu_queue_command(iommu, &cmd);
1182 }
1183
amd_iommu_flush_irt_all(struct amd_iommu * iommu)1184 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1185 {
1186 u32 devid;
1187
1188 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1189 iommu_flush_irt(iommu, devid);
1190
1191 iommu_completion_wait(iommu);
1192 }
1193
iommu_flush_all_caches(struct amd_iommu * iommu)1194 void iommu_flush_all_caches(struct amd_iommu *iommu)
1195 {
1196 if (iommu_feature(iommu, FEATURE_IA)) {
1197 amd_iommu_flush_all(iommu);
1198 } else {
1199 amd_iommu_flush_dte_all(iommu);
1200 amd_iommu_flush_irt_all(iommu);
1201 amd_iommu_flush_tlb_all(iommu);
1202 }
1203 }
1204
1205 /*
1206 * Command send function for flushing on-device TLB
1207 */
device_flush_iotlb(struct iommu_dev_data * dev_data,u64 address,size_t size)1208 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1209 u64 address, size_t size)
1210 {
1211 struct amd_iommu *iommu;
1212 struct iommu_cmd cmd;
1213 int qdep;
1214
1215 qdep = dev_data->ats.qdep;
1216 iommu = amd_iommu_rlookup_table[dev_data->devid];
1217
1218 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1219
1220 return iommu_queue_command(iommu, &cmd);
1221 }
1222
device_flush_dte_alias(struct pci_dev * pdev,u16 alias,void * data)1223 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1224 {
1225 struct amd_iommu *iommu = data;
1226
1227 return iommu_flush_dte(iommu, alias);
1228 }
1229
1230 /*
1231 * Command send function for invalidating a device table entry
1232 */
device_flush_dte(struct iommu_dev_data * dev_data)1233 static int device_flush_dte(struct iommu_dev_data *dev_data)
1234 {
1235 struct amd_iommu *iommu;
1236 u16 alias;
1237 int ret;
1238
1239 iommu = amd_iommu_rlookup_table[dev_data->devid];
1240
1241 if (dev_data->pdev)
1242 ret = pci_for_each_dma_alias(dev_data->pdev,
1243 device_flush_dte_alias, iommu);
1244 else
1245 ret = iommu_flush_dte(iommu, dev_data->devid);
1246 if (ret)
1247 return ret;
1248
1249 alias = amd_iommu_alias_table[dev_data->devid];
1250 if (alias != dev_data->devid) {
1251 ret = iommu_flush_dte(iommu, alias);
1252 if (ret)
1253 return ret;
1254 }
1255
1256 if (dev_data->ats.enabled)
1257 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1258
1259 return ret;
1260 }
1261
1262 /*
1263 * TLB invalidation function which is called from the mapping functions.
1264 * It invalidates a single PTE if the range to flush is within a single
1265 * page. Otherwise it flushes the whole TLB of the IOMMU.
1266 */
__domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1267 static void __domain_flush_pages(struct protection_domain *domain,
1268 u64 address, size_t size, int pde)
1269 {
1270 struct iommu_dev_data *dev_data;
1271 struct iommu_cmd cmd;
1272 int ret = 0, i;
1273
1274 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1275
1276 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1277 if (!domain->dev_iommu[i])
1278 continue;
1279
1280 /*
1281 * Devices of this domain are behind this IOMMU
1282 * We need a TLB flush
1283 */
1284 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1285 }
1286
1287 list_for_each_entry(dev_data, &domain->dev_list, list) {
1288
1289 if (!dev_data->ats.enabled)
1290 continue;
1291
1292 ret |= device_flush_iotlb(dev_data, address, size);
1293 }
1294
1295 WARN_ON(ret);
1296 }
1297
domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1298 static void domain_flush_pages(struct protection_domain *domain,
1299 u64 address, size_t size, int pde)
1300 {
1301 if (likely(!amd_iommu_np_cache)) {
1302 __domain_flush_pages(domain, address, size, pde);
1303 return;
1304 }
1305
1306 /*
1307 * When NpCache is on, we infer that we run in a VM and use a vIOMMU.
1308 * In such setups it is best to avoid flushes of ranges which are not
1309 * naturally aligned, since it would lead to flushes of unmodified
1310 * PTEs. Such flushes would require the hypervisor to do more work than
1311 * necessary. Therefore, perform repeated flushes of aligned ranges
1312 * until you cover the range. Each iteration flushes the smaller
1313 * between the natural alignment of the address that we flush and the
1314 * greatest naturally aligned region that fits in the range.
1315 */
1316 while (size != 0) {
1317 int addr_alignment = __ffs(address);
1318 int size_alignment = __fls(size);
1319 int min_alignment;
1320 size_t flush_size;
1321
1322 /*
1323 * size is always non-zero, but address might be zero, causing
1324 * addr_alignment to be negative. As the casting of the
1325 * argument in __ffs(address) to long might trim the high bits
1326 * of the address on x86-32, cast to long when doing the check.
1327 */
1328 if (likely((unsigned long)address != 0))
1329 min_alignment = min(addr_alignment, size_alignment);
1330 else
1331 min_alignment = size_alignment;
1332
1333 flush_size = 1ul << min_alignment;
1334
1335 __domain_flush_pages(domain, address, flush_size, pde);
1336 address += flush_size;
1337 size -= flush_size;
1338 }
1339 }
1340
1341 /* Flush the whole IO/TLB for a given protection domain - including PDE */
amd_iommu_domain_flush_tlb_pde(struct protection_domain * domain)1342 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain)
1343 {
1344 domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1345 }
1346
amd_iommu_domain_flush_complete(struct protection_domain * domain)1347 void amd_iommu_domain_flush_complete(struct protection_domain *domain)
1348 {
1349 int i;
1350
1351 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1352 if (domain && !domain->dev_iommu[i])
1353 continue;
1354
1355 /*
1356 * Devices of this domain are behind this IOMMU
1357 * We need to wait for completion of all commands.
1358 */
1359 iommu_completion_wait(amd_iommus[i]);
1360 }
1361 }
1362
1363 /* Flush the not present cache if it exists */
domain_flush_np_cache(struct protection_domain * domain,dma_addr_t iova,size_t size)1364 static void domain_flush_np_cache(struct protection_domain *domain,
1365 dma_addr_t iova, size_t size)
1366 {
1367 if (unlikely(amd_iommu_np_cache)) {
1368 unsigned long flags;
1369
1370 spin_lock_irqsave(&domain->lock, flags);
1371 domain_flush_pages(domain, iova, size, 1);
1372 amd_iommu_domain_flush_complete(domain);
1373 spin_unlock_irqrestore(&domain->lock, flags);
1374 }
1375 }
1376
1377
1378 /*
1379 * This function flushes the DTEs for all devices in domain
1380 */
domain_flush_devices(struct protection_domain * domain)1381 static void domain_flush_devices(struct protection_domain *domain)
1382 {
1383 struct iommu_dev_data *dev_data;
1384
1385 list_for_each_entry(dev_data, &domain->dev_list, list)
1386 device_flush_dte(dev_data);
1387 }
1388
1389 /****************************************************************************
1390 *
1391 * The next functions belong to the domain allocation. A domain is
1392 * allocated for every IOMMU as the default domain. If device isolation
1393 * is enabled, every device get its own domain. The most important thing
1394 * about domains is the page table mapping the DMA address space they
1395 * contain.
1396 *
1397 ****************************************************************************/
1398
domain_id_alloc(void)1399 static u16 domain_id_alloc(void)
1400 {
1401 int id;
1402
1403 spin_lock(&pd_bitmap_lock);
1404 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1405 BUG_ON(id == 0);
1406 if (id > 0 && id < MAX_DOMAIN_ID)
1407 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1408 else
1409 id = 0;
1410 spin_unlock(&pd_bitmap_lock);
1411
1412 return id;
1413 }
1414
domain_id_free(int id)1415 static void domain_id_free(int id)
1416 {
1417 spin_lock(&pd_bitmap_lock);
1418 if (id > 0 && id < MAX_DOMAIN_ID)
1419 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1420 spin_unlock(&pd_bitmap_lock);
1421 }
1422
free_gcr3_tbl_level1(u64 * tbl)1423 static void free_gcr3_tbl_level1(u64 *tbl)
1424 {
1425 u64 *ptr;
1426 int i;
1427
1428 for (i = 0; i < 512; ++i) {
1429 if (!(tbl[i] & GCR3_VALID))
1430 continue;
1431
1432 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1433
1434 free_page((unsigned long)ptr);
1435 }
1436 }
1437
free_gcr3_tbl_level2(u64 * tbl)1438 static void free_gcr3_tbl_level2(u64 *tbl)
1439 {
1440 u64 *ptr;
1441 int i;
1442
1443 for (i = 0; i < 512; ++i) {
1444 if (!(tbl[i] & GCR3_VALID))
1445 continue;
1446
1447 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1448
1449 free_gcr3_tbl_level1(ptr);
1450 }
1451 }
1452
free_gcr3_table(struct protection_domain * domain)1453 static void free_gcr3_table(struct protection_domain *domain)
1454 {
1455 if (domain->glx == 2)
1456 free_gcr3_tbl_level2(domain->gcr3_tbl);
1457 else if (domain->glx == 1)
1458 free_gcr3_tbl_level1(domain->gcr3_tbl);
1459 else
1460 BUG_ON(domain->glx != 0);
1461
1462 free_page((unsigned long)domain->gcr3_tbl);
1463 }
1464
set_dte_entry(u16 devid,struct protection_domain * domain,bool ats,bool ppr)1465 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1466 bool ats, bool ppr)
1467 {
1468 u64 pte_root = 0;
1469 u64 flags = 0;
1470 u32 old_domid;
1471
1472 if (domain->iop.mode != PAGE_MODE_NONE)
1473 pte_root = iommu_virt_to_phys(domain->iop.root);
1474
1475 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK)
1476 << DEV_ENTRY_MODE_SHIFT;
1477 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1478
1479 flags = amd_iommu_dev_table[devid].data[1];
1480
1481 if (ats)
1482 flags |= DTE_FLAG_IOTLB;
1483
1484 if (ppr) {
1485 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1486
1487 if (iommu_feature(iommu, FEATURE_EPHSUP))
1488 pte_root |= 1ULL << DEV_ENTRY_PPR;
1489 }
1490
1491 if (domain->flags & PD_IOMMUV2_MASK) {
1492 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1493 u64 glx = domain->glx;
1494 u64 tmp;
1495
1496 pte_root |= DTE_FLAG_GV;
1497 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1498
1499 /* First mask out possible old values for GCR3 table */
1500 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1501 flags &= ~tmp;
1502
1503 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1504 flags &= ~tmp;
1505
1506 /* Encode GCR3 table into DTE */
1507 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1508 pte_root |= tmp;
1509
1510 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1511 flags |= tmp;
1512
1513 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1514 flags |= tmp;
1515 }
1516
1517 flags &= ~DEV_DOMID_MASK;
1518 flags |= domain->id;
1519
1520 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1521 amd_iommu_dev_table[devid].data[1] = flags;
1522 amd_iommu_dev_table[devid].data[0] = pte_root;
1523
1524 /*
1525 * A kdump kernel might be replacing a domain ID that was copied from
1526 * the previous kernel--if so, it needs to flush the translation cache
1527 * entries for the old domain ID that is being overwritten
1528 */
1529 if (old_domid) {
1530 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1531
1532 amd_iommu_flush_tlb_domid(iommu, old_domid);
1533 }
1534 }
1535
clear_dte_entry(u16 devid)1536 static void clear_dte_entry(u16 devid)
1537 {
1538 /* remove entry from the device table seen by the hardware */
1539 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1540 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1541
1542 amd_iommu_apply_erratum_63(devid);
1543 }
1544
do_attach(struct iommu_dev_data * dev_data,struct protection_domain * domain)1545 static void do_attach(struct iommu_dev_data *dev_data,
1546 struct protection_domain *domain)
1547 {
1548 struct amd_iommu *iommu;
1549 bool ats;
1550
1551 iommu = amd_iommu_rlookup_table[dev_data->devid];
1552 ats = dev_data->ats.enabled;
1553
1554 /* Update data structures */
1555 dev_data->domain = domain;
1556 list_add(&dev_data->list, &domain->dev_list);
1557
1558 /* Do reference counting */
1559 domain->dev_iommu[iommu->index] += 1;
1560 domain->dev_cnt += 1;
1561
1562 /* Update device table */
1563 set_dte_entry(dev_data->devid, domain,
1564 ats, dev_data->iommu_v2);
1565 clone_aliases(dev_data->pdev);
1566
1567 device_flush_dte(dev_data);
1568 }
1569
do_detach(struct iommu_dev_data * dev_data)1570 static void do_detach(struct iommu_dev_data *dev_data)
1571 {
1572 struct protection_domain *domain = dev_data->domain;
1573 struct amd_iommu *iommu;
1574
1575 iommu = amd_iommu_rlookup_table[dev_data->devid];
1576
1577 /* Update data structures */
1578 dev_data->domain = NULL;
1579 list_del(&dev_data->list);
1580 clear_dte_entry(dev_data->devid);
1581 clone_aliases(dev_data->pdev);
1582
1583 /* Flush the DTE entry */
1584 device_flush_dte(dev_data);
1585
1586 /* Flush IOTLB */
1587 amd_iommu_domain_flush_tlb_pde(domain);
1588
1589 /* Wait for the flushes to finish */
1590 amd_iommu_domain_flush_complete(domain);
1591
1592 /* decrease reference counters - needs to happen after the flushes */
1593 domain->dev_iommu[iommu->index] -= 1;
1594 domain->dev_cnt -= 1;
1595 }
1596
pdev_iommuv2_disable(struct pci_dev * pdev)1597 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1598 {
1599 pci_disable_ats(pdev);
1600 pci_disable_pri(pdev);
1601 pci_disable_pasid(pdev);
1602 }
1603
pdev_iommuv2_enable(struct pci_dev * pdev)1604 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1605 {
1606 int ret;
1607
1608 /* Only allow access to user-accessible pages */
1609 ret = pci_enable_pasid(pdev, 0);
1610 if (ret)
1611 goto out_err;
1612
1613 /* First reset the PRI state of the device */
1614 ret = pci_reset_pri(pdev);
1615 if (ret)
1616 goto out_err;
1617
1618 /* Enable PRI */
1619 /* FIXME: Hardcode number of outstanding requests for now */
1620 ret = pci_enable_pri(pdev, 32);
1621 if (ret)
1622 goto out_err;
1623
1624 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1625 if (ret)
1626 goto out_err;
1627
1628 return 0;
1629
1630 out_err:
1631 pci_disable_pri(pdev);
1632 pci_disable_pasid(pdev);
1633
1634 return ret;
1635 }
1636
1637 /*
1638 * If a device is not yet associated with a domain, this function makes the
1639 * device visible in the domain
1640 */
attach_device(struct device * dev,struct protection_domain * domain)1641 static int attach_device(struct device *dev,
1642 struct protection_domain *domain)
1643 {
1644 struct iommu_dev_data *dev_data;
1645 struct pci_dev *pdev;
1646 unsigned long flags;
1647 int ret;
1648
1649 spin_lock_irqsave(&domain->lock, flags);
1650
1651 dev_data = dev_iommu_priv_get(dev);
1652
1653 spin_lock(&dev_data->lock);
1654
1655 ret = -EBUSY;
1656 if (dev_data->domain != NULL)
1657 goto out;
1658
1659 if (!dev_is_pci(dev))
1660 goto skip_ats_check;
1661
1662 pdev = to_pci_dev(dev);
1663 if (domain->flags & PD_IOMMUV2_MASK) {
1664 struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
1665
1666 ret = -EINVAL;
1667 if (def_domain->type != IOMMU_DOMAIN_IDENTITY)
1668 goto out;
1669
1670 if (dev_data->iommu_v2) {
1671 if (pdev_iommuv2_enable(pdev) != 0)
1672 goto out;
1673
1674 dev_data->ats.enabled = true;
1675 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1676 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
1677 }
1678 } else if (amd_iommu_iotlb_sup &&
1679 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1680 dev_data->ats.enabled = true;
1681 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1682 }
1683
1684 skip_ats_check:
1685 ret = 0;
1686
1687 do_attach(dev_data, domain);
1688
1689 /*
1690 * We might boot into a crash-kernel here. The crashed kernel
1691 * left the caches in the IOMMU dirty. So we have to flush
1692 * here to evict all dirty stuff.
1693 */
1694 amd_iommu_domain_flush_tlb_pde(domain);
1695
1696 amd_iommu_domain_flush_complete(domain);
1697
1698 out:
1699 spin_unlock(&dev_data->lock);
1700
1701 spin_unlock_irqrestore(&domain->lock, flags);
1702
1703 return ret;
1704 }
1705
1706 /*
1707 * Removes a device from a protection domain (with devtable_lock held)
1708 */
detach_device(struct device * dev)1709 static void detach_device(struct device *dev)
1710 {
1711 struct protection_domain *domain;
1712 struct iommu_dev_data *dev_data;
1713 unsigned long flags;
1714
1715 dev_data = dev_iommu_priv_get(dev);
1716 domain = dev_data->domain;
1717
1718 spin_lock_irqsave(&domain->lock, flags);
1719
1720 spin_lock(&dev_data->lock);
1721
1722 /*
1723 * First check if the device is still attached. It might already
1724 * be detached from its domain because the generic
1725 * iommu_detach_group code detached it and we try again here in
1726 * our alias handling.
1727 */
1728 if (WARN_ON(!dev_data->domain))
1729 goto out;
1730
1731 do_detach(dev_data);
1732
1733 if (!dev_is_pci(dev))
1734 goto out;
1735
1736 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
1737 pdev_iommuv2_disable(to_pci_dev(dev));
1738 else if (dev_data->ats.enabled)
1739 pci_disable_ats(to_pci_dev(dev));
1740
1741 dev_data->ats.enabled = false;
1742
1743 out:
1744 spin_unlock(&dev_data->lock);
1745
1746 spin_unlock_irqrestore(&domain->lock, flags);
1747 }
1748
amd_iommu_probe_device(struct device * dev)1749 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
1750 {
1751 struct iommu_device *iommu_dev;
1752 struct amd_iommu *iommu;
1753 int ret, devid;
1754
1755 if (!check_device(dev))
1756 return ERR_PTR(-ENODEV);
1757
1758 devid = get_device_id(dev);
1759 iommu = amd_iommu_rlookup_table[devid];
1760
1761 if (dev_iommu_priv_get(dev))
1762 return &iommu->iommu;
1763
1764 ret = iommu_init_device(dev);
1765 if (ret) {
1766 if (ret != -ENOTSUPP)
1767 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
1768 iommu_dev = ERR_PTR(ret);
1769 iommu_ignore_device(dev);
1770 } else {
1771 amd_iommu_set_pci_msi_domain(dev, iommu);
1772 iommu_dev = &iommu->iommu;
1773 }
1774
1775 iommu_completion_wait(iommu);
1776
1777 return iommu_dev;
1778 }
1779
amd_iommu_probe_finalize(struct device * dev)1780 static void amd_iommu_probe_finalize(struct device *dev)
1781 {
1782 /* Domains are initialized for this device - have a look what we ended up with */
1783 set_dma_ops(dev, NULL);
1784 iommu_setup_dma_ops(dev, 0, U64_MAX);
1785 }
1786
amd_iommu_release_device(struct device * dev)1787 static void amd_iommu_release_device(struct device *dev)
1788 {
1789 int devid = get_device_id(dev);
1790 struct amd_iommu *iommu;
1791
1792 if (!check_device(dev))
1793 return;
1794
1795 iommu = amd_iommu_rlookup_table[devid];
1796
1797 amd_iommu_uninit_device(dev);
1798 iommu_completion_wait(iommu);
1799 }
1800
amd_iommu_device_group(struct device * dev)1801 static struct iommu_group *amd_iommu_device_group(struct device *dev)
1802 {
1803 if (dev_is_pci(dev))
1804 return pci_device_group(dev);
1805
1806 return acpihid_device_group(dev);
1807 }
1808
1809 /*****************************************************************************
1810 *
1811 * The next functions belong to the dma_ops mapping/unmapping code.
1812 *
1813 *****************************************************************************/
1814
update_device_table(struct protection_domain * domain)1815 static void update_device_table(struct protection_domain *domain)
1816 {
1817 struct iommu_dev_data *dev_data;
1818
1819 list_for_each_entry(dev_data, &domain->dev_list, list) {
1820 set_dte_entry(dev_data->devid, domain,
1821 dev_data->ats.enabled, dev_data->iommu_v2);
1822 clone_aliases(dev_data->pdev);
1823 }
1824 }
1825
amd_iommu_update_and_flush_device_table(struct protection_domain * domain)1826 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain)
1827 {
1828 update_device_table(domain);
1829 domain_flush_devices(domain);
1830 }
1831
amd_iommu_domain_update(struct protection_domain * domain)1832 void amd_iommu_domain_update(struct protection_domain *domain)
1833 {
1834 /* Update device table */
1835 amd_iommu_update_and_flush_device_table(domain);
1836
1837 /* Flush domain TLB(s) and wait for completion */
1838 amd_iommu_domain_flush_tlb_pde(domain);
1839 amd_iommu_domain_flush_complete(domain);
1840 }
1841
amd_iommu_init_api(void)1842 int __init amd_iommu_init_api(void)
1843 {
1844 int err;
1845
1846 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
1847 if (err)
1848 return err;
1849 #ifdef CONFIG_ARM_AMBA
1850 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
1851 if (err)
1852 return err;
1853 #endif
1854 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
1855 if (err)
1856 return err;
1857
1858 return 0;
1859 }
1860
1861 /*****************************************************************************
1862 *
1863 * The following functions belong to the exported interface of AMD IOMMU
1864 *
1865 * This interface allows access to lower level functions of the IOMMU
1866 * like protection domain handling and assignement of devices to domains
1867 * which is not possible with the dma_ops interface.
1868 *
1869 *****************************************************************************/
1870
cleanup_domain(struct protection_domain * domain)1871 static void cleanup_domain(struct protection_domain *domain)
1872 {
1873 struct iommu_dev_data *entry;
1874 unsigned long flags;
1875
1876 spin_lock_irqsave(&domain->lock, flags);
1877
1878 while (!list_empty(&domain->dev_list)) {
1879 entry = list_first_entry(&domain->dev_list,
1880 struct iommu_dev_data, list);
1881 BUG_ON(!entry->domain);
1882 do_detach(entry);
1883 }
1884
1885 spin_unlock_irqrestore(&domain->lock, flags);
1886 }
1887
protection_domain_free(struct protection_domain * domain)1888 static void protection_domain_free(struct protection_domain *domain)
1889 {
1890 if (!domain)
1891 return;
1892
1893 if (domain->id)
1894 domain_id_free(domain->id);
1895
1896 if (domain->iop.pgtbl_cfg.tlb)
1897 free_io_pgtable_ops(&domain->iop.iop.ops);
1898
1899 kfree(domain);
1900 }
1901
protection_domain_init_v1(struct protection_domain * domain,int mode)1902 static int protection_domain_init_v1(struct protection_domain *domain, int mode)
1903 {
1904 u64 *pt_root = NULL;
1905
1906 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
1907
1908 spin_lock_init(&domain->lock);
1909 domain->id = domain_id_alloc();
1910 if (!domain->id)
1911 return -ENOMEM;
1912 INIT_LIST_HEAD(&domain->dev_list);
1913
1914 if (mode != PAGE_MODE_NONE) {
1915 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1916 if (!pt_root)
1917 return -ENOMEM;
1918 }
1919
1920 amd_iommu_domain_set_pgtable(domain, pt_root, mode);
1921
1922 return 0;
1923 }
1924
protection_domain_alloc(unsigned int type)1925 static struct protection_domain *protection_domain_alloc(unsigned int type)
1926 {
1927 struct io_pgtable_ops *pgtbl_ops;
1928 struct protection_domain *domain;
1929 int pgtable = amd_iommu_pgtable;
1930 int mode = DEFAULT_PGTABLE_LEVEL;
1931 int ret;
1932
1933 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1934 if (!domain)
1935 return NULL;
1936
1937 /*
1938 * Force IOMMU v1 page table when iommu=pt and
1939 * when allocating domain for pass-through devices.
1940 */
1941 if (type == IOMMU_DOMAIN_IDENTITY) {
1942 pgtable = AMD_IOMMU_V1;
1943 mode = PAGE_MODE_NONE;
1944 } else if (type == IOMMU_DOMAIN_UNMANAGED) {
1945 pgtable = AMD_IOMMU_V1;
1946 }
1947
1948 switch (pgtable) {
1949 case AMD_IOMMU_V1:
1950 ret = protection_domain_init_v1(domain, mode);
1951 break;
1952 default:
1953 ret = -EINVAL;
1954 }
1955
1956 if (ret)
1957 goto out_err;
1958
1959 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
1960 if (!pgtbl_ops)
1961 goto out_err;
1962
1963 return domain;
1964 out_err:
1965 kfree(domain);
1966 return NULL;
1967 }
1968
amd_iommu_domain_alloc(unsigned type)1969 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
1970 {
1971 struct protection_domain *domain;
1972
1973 domain = protection_domain_alloc(type);
1974 if (!domain)
1975 return NULL;
1976
1977 domain->domain.geometry.aperture_start = 0;
1978 domain->domain.geometry.aperture_end = ~0ULL;
1979 domain->domain.geometry.force_aperture = true;
1980
1981 return &domain->domain;
1982 }
1983
amd_iommu_domain_free(struct iommu_domain * dom)1984 static void amd_iommu_domain_free(struct iommu_domain *dom)
1985 {
1986 struct protection_domain *domain;
1987
1988 domain = to_pdomain(dom);
1989
1990 if (domain->dev_cnt > 0)
1991 cleanup_domain(domain);
1992
1993 BUG_ON(domain->dev_cnt != 0);
1994
1995 if (!dom)
1996 return;
1997
1998 if (domain->flags & PD_IOMMUV2_MASK)
1999 free_gcr3_table(domain);
2000
2001 protection_domain_free(domain);
2002 }
2003
amd_iommu_detach_device(struct iommu_domain * dom,struct device * dev)2004 static void amd_iommu_detach_device(struct iommu_domain *dom,
2005 struct device *dev)
2006 {
2007 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2008 int devid = get_device_id(dev);
2009 struct amd_iommu *iommu;
2010
2011 if (!check_device(dev))
2012 return;
2013
2014 if (dev_data->domain != NULL)
2015 detach_device(dev);
2016
2017 iommu = amd_iommu_rlookup_table[devid];
2018 if (!iommu)
2019 return;
2020
2021 #ifdef CONFIG_IRQ_REMAP
2022 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2023 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2024 dev_data->use_vapic = 0;
2025 #endif
2026
2027 iommu_completion_wait(iommu);
2028 }
2029
amd_iommu_attach_device(struct iommu_domain * dom,struct device * dev)2030 static int amd_iommu_attach_device(struct iommu_domain *dom,
2031 struct device *dev)
2032 {
2033 struct protection_domain *domain = to_pdomain(dom);
2034 struct iommu_dev_data *dev_data;
2035 struct amd_iommu *iommu;
2036 int ret;
2037
2038 if (!check_device(dev))
2039 return -EINVAL;
2040
2041 dev_data = dev_iommu_priv_get(dev);
2042 dev_data->defer_attach = false;
2043
2044 iommu = amd_iommu_rlookup_table[dev_data->devid];
2045 if (!iommu)
2046 return -EINVAL;
2047
2048 if (dev_data->domain)
2049 detach_device(dev);
2050
2051 ret = attach_device(dev, domain);
2052
2053 #ifdef CONFIG_IRQ_REMAP
2054 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2055 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2056 dev_data->use_vapic = 1;
2057 else
2058 dev_data->use_vapic = 0;
2059 }
2060 #endif
2061
2062 iommu_completion_wait(iommu);
2063
2064 return ret;
2065 }
2066
amd_iommu_iotlb_sync_map(struct iommu_domain * dom,unsigned long iova,size_t size)2067 static void amd_iommu_iotlb_sync_map(struct iommu_domain *dom,
2068 unsigned long iova, size_t size)
2069 {
2070 struct protection_domain *domain = to_pdomain(dom);
2071 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2072
2073 if (ops->map)
2074 domain_flush_np_cache(domain, iova, size);
2075 }
2076
amd_iommu_map(struct iommu_domain * dom,unsigned long iova,phys_addr_t paddr,size_t page_size,int iommu_prot,gfp_t gfp)2077 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2078 phys_addr_t paddr, size_t page_size, int iommu_prot,
2079 gfp_t gfp)
2080 {
2081 struct protection_domain *domain = to_pdomain(dom);
2082 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2083 int prot = 0;
2084 int ret = -EINVAL;
2085
2086 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2087 (domain->iop.mode == PAGE_MODE_NONE))
2088 return -EINVAL;
2089
2090 if (iommu_prot & IOMMU_READ)
2091 prot |= IOMMU_PROT_IR;
2092 if (iommu_prot & IOMMU_WRITE)
2093 prot |= IOMMU_PROT_IW;
2094
2095 if (ops->map)
2096 ret = ops->map(ops, iova, paddr, page_size, prot, gfp);
2097
2098 return ret;
2099 }
2100
amd_iommu_iotlb_gather_add_page(struct iommu_domain * domain,struct iommu_iotlb_gather * gather,unsigned long iova,size_t size)2101 static void amd_iommu_iotlb_gather_add_page(struct iommu_domain *domain,
2102 struct iommu_iotlb_gather *gather,
2103 unsigned long iova, size_t size)
2104 {
2105 /*
2106 * AMD's IOMMU can flush as many pages as necessary in a single flush.
2107 * Unless we run in a virtual machine, which can be inferred according
2108 * to whether "non-present cache" is on, it is probably best to prefer
2109 * (potentially) too extensive TLB flushing (i.e., more misses) over
2110 * mutliple TLB flushes (i.e., more flushes). For virtual machines the
2111 * hypervisor needs to synchronize the host IOMMU PTEs with those of
2112 * the guest, and the trade-off is different: unnecessary TLB flushes
2113 * should be avoided.
2114 */
2115 if (amd_iommu_np_cache &&
2116 iommu_iotlb_gather_is_disjoint(gather, iova, size))
2117 iommu_iotlb_sync(domain, gather);
2118
2119 iommu_iotlb_gather_add_range(gather, iova, size);
2120 }
2121
amd_iommu_unmap(struct iommu_domain * dom,unsigned long iova,size_t page_size,struct iommu_iotlb_gather * gather)2122 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2123 size_t page_size,
2124 struct iommu_iotlb_gather *gather)
2125 {
2126 struct protection_domain *domain = to_pdomain(dom);
2127 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2128 size_t r;
2129
2130 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2131 (domain->iop.mode == PAGE_MODE_NONE))
2132 return 0;
2133
2134 r = (ops->unmap) ? ops->unmap(ops, iova, page_size, gather) : 0;
2135
2136 amd_iommu_iotlb_gather_add_page(dom, gather, iova, page_size);
2137
2138 return r;
2139 }
2140
amd_iommu_iova_to_phys(struct iommu_domain * dom,dma_addr_t iova)2141 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2142 dma_addr_t iova)
2143 {
2144 struct protection_domain *domain = to_pdomain(dom);
2145 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2146
2147 return ops->iova_to_phys(ops, iova);
2148 }
2149
amd_iommu_capable(enum iommu_cap cap)2150 static bool amd_iommu_capable(enum iommu_cap cap)
2151 {
2152 switch (cap) {
2153 case IOMMU_CAP_CACHE_COHERENCY:
2154 return true;
2155 case IOMMU_CAP_INTR_REMAP:
2156 return (irq_remapping_enabled == 1);
2157 case IOMMU_CAP_NOEXEC:
2158 return false;
2159 case IOMMU_CAP_PRE_BOOT_PROTECTION:
2160 return amdr_ivrs_remap_support;
2161 default:
2162 break;
2163 }
2164
2165 return false;
2166 }
2167
amd_iommu_get_resv_regions(struct device * dev,struct list_head * head)2168 static void amd_iommu_get_resv_regions(struct device *dev,
2169 struct list_head *head)
2170 {
2171 struct iommu_resv_region *region;
2172 struct unity_map_entry *entry;
2173 int devid;
2174
2175 devid = get_device_id(dev);
2176 if (devid < 0)
2177 return;
2178
2179 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2180 int type, prot = 0;
2181 size_t length;
2182
2183 if (devid < entry->devid_start || devid > entry->devid_end)
2184 continue;
2185
2186 type = IOMMU_RESV_DIRECT;
2187 length = entry->address_end - entry->address_start;
2188 if (entry->prot & IOMMU_PROT_IR)
2189 prot |= IOMMU_READ;
2190 if (entry->prot & IOMMU_PROT_IW)
2191 prot |= IOMMU_WRITE;
2192 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2193 /* Exclusion range */
2194 type = IOMMU_RESV_RESERVED;
2195
2196 region = iommu_alloc_resv_region(entry->address_start,
2197 length, prot, type);
2198 if (!region) {
2199 dev_err(dev, "Out of memory allocating dm-regions\n");
2200 return;
2201 }
2202 list_add_tail(®ion->list, head);
2203 }
2204
2205 region = iommu_alloc_resv_region(MSI_RANGE_START,
2206 MSI_RANGE_END - MSI_RANGE_START + 1,
2207 0, IOMMU_RESV_MSI);
2208 if (!region)
2209 return;
2210 list_add_tail(®ion->list, head);
2211
2212 region = iommu_alloc_resv_region(HT_RANGE_START,
2213 HT_RANGE_END - HT_RANGE_START + 1,
2214 0, IOMMU_RESV_RESERVED);
2215 if (!region)
2216 return;
2217 list_add_tail(®ion->list, head);
2218 }
2219
amd_iommu_is_attach_deferred(struct device * dev)2220 bool amd_iommu_is_attach_deferred(struct device *dev)
2221 {
2222 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2223
2224 return dev_data->defer_attach;
2225 }
2226 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2227
amd_iommu_flush_iotlb_all(struct iommu_domain * domain)2228 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2229 {
2230 struct protection_domain *dom = to_pdomain(domain);
2231 unsigned long flags;
2232
2233 spin_lock_irqsave(&dom->lock, flags);
2234 amd_iommu_domain_flush_tlb_pde(dom);
2235 amd_iommu_domain_flush_complete(dom);
2236 spin_unlock_irqrestore(&dom->lock, flags);
2237 }
2238
amd_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)2239 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2240 struct iommu_iotlb_gather *gather)
2241 {
2242 struct protection_domain *dom = to_pdomain(domain);
2243 unsigned long flags;
2244
2245 spin_lock_irqsave(&dom->lock, flags);
2246 domain_flush_pages(dom, gather->start, gather->end - gather->start, 1);
2247 amd_iommu_domain_flush_complete(dom);
2248 spin_unlock_irqrestore(&dom->lock, flags);
2249 }
2250
amd_iommu_def_domain_type(struct device * dev)2251 static int amd_iommu_def_domain_type(struct device *dev)
2252 {
2253 struct iommu_dev_data *dev_data;
2254
2255 dev_data = dev_iommu_priv_get(dev);
2256 if (!dev_data)
2257 return 0;
2258
2259 /*
2260 * Do not identity map IOMMUv2 capable devices when memory encryption is
2261 * active, because some of those devices (AMD GPUs) don't have the
2262 * encryption bit in their DMA-mask and require remapping.
2263 */
2264 if (!cc_platform_has(CC_ATTR_MEM_ENCRYPT) && dev_data->iommu_v2)
2265 return IOMMU_DOMAIN_IDENTITY;
2266
2267 return 0;
2268 }
2269
amd_iommu_enforce_cache_coherency(struct iommu_domain * domain)2270 static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain)
2271 {
2272 /* IOMMU_PTE_FC is always set */
2273 return true;
2274 }
2275
2276 const struct iommu_ops amd_iommu_ops = {
2277 .capable = amd_iommu_capable,
2278 .domain_alloc = amd_iommu_domain_alloc,
2279 .probe_device = amd_iommu_probe_device,
2280 .release_device = amd_iommu_release_device,
2281 .probe_finalize = amd_iommu_probe_finalize,
2282 .device_group = amd_iommu_device_group,
2283 .get_resv_regions = amd_iommu_get_resv_regions,
2284 .put_resv_regions = generic_iommu_put_resv_regions,
2285 .is_attach_deferred = amd_iommu_is_attach_deferred,
2286 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2287 .def_domain_type = amd_iommu_def_domain_type,
2288 .default_domain_ops = &(const struct iommu_domain_ops) {
2289 .attach_dev = amd_iommu_attach_device,
2290 .detach_dev = amd_iommu_detach_device,
2291 .map = amd_iommu_map,
2292 .unmap = amd_iommu_unmap,
2293 .iotlb_sync_map = amd_iommu_iotlb_sync_map,
2294 .iova_to_phys = amd_iommu_iova_to_phys,
2295 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2296 .iotlb_sync = amd_iommu_iotlb_sync,
2297 .free = amd_iommu_domain_free,
2298 .enforce_cache_coherency = amd_iommu_enforce_cache_coherency,
2299 }
2300 };
2301
2302 /*****************************************************************************
2303 *
2304 * The next functions do a basic initialization of IOMMU for pass through
2305 * mode
2306 *
2307 * In passthrough mode the IOMMU is initialized and enabled but not used for
2308 * DMA-API translation.
2309 *
2310 *****************************************************************************/
2311
2312 /* IOMMUv2 specific functions */
amd_iommu_register_ppr_notifier(struct notifier_block * nb)2313 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2314 {
2315 return atomic_notifier_chain_register(&ppr_notifier, nb);
2316 }
2317 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2318
amd_iommu_unregister_ppr_notifier(struct notifier_block * nb)2319 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2320 {
2321 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2322 }
2323 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2324
amd_iommu_domain_direct_map(struct iommu_domain * dom)2325 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2326 {
2327 struct protection_domain *domain = to_pdomain(dom);
2328 unsigned long flags;
2329
2330 spin_lock_irqsave(&domain->lock, flags);
2331
2332 if (domain->iop.pgtbl_cfg.tlb)
2333 free_io_pgtable_ops(&domain->iop.iop.ops);
2334
2335 spin_unlock_irqrestore(&domain->lock, flags);
2336 }
2337 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2338
amd_iommu_domain_enable_v2(struct iommu_domain * dom,int pasids)2339 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2340 {
2341 struct protection_domain *domain = to_pdomain(dom);
2342 unsigned long flags;
2343 int levels, ret;
2344
2345 /* Number of GCR3 table levels required */
2346 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2347 levels += 1;
2348
2349 if (levels > amd_iommu_max_glx_val)
2350 return -EINVAL;
2351
2352 spin_lock_irqsave(&domain->lock, flags);
2353
2354 /*
2355 * Save us all sanity checks whether devices already in the
2356 * domain support IOMMUv2. Just force that the domain has no
2357 * devices attached when it is switched into IOMMUv2 mode.
2358 */
2359 ret = -EBUSY;
2360 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2361 goto out;
2362
2363 ret = -ENOMEM;
2364 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2365 if (domain->gcr3_tbl == NULL)
2366 goto out;
2367
2368 domain->glx = levels;
2369 domain->flags |= PD_IOMMUV2_MASK;
2370
2371 amd_iommu_domain_update(domain);
2372
2373 ret = 0;
2374
2375 out:
2376 spin_unlock_irqrestore(&domain->lock, flags);
2377
2378 return ret;
2379 }
2380 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2381
__flush_pasid(struct protection_domain * domain,u32 pasid,u64 address,bool size)2382 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2383 u64 address, bool size)
2384 {
2385 struct iommu_dev_data *dev_data;
2386 struct iommu_cmd cmd;
2387 int i, ret;
2388
2389 if (!(domain->flags & PD_IOMMUV2_MASK))
2390 return -EINVAL;
2391
2392 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2393
2394 /*
2395 * IOMMU TLB needs to be flushed before Device TLB to
2396 * prevent device TLB refill from IOMMU TLB
2397 */
2398 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2399 if (domain->dev_iommu[i] == 0)
2400 continue;
2401
2402 ret = iommu_queue_command(amd_iommus[i], &cmd);
2403 if (ret != 0)
2404 goto out;
2405 }
2406
2407 /* Wait until IOMMU TLB flushes are complete */
2408 amd_iommu_domain_flush_complete(domain);
2409
2410 /* Now flush device TLBs */
2411 list_for_each_entry(dev_data, &domain->dev_list, list) {
2412 struct amd_iommu *iommu;
2413 int qdep;
2414
2415 /*
2416 There might be non-IOMMUv2 capable devices in an IOMMUv2
2417 * domain.
2418 */
2419 if (!dev_data->ats.enabled)
2420 continue;
2421
2422 qdep = dev_data->ats.qdep;
2423 iommu = amd_iommu_rlookup_table[dev_data->devid];
2424
2425 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2426 qdep, address, size);
2427
2428 ret = iommu_queue_command(iommu, &cmd);
2429 if (ret != 0)
2430 goto out;
2431 }
2432
2433 /* Wait until all device TLBs are flushed */
2434 amd_iommu_domain_flush_complete(domain);
2435
2436 ret = 0;
2437
2438 out:
2439
2440 return ret;
2441 }
2442
__amd_iommu_flush_page(struct protection_domain * domain,u32 pasid,u64 address)2443 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2444 u64 address)
2445 {
2446 return __flush_pasid(domain, pasid, address, false);
2447 }
2448
amd_iommu_flush_page(struct iommu_domain * dom,u32 pasid,u64 address)2449 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2450 u64 address)
2451 {
2452 struct protection_domain *domain = to_pdomain(dom);
2453 unsigned long flags;
2454 int ret;
2455
2456 spin_lock_irqsave(&domain->lock, flags);
2457 ret = __amd_iommu_flush_page(domain, pasid, address);
2458 spin_unlock_irqrestore(&domain->lock, flags);
2459
2460 return ret;
2461 }
2462 EXPORT_SYMBOL(amd_iommu_flush_page);
2463
__amd_iommu_flush_tlb(struct protection_domain * domain,u32 pasid)2464 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2465 {
2466 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2467 true);
2468 }
2469
amd_iommu_flush_tlb(struct iommu_domain * dom,u32 pasid)2470 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2471 {
2472 struct protection_domain *domain = to_pdomain(dom);
2473 unsigned long flags;
2474 int ret;
2475
2476 spin_lock_irqsave(&domain->lock, flags);
2477 ret = __amd_iommu_flush_tlb(domain, pasid);
2478 spin_unlock_irqrestore(&domain->lock, flags);
2479
2480 return ret;
2481 }
2482 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2483
__get_gcr3_pte(u64 * root,int level,u32 pasid,bool alloc)2484 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2485 {
2486 int index;
2487 u64 *pte;
2488
2489 while (true) {
2490
2491 index = (pasid >> (9 * level)) & 0x1ff;
2492 pte = &root[index];
2493
2494 if (level == 0)
2495 break;
2496
2497 if (!(*pte & GCR3_VALID)) {
2498 if (!alloc)
2499 return NULL;
2500
2501 root = (void *)get_zeroed_page(GFP_ATOMIC);
2502 if (root == NULL)
2503 return NULL;
2504
2505 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
2506 }
2507
2508 root = iommu_phys_to_virt(*pte & PAGE_MASK);
2509
2510 level -= 1;
2511 }
2512
2513 return pte;
2514 }
2515
__set_gcr3(struct protection_domain * domain,u32 pasid,unsigned long cr3)2516 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
2517 unsigned long cr3)
2518 {
2519 u64 *pte;
2520
2521 if (domain->iop.mode != PAGE_MODE_NONE)
2522 return -EINVAL;
2523
2524 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2525 if (pte == NULL)
2526 return -ENOMEM;
2527
2528 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2529
2530 return __amd_iommu_flush_tlb(domain, pasid);
2531 }
2532
__clear_gcr3(struct protection_domain * domain,u32 pasid)2533 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
2534 {
2535 u64 *pte;
2536
2537 if (domain->iop.mode != PAGE_MODE_NONE)
2538 return -EINVAL;
2539
2540 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2541 if (pte == NULL)
2542 return 0;
2543
2544 *pte = 0;
2545
2546 return __amd_iommu_flush_tlb(domain, pasid);
2547 }
2548
amd_iommu_domain_set_gcr3(struct iommu_domain * dom,u32 pasid,unsigned long cr3)2549 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
2550 unsigned long cr3)
2551 {
2552 struct protection_domain *domain = to_pdomain(dom);
2553 unsigned long flags;
2554 int ret;
2555
2556 spin_lock_irqsave(&domain->lock, flags);
2557 ret = __set_gcr3(domain, pasid, cr3);
2558 spin_unlock_irqrestore(&domain->lock, flags);
2559
2560 return ret;
2561 }
2562 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2563
amd_iommu_domain_clear_gcr3(struct iommu_domain * dom,u32 pasid)2564 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
2565 {
2566 struct protection_domain *domain = to_pdomain(dom);
2567 unsigned long flags;
2568 int ret;
2569
2570 spin_lock_irqsave(&domain->lock, flags);
2571 ret = __clear_gcr3(domain, pasid);
2572 spin_unlock_irqrestore(&domain->lock, flags);
2573
2574 return ret;
2575 }
2576 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2577
amd_iommu_complete_ppr(struct pci_dev * pdev,u32 pasid,int status,int tag)2578 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
2579 int status, int tag)
2580 {
2581 struct iommu_dev_data *dev_data;
2582 struct amd_iommu *iommu;
2583 struct iommu_cmd cmd;
2584
2585 dev_data = dev_iommu_priv_get(&pdev->dev);
2586 iommu = amd_iommu_rlookup_table[dev_data->devid];
2587
2588 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2589 tag, dev_data->pri_tlp);
2590
2591 return iommu_queue_command(iommu, &cmd);
2592 }
2593 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2594
amd_iommu_device_info(struct pci_dev * pdev,struct amd_iommu_device_info * info)2595 int amd_iommu_device_info(struct pci_dev *pdev,
2596 struct amd_iommu_device_info *info)
2597 {
2598 int max_pasids;
2599 int pos;
2600
2601 if (pdev == NULL || info == NULL)
2602 return -EINVAL;
2603
2604 if (!amd_iommu_v2_supported())
2605 return -EINVAL;
2606
2607 memset(info, 0, sizeof(*info));
2608
2609 if (pci_ats_supported(pdev))
2610 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
2611
2612 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2613 if (pos)
2614 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
2615
2616 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
2617 if (pos) {
2618 int features;
2619
2620 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
2621 max_pasids = min(max_pasids, (1 << 20));
2622
2623 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
2624 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
2625
2626 features = pci_pasid_features(pdev);
2627 if (features & PCI_PASID_CAP_EXEC)
2628 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
2629 if (features & PCI_PASID_CAP_PRIV)
2630 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
2631 }
2632
2633 return 0;
2634 }
2635 EXPORT_SYMBOL(amd_iommu_device_info);
2636
2637 #ifdef CONFIG_IRQ_REMAP
2638
2639 /*****************************************************************************
2640 *
2641 * Interrupt Remapping Implementation
2642 *
2643 *****************************************************************************/
2644
2645 static struct irq_chip amd_ir_chip;
2646 static DEFINE_SPINLOCK(iommu_table_lock);
2647
set_dte_irq_entry(u16 devid,struct irq_remap_table * table)2648 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
2649 {
2650 u64 dte;
2651
2652 dte = amd_iommu_dev_table[devid].data[2];
2653 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
2654 dte |= iommu_virt_to_phys(table->table);
2655 dte |= DTE_IRQ_REMAP_INTCTL;
2656 dte |= DTE_INTTABLEN;
2657 dte |= DTE_IRQ_REMAP_ENABLE;
2658
2659 amd_iommu_dev_table[devid].data[2] = dte;
2660 }
2661
get_irq_table(u16 devid)2662 static struct irq_remap_table *get_irq_table(u16 devid)
2663 {
2664 struct irq_remap_table *table;
2665
2666 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
2667 "%s: no iommu for devid %x\n", __func__, devid))
2668 return NULL;
2669
2670 table = irq_lookup_table[devid];
2671 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
2672 return NULL;
2673
2674 return table;
2675 }
2676
__alloc_irq_table(void)2677 static struct irq_remap_table *__alloc_irq_table(void)
2678 {
2679 struct irq_remap_table *table;
2680
2681 table = kzalloc(sizeof(*table), GFP_KERNEL);
2682 if (!table)
2683 return NULL;
2684
2685 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
2686 if (!table->table) {
2687 kfree(table);
2688 return NULL;
2689 }
2690 raw_spin_lock_init(&table->lock);
2691
2692 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2693 memset(table->table, 0,
2694 MAX_IRQS_PER_TABLE * sizeof(u32));
2695 else
2696 memset(table->table, 0,
2697 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
2698 return table;
2699 }
2700
set_remap_table_entry(struct amd_iommu * iommu,u16 devid,struct irq_remap_table * table)2701 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
2702 struct irq_remap_table *table)
2703 {
2704 irq_lookup_table[devid] = table;
2705 set_dte_irq_entry(devid, table);
2706 iommu_flush_dte(iommu, devid);
2707 }
2708
set_remap_table_entry_alias(struct pci_dev * pdev,u16 alias,void * data)2709 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
2710 void *data)
2711 {
2712 struct irq_remap_table *table = data;
2713
2714 irq_lookup_table[alias] = table;
2715 set_dte_irq_entry(alias, table);
2716
2717 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
2718
2719 return 0;
2720 }
2721
alloc_irq_table(u16 devid,struct pci_dev * pdev)2722 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
2723 {
2724 struct irq_remap_table *table = NULL;
2725 struct irq_remap_table *new_table = NULL;
2726 struct amd_iommu *iommu;
2727 unsigned long flags;
2728 u16 alias;
2729
2730 spin_lock_irqsave(&iommu_table_lock, flags);
2731
2732 iommu = amd_iommu_rlookup_table[devid];
2733 if (!iommu)
2734 goto out_unlock;
2735
2736 table = irq_lookup_table[devid];
2737 if (table)
2738 goto out_unlock;
2739
2740 alias = amd_iommu_alias_table[devid];
2741 table = irq_lookup_table[alias];
2742 if (table) {
2743 set_remap_table_entry(iommu, devid, table);
2744 goto out_wait;
2745 }
2746 spin_unlock_irqrestore(&iommu_table_lock, flags);
2747
2748 /* Nothing there yet, allocate new irq remapping table */
2749 new_table = __alloc_irq_table();
2750 if (!new_table)
2751 return NULL;
2752
2753 spin_lock_irqsave(&iommu_table_lock, flags);
2754
2755 table = irq_lookup_table[devid];
2756 if (table)
2757 goto out_unlock;
2758
2759 table = irq_lookup_table[alias];
2760 if (table) {
2761 set_remap_table_entry(iommu, devid, table);
2762 goto out_wait;
2763 }
2764
2765 table = new_table;
2766 new_table = NULL;
2767
2768 if (pdev)
2769 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
2770 table);
2771 else
2772 set_remap_table_entry(iommu, devid, table);
2773
2774 if (devid != alias)
2775 set_remap_table_entry(iommu, alias, table);
2776
2777 out_wait:
2778 iommu_completion_wait(iommu);
2779
2780 out_unlock:
2781 spin_unlock_irqrestore(&iommu_table_lock, flags);
2782
2783 if (new_table) {
2784 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
2785 kfree(new_table);
2786 }
2787 return table;
2788 }
2789
alloc_irq_index(u16 devid,int count,bool align,struct pci_dev * pdev)2790 static int alloc_irq_index(u16 devid, int count, bool align,
2791 struct pci_dev *pdev)
2792 {
2793 struct irq_remap_table *table;
2794 int index, c, alignment = 1;
2795 unsigned long flags;
2796 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2797
2798 if (!iommu)
2799 return -ENODEV;
2800
2801 table = alloc_irq_table(devid, pdev);
2802 if (!table)
2803 return -ENODEV;
2804
2805 if (align)
2806 alignment = roundup_pow_of_two(count);
2807
2808 raw_spin_lock_irqsave(&table->lock, flags);
2809
2810 /* Scan table for free entries */
2811 for (index = ALIGN(table->min_index, alignment), c = 0;
2812 index < MAX_IRQS_PER_TABLE;) {
2813 if (!iommu->irte_ops->is_allocated(table, index)) {
2814 c += 1;
2815 } else {
2816 c = 0;
2817 index = ALIGN(index + 1, alignment);
2818 continue;
2819 }
2820
2821 if (c == count) {
2822 for (; c != 0; --c)
2823 iommu->irte_ops->set_allocated(table, index - c + 1);
2824
2825 index -= count - 1;
2826 goto out;
2827 }
2828
2829 index++;
2830 }
2831
2832 index = -ENOSPC;
2833
2834 out:
2835 raw_spin_unlock_irqrestore(&table->lock, flags);
2836
2837 return index;
2838 }
2839
modify_irte_ga(u16 devid,int index,struct irte_ga * irte,struct amd_ir_data * data)2840 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
2841 struct amd_ir_data *data)
2842 {
2843 bool ret;
2844 struct irq_remap_table *table;
2845 struct amd_iommu *iommu;
2846 unsigned long flags;
2847 struct irte_ga *entry;
2848
2849 iommu = amd_iommu_rlookup_table[devid];
2850 if (iommu == NULL)
2851 return -EINVAL;
2852
2853 table = get_irq_table(devid);
2854 if (!table)
2855 return -ENOMEM;
2856
2857 raw_spin_lock_irqsave(&table->lock, flags);
2858
2859 entry = (struct irte_ga *)table->table;
2860 entry = &entry[index];
2861
2862 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
2863 entry->lo.val, entry->hi.val,
2864 irte->lo.val, irte->hi.val);
2865 /*
2866 * We use cmpxchg16 to atomically update the 128-bit IRTE,
2867 * and it cannot be updated by the hardware or other processors
2868 * behind us, so the return value of cmpxchg16 should be the
2869 * same as the old value.
2870 */
2871 WARN_ON(!ret);
2872
2873 if (data)
2874 data->ref = entry;
2875
2876 raw_spin_unlock_irqrestore(&table->lock, flags);
2877
2878 iommu_flush_irt(iommu, devid);
2879 iommu_completion_wait(iommu);
2880
2881 return 0;
2882 }
2883
modify_irte(u16 devid,int index,union irte * irte)2884 static int modify_irte(u16 devid, int index, union irte *irte)
2885 {
2886 struct irq_remap_table *table;
2887 struct amd_iommu *iommu;
2888 unsigned long flags;
2889
2890 iommu = amd_iommu_rlookup_table[devid];
2891 if (iommu == NULL)
2892 return -EINVAL;
2893
2894 table = get_irq_table(devid);
2895 if (!table)
2896 return -ENOMEM;
2897
2898 raw_spin_lock_irqsave(&table->lock, flags);
2899 table->table[index] = irte->val;
2900 raw_spin_unlock_irqrestore(&table->lock, flags);
2901
2902 iommu_flush_irt(iommu, devid);
2903 iommu_completion_wait(iommu);
2904
2905 return 0;
2906 }
2907
free_irte(u16 devid,int index)2908 static void free_irte(u16 devid, int index)
2909 {
2910 struct irq_remap_table *table;
2911 struct amd_iommu *iommu;
2912 unsigned long flags;
2913
2914 iommu = amd_iommu_rlookup_table[devid];
2915 if (iommu == NULL)
2916 return;
2917
2918 table = get_irq_table(devid);
2919 if (!table)
2920 return;
2921
2922 raw_spin_lock_irqsave(&table->lock, flags);
2923 iommu->irte_ops->clear_allocated(table, index);
2924 raw_spin_unlock_irqrestore(&table->lock, flags);
2925
2926 iommu_flush_irt(iommu, devid);
2927 iommu_completion_wait(iommu);
2928 }
2929
irte_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)2930 static void irte_prepare(void *entry,
2931 u32 delivery_mode, bool dest_mode,
2932 u8 vector, u32 dest_apicid, int devid)
2933 {
2934 union irte *irte = (union irte *) entry;
2935
2936 irte->val = 0;
2937 irte->fields.vector = vector;
2938 irte->fields.int_type = delivery_mode;
2939 irte->fields.destination = dest_apicid;
2940 irte->fields.dm = dest_mode;
2941 irte->fields.valid = 1;
2942 }
2943
irte_ga_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)2944 static void irte_ga_prepare(void *entry,
2945 u32 delivery_mode, bool dest_mode,
2946 u8 vector, u32 dest_apicid, int devid)
2947 {
2948 struct irte_ga *irte = (struct irte_ga *) entry;
2949
2950 irte->lo.val = 0;
2951 irte->hi.val = 0;
2952 irte->lo.fields_remap.int_type = delivery_mode;
2953 irte->lo.fields_remap.dm = dest_mode;
2954 irte->hi.fields.vector = vector;
2955 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
2956 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
2957 irte->lo.fields_remap.valid = 1;
2958 }
2959
irte_activate(void * entry,u16 devid,u16 index)2960 static void irte_activate(void *entry, u16 devid, u16 index)
2961 {
2962 union irte *irte = (union irte *) entry;
2963
2964 irte->fields.valid = 1;
2965 modify_irte(devid, index, irte);
2966 }
2967
irte_ga_activate(void * entry,u16 devid,u16 index)2968 static void irte_ga_activate(void *entry, u16 devid, u16 index)
2969 {
2970 struct irte_ga *irte = (struct irte_ga *) entry;
2971
2972 irte->lo.fields_remap.valid = 1;
2973 modify_irte_ga(devid, index, irte, NULL);
2974 }
2975
irte_deactivate(void * entry,u16 devid,u16 index)2976 static void irte_deactivate(void *entry, u16 devid, u16 index)
2977 {
2978 union irte *irte = (union irte *) entry;
2979
2980 irte->fields.valid = 0;
2981 modify_irte(devid, index, irte);
2982 }
2983
irte_ga_deactivate(void * entry,u16 devid,u16 index)2984 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
2985 {
2986 struct irte_ga *irte = (struct irte_ga *) entry;
2987
2988 irte->lo.fields_remap.valid = 0;
2989 modify_irte_ga(devid, index, irte, NULL);
2990 }
2991
irte_set_affinity(void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)2992 static void irte_set_affinity(void *entry, u16 devid, u16 index,
2993 u8 vector, u32 dest_apicid)
2994 {
2995 union irte *irte = (union irte *) entry;
2996
2997 irte->fields.vector = vector;
2998 irte->fields.destination = dest_apicid;
2999 modify_irte(devid, index, irte);
3000 }
3001
irte_ga_set_affinity(void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)3002 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3003 u8 vector, u32 dest_apicid)
3004 {
3005 struct irte_ga *irte = (struct irte_ga *) entry;
3006
3007 if (!irte->lo.fields_remap.guest_mode) {
3008 irte->hi.fields.vector = vector;
3009 irte->lo.fields_remap.destination =
3010 APICID_TO_IRTE_DEST_LO(dest_apicid);
3011 irte->hi.fields.destination =
3012 APICID_TO_IRTE_DEST_HI(dest_apicid);
3013 modify_irte_ga(devid, index, irte, NULL);
3014 }
3015 }
3016
3017 #define IRTE_ALLOCATED (~1U)
irte_set_allocated(struct irq_remap_table * table,int index)3018 static void irte_set_allocated(struct irq_remap_table *table, int index)
3019 {
3020 table->table[index] = IRTE_ALLOCATED;
3021 }
3022
irte_ga_set_allocated(struct irq_remap_table * table,int index)3023 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3024 {
3025 struct irte_ga *ptr = (struct irte_ga *)table->table;
3026 struct irte_ga *irte = &ptr[index];
3027
3028 memset(&irte->lo.val, 0, sizeof(u64));
3029 memset(&irte->hi.val, 0, sizeof(u64));
3030 irte->hi.fields.vector = 0xff;
3031 }
3032
irte_is_allocated(struct irq_remap_table * table,int index)3033 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3034 {
3035 union irte *ptr = (union irte *)table->table;
3036 union irte *irte = &ptr[index];
3037
3038 return irte->val != 0;
3039 }
3040
irte_ga_is_allocated(struct irq_remap_table * table,int index)3041 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3042 {
3043 struct irte_ga *ptr = (struct irte_ga *)table->table;
3044 struct irte_ga *irte = &ptr[index];
3045
3046 return irte->hi.fields.vector != 0;
3047 }
3048
irte_clear_allocated(struct irq_remap_table * table,int index)3049 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3050 {
3051 table->table[index] = 0;
3052 }
3053
irte_ga_clear_allocated(struct irq_remap_table * table,int index)3054 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3055 {
3056 struct irte_ga *ptr = (struct irte_ga *)table->table;
3057 struct irte_ga *irte = &ptr[index];
3058
3059 memset(&irte->lo.val, 0, sizeof(u64));
3060 memset(&irte->hi.val, 0, sizeof(u64));
3061 }
3062
get_devid(struct irq_alloc_info * info)3063 static int get_devid(struct irq_alloc_info *info)
3064 {
3065 switch (info->type) {
3066 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3067 return get_ioapic_devid(info->devid);
3068 case X86_IRQ_ALLOC_TYPE_HPET:
3069 return get_hpet_devid(info->devid);
3070 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3071 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3072 return get_device_id(msi_desc_to_dev(info->desc));
3073 default:
3074 WARN_ON_ONCE(1);
3075 return -1;
3076 }
3077 }
3078
3079 struct irq_remap_ops amd_iommu_irq_ops = {
3080 .prepare = amd_iommu_prepare,
3081 .enable = amd_iommu_enable,
3082 .disable = amd_iommu_disable,
3083 .reenable = amd_iommu_reenable,
3084 .enable_faulting = amd_iommu_enable_faulting,
3085 };
3086
fill_msi_msg(struct msi_msg * msg,u32 index)3087 static void fill_msi_msg(struct msi_msg *msg, u32 index)
3088 {
3089 msg->data = index;
3090 msg->address_lo = 0;
3091 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
3092 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
3093 }
3094
irq_remapping_prepare_irte(struct amd_ir_data * data,struct irq_cfg * irq_cfg,struct irq_alloc_info * info,int devid,int index,int sub_handle)3095 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3096 struct irq_cfg *irq_cfg,
3097 struct irq_alloc_info *info,
3098 int devid, int index, int sub_handle)
3099 {
3100 struct irq_2_irte *irte_info = &data->irq_2_irte;
3101 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3102
3103 if (!iommu)
3104 return;
3105
3106 data->irq_2_irte.devid = devid;
3107 data->irq_2_irte.index = index + sub_handle;
3108 iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
3109 apic->dest_mode_logical, irq_cfg->vector,
3110 irq_cfg->dest_apicid, devid);
3111
3112 switch (info->type) {
3113 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3114 case X86_IRQ_ALLOC_TYPE_HPET:
3115 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3116 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3117 fill_msi_msg(&data->msi_entry, irte_info->index);
3118 break;
3119
3120 default:
3121 BUG_ON(1);
3122 break;
3123 }
3124 }
3125
3126 struct amd_irte_ops irte_32_ops = {
3127 .prepare = irte_prepare,
3128 .activate = irte_activate,
3129 .deactivate = irte_deactivate,
3130 .set_affinity = irte_set_affinity,
3131 .set_allocated = irte_set_allocated,
3132 .is_allocated = irte_is_allocated,
3133 .clear_allocated = irte_clear_allocated,
3134 };
3135
3136 struct amd_irte_ops irte_128_ops = {
3137 .prepare = irte_ga_prepare,
3138 .activate = irte_ga_activate,
3139 .deactivate = irte_ga_deactivate,
3140 .set_affinity = irte_ga_set_affinity,
3141 .set_allocated = irte_ga_set_allocated,
3142 .is_allocated = irte_ga_is_allocated,
3143 .clear_allocated = irte_ga_clear_allocated,
3144 };
3145
irq_remapping_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)3146 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3147 unsigned int nr_irqs, void *arg)
3148 {
3149 struct irq_alloc_info *info = arg;
3150 struct irq_data *irq_data;
3151 struct amd_ir_data *data = NULL;
3152 struct irq_cfg *cfg;
3153 int i, ret, devid;
3154 int index;
3155
3156 if (!info)
3157 return -EINVAL;
3158 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
3159 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
3160 return -EINVAL;
3161
3162 /*
3163 * With IRQ remapping enabled, don't need contiguous CPU vectors
3164 * to support multiple MSI interrupts.
3165 */
3166 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
3167 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3168
3169 devid = get_devid(info);
3170 if (devid < 0)
3171 return -EINVAL;
3172
3173 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3174 if (ret < 0)
3175 return ret;
3176
3177 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3178 struct irq_remap_table *table;
3179 struct amd_iommu *iommu;
3180
3181 table = alloc_irq_table(devid, NULL);
3182 if (table) {
3183 if (!table->min_index) {
3184 /*
3185 * Keep the first 32 indexes free for IOAPIC
3186 * interrupts.
3187 */
3188 table->min_index = 32;
3189 iommu = amd_iommu_rlookup_table[devid];
3190 for (i = 0; i < 32; ++i)
3191 iommu->irte_ops->set_allocated(table, i);
3192 }
3193 WARN_ON(table->min_index != 32);
3194 index = info->ioapic.pin;
3195 } else {
3196 index = -ENOMEM;
3197 }
3198 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3199 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3200 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3201
3202 index = alloc_irq_index(devid, nr_irqs, align,
3203 msi_desc_to_pci_dev(info->desc));
3204 } else {
3205 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3206 }
3207
3208 if (index < 0) {
3209 pr_warn("Failed to allocate IRTE\n");
3210 ret = index;
3211 goto out_free_parent;
3212 }
3213
3214 for (i = 0; i < nr_irqs; i++) {
3215 irq_data = irq_domain_get_irq_data(domain, virq + i);
3216 cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3217 if (!cfg) {
3218 ret = -EINVAL;
3219 goto out_free_data;
3220 }
3221
3222 ret = -ENOMEM;
3223 data = kzalloc(sizeof(*data), GFP_KERNEL);
3224 if (!data)
3225 goto out_free_data;
3226
3227 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3228 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3229 else
3230 data->entry = kzalloc(sizeof(struct irte_ga),
3231 GFP_KERNEL);
3232 if (!data->entry) {
3233 kfree(data);
3234 goto out_free_data;
3235 }
3236
3237 irq_data->hwirq = (devid << 16) + i;
3238 irq_data->chip_data = data;
3239 irq_data->chip = &amd_ir_chip;
3240 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3241 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3242 }
3243
3244 return 0;
3245
3246 out_free_data:
3247 for (i--; i >= 0; i--) {
3248 irq_data = irq_domain_get_irq_data(domain, virq + i);
3249 if (irq_data)
3250 kfree(irq_data->chip_data);
3251 }
3252 for (i = 0; i < nr_irqs; i++)
3253 free_irte(devid, index + i);
3254 out_free_parent:
3255 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3256 return ret;
3257 }
3258
irq_remapping_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3259 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3260 unsigned int nr_irqs)
3261 {
3262 struct irq_2_irte *irte_info;
3263 struct irq_data *irq_data;
3264 struct amd_ir_data *data;
3265 int i;
3266
3267 for (i = 0; i < nr_irqs; i++) {
3268 irq_data = irq_domain_get_irq_data(domain, virq + i);
3269 if (irq_data && irq_data->chip_data) {
3270 data = irq_data->chip_data;
3271 irte_info = &data->irq_2_irte;
3272 free_irte(irte_info->devid, irte_info->index);
3273 kfree(data->entry);
3274 kfree(data);
3275 }
3276 }
3277 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3278 }
3279
3280 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3281 struct amd_ir_data *ir_data,
3282 struct irq_2_irte *irte_info,
3283 struct irq_cfg *cfg);
3284
irq_remapping_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)3285 static int irq_remapping_activate(struct irq_domain *domain,
3286 struct irq_data *irq_data, bool reserve)
3287 {
3288 struct amd_ir_data *data = irq_data->chip_data;
3289 struct irq_2_irte *irte_info = &data->irq_2_irte;
3290 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3291 struct irq_cfg *cfg = irqd_cfg(irq_data);
3292
3293 if (!iommu)
3294 return 0;
3295
3296 iommu->irte_ops->activate(data->entry, irte_info->devid,
3297 irte_info->index);
3298 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3299 return 0;
3300 }
3301
irq_remapping_deactivate(struct irq_domain * domain,struct irq_data * irq_data)3302 static void irq_remapping_deactivate(struct irq_domain *domain,
3303 struct irq_data *irq_data)
3304 {
3305 struct amd_ir_data *data = irq_data->chip_data;
3306 struct irq_2_irte *irte_info = &data->irq_2_irte;
3307 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3308
3309 if (iommu)
3310 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3311 irte_info->index);
3312 }
3313
irq_remapping_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)3314 static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
3315 enum irq_domain_bus_token bus_token)
3316 {
3317 struct amd_iommu *iommu;
3318 int devid = -1;
3319
3320 if (!amd_iommu_irq_remap)
3321 return 0;
3322
3323 if (x86_fwspec_is_ioapic(fwspec))
3324 devid = get_ioapic_devid(fwspec->param[0]);
3325 else if (x86_fwspec_is_hpet(fwspec))
3326 devid = get_hpet_devid(fwspec->param[0]);
3327
3328 if (devid < 0)
3329 return 0;
3330
3331 iommu = amd_iommu_rlookup_table[devid];
3332 return iommu && iommu->ir_domain == d;
3333 }
3334
3335 static const struct irq_domain_ops amd_ir_domain_ops = {
3336 .select = irq_remapping_select,
3337 .alloc = irq_remapping_alloc,
3338 .free = irq_remapping_free,
3339 .activate = irq_remapping_activate,
3340 .deactivate = irq_remapping_deactivate,
3341 };
3342
amd_iommu_activate_guest_mode(void * data)3343 int amd_iommu_activate_guest_mode(void *data)
3344 {
3345 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3346 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3347 u64 valid;
3348
3349 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3350 !entry || entry->lo.fields_vapic.guest_mode)
3351 return 0;
3352
3353 valid = entry->lo.fields_vapic.valid;
3354
3355 entry->lo.val = 0;
3356 entry->hi.val = 0;
3357
3358 entry->lo.fields_vapic.valid = valid;
3359 entry->lo.fields_vapic.guest_mode = 1;
3360 entry->lo.fields_vapic.ga_log_intr = 1;
3361 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3362 entry->hi.fields.vector = ir_data->ga_vector;
3363 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3364
3365 return modify_irte_ga(ir_data->irq_2_irte.devid,
3366 ir_data->irq_2_irte.index, entry, ir_data);
3367 }
3368 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3369
amd_iommu_deactivate_guest_mode(void * data)3370 int amd_iommu_deactivate_guest_mode(void *data)
3371 {
3372 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3373 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3374 struct irq_cfg *cfg = ir_data->cfg;
3375 u64 valid;
3376
3377 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3378 !entry || !entry->lo.fields_vapic.guest_mode)
3379 return 0;
3380
3381 valid = entry->lo.fields_remap.valid;
3382
3383 entry->lo.val = 0;
3384 entry->hi.val = 0;
3385
3386 entry->lo.fields_remap.valid = valid;
3387 entry->lo.fields_remap.dm = apic->dest_mode_logical;
3388 entry->lo.fields_remap.int_type = apic->delivery_mode;
3389 entry->hi.fields.vector = cfg->vector;
3390 entry->lo.fields_remap.destination =
3391 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3392 entry->hi.fields.destination =
3393 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3394
3395 return modify_irte_ga(ir_data->irq_2_irte.devid,
3396 ir_data->irq_2_irte.index, entry, ir_data);
3397 }
3398 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3399
amd_ir_set_vcpu_affinity(struct irq_data * data,void * vcpu_info)3400 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3401 {
3402 int ret;
3403 struct amd_iommu *iommu;
3404 struct amd_iommu_pi_data *pi_data = vcpu_info;
3405 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3406 struct amd_ir_data *ir_data = data->chip_data;
3407 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3408 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3409
3410 /* Note:
3411 * This device has never been set up for guest mode.
3412 * we should not modify the IRTE
3413 */
3414 if (!dev_data || !dev_data->use_vapic)
3415 return 0;
3416
3417 ir_data->cfg = irqd_cfg(data);
3418 pi_data->ir_data = ir_data;
3419
3420 /* Note:
3421 * SVM tries to set up for VAPIC mode, but we are in
3422 * legacy mode. So, we force legacy mode instead.
3423 */
3424 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3425 pr_debug("%s: Fall back to using intr legacy remap\n",
3426 __func__);
3427 pi_data->is_guest_mode = false;
3428 }
3429
3430 iommu = amd_iommu_rlookup_table[irte_info->devid];
3431 if (iommu == NULL)
3432 return -EINVAL;
3433
3434 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3435 if (pi_data->is_guest_mode) {
3436 ir_data->ga_root_ptr = (pi_data->base >> 12);
3437 ir_data->ga_vector = vcpu_pi_info->vector;
3438 ir_data->ga_tag = pi_data->ga_tag;
3439 ret = amd_iommu_activate_guest_mode(ir_data);
3440 if (!ret)
3441 ir_data->cached_ga_tag = pi_data->ga_tag;
3442 } else {
3443 ret = amd_iommu_deactivate_guest_mode(ir_data);
3444
3445 /*
3446 * This communicates the ga_tag back to the caller
3447 * so that it can do all the necessary clean up.
3448 */
3449 if (!ret)
3450 ir_data->cached_ga_tag = 0;
3451 }
3452
3453 return ret;
3454 }
3455
3456
amd_ir_update_irte(struct irq_data * irqd,struct amd_iommu * iommu,struct amd_ir_data * ir_data,struct irq_2_irte * irte_info,struct irq_cfg * cfg)3457 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3458 struct amd_ir_data *ir_data,
3459 struct irq_2_irte *irte_info,
3460 struct irq_cfg *cfg)
3461 {
3462
3463 /*
3464 * Atomically updates the IRTE with the new destination, vector
3465 * and flushes the interrupt entry cache.
3466 */
3467 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
3468 irte_info->index, cfg->vector,
3469 cfg->dest_apicid);
3470 }
3471
amd_ir_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)3472 static int amd_ir_set_affinity(struct irq_data *data,
3473 const struct cpumask *mask, bool force)
3474 {
3475 struct amd_ir_data *ir_data = data->chip_data;
3476 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3477 struct irq_cfg *cfg = irqd_cfg(data);
3478 struct irq_data *parent = data->parent_data;
3479 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3480 int ret;
3481
3482 if (!iommu)
3483 return -ENODEV;
3484
3485 ret = parent->chip->irq_set_affinity(parent, mask, force);
3486 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3487 return ret;
3488
3489 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3490 /*
3491 * After this point, all the interrupts will start arriving
3492 * at the new destination. So, time to cleanup the previous
3493 * vector allocation.
3494 */
3495 send_cleanup_vector(cfg);
3496
3497 return IRQ_SET_MASK_OK_DONE;
3498 }
3499
ir_compose_msi_msg(struct irq_data * irq_data,struct msi_msg * msg)3500 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3501 {
3502 struct amd_ir_data *ir_data = irq_data->chip_data;
3503
3504 *msg = ir_data->msi_entry;
3505 }
3506
3507 static struct irq_chip amd_ir_chip = {
3508 .name = "AMD-IR",
3509 .irq_ack = apic_ack_irq,
3510 .irq_set_affinity = amd_ir_set_affinity,
3511 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
3512 .irq_compose_msi_msg = ir_compose_msi_msg,
3513 };
3514
amd_iommu_create_irq_domain(struct amd_iommu * iommu)3515 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3516 {
3517 struct fwnode_handle *fn;
3518
3519 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3520 if (!fn)
3521 return -ENOMEM;
3522 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
3523 if (!iommu->ir_domain) {
3524 irq_domain_free_fwnode(fn);
3525 return -ENOMEM;
3526 }
3527
3528 iommu->ir_domain->parent = arch_get_ir_parent_domain();
3529 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
3530 "AMD-IR-MSI",
3531 iommu->index);
3532 return 0;
3533 }
3534
amd_iommu_update_ga(int cpu,bool is_run,void * data)3535 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
3536 {
3537 unsigned long flags;
3538 struct amd_iommu *iommu;
3539 struct irq_remap_table *table;
3540 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3541 int devid = ir_data->irq_2_irte.devid;
3542 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3543 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
3544
3545 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3546 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
3547 return 0;
3548
3549 iommu = amd_iommu_rlookup_table[devid];
3550 if (!iommu)
3551 return -ENODEV;
3552
3553 table = get_irq_table(devid);
3554 if (!table)
3555 return -ENODEV;
3556
3557 raw_spin_lock_irqsave(&table->lock, flags);
3558
3559 if (ref->lo.fields_vapic.guest_mode) {
3560 if (cpu >= 0) {
3561 ref->lo.fields_vapic.destination =
3562 APICID_TO_IRTE_DEST_LO(cpu);
3563 ref->hi.fields.destination =
3564 APICID_TO_IRTE_DEST_HI(cpu);
3565 }
3566 ref->lo.fields_vapic.is_run = is_run;
3567 barrier();
3568 }
3569
3570 raw_spin_unlock_irqrestore(&table->lock, flags);
3571
3572 iommu_flush_irt(iommu, devid);
3573 iommu_completion_wait(iommu);
3574 return 0;
3575 }
3576 EXPORT_SYMBOL(amd_iommu_update_ga);
3577 #endif
3578